arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 extern void device_scan(void);
  41
  42 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  43
  44 unsigned long *sparc64_valid_addr_bitmap;
  45
  46 /* Ugly, but necessary... -DaveM */
  47 unsigned long phys_base;
  48 unsigned long kern_base;
  49 unsigned long kern_size;
  50 unsigned long pfn_base;
  51
  52 /* This is even uglier. We have a problem where the kernel may not be
  53  * located at phys_base. However, initial __alloc_bootmem() calls need to
  54  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  55  * those page mappings wont work. Things are ok after inherit_prom_mappings
  56  * is called though. Dave says he'll clean this up some other time.
  57  * -- BenC
  58  */
  59 static unsigned long bootmap_base;
  60
  61 /* get_new_mmu_context() uses "cache + 1".  */
  62 spinlock_t ctx_alloc_lock = SPIN_LOCK_UNLOCKED;
  63 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  64 #define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6))
  65 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  66
  67 /* References to special section boundaries */
  68 extern char  _start[], _end[];
  69
  70 /* Initial ramdisk setup */
  71 extern unsigned int sparc_ramdisk_image;
  72 extern unsigned int sparc_ramdisk_size;
  73
  74 struct page *mem_map_zero;
  75
  76 int bigkernel = 0;
  77
  78 /* XXX Tune this... */
  79 #define PGT_CACHE_LOW   25
  80 #define PGT_CACHE_HIGH  50
  81
  82 void check_pgt_cache(void)
  83 {
  84         preempt_disable();
  85         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  86                 do {
  87 #ifdef CONFIG_SMP
  88                         if (pgd_quicklist)
  89                                 free_pgd_slow(get_pgd_fast());
  90 #endif
  91                         if (pte_quicklist[0])
  92                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  93                         if (pte_quicklist[1])
  94                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  95                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  96         }
  97 #ifndef CONFIG_SMP
  98         if (pgd_cache_size > PGT_CACHE_HIGH / 4) {
  99                 struct page *page, *page2;
 100                 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
 101                         if ((unsigned long)page->lru.prev == 3) {
 102                                 if (page2)
 103                                         page2->lru.next = page->lru.next;
 104                                 else
 105                                         pgd_quicklist = (void *) page->lru.next;
 106                                 pgd_cache_size -= 2;
 107                                 __free_page(page);
 108                                 if (page2)
 109                                         page = (struct page *)page2->lru.next;
 110                                 else
 111                                         page = (struct page *)pgd_quicklist;
 112                                 if (pgd_cache_size <= PGT_CACHE_LOW / 4)
 113                                         break;
 114                                 continue;
 115                         }
 116                         page2 = page;
 117                         page = (struct page *)page->lru.next;
 118                 }
 119         }
 120 #endif
 121         preempt_enable();
 122 }
 123
 124 #ifdef CONFIG_DEBUG_DCFLUSH
 125 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 126 #ifdef CONFIG_SMP
 127 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 128 #endif
 129 #endif
 130
 131 __inline__ void flush_dcache_page_impl(struct page *page)
 132 {
 133 #ifdef CONFIG_DEBUG_DCFLUSH
 134         atomic_inc(&dcpage_flushes);
 135 #endif
 136
 137 #if (L1DCACHE_SIZE > PAGE_SIZE)
 138         __flush_dcache_page(page_address(page),
 139                             ((tlb_type == spitfire) &&
 140                              page_mapping(page) != NULL));
 141 #else
 142         if (page_mapping(page) != NULL &&
 143             tlb_type == spitfire)
 144                 __flush_icache_page(__pa(page_address(page)));
 145 #endif
 146 }
 147
 148 #define PG_dcache_dirty         PG_arch_1
 149
 150 #define dcache_dirty_cpu(page) \
 151         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 152
 153 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 154 {
 155         unsigned long mask = this_cpu;
 156         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 157         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 158         __asm__ __volatile__("1:\n\t"
 159                              "ldx       [%2], %%g7\n\t"
 160                              "and       %%g7, %1, %%g5\n\t"
 161                              "or        %%g5, %0, %%g5\n\t"
 162                              "casx      [%2], %%g7, %%g5\n\t"
 163                              "cmp       %%g7, %%g5\n\t"
 164                              "bne,pn    %%xcc, 1b\n\t"
 165                              " membar   #StoreLoad | #StoreStore"
 166                              : /* no outputs */
 167                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 168                              : "g5", "g7");
 169 }
 170
 171 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 172 {
 173         unsigned long mask = (1UL << PG_dcache_dirty);
 174
 175         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 176                              "1:\n\t"
 177                              "ldx       [%2], %%g7\n\t"
 178                              "srlx      %%g7, 24, %%g5\n\t"
 179                              "and       %%g5, %3, %%g5\n\t"
 180                              "cmp       %%g5, %0\n\t"
 181                              "bne,pn    %%icc, 2f\n\t"
 182                              " andn     %%g7, %1, %%g5\n\t"
 183                              "casx      [%2], %%g7, %%g5\n\t"
 184                              "cmp       %%g7, %%g5\n\t"
 185                              "bne,pn    %%xcc, 1b\n\t"
 186                              " membar   #StoreLoad | #StoreStore\n"
 187                              "2:"
 188                              : /* no outputs */
 189                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 190                                "i" (NR_CPUS - 1UL)
 191                              : "g5", "g7");
 192 }
 193
 194 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 195
 196 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 197 {
 198         struct page *page;
 199         unsigned long pfn;
 200         unsigned long pg_flags;
 201
 202         pfn = pte_pfn(pte);
 203         if (pfn_valid(pfn) &&
 204             (page = pfn_to_page(pfn), page_mapping(page)) &&
 205             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 206                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 207                 int this_cpu = get_cpu();
 208
 209                 /* This is just to optimize away some function calls
 210                  * in the SMP case.
 211                  */
 212                 if (cpu == this_cpu)
 213                         flush_dcache_page_impl(page);
 214                 else
 215                         smp_flush_dcache_page_impl(page, cpu);
 216
 217                 clear_dcache_dirty_cpu(page, cpu);
 218
 219                 put_cpu();
 220         }
 221         if (get_thread_fault_code())
 222                 __update_mmu_cache(vma->vm_mm->context & TAG_CONTEXT_BITS,
 223                                    address, pte, get_thread_fault_code());
 224 }
 225
 226 void flush_dcache_page(struct page *page)
 227 {
 228         struct address_space *mapping = page_mapping(page);
 229         int dirty = test_bit(PG_dcache_dirty, &page->flags);
 230         int dirty_cpu = dcache_dirty_cpu(page);
 231         int this_cpu = get_cpu();
 232
 233         if (mapping && !mapping_mapped(mapping)) {
 234                 if (dirty) {
 235                         if (dirty_cpu == this_cpu)
 236                                 goto out;
 237                         smp_flush_dcache_page_impl(page, dirty_cpu);
 238                 }
 239                 set_dcache_dirty(page, this_cpu);
 240         } else {
 241                 /* We could delay the flush for the !page_mapping
 242                  * case too.  But that case is for exec env/arg
 243                  * pages and those are %99 certainly going to get
 244                  * faulted into the tlb (and thus flushed) anyways.
 245                  */
 246                 flush_dcache_page_impl(page);
 247         }
 248
 249 out:
 250         put_cpu();
 251 }
 252
 253 void flush_icache_range(unsigned long start, unsigned long end)
 254 {
 255         /* Cheetah has coherent I-cache. */
 256         if (tlb_type == spitfire) {
 257                 unsigned long kaddr;
 258
 259                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 260                         __flush_icache_page(__get_phys(kaddr));
 261         }
 262 }
 263
 264 unsigned long page_to_pfn(struct page *page)
 265 {
 266         return (unsigned long) ((page - mem_map) + pfn_base);
 267 }
 268
 269 struct page *pfn_to_page(unsigned long pfn)
 270 {
 271         return (mem_map + (pfn - pfn_base));
 272 }
 273
 274 void show_mem(void)
 275 {
 276         printk("Mem-info:\n");
 277         show_free_areas();
 278         printk("Free swap:       %6ldkB\n",
 279                nr_swap_pages << (PAGE_SHIFT-10));
 280         printk("%ld pages of RAM\n", num_physpages);
 281         printk("%d free pages\n", nr_free_pages());
 282         printk("%d pages in page table cache\n",pgtable_cache_size);
 283 #ifndef CONFIG_SMP
 284         printk("%d entries in page dir cache\n",pgd_cache_size);
 285 #endif
 286 }
 287
 288 void mmu_info(struct seq_file *m)
 289 {
 290         if (tlb_type == cheetah)
 291                 seq_printf(m, "MMU Type\t: Cheetah\n");
 292         else if (tlb_type == cheetah_plus)
 293                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 294         else if (tlb_type == spitfire)
 295                 seq_printf(m, "MMU Type\t: Spitfire\n");
 296         else
 297                 seq_printf(m, "MMU Type\t: ???\n");
 298
 299 #ifdef CONFIG_DEBUG_DCFLUSH
 300         seq_printf(m, "DCPageFlushes\t: %d\n",
 301                    atomic_read(&dcpage_flushes));
 302 #ifdef CONFIG_SMP
 303         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 304                    atomic_read(&dcpage_flushes_xcall));
 305 #endif /* CONFIG_SMP */
 306 #endif /* CONFIG_DEBUG_DCFLUSH */
 307 }
 308
 309 struct linux_prom_translation {
 310         unsigned long virt;
 311         unsigned long size;
 312         unsigned long data;
 313 };
 314
 315 extern unsigned long prom_boot_page;
 316 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 317 extern int prom_get_mmu_ihandle(void);
 318 extern void register_prom_callbacks(void);
 319
 320 /* Exported for SMP bootup purposes. */
 321 unsigned long kern_locked_tte_data;
 322
 323 void __init early_pgtable_allocfail(char *type)
 324 {
 325         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 326         prom_halt();
 327 }
 328
 329 #define BASE_PAGE_SIZE 8192
 330 static pmd_t *prompmd;
 331
 332 /*
 333  * Translate PROM's mapping we capture at boot time into physical address.
 334  * The second parameter is only set from prom_callback() invocations.
 335  */
 336 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 337 {
 338         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 339         pte_t *ptep;
 340         unsigned long base;
 341
 342         if (pmd_none(*pmdp)) {
 343                 if (error)
 344                         *error = 1;
 345                 return(0);
 346         }
 347         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 348         if (!pte_present(*ptep)) {
 349                 if (error)
 350                         *error = 1;
 351                 return(0);
 352         }
 353         if (error) {
 354                 *error = 0;
 355                 return(pte_val(*ptep));
 356         }
 357         base = pte_val(*ptep) & _PAGE_PADDR;
 358         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 359 }
 360
 361 static void inherit_prom_mappings(void)
 362 {
 363         struct linux_prom_translation *trans;
 364         unsigned long phys_page, tte_vaddr, tte_data;
 365         void (*remap_func)(unsigned long, unsigned long, int);
 366         pmd_t *pmdp;
 367         pte_t *ptep;
 368         int node, n, i, tsz;
 369         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 370
 371         node = prom_finddevice("/virtual-memory");
 372         n = prom_getproplen(node, "translations");
 373         if (n == 0 || n == -1) {
 374                 prom_printf("Couldn't get translation property\n");
 375                 prom_halt();
 376         }
 377         n += 5 * sizeof(struct linux_prom_translation);
 378         for (tsz = 1; tsz < n; tsz <<= 1)
 379                 /* empty */;
 380         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 381         if (trans == NULL) {
 382                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 383                 prom_halt();
 384         }
 385         memset(trans, 0, tsz);
 386
 387         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 388                 prom_printf("Couldn't get translation property\n");
 389                 prom_halt();
 390         }
 391         n = n / sizeof(*trans);
 392
 393         /*
 394          * The obp translations are saved based on 8k pagesize, since obp can use
 395          * a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, ie obp
 396          * range, are handled in entry.S and do not use the vpte scheme (see rant
 397          * in inherit_locked_prom_mappings()).
 398          */
 399 #define OBP_PMD_SIZE 2048
 400         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 401         if (prompmd == NULL)
 402                 early_pgtable_allocfail("pmd");
 403         memset(prompmd, 0, OBP_PMD_SIZE);
 404         for (i = 0; i < n; i++) {
 405                 unsigned long vaddr;
 406
 407                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 408                         for (vaddr = trans[i].virt;
 409                              ((vaddr < trans[i].virt + trans[i].size) &&
 410                              (vaddr < HI_OBP_ADDRESS));
 411                              vaddr += BASE_PAGE_SIZE) {
 412                                 unsigned long val;
 413
 414                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 415                                 if (pmd_none(*pmdp)) {
 416                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 417                                                                BASE_PAGE_SIZE,
 418                                                                bootmap_base);
 419                                         if (ptep == NULL)
 420                                                 early_pgtable_allocfail("pte");
 421                                         memset(ptep, 0, BASE_PAGE_SIZE);
 422                                         pmd_set(pmdp, ptep);
 423                                 }
 424                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 425                                                 ((vaddr >> 13) & 0x3ff);
 426
 427                                 val = trans[i].data;
 428
 429                                 /* Clear diag TTE bits. */
 430                                 if (tlb_type == spitfire)
 431                                         val &= ~0x0003fe0000000000UL;
 432
 433                                 set_pte (ptep, __pte(val | _PAGE_MODIFIED));
 434                                 trans[i].data += BASE_PAGE_SIZE;
 435                         }
 436                 }
 437         }
 438         phys_page = __pa(prompmd);
 439         obp_iaddr_patch[0] |= (phys_page >> 10);
 440         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 441         flushi((long)&obp_iaddr_patch[0]);
 442         obp_daddr_patch[0] |= (phys_page >> 10);
 443         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 444         flushi((long)&obp_daddr_patch[0]);
 445
 446         /* Now fixup OBP's idea about where we really are mapped. */
 447         prom_printf("Remapping the kernel... ");
 448
 449         /* Spitfire Errata #32 workaround */
 450         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 451                              "flush     %%g6"
 452                              : /* No outputs */
 453                              : "r" (0),
 454                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 455
 456         switch (tlb_type) {
 457         default:
 458         case spitfire:
 459                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 460                 break;
 461
 462         case cheetah:
 463         case cheetah_plus:
 464                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 465                 break;
 466         };
 467
 468         phys_page &= _PAGE_PADDR;
 469         phys_page += ((unsigned long)&prom_boot_page -
 470                       (unsigned long)KERNBASE);
 471
 472         if (tlb_type == spitfire) {
 473                 /* Lock this into i/d tlb entry 59 */
 474                 __asm__ __volatile__(
 475                         "stxa   %%g0, [%2] %3\n\t"
 476                         "stxa   %0, [%1] %4\n\t"
 477                         "membar #Sync\n\t"
 478                         "flush  %%g6\n\t"
 479                         "stxa   %%g0, [%2] %5\n\t"
 480                         "stxa   %0, [%1] %6\n\t"
 481                         "membar #Sync\n\t"
 482                         "flush  %%g6"
 483                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 484                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 485                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 486                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 487                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 488                         : "memory");
 489         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 490                 /* Lock this into i/d tlb-0 entry 11 */
 491                 __asm__ __volatile__(
 492                         "stxa   %%g0, [%2] %3\n\t"
 493                         "stxa   %0, [%1] %4\n\t"
 494                         "membar #Sync\n\t"
 495                         "flush  %%g6\n\t"
 496                         "stxa   %%g0, [%2] %5\n\t"
 497                         "stxa   %0, [%1] %6\n\t"
 498                         "membar #Sync\n\t"
 499                         "flush  %%g6"
 500                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 501                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 502                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 503                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 504                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 505                         : "memory");
 506         } else {
 507                 /* Implement me :-) */
 508                 BUG();
 509         }
 510
 511         tte_vaddr = (unsigned long) KERNBASE;
 512
 513         /* Spitfire Errata #32 workaround */
 514         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 515                              "flush     %%g6"
 516                              : /* No outputs */
 517                              : "r" (0),
 518                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 519
 520         if (tlb_type == spitfire)
 521                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 522         else
 523                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 524
 525         kern_locked_tte_data = tte_data;
 526
 527         remap_func = (void *)  ((unsigned long) &prom_remap -
 528                                 (unsigned long) &prom_boot_page);
 529
 530
 531         /* Spitfire Errata #32 workaround */
 532         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 533                              "flush     %%g6"
 534                              : /* No outputs */
 535                              : "r" (0),
 536                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 537
 538         remap_func((tlb_type == spitfire ?
 539                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 540                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 541                    (unsigned long) KERNBASE,
 542                    prom_get_mmu_ihandle());
 543
 544         if (bigkernel)
 545                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 546                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 547
 548         /* Flush out that temporary mapping. */
 549         spitfire_flush_dtlb_nucleus_page(0x0);
 550         spitfire_flush_itlb_nucleus_page(0x0);
 551
 552         /* Now lock us back into the TLBs via OBP. */
 553         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 554         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 555         if (bigkernel) {
 556                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 557                                                                 tte_vaddr + 0x400000);
 558                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 559                                                                 tte_vaddr + 0x400000);
 560         }
 561
 562         /* Re-read translations property. */
 563         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 564                 prom_printf("Couldn't get translation property\n");
 565                 prom_halt();
 566         }
 567         n = n / sizeof(*trans);
 568
 569         for (i = 0; i < n; i++) {
 570                 unsigned long vaddr = trans[i].virt;
 571                 unsigned long size = trans[i].size;
 572
 573                 if (vaddr < 0xf0000000UL) {
 574                         unsigned long avoid_start = (unsigned long) KERNBASE;
 575                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 576
 577                         if (bigkernel)
 578                                 avoid_end += (4 * 1024 * 1024);
 579                         if (vaddr < avoid_start) {
 580                                 unsigned long top = vaddr + size;
 581
 582                                 if (top > avoid_start)
 583                                         top = avoid_start;
 584                                 prom_unmap(top - vaddr, vaddr);
 585                         }
 586                         if ((vaddr + size) > avoid_end) {
 587                                 unsigned long bottom = vaddr;
 588
 589                                 if (bottom < avoid_end)
 590                                         bottom = avoid_end;
 591                                 prom_unmap((vaddr + size) - bottom, bottom);
 592                         }
 593                 }
 594         }
 595
 596         prom_printf("done.\n");
 597
 598         register_prom_callbacks();
 599 }
 600
 601 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 602  * upwards as reserved for use by the firmware (I wonder if this
 603  * will be the same on Cheetah...).  We use this virtual address
 604  * range for the VPTE table mappings of the nucleus so we need
 605  * to zap them when we enter the PROM.  -DaveM
 606  */
 607 static void __flush_nucleus_vptes(void)
 608 {
 609         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 610         int i;
 611
 612         /* Only DTLB must be checked for VPTE entries. */
 613         if (tlb_type == spitfire) {
 614                 for (i = 0; i < 63; i++) {
 615                         unsigned long tag;
 616
 617                         /* Spitfire Errata #32 workaround */
 618                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 619                                              "flush     %%g6"
 620                                              : /* No outputs */
 621                                              : "r" (0),
 622                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 623
 624                         tag = spitfire_get_dtlb_tag(i);
 625                         if (((tag & ~(PAGE_MASK)) == 0) &&
 626                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 627                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 628                                                      "membar #Sync"
 629                                                      : /* no outputs */
 630                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 631                                 spitfire_put_dtlb_data(i, 0x0UL);
 632                         }
 633                 }
 634         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 635                 for (i = 0; i < 512; i++) {
 636                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 637
 638                         if ((tag & ~PAGE_MASK) == 0 &&
 639                             (tag & PAGE_MASK) >= prom_reserved_base) {
 640                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 641                                                      "membar #Sync"
 642                                                      : /* no outputs */
 643                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 644                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 645                         }
 646
 647                         if (tlb_type != cheetah_plus)
 648                                 continue;
 649
 650                         tag = cheetah_get_dtlb_tag(i, 3);
 651
 652                         if ((tag & ~PAGE_MASK) == 0 &&
 653                             (tag & PAGE_MASK) >= prom_reserved_base) {
 654                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 655                                                      "membar #Sync"
 656                                                      : /* no outputs */
 657                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 658                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 659                         }
 660                 }
 661         } else {
 662                 /* Implement me :-) */
 663                 BUG();
 664         }
 665 }
 666
 667 static int prom_ditlb_set;
 668 struct prom_tlb_entry {
 669         int             tlb_ent;
 670         unsigned long   tlb_tag;
 671         unsigned long   tlb_data;
 672 };
 673 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 674
 675 void prom_world(int enter)
 676 {
 677         unsigned long pstate;
 678         int i;
 679
 680         if (!enter)
 681                 set_fs((mm_segment_t) { get_thread_current_ds() });
 682
 683         if (!prom_ditlb_set)
 684                 return;
 685
 686         /* Make sure the following runs atomically. */
 687         __asm__ __volatile__("flushw\n\t"
 688                              "rdpr      %%pstate, %0\n\t"
 689                              "wrpr      %0, %1, %%pstate"
 690                              : "=r" (pstate)
 691                              : "i" (PSTATE_IE));
 692
 693         if (enter) {
 694                 /* Kick out nucleus VPTEs. */
 695                 __flush_nucleus_vptes();
 696
 697                 /* Install PROM world. */
 698                 for (i = 0; i < 16; i++) {
 699                         if (prom_dtlb[i].tlb_ent != -1) {
 700                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 701                                                      "membar #Sync"
 702                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 703                                         "i" (ASI_DMMU));
 704                                 if (tlb_type == spitfire)
 705                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 706                                                                prom_dtlb[i].tlb_data);
 707                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 708                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 709                                                                prom_dtlb[i].tlb_data);
 710                         }
 711                         if (prom_itlb[i].tlb_ent != -1) {
 712                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 713                                                      "membar #Sync"
 714                                                      : : "r" (prom_itlb[i].tlb_tag),
 715                                                      "r" (TLB_TAG_ACCESS),
 716                                                      "i" (ASI_IMMU));
 717                                 if (tlb_type == spitfire)
 718                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 719                                                                prom_itlb[i].tlb_data);
 720                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 721                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 722                                                                prom_itlb[i].tlb_data);
 723                         }
 724                 }
 725         } else {
 726                 for (i = 0; i < 16; i++) {
 727                         if (prom_dtlb[i].tlb_ent != -1) {
 728                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 729                                                      "membar #Sync"
 730                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 731                                 if (tlb_type == spitfire)
 732                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 733                                 else
 734                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 735                         }
 736                         if (prom_itlb[i].tlb_ent != -1) {
 737                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 738                                                      "membar #Sync"
 739                                                      : : "r" (TLB_TAG_ACCESS),
 740                                                      "i" (ASI_IMMU));
 741                                 if (tlb_type == spitfire)
 742                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 743                                 else
 744                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 745                         }
 746                 }
 747         }
 748         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 749                              : : "r" (pstate));
 750 }
 751
 752 void inherit_locked_prom_mappings(int save_p)
 753 {
 754         int i;
 755         int dtlb_seen = 0;
 756         int itlb_seen = 0;
 757
 758         /* Fucking losing PROM has more mappings in the TLB, but
 759          * it (conveniently) fails to mention any of these in the
 760          * translations property.  The only ones that matter are
 761          * the locked PROM tlb entries, so we impose the following
 762          * irrecovable rule on the PROM, it is allowed 8 locked
 763          * entries in the ITLB and 8 in the DTLB.
 764          *
 765          * Supposedly the upper 16GB of the address space is
 766          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 767          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 768          * used between the client program and the firmware on sun5
 769          * systems to coordinate mmu mappings is also COMPLETELY
 770          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 771          */
 772         if (save_p) {
 773                 for (i = 0; i < 16; i++) {
 774                         prom_itlb[i].tlb_ent = -1;
 775                         prom_dtlb[i].tlb_ent = -1;
 776                 }
 777         }
 778         if (tlb_type == spitfire) {
 779                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 780                 for (i = 0; i < high; i++) {
 781                         unsigned long data;
 782
 783                         /* Spitfire Errata #32 workaround */
 784                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 785                                              "flush     %%g6"
 786                                              : /* No outputs */
 787                                              : "r" (0),
 788                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 789
 790                         data = spitfire_get_dtlb_data(i);
 791                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 792                                 unsigned long tag;
 793
 794                                 /* Spitfire Errata #32 workaround */
 795                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 796                                                      "flush     %%g6"
 797                                                      : /* No outputs */
 798                                                      : "r" (0),
 799                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 800
 801                                 tag = spitfire_get_dtlb_tag(i);
 802                                 if (save_p) {
 803                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 804                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 805                                         prom_dtlb[dtlb_seen].tlb_data = data;
 806                                 }
 807                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 808                                                      "membar #Sync"
 809                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 810                                 spitfire_put_dtlb_data(i, 0x0UL);
 811
 812                                 dtlb_seen++;
 813                                 if (dtlb_seen > 15)
 814                                         break;
 815                         }
 816                 }
 817
 818                 for (i = 0; i < high; i++) {
 819                         unsigned long data;
 820
 821                         /* Spitfire Errata #32 workaround */
 822                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 823                                              "flush     %%g6"
 824                                              : /* No outputs */
 825                                              : "r" (0),
 826                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 827
 828                         data = spitfire_get_itlb_data(i);
 829                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 830                                 unsigned long tag;
 831
 832                                 /* Spitfire Errata #32 workaround */
 833                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 834                                                      "flush     %%g6"
 835                                                      : /* No outputs */
 836                                                      : "r" (0),
 837                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 838
 839                                 tag = spitfire_get_itlb_tag(i);
 840                                 if (save_p) {
 841                                         prom_itlb[itlb_seen].tlb_ent = i;
 842                                         prom_itlb[itlb_seen].tlb_tag = tag;
 843                                         prom_itlb[itlb_seen].tlb_data = data;
 844                                 }
 845                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 846                                                      "membar #Sync"
 847                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 848                                 spitfire_put_itlb_data(i, 0x0UL);
 849
 850                                 itlb_seen++;
 851                                 if (itlb_seen > 15)
 852                                         break;
 853                         }
 854                 }
 855         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 856                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 857
 858                 for (i = 0; i < high; i++) {
 859                         unsigned long data;
 860
 861                         data = cheetah_get_ldtlb_data(i);
 862                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 863                                 unsigned long tag;
 864
 865                                 tag = cheetah_get_ldtlb_tag(i);
 866                                 if (save_p) {
 867                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 868                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 869                                         prom_dtlb[dtlb_seen].tlb_data = data;
 870                                 }
 871                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 872                                                      "membar #Sync"
 873                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 874                                 cheetah_put_ldtlb_data(i, 0x0UL);
 875
 876                                 dtlb_seen++;
 877                                 if (dtlb_seen > 15)
 878                                         break;
 879                         }
 880                 }
 881
 882                 for (i = 0; i < high; i++) {
 883                         unsigned long data;
 884
 885                         data = cheetah_get_litlb_data(i);
 886                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 887                                 unsigned long tag;
 888
 889                                 tag = cheetah_get_litlb_tag(i);
 890                                 if (save_p) {
 891                                         prom_itlb[itlb_seen].tlb_ent = i;
 892                                         prom_itlb[itlb_seen].tlb_tag = tag;
 893                                         prom_itlb[itlb_seen].tlb_data = data;
 894                                 }
 895                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 896                                                      "membar #Sync"
 897                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 898                                 cheetah_put_litlb_data(i, 0x0UL);
 899
 900                                 itlb_seen++;
 901                                 if (itlb_seen > 15)
 902                                         break;
 903                         }
 904                 }
 905         } else {
 906                 /* Implement me :-) */
 907                 BUG();
 908         }
 909         if (save_p)
 910                 prom_ditlb_set = 1;
 911 }
 912
 913 /* Give PROM back his world, done during reboots... */
 914 void prom_reload_locked(void)
 915 {
 916         int i;
 917
 918         for (i = 0; i < 16; i++) {
 919                 if (prom_dtlb[i].tlb_ent != -1) {
 920                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 921                                              "membar #Sync"
 922                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 923                                 "i" (ASI_DMMU));
 924                         if (tlb_type == spitfire)
 925                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 926                                                        prom_dtlb[i].tlb_data);
 927                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 928                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 929                                                       prom_dtlb[i].tlb_data);
 930                 }
 931
 932                 if (prom_itlb[i].tlb_ent != -1) {
 933                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 934                                              "membar #Sync"
 935                                              : : "r" (prom_itlb[i].tlb_tag),
 936                                              "r" (TLB_TAG_ACCESS),
 937                                              "i" (ASI_IMMU));
 938                         if (tlb_type == spitfire)
 939                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 940                                                        prom_itlb[i].tlb_data);
 941                         else
 942                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 943                                                        prom_itlb[i].tlb_data);
 944                 }
 945         }
 946 }
 947
 948 void __flush_dcache_range(unsigned long start, unsigned long end)
 949 {
 950         unsigned long va;
 951
 952         if (tlb_type == spitfire) {
 953                 int n = 0;
 954
 955                 for (va = start; va < end; va += 32) {
 956                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 957                         if (++n >= 512)
 958                                 break;
 959                 }
 960         } else {
 961                 start = __pa(start);
 962                 end = __pa(end);
 963                 for (va = start; va < end; va += 32)
 964                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 965                                              "membar #Sync"
 966                                              : /* no outputs */
 967                                              : "r" (va),
 968                                                "i" (ASI_DCACHE_INVALIDATE));
 969         }
 970 }
 971
 972 /* If not locked, zap it. */
 973 void __flush_tlb_all(void)
 974 {
 975         unsigned long pstate;
 976         int i;
 977
 978         __asm__ __volatile__("flushw\n\t"
 979                              "rdpr      %%pstate, %0\n\t"
 980                              "wrpr      %0, %1, %%pstate"
 981                              : "=r" (pstate)
 982                              : "i" (PSTATE_IE));
 983         if (tlb_type == spitfire) {
 984                 for (i = 0; i < 64; i++) {
 985                         /* Spitfire Errata #32 workaround */
 986                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 987                                              "flush     %%g6"
 988                                              : /* No outputs */
 989                                              : "r" (0),
 990                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 991
 992                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 993                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 994                                                      "membar #Sync"
 995                                                      : /* no outputs */
 996                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 997                                 spitfire_put_dtlb_data(i, 0x0UL);
 998                         }
 999
1000                         /* Spitfire Errata #32 workaround */
1001                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1002                                              "flush     %%g6"
1003                                              : /* No outputs */
1004                                              : "r" (0),
1005                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1006
1007                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1008                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1009                                                      "membar #Sync"
1010                                                      : /* no outputs */
1011                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1012                                 spitfire_put_itlb_data(i, 0x0UL);
1013                         }
1014                 }
1015         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1016                 cheetah_flush_dtlb_all();
1017                 cheetah_flush_itlb_all();
1018         }
1019         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1020                              : : "r" (pstate));
1021 }
1022
1023 /* Caller does TLB context flushing on local CPU if necessary.
1024  * The caller also ensures that CTX_VALID(mm->context) is false.
1025  *
1026  * We must be careful about boundary cases so that we never
1027  * let the user have CTX 0 (nucleus) or we ever use a CTX
1028  * version of zero (and thus NO_CONTEXT would not be caught
1029  * by version mis-match tests in mmu_context.h).
1030  */
1031 void get_new_mmu_context(struct mm_struct *mm)
1032 {
1033         unsigned long ctx, new_ctx;
1034
1035         spin_lock(&ctx_alloc_lock);
1036         ctx = CTX_HWBITS(tlb_context_cache + 1);
1037         new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx);
1038         if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) {
1039                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1040                 if (new_ctx >= ctx) {
1041                         int i;
1042                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1043                                 CTX_FIRST_VERSION;
1044                         if (new_ctx == 1)
1045                                 new_ctx = CTX_FIRST_VERSION;
1046
1047                         /* Don't call memset, for 16 entries that's just
1048                          * plain silly...
1049                          */
1050                         mmu_context_bmap[0] = 3;
1051                         mmu_context_bmap[1] = 0;
1052                         mmu_context_bmap[2] = 0;
1053                         mmu_context_bmap[3] = 0;
1054                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1055                                 mmu_context_bmap[i + 0] = 0;
1056                                 mmu_context_bmap[i + 1] = 0;
1057                                 mmu_context_bmap[i + 2] = 0;
1058                                 mmu_context_bmap[i + 3] = 0;
1059                         }
1060                         goto out;
1061                 }
1062         }
1063         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1064         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1065 out:
1066         tlb_context_cache = new_ctx;
1067         spin_unlock(&ctx_alloc_lock);
1068
1069         mm->context = new_ctx;
1070 }
1071
1072 #ifndef CONFIG_SMP
1073 struct pgtable_cache_struct pgt_quicklists;
1074 #endif
1075
1076 /* OK, we have to color these pages. The page tables are accessed
1077  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1078  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1079  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1080  * fast handlers do not get data from old/garbage dcache lines that
1081  * correspond to an old/stale virtual address (user/kernel) that
1082  * previously mapped the pagetable page while accessing vpte range
1083  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1084  * color is the same, then when the kernel initializes the pagetable
1085  * using the later address range, accesses with the first address
1086  * range will see the newly initialized data rather than the garbage.
1087  */
1088 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1089 #define DC_ALIAS_SHIFT  1
1090 #else
1091 #define DC_ALIAS_SHIFT  0
1092 #endif
1093 pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1094 {
1095         struct page *page;
1096         unsigned long color;
1097
1098         {
1099                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1100
1101                 if (ptep)
1102                         return ptep;
1103         }
1104
1105         color = VPTE_COLOR(address);
1106         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1107         if (page) {
1108                 unsigned long *to_free;
1109                 unsigned long paddr;
1110                 pte_t *pte;
1111
1112 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1113                 set_page_count(page, 1);
1114                 ClearPageCompound(page);
1115
1116                 set_page_count((page + 1), 1);
1117                 ClearPageCompound(page + 1);
1118 #endif
1119                 paddr = (unsigned long) page_address(page);
1120                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1121
1122                 if (!color) {
1123                         pte = (pte_t *) paddr;
1124                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1125                 } else {
1126                         pte = (pte_t *) (paddr + PAGE_SIZE);
1127                         to_free = (unsigned long *) paddr;
1128                 }
1129
1130 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1131                 /* Now free the other one up, adjust cache size. */
1132                 preempt_disable();
1133                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1134                 pte_quicklist[color ^ 0x1] = to_free;
1135                 pgtable_cache_size++;
1136                 preempt_enable();
1137 #endif
1138
1139                 return pte;
1140         }
1141         return NULL;
1142 }
1143
1144 void sparc_ultra_dump_itlb(void)
1145 {
1146         int slot;
1147
1148         if (tlb_type == spitfire) {
1149                 printk ("Contents of itlb: ");
1150                 for (slot = 0; slot < 14; slot++) printk ("    ");
1151                 printk ("%2x:%016lx,%016lx\n",
1152                         0,
1153                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1154                 for (slot = 1; slot < 64; slot+=3) {
1155                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1156                                 slot,
1157                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1158                                 slot+1,
1159                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1160                                 slot+2,
1161                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1162                 }
1163         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1164                 printk ("Contents of itlb0:\n");
1165                 for (slot = 0; slot < 16; slot+=2) {
1166                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1167                                 slot,
1168                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1169                                 slot+1,
1170                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1171                 }
1172                 printk ("Contents of itlb2:\n");
1173                 for (slot = 0; slot < 128; slot+=2) {
1174                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1175                                 slot,
1176                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1177                                 slot+1,
1178                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1179                 }
1180         }
1181 }
1182
1183 void sparc_ultra_dump_dtlb(void)
1184 {
1185         int slot;
1186
1187         if (tlb_type == spitfire) {
1188                 printk ("Contents of dtlb: ");
1189                 for (slot = 0; slot < 14; slot++) printk ("    ");
1190                 printk ("%2x:%016lx,%016lx\n", 0,
1191                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1192                 for (slot = 1; slot < 64; slot+=3) {
1193                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1194                                 slot,
1195                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1196                                 slot+1,
1197                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1198                                 slot+2,
1199                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1200                 }
1201         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1202                 printk ("Contents of dtlb0:\n");
1203                 for (slot = 0; slot < 16; slot+=2) {
1204                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1205                                 slot,
1206                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1207                                 slot+1,
1208                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1209                 }
1210                 printk ("Contents of dtlb2:\n");
1211                 for (slot = 0; slot < 512; slot+=2) {
1212                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1213                                 slot,
1214                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1215                                 slot+1,
1216                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1217                 }
1218                 if (tlb_type == cheetah_plus) {
1219                         printk ("Contents of dtlb3:\n");
1220                         for (slot = 0; slot < 512; slot+=2) {
1221                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1222                                         slot,
1223                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1224                                         slot+1,
1225                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1226                         }
1227                 }
1228         }
1229 }
1230
1231 extern unsigned long cmdline_memory_size;
1232
1233 unsigned long __init bootmem_init(unsigned long *pages_avail)
1234 {
1235         unsigned long bootmap_size, start_pfn, end_pfn;
1236         unsigned long end_of_phys_memory = 0UL;
1237         unsigned long bootmap_pfn, bytes_avail, size;
1238         int i;
1239
1240 #ifdef CONFIG_DEBUG_BOOTMEM
1241         prom_printf("bootmem_init: Scan sp_banks, ");
1242 #endif
1243
1244         bytes_avail = 0UL;
1245         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1246                 end_of_phys_memory = sp_banks[i].base_addr +
1247                         sp_banks[i].num_bytes;
1248                 bytes_avail += sp_banks[i].num_bytes;
1249                 if (cmdline_memory_size) {
1250                         if (bytes_avail > cmdline_memory_size) {
1251                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1252
1253                                 bytes_avail -= slack;
1254                                 end_of_phys_memory -= slack;
1255
1256                                 sp_banks[i].num_bytes -= slack;
1257                                 if (sp_banks[i].num_bytes == 0) {
1258                                         sp_banks[i].base_addr = 0xdeadbeef;
1259                                 } else {
1260                                         sp_banks[i+1].num_bytes = 0;
1261                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1262                                 }
1263                                 break;
1264                         }
1265                 }
1266         }
1267
1268         *pages_avail = bytes_avail >> PAGE_SHIFT;
1269
1270         /* Start with page aligned address of last symbol in kernel
1271          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1272          * 4MB locked TLB translation.
1273          */
1274         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1275
1276         bootmap_pfn = start_pfn;
1277
1278         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1279
1280 #ifdef CONFIG_BLK_DEV_INITRD
1281         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1282         if (sparc_ramdisk_image) {
1283                 if (sparc_ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1284                         sparc_ramdisk_image -= KERNBASE;
1285                 initrd_start = sparc_ramdisk_image + phys_base;
1286                 initrd_end = initrd_start + sparc_ramdisk_size;
1287                 if (initrd_end > end_of_phys_memory) {
1288                         printk(KERN_CRIT "initrd extends beyond end of memory "
1289                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1290                                initrd_end, end_of_phys_memory);
1291                         initrd_start = 0;
1292                 }
1293                 if (initrd_start) {
1294                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1295                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1296                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1297                 }
1298         }
1299 #endif
1300         /* Initialize the boot-time allocator. */
1301         max_pfn = max_low_pfn = end_pfn;
1302         min_low_pfn = pfn_base;
1303
1304 #ifdef CONFIG_DEBUG_BOOTMEM
1305         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1306                     min_low_pfn, bootmap_pfn, max_low_pfn);
1307 #endif
1308         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1309
1310         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1311
1312         /* Now register the available physical memory with the
1313          * allocator.
1314          */
1315         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1316 #ifdef CONFIG_DEBUG_BOOTMEM
1317                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1318                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1319 #endif
1320                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1321         }
1322
1323 #ifdef CONFIG_BLK_DEV_INITRD
1324         if (initrd_start) {
1325                 size = initrd_end - initrd_start;
1326
1327                 /* Resert the initrd image area. */
1328                 reserve_bootmem(initrd_start, size);
1329                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1330
1331                 initrd_start += PAGE_OFFSET;
1332                 initrd_end += PAGE_OFFSET;
1333         }
1334 #endif
1335         /* Reserve the kernel text/data/bss. */
1336 #ifdef CONFIG_DEBUG_BOOTMEM
1337         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1338 #endif
1339         reserve_bootmem(kern_base, kern_size);
1340         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1341
1342         /* Reserve the bootmem map.   We do not account for it
1343          * in pages_avail because we will release that memory
1344          * in free_all_bootmem.
1345          */
1346         size = bootmap_size;
1347 #ifdef CONFIG_DEBUG_BOOTMEM
1348         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1349                     (bootmap_pfn << PAGE_SHIFT), size);
1350 #endif
1351         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1352         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1353
1354         return end_pfn;
1355 }
1356
1357 /* paging_init() sets up the page tables */
1358
1359 extern void cheetah_ecache_flush_init(void);
1360
1361 static unsigned long last_valid_pfn;
1362
1363 void __init paging_init(void)
1364 {
1365         extern pmd_t swapper_pmd_dir[1024];
1366         extern unsigned int sparc64_vpte_patchme1[1];
1367         extern unsigned int sparc64_vpte_patchme2[1];
1368         unsigned long alias_base = kern_base + PAGE_OFFSET;
1369         unsigned long second_alias_page = 0;
1370         unsigned long pt, flags, end_pfn, pages_avail;
1371         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1372         unsigned long real_end;
1373
1374         set_bit(0, mmu_context_bmap);
1375
1376         real_end = (unsigned long)_end;
1377         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1378                 bigkernel = 1;
1379 #ifdef CONFIG_BLK_DEV_INITRD
1380         if (sparc_ramdisk_image)
1381                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1382 #endif
1383
1384         /* We assume physical memory starts at some 4mb multiple,
1385          * if this were not true we wouldn't boot up to this point
1386          * anyways.
1387          */
1388         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1389         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1390         local_irq_save(flags);
1391         if (tlb_type == spitfire) {
1392                 __asm__ __volatile__(
1393         "       stxa    %1, [%0] %3\n"
1394         "       stxa    %2, [%5] %4\n"
1395         "       membar  #Sync\n"
1396         "       flush   %%g6\n"
1397         "       nop\n"
1398         "       nop\n"
1399         "       nop\n"
1400                 : /* No outputs */
1401                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1402                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1403                 : "memory");
1404                 if (real_end >= KERNBASE + 0x340000) {
1405                         second_alias_page = alias_base + 0x400000;
1406                         __asm__ __volatile__(
1407                 "       stxa    %1, [%0] %3\n"
1408                 "       stxa    %2, [%5] %4\n"
1409                 "       membar  #Sync\n"
1410                 "       flush   %%g6\n"
1411                 "       nop\n"
1412                 "       nop\n"
1413                 "       nop\n"
1414                         : /* No outputs */
1415                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1416                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1417                         : "memory");
1418                 }
1419         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1420                 __asm__ __volatile__(
1421         "       stxa    %1, [%0] %3\n"
1422         "       stxa    %2, [%5] %4\n"
1423         "       membar  #Sync\n"
1424         "       flush   %%g6\n"
1425         "       nop\n"
1426         "       nop\n"
1427         "       nop\n"
1428                 : /* No outputs */
1429                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1430                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1431                 : "memory");
1432                 if (real_end >= KERNBASE + 0x340000) {
1433                         second_alias_page = alias_base + 0x400000;
1434                         __asm__ __volatile__(
1435                 "       stxa    %1, [%0] %3\n"
1436                 "       stxa    %2, [%5] %4\n"
1437                 "       membar  #Sync\n"
1438                 "       flush   %%g6\n"
1439                 "       nop\n"
1440                 "       nop\n"
1441                 "       nop\n"
1442                         : /* No outputs */
1443                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1444                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1445                         : "memory");
1446                 }
1447         }
1448         local_irq_restore(flags);
1449
1450         /* Now set kernel pgd to upper alias so physical page computations
1451          * work.
1452          */
1453         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1454
1455         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1456
1457         /* Now can init the kernel/bad page tables. */
1458         pgd_set(&swapper_pg_dir[0], swapper_pmd_dir + (shift / sizeof(pgd_t)));
1459
1460         sparc64_vpte_patchme1[0] |=
1461                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1462         sparc64_vpte_patchme2[0] |=
1463                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1464         flushi((long)&sparc64_vpte_patchme1[0]);
1465
1466         /* Setup bootmem... */
1467         pages_avail = 0;
1468         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1469
1470         /* Inherit non-locked OBP mappings. */
1471         inherit_prom_mappings();
1472
1473         /* Ok, we can use our TLB miss and window trap handlers safely.
1474          * We need to do a quick peek here to see if we are on StarFire
1475          * or not, so setup_tba can setup the IRQ globals correctly (it
1476          * needs to get the hard smp processor id correctly).
1477          */
1478         {
1479                 extern void setup_tba(int);
1480                 setup_tba(this_is_starfire);
1481         }
1482
1483         inherit_locked_prom_mappings(1);
1484
1485         /* We only created DTLB mapping of this stuff. */
1486         spitfire_flush_dtlb_nucleus_page(alias_base);
1487         if (second_alias_page)
1488                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1489
1490         __flush_tlb_all();
1491
1492         {
1493                 unsigned long zones_size[MAX_NR_ZONES];
1494                 unsigned long zholes_size[MAX_NR_ZONES];
1495                 unsigned long npages;
1496                 int znum;
1497
1498                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1499                         zones_size[znum] = zholes_size[znum] = 0;
1500
1501                 npages = end_pfn - pfn_base;
1502                 zones_size[ZONE_DMA] = npages;
1503                 zholes_size[ZONE_DMA] = npages - pages_avail;
1504
1505                 free_area_init_node(0, &contig_page_data, NULL, zones_size,
1506                                     phys_base >> PAGE_SHIFT, zholes_size);
1507                 mem_map = contig_page_data.node_mem_map;
1508         }
1509
1510         device_scan();
1511 }
1512
1513 /* Ok, it seems that the prom can allocate some more memory chunks
1514  * as a side effect of some prom calls we perform during the
1515  * boot sequence.  My most likely theory is that it is from the
1516  * prom_set_traptable() call, and OBP is allocating a scratchpad
1517  * for saving client program register state etc.
1518  */
1519 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1520 {
1521         int swapi = 0;
1522         int i, mitr;
1523         unsigned long tmpaddr, tmpsize;
1524         unsigned long lowest;
1525
1526         for (i = 0; thislist[i].theres_more != 0; i++) {
1527                 lowest = thislist[i].start_adr;
1528                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1529                         if (thislist[mitr].start_adr < lowest) {
1530                                 lowest = thislist[mitr].start_adr;
1531                                 swapi = mitr;
1532                         }
1533                 if (lowest == thislist[i].start_adr)
1534                         continue;
1535                 tmpaddr = thislist[swapi].start_adr;
1536                 tmpsize = thislist[swapi].num_bytes;
1537                 for (mitr = swapi; mitr > i; mitr--) {
1538                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1539                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1540                 }
1541                 thislist[i].start_adr = tmpaddr;
1542                 thislist[i].num_bytes = tmpsize;
1543         }
1544 }
1545
1546 void __init rescan_sp_banks(void)
1547 {
1548         struct linux_prom64_registers memlist[64];
1549         struct linux_mlist_p1275 avail[64], *mlist;
1550         unsigned long bytes, base_paddr;
1551         int num_regs, node = prom_finddevice("/memory");
1552         int i;
1553
1554         num_regs = prom_getproperty(node, "available",
1555                                     (char *) memlist, sizeof(memlist));
1556         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1557         for (i = 0; i < num_regs; i++) {
1558                 avail[i].start_adr = memlist[i].phys_addr;
1559                 avail[i].num_bytes = memlist[i].reg_size;
1560                 avail[i].theres_more = &avail[i + 1];
1561         }
1562         avail[i - 1].theres_more = NULL;
1563         sort_memlist(avail);
1564
1565         mlist = &avail[0];
1566         i = 0;
1567         bytes = mlist->num_bytes;
1568         base_paddr = mlist->start_adr;
1569
1570         sp_banks[0].base_addr = base_paddr;
1571         sp_banks[0].num_bytes = bytes;
1572
1573         while (mlist->theres_more != NULL){
1574                 i++;
1575                 mlist = mlist->theres_more;
1576                 bytes = mlist->num_bytes;
1577                 if (i >= SPARC_PHYS_BANKS-1) {
1578                         printk ("The machine has more banks than "
1579                                 "this kernel can support\n"
1580                                 "Increase the SPARC_PHYS_BANKS "
1581                                 "setting (currently %d)\n",
1582                                 SPARC_PHYS_BANKS);
1583                         i = SPARC_PHYS_BANKS-1;
1584                         break;
1585                 }
1586
1587                 sp_banks[i].base_addr = mlist->start_adr;
1588                 sp_banks[i].num_bytes = mlist->num_bytes;
1589         }
1590
1591         i++;
1592         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1593         sp_banks[i].num_bytes = 0;
1594
1595         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1596                 sp_banks[i].num_bytes &= PAGE_MASK;
1597 }
1598
1599 static void __init taint_real_pages(void)
1600 {
1601         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1602         int i;
1603
1604         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1605                 saved_sp_banks[i].base_addr =
1606                         sp_banks[i].base_addr;
1607                 saved_sp_banks[i].num_bytes =
1608                         sp_banks[i].num_bytes;
1609         }
1610
1611         rescan_sp_banks();
1612
1613         /* Find changes discovered in the sp_bank rescan and
1614          * reserve the lost portions in the bootmem maps.
1615          */
1616         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1617                 unsigned long old_start, old_end;
1618
1619                 old_start = saved_sp_banks[i].base_addr;
1620                 old_end = old_start +
1621                         saved_sp_banks[i].num_bytes;
1622                 while (old_start < old_end) {
1623                         int n;
1624
1625                         for (n = 0; sp_banks[n].num_bytes; n++) {
1626                                 unsigned long new_start, new_end;
1627
1628                                 new_start = sp_banks[n].base_addr;
1629                                 new_end = new_start + sp_banks[n].num_bytes;
1630
1631                                 if (new_start <= old_start &&
1632                                     new_end >= (old_start + PAGE_SIZE)) {
1633                                         set_bit (old_start >> 22,
1634                                                  sparc64_valid_addr_bitmap);
1635                                         goto do_next_page;
1636                                 }
1637                         }
1638                         reserve_bootmem(old_start, PAGE_SIZE);
1639
1640                 do_next_page:
1641                         old_start += PAGE_SIZE;
1642                 }
1643         }
1644 }
1645
1646 void __init mem_init(void)
1647 {
1648         unsigned long codepages, datapages, initpages;
1649         unsigned long addr, last;
1650         int i;
1651
1652         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1653         i += 1;
1654         sparc64_valid_addr_bitmap = (unsigned long *)
1655                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1656         if (sparc64_valid_addr_bitmap == NULL) {
1657                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1658                 prom_halt();
1659         }
1660         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1661
1662         addr = PAGE_OFFSET + kern_base;
1663         last = PAGE_ALIGN(kern_size) + addr;
1664         while (addr < last) {
1665                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1666                 addr += PAGE_SIZE;
1667         }
1668
1669         taint_real_pages();
1670
1671         max_mapnr = last_valid_pfn - pfn_base;
1672         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1673
1674 #ifdef CONFIG_DEBUG_BOOTMEM
1675         prom_printf("mem_init: Calling free_all_bootmem().\n");
1676 #endif
1677         totalram_pages = num_physpages = free_all_bootmem() - 1;
1678
1679         /*
1680          * Set up the zero page, mark it reserved, so that page count
1681          * is not manipulated when freeing the page from user ptes.
1682          */
1683         mem_map_zero = alloc_pages(GFP_KERNEL, 0);
1684         if (mem_map_zero == NULL) {
1685                 prom_printf("paging_init: Cannot alloc zero page.\n");
1686                 prom_halt();
1687         }
1688         SetPageReserved(mem_map_zero);
1689         clear_page(page_address(mem_map_zero));
1690
1691         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1692         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1693         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1694         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1695         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1696         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1697
1698 #ifndef CONFIG_SMP
1699         {
1700                 /* Put empty_pg_dir on pgd_quicklist */
1701                 extern pgd_t empty_pg_dir[1024];
1702                 unsigned long addr = (unsigned long)empty_pg_dir;
1703                 unsigned long alias_base = kern_base + PAGE_OFFSET -
1704                         (long)(KERNBASE);
1705
1706                 memset(empty_pg_dir, 0, sizeof(empty_pg_dir));
1707                 addr += alias_base;
1708                 free_pgd_fast((pgd_t *)addr);
1709                 num_physpages++;
1710                 totalram_pages++;
1711         }
1712 #endif
1713
1714         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1715                nr_free_pages() << (PAGE_SHIFT-10),
1716                codepages << (PAGE_SHIFT-10),
1717                datapages << (PAGE_SHIFT-10),
1718                initpages << (PAGE_SHIFT-10),
1719                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1720
1721         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1722                 cheetah_ecache_flush_init();
1723 }
1724
1725 void free_initmem (void)
1726 {
1727         unsigned long addr, initend;
1728
1729         /*
1730          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1731          */
1732         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1733         initend = (unsigned long)(__init_end) & PAGE_MASK;
1734         for (; addr < initend; addr += PAGE_SIZE) {
1735                 unsigned long page;
1736                 struct page *p;
1737
1738                 page = (addr +
1739                         ((unsigned long) __va(kern_base)) -
1740                         ((unsigned long) KERNBASE));
1741                 p = virt_to_page(page);
1742
1743                 ClearPageReserved(p);
1744                 set_page_count(p, 1);
1745                 __free_page(p);
1746                 num_physpages++;
1747                 totalram_pages++;
1748         }
1749 }
1750
1751 #ifdef CONFIG_BLK_DEV_INITRD
1752 void free_initrd_mem(unsigned long start, unsigned long end)
1753 {
1754         if (start < end)
1755                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1756         for (; start < end; start += PAGE_SIZE) {
1757                 struct page *p = virt_to_page(start);
1758
1759                 ClearPageReserved(p);
1760                 set_page_count(p, 1);
1761                 __free_page(p);
1762                 num_physpages++;
1763                 totalram_pages++;
1764         }
1765 }
1766 #endif