arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  41
  42 extern void device_scan(void);
  43
  44 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  45
  46 unsigned long *sparc64_valid_addr_bitmap;
  47
  48 /* Ugly, but necessary... -DaveM */
  49 unsigned long phys_base;
  50 unsigned long kern_base;
  51 unsigned long kern_size;
  52 unsigned long pfn_base;
  53
  54 /* This is even uglier. We have a problem where the kernel may not be
  55  * located at phys_base. However, initial __alloc_bootmem() calls need to
  56  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  57  * those page mappings wont work. Things are ok after inherit_prom_mappings
  58  * is called though. Dave says he'll clean this up some other time.
  59  * -- BenC
  60  */
  61 static unsigned long bootmap_base;
  62
  63 /* get_new_mmu_context() uses "cache + 1".  */
  64 spinlock_t ctx_alloc_lock = SPIN_LOCK_UNLOCKED;
  65 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  66 #define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6))
  67 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  68
  69 /* References to special section boundaries */
  70 extern char  _start[], _end[];
  71
  72 /* Initial ramdisk setup */
  73 extern unsigned int sparc_ramdisk_image;
  74 extern unsigned int sparc_ramdisk_size;
  75
  76 struct page *mem_map_zero;
  77
  78 int bigkernel = 0;
  79
  80 /* XXX Tune this... */
  81 #define PGT_CACHE_LOW   25
  82 #define PGT_CACHE_HIGH  50
  83
  84 void check_pgt_cache(void)
  85 {
  86         preempt_disable();
  87         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  88                 do {
  89 #ifdef CONFIG_SMP
  90                         if (pgd_quicklist)
  91                                 free_pgd_slow(get_pgd_fast());
  92 #endif
  93                         if (pte_quicklist[0])
  94                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  95                         if (pte_quicklist[1])
  96                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  97                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  98         }
  99 #ifndef CONFIG_SMP
 100         if (pgd_cache_size > PGT_CACHE_HIGH / 4) {
 101                 struct page *page, *page2;
 102                 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
 103                         if ((unsigned long)page->lru.prev == 3) {
 104                                 if (page2)
 105                                         page2->lru.next = page->lru.next;
 106                                 else
 107                                         pgd_quicklist = (void *) page->lru.next;
 108                                 pgd_cache_size -= 2;
 109                                 __free_page(page);
 110                                 if (page2)
 111                                         page = (struct page *)page2->lru.next;
 112                                 else
 113                                         page = (struct page *)pgd_quicklist;
 114                                 if (pgd_cache_size <= PGT_CACHE_LOW / 4)
 115                                         break;
 116                                 continue;
 117                         }
 118                         page2 = page;
 119                         page = (struct page *)page->lru.next;
 120                 }
 121         }
 122 #endif
 123         preempt_enable();
 124 }
 125
 126 #ifdef CONFIG_DEBUG_DCFLUSH
 127 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 128 #ifdef CONFIG_SMP
 129 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 130 #endif
 131 #endif
 132
 133 __inline__ void flush_dcache_page_impl(struct page *page)
 134 {
 135 #ifdef CONFIG_DEBUG_DCFLUSH
 136         atomic_inc(&dcpage_flushes);
 137 #endif
 138
 139 #if (L1DCACHE_SIZE > PAGE_SIZE)
 140         __flush_dcache_page(page_address(page),
 141                             ((tlb_type == spitfire) &&
 142                              page_mapping(page) != NULL));
 143 #else
 144         if (page_mapping(page) != NULL &&
 145             tlb_type == spitfire)
 146                 __flush_icache_page(__pa(page_address(page)));
 147 #endif
 148 }
 149
 150 #define PG_dcache_dirty         PG_arch_1
 151
 152 #define dcache_dirty_cpu(page) \
 153         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 154
 155 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 156 {
 157         unsigned long mask = this_cpu;
 158         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 159         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 160         __asm__ __volatile__("1:\n\t"
 161                              "ldx       [%2], %%g7\n\t"
 162                              "and       %%g7, %1, %%g5\n\t"
 163                              "or        %%g5, %0, %%g5\n\t"
 164                              "casx      [%2], %%g7, %%g5\n\t"
 165                              "cmp       %%g7, %%g5\n\t"
 166                              "bne,pn    %%xcc, 1b\n\t"
 167                              " membar   #StoreLoad | #StoreStore"
 168                              : /* no outputs */
 169                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 170                              : "g5", "g7");
 171 }
 172
 173 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 174 {
 175         unsigned long mask = (1UL << PG_dcache_dirty);
 176
 177         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 178                              "1:\n\t"
 179                              "ldx       [%2], %%g7\n\t"
 180                              "srlx      %%g7, 24, %%g5\n\t"
 181                              "and       %%g5, %3, %%g5\n\t"
 182                              "cmp       %%g5, %0\n\t"
 183                              "bne,pn    %%icc, 2f\n\t"
 184                              " andn     %%g7, %1, %%g5\n\t"
 185                              "casx      [%2], %%g7, %%g5\n\t"
 186                              "cmp       %%g7, %%g5\n\t"
 187                              "bne,pn    %%xcc, 1b\n\t"
 188                              " membar   #StoreLoad | #StoreStore\n"
 189                              "2:"
 190                              : /* no outputs */
 191                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 192                                "i" (NR_CPUS - 1UL)
 193                              : "g5", "g7");
 194 }
 195
 196 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 197
 198 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 199 {
 200         struct page *page;
 201         unsigned long pfn;
 202         unsigned long pg_flags;
 203
 204         pfn = pte_pfn(pte);
 205         if (pfn_valid(pfn) &&
 206             (page = pfn_to_page(pfn), page_mapping(page)) &&
 207             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 208                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 209                 int this_cpu = get_cpu();
 210
 211                 /* This is just to optimize away some function calls
 212                  * in the SMP case.
 213                  */
 214                 if (cpu == this_cpu)
 215                         flush_dcache_page_impl(page);
 216                 else
 217                         smp_flush_dcache_page_impl(page, cpu);
 218
 219                 clear_dcache_dirty_cpu(page, cpu);
 220
 221                 put_cpu();
 222         }
 223         if (get_thread_fault_code())
 224                 __update_mmu_cache(vma->vm_mm->context & TAG_CONTEXT_BITS,
 225                                    address, pte, get_thread_fault_code());
 226 }
 227
 228 void flush_dcache_page(struct page *page)
 229 {
 230         struct address_space *mapping = page_mapping(page);
 231         int dirty = test_bit(PG_dcache_dirty, &page->flags);
 232         int dirty_cpu = dcache_dirty_cpu(page);
 233         int this_cpu = get_cpu();
 234
 235         if (mapping && !mapping_mapped(mapping)) {
 236                 if (dirty) {
 237                         if (dirty_cpu == this_cpu)
 238                                 goto out;
 239                         smp_flush_dcache_page_impl(page, dirty_cpu);
 240                 }
 241                 set_dcache_dirty(page, this_cpu);
 242         } else {
 243                 /* We could delay the flush for the !page_mapping
 244                  * case too.  But that case is for exec env/arg
 245                  * pages and those are %99 certainly going to get
 246                  * faulted into the tlb (and thus flushed) anyways.
 247                  */
 248                 flush_dcache_page_impl(page);
 249         }
 250
 251 out:
 252         put_cpu();
 253 }
 254
 255 /* When shared+writable mmaps of files go away, we lose all dirty
 256  * page state, so we have to deal with D-cache aliasing here.
 257  *
 258  * This code relies on the fact that flush_cache_range() is always
 259  * called for an area composed by a single VMA.  It also assumes that
 260  * the MM's page_table_lock is held.
 261  */
 262 static inline void flush_cache_pte_range(struct mm_struct *mm, pmd_t *pmd, unsigned long address, unsigned long size)
 263 {
 264         unsigned long offset;
 265         pte_t *ptep;
 266
 267         if (pmd_none(*pmd))
 268                 return;
 269         ptep = pte_offset_map(pmd, address);
 270         offset = address & ~PMD_MASK;
 271         if (offset + size > PMD_SIZE)
 272                 size = PMD_SIZE - offset;
 273         size &= PAGE_MASK;
 274         for (offset = 0; offset < size; ptep++, offset += PAGE_SIZE) {
 275                 pte_t pte = *ptep;
 276
 277                 if (pte_none(pte))
 278                         continue;
 279
 280                 if (pte_present(pte) && pte_dirty(pte)) {
 281                         struct page *page;
 282                         unsigned long pgaddr, uaddr;
 283                         unsigned long pfn = pte_pfn(pte);
 284
 285                         if (!pfn_valid(pfn))
 286                                 continue;
 287                         page = pfn_to_page(pfn);
 288                         if (PageReserved(page) || !page_mapping(page))
 289                                 continue;
 290                         pgaddr = (unsigned long) page_address(page);
 291                         uaddr = address + offset;
 292                         if ((pgaddr ^ uaddr) & (1 << 13))
 293                                 flush_dcache_page_all(mm, page);
 294                 }
 295         }
 296         pte_unmap(ptep - 1);
 297 }
 298
 299 static inline void flush_cache_pmd_range(struct mm_struct *mm, pgd_t *dir, unsigned long address, unsigned long size)
 300 {
 301         pmd_t *pmd;
 302         unsigned long end;
 303
 304         if (pgd_none(*dir))
 305                 return;
 306         pmd = pmd_offset(dir, address);
 307         end = address + size;
 308         if (end > ((address + PGDIR_SIZE) & PGDIR_MASK))
 309                 end = ((address + PGDIR_SIZE) & PGDIR_MASK);
 310         do {
 311                 flush_cache_pte_range(mm, pmd, address, end - address);
 312                 address = (address + PMD_SIZE) & PMD_MASK;
 313                 pmd++;
 314         } while (address < end);
 315 }
 316
 317 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 318 {
 319         struct mm_struct *mm = vma->vm_mm;
 320         pgd_t *dir = pgd_offset(mm, start);
 321
 322         if (mm == current->mm)
 323                 flushw_user();
 324
 325         if (vma->vm_file == NULL ||
 326             ((vma->vm_flags & (VM_SHARED|VM_WRITE)) != (VM_SHARED|VM_WRITE)))
 327                 return;
 328
 329         do {
 330                 flush_cache_pmd_range(mm, dir, start, end - start);
 331                 start = (start + PGDIR_SIZE) & PGDIR_MASK;
 332                 dir++;
 333         } while (start && (start < end));
 334 }
 335
 336 void flush_icache_range(unsigned long start, unsigned long end)
 337 {
 338         /* Cheetah has coherent I-cache. */
 339         if (tlb_type == spitfire) {
 340                 unsigned long kaddr;
 341
 342                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 343                         __flush_icache_page(__get_phys(kaddr));
 344         }
 345 }
 346
 347 unsigned long page_to_pfn(struct page *page)
 348 {
 349         return (unsigned long) ((page - mem_map) + pfn_base);
 350 }
 351
 352 struct page *pfn_to_page(unsigned long pfn)
 353 {
 354         return (mem_map + (pfn - pfn_base));
 355 }
 356
 357 void show_mem(void)
 358 {
 359         printk("Mem-info:\n");
 360         show_free_areas();
 361         printk("Free swap:       %6ldkB\n",
 362                nr_swap_pages << (PAGE_SHIFT-10));
 363         printk("%ld pages of RAM\n", num_physpages);
 364         printk("%d free pages\n", nr_free_pages());
 365         printk("%d pages in page table cache\n",pgtable_cache_size);
 366 #ifndef CONFIG_SMP
 367         printk("%d entries in page dir cache\n",pgd_cache_size);
 368 #endif
 369 }
 370
 371 void mmu_info(struct seq_file *m)
 372 {
 373         if (tlb_type == cheetah)
 374                 seq_printf(m, "MMU Type\t: Cheetah\n");
 375         else if (tlb_type == cheetah_plus)
 376                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 377         else if (tlb_type == spitfire)
 378                 seq_printf(m, "MMU Type\t: Spitfire\n");
 379         else
 380                 seq_printf(m, "MMU Type\t: ???\n");
 381
 382 #ifdef CONFIG_DEBUG_DCFLUSH
 383         seq_printf(m, "DCPageFlushes\t: %d\n",
 384                    atomic_read(&dcpage_flushes));
 385 #ifdef CONFIG_SMP
 386         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 387                    atomic_read(&dcpage_flushes_xcall));
 388 #endif /* CONFIG_SMP */
 389 #endif /* CONFIG_DEBUG_DCFLUSH */
 390 }
 391
 392 struct linux_prom_translation {
 393         unsigned long virt;
 394         unsigned long size;
 395         unsigned long data;
 396 };
 397
 398 extern unsigned long prom_boot_page;
 399 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 400 extern int prom_get_mmu_ihandle(void);
 401 extern void register_prom_callbacks(void);
 402
 403 /* Exported for SMP bootup purposes. */
 404 unsigned long kern_locked_tte_data;
 405
 406 void __init early_pgtable_allocfail(char *type)
 407 {
 408         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 409         prom_halt();
 410 }
 411
 412 #define BASE_PAGE_SIZE 8192
 413 static pmd_t *prompmd;
 414
 415 /*
 416  * Translate PROM's mapping we capture at boot time into physical address.
 417  * The second parameter is only set from prom_callback() invocations.
 418  */
 419 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 420 {
 421         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 422         pte_t *ptep;
 423         unsigned long base;
 424
 425         if (pmd_none(*pmdp)) {
 426                 if (error)
 427                         *error = 1;
 428                 return(0);
 429         }
 430         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 431         if (!pte_present(*ptep)) {
 432                 if (error)
 433                         *error = 1;
 434                 return(0);
 435         }
 436         if (error) {
 437                 *error = 0;
 438                 return(pte_val(*ptep));
 439         }
 440         base = pte_val(*ptep) & _PAGE_PADDR;
 441         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 442 }
 443
 444 static void inherit_prom_mappings(void)
 445 {
 446         struct linux_prom_translation *trans;
 447         unsigned long phys_page, tte_vaddr, tte_data;
 448         void (*remap_func)(unsigned long, unsigned long, int);
 449         pmd_t *pmdp;
 450         pte_t *ptep;
 451         int node, n, i, tsz;
 452         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 453
 454         node = prom_finddevice("/virtual-memory");
 455         n = prom_getproplen(node, "translations");
 456         if (n == 0 || n == -1) {
 457                 prom_printf("Couldn't get translation property\n");
 458                 prom_halt();
 459         }
 460         n += 5 * sizeof(struct linux_prom_translation);
 461         for (tsz = 1; tsz < n; tsz <<= 1)
 462                 /* empty */;
 463         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 464         if (trans == NULL) {
 465                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 466                 prom_halt();
 467         }
 468         memset(trans, 0, tsz);
 469
 470         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 471                 prom_printf("Couldn't get translation property\n");
 472                 prom_halt();
 473         }
 474         n = n / sizeof(*trans);
 475
 476         /*
 477          * The obp translations are saved based on 8k pagesize, since obp can use
 478          * a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, ie obp
 479          * range, are handled in entry.S and do not use the vpte scheme (see rant
 480          * in inherit_locked_prom_mappings()).
 481          */
 482 #define OBP_PMD_SIZE 2048
 483         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 484         if (prompmd == NULL)
 485                 early_pgtable_allocfail("pmd");
 486         memset(prompmd, 0, OBP_PMD_SIZE);
 487         for (i = 0; i < n; i++) {
 488                 unsigned long vaddr;
 489
 490                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 491                         for (vaddr = trans[i].virt;
 492                              ((vaddr < trans[i].virt + trans[i].size) &&
 493                              (vaddr < HI_OBP_ADDRESS));
 494                              vaddr += BASE_PAGE_SIZE) {
 495                                 unsigned long val;
 496
 497                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 498                                 if (pmd_none(*pmdp)) {
 499                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 500                                                                BASE_PAGE_SIZE,
 501                                                                bootmap_base);
 502                                         if (ptep == NULL)
 503                                                 early_pgtable_allocfail("pte");
 504                                         memset(ptep, 0, BASE_PAGE_SIZE);
 505                                         pmd_set(pmdp, ptep);
 506                                 }
 507                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 508                                                 ((vaddr >> 13) & 0x3ff);
 509
 510                                 val = trans[i].data;
 511
 512                                 /* Clear diag TTE bits. */
 513                                 if (tlb_type == spitfire)
 514                                         val &= ~0x0003fe0000000000UL;
 515
 516                                 set_pte (ptep, __pte(val | _PAGE_MODIFIED));
 517                                 trans[i].data += BASE_PAGE_SIZE;
 518                         }
 519                 }
 520         }
 521         phys_page = __pa(prompmd);
 522         obp_iaddr_patch[0] |= (phys_page >> 10);
 523         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 524         flushi((long)&obp_iaddr_patch[0]);
 525         obp_daddr_patch[0] |= (phys_page >> 10);
 526         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 527         flushi((long)&obp_daddr_patch[0]);
 528
 529         /* Now fixup OBP's idea about where we really are mapped. */
 530         prom_printf("Remapping the kernel... ");
 531
 532         /* Spitfire Errata #32 workaround */
 533         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 534                              "flush     %%g6"
 535                              : /* No outputs */
 536                              : "r" (0),
 537                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 538
 539         switch (tlb_type) {
 540         default:
 541         case spitfire:
 542                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 543                 break;
 544
 545         case cheetah:
 546         case cheetah_plus:
 547                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 548                 break;
 549         };
 550
 551         phys_page &= _PAGE_PADDR;
 552         phys_page += ((unsigned long)&prom_boot_page -
 553                       (unsigned long)KERNBASE);
 554
 555         if (tlb_type == spitfire) {
 556                 /* Lock this into i/d tlb entry 59 */
 557                 __asm__ __volatile__(
 558                         "stxa   %%g0, [%2] %3\n\t"
 559                         "stxa   %0, [%1] %4\n\t"
 560                         "membar #Sync\n\t"
 561                         "flush  %%g6\n\t"
 562                         "stxa   %%g0, [%2] %5\n\t"
 563                         "stxa   %0, [%1] %6\n\t"
 564                         "membar #Sync\n\t"
 565                         "flush  %%g6"
 566                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 567                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 568                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 569                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 570                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 571                         : "memory");
 572         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 573                 /* Lock this into i/d tlb-0 entry 11 */
 574                 __asm__ __volatile__(
 575                         "stxa   %%g0, [%2] %3\n\t"
 576                         "stxa   %0, [%1] %4\n\t"
 577                         "membar #Sync\n\t"
 578                         "flush  %%g6\n\t"
 579                         "stxa   %%g0, [%2] %5\n\t"
 580                         "stxa   %0, [%1] %6\n\t"
 581                         "membar #Sync\n\t"
 582                         "flush  %%g6"
 583                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 584                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 585                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 586                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 587                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 588                         : "memory");
 589         } else {
 590                 /* Implement me :-) */
 591                 BUG();
 592         }
 593
 594         tte_vaddr = (unsigned long) KERNBASE;
 595
 596         /* Spitfire Errata #32 workaround */
 597         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 598                              "flush     %%g6"
 599                              : /* No outputs */
 600                              : "r" (0),
 601                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 602
 603         if (tlb_type == spitfire)
 604                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 605         else
 606                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 607
 608         kern_locked_tte_data = tte_data;
 609
 610         remap_func = (void *)  ((unsigned long) &prom_remap -
 611                                 (unsigned long) &prom_boot_page);
 612
 613
 614         /* Spitfire Errata #32 workaround */
 615         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 616                              "flush     %%g6"
 617                              : /* No outputs */
 618                              : "r" (0),
 619                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 620
 621         remap_func((tlb_type == spitfire ?
 622                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 623                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 624                    (unsigned long) KERNBASE,
 625                    prom_get_mmu_ihandle());
 626
 627         if (bigkernel)
 628                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 629                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 630
 631         /* Flush out that temporary mapping. */
 632         spitfire_flush_dtlb_nucleus_page(0x0);
 633         spitfire_flush_itlb_nucleus_page(0x0);
 634
 635         /* Now lock us back into the TLBs via OBP. */
 636         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 637         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 638         if (bigkernel) {
 639                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 640                                                                 tte_vaddr + 0x400000);
 641                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 642                                                                 tte_vaddr + 0x400000);
 643         }
 644
 645         /* Re-read translations property. */
 646         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 647                 prom_printf("Couldn't get translation property\n");
 648                 prom_halt();
 649         }
 650         n = n / sizeof(*trans);
 651
 652         for (i = 0; i < n; i++) {
 653                 unsigned long vaddr = trans[i].virt;
 654                 unsigned long size = trans[i].size;
 655
 656                 if (vaddr < 0xf0000000UL) {
 657                         unsigned long avoid_start = (unsigned long) KERNBASE;
 658                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 659
 660                         if (bigkernel)
 661                                 avoid_end += (4 * 1024 * 1024);
 662                         if (vaddr < avoid_start) {
 663                                 unsigned long top = vaddr + size;
 664
 665                                 if (top > avoid_start)
 666                                         top = avoid_start;
 667                                 prom_unmap(top - vaddr, vaddr);
 668                         }
 669                         if ((vaddr + size) > avoid_end) {
 670                                 unsigned long bottom = vaddr;
 671
 672                                 if (bottom < avoid_end)
 673                                         bottom = avoid_end;
 674                                 prom_unmap((vaddr + size) - bottom, bottom);
 675                         }
 676                 }
 677         }
 678
 679         prom_printf("done.\n");
 680
 681         register_prom_callbacks();
 682 }
 683
 684 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 685  * upwards as reserved for use by the firmware (I wonder if this
 686  * will be the same on Cheetah...).  We use this virtual address
 687  * range for the VPTE table mappings of the nucleus so we need
 688  * to zap them when we enter the PROM.  -DaveM
 689  */
 690 static void __flush_nucleus_vptes(void)
 691 {
 692         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 693         int i;
 694
 695         /* Only DTLB must be checked for VPTE entries. */
 696         if (tlb_type == spitfire) {
 697                 for (i = 0; i < 63; i++) {
 698                         unsigned long tag;
 699
 700                         /* Spitfire Errata #32 workaround */
 701                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 702                                              "flush     %%g6"
 703                                              : /* No outputs */
 704                                              : "r" (0),
 705                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 706
 707                         tag = spitfire_get_dtlb_tag(i);
 708                         if (((tag & ~(PAGE_MASK)) == 0) &&
 709                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 710                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 711                                                      "membar #Sync"
 712                                                      : /* no outputs */
 713                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 714                                 spitfire_put_dtlb_data(i, 0x0UL);
 715                         }
 716                 }
 717         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 718                 for (i = 0; i < 512; i++) {
 719                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 720
 721                         if ((tag & ~PAGE_MASK) == 0 &&
 722                             (tag & PAGE_MASK) >= prom_reserved_base) {
 723                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 724                                                      "membar #Sync"
 725                                                      : /* no outputs */
 726                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 727                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 728                         }
 729
 730                         if (tlb_type != cheetah_plus)
 731                                 continue;
 732
 733                         tag = cheetah_get_dtlb_tag(i, 3);
 734
 735                         if ((tag & ~PAGE_MASK) == 0 &&
 736                             (tag & PAGE_MASK) >= prom_reserved_base) {
 737                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 738                                                      "membar #Sync"
 739                                                      : /* no outputs */
 740                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 741                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 742                         }
 743                 }
 744         } else {
 745                 /* Implement me :-) */
 746                 BUG();
 747         }
 748 }
 749
 750 static int prom_ditlb_set;
 751 struct prom_tlb_entry {
 752         int             tlb_ent;
 753         unsigned long   tlb_tag;
 754         unsigned long   tlb_data;
 755 };
 756 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 757
 758 void prom_world(int enter)
 759 {
 760         unsigned long pstate;
 761         int i;
 762
 763         if (!enter)
 764                 set_fs((mm_segment_t) { get_thread_current_ds() });
 765
 766         if (!prom_ditlb_set)
 767                 return;
 768
 769         /* Make sure the following runs atomically. */
 770         __asm__ __volatile__("flushw\n\t"
 771                              "rdpr      %%pstate, %0\n\t"
 772                              "wrpr      %0, %1, %%pstate"
 773                              : "=r" (pstate)
 774                              : "i" (PSTATE_IE));
 775
 776         if (enter) {
 777                 /* Kick out nucleus VPTEs. */
 778                 __flush_nucleus_vptes();
 779
 780                 /* Install PROM world. */
 781                 for (i = 0; i < 16; i++) {
 782                         if (prom_dtlb[i].tlb_ent != -1) {
 783                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 784                                                      "membar #Sync"
 785                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 786                                         "i" (ASI_DMMU));
 787                                 if (tlb_type == spitfire)
 788                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 789                                                                prom_dtlb[i].tlb_data);
 790                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 791                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 792                                                                prom_dtlb[i].tlb_data);
 793                         }
 794                         if (prom_itlb[i].tlb_ent != -1) {
 795                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 796                                                      "membar #Sync"
 797                                                      : : "r" (prom_itlb[i].tlb_tag),
 798                                                      "r" (TLB_TAG_ACCESS),
 799                                                      "i" (ASI_IMMU));
 800                                 if (tlb_type == spitfire)
 801                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 802                                                                prom_itlb[i].tlb_data);
 803                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 804                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 805                                                                prom_itlb[i].tlb_data);
 806                         }
 807                 }
 808         } else {
 809                 for (i = 0; i < 16; i++) {
 810                         if (prom_dtlb[i].tlb_ent != -1) {
 811                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 812                                                      "membar #Sync"
 813                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 814                                 if (tlb_type == spitfire)
 815                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 816                                 else
 817                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 818                         }
 819                         if (prom_itlb[i].tlb_ent != -1) {
 820                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 821                                                      "membar #Sync"
 822                                                      : : "r" (TLB_TAG_ACCESS),
 823                                                      "i" (ASI_IMMU));
 824                                 if (tlb_type == spitfire)
 825                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 826                                 else
 827                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 828                         }
 829                 }
 830         }
 831         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 832                              : : "r" (pstate));
 833 }
 834
 835 void inherit_locked_prom_mappings(int save_p)
 836 {
 837         int i;
 838         int dtlb_seen = 0;
 839         int itlb_seen = 0;
 840
 841         /* Fucking losing PROM has more mappings in the TLB, but
 842          * it (conveniently) fails to mention any of these in the
 843          * translations property.  The only ones that matter are
 844          * the locked PROM tlb entries, so we impose the following
 845          * irrecovable rule on the PROM, it is allowed 8 locked
 846          * entries in the ITLB and 8 in the DTLB.
 847          *
 848          * Supposedly the upper 16GB of the address space is
 849          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 850          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 851          * used between the client program and the firmware on sun5
 852          * systems to coordinate mmu mappings is also COMPLETELY
 853          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 854          */
 855         if (save_p) {
 856                 for (i = 0; i < 16; i++) {
 857                         prom_itlb[i].tlb_ent = -1;
 858                         prom_dtlb[i].tlb_ent = -1;
 859                 }
 860         }
 861         if (tlb_type == spitfire) {
 862                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 863                 for (i = 0; i < high; i++) {
 864                         unsigned long data;
 865
 866                         /* Spitfire Errata #32 workaround */
 867                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 868                                              "flush     %%g6"
 869                                              : /* No outputs */
 870                                              : "r" (0),
 871                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 872
 873                         data = spitfire_get_dtlb_data(i);
 874                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 875                                 unsigned long tag;
 876
 877                                 /* Spitfire Errata #32 workaround */
 878                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 879                                                      "flush     %%g6"
 880                                                      : /* No outputs */
 881                                                      : "r" (0),
 882                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 883
 884                                 tag = spitfire_get_dtlb_tag(i);
 885                                 if (save_p) {
 886                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 887                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 888                                         prom_dtlb[dtlb_seen].tlb_data = data;
 889                                 }
 890                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 891                                                      "membar #Sync"
 892                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 893                                 spitfire_put_dtlb_data(i, 0x0UL);
 894
 895                                 dtlb_seen++;
 896                                 if (dtlb_seen > 15)
 897                                         break;
 898                         }
 899                 }
 900
 901                 for (i = 0; i < high; i++) {
 902                         unsigned long data;
 903
 904                         /* Spitfire Errata #32 workaround */
 905                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 906                                              "flush     %%g6"
 907                                              : /* No outputs */
 908                                              : "r" (0),
 909                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 910
 911                         data = spitfire_get_itlb_data(i);
 912                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 913                                 unsigned long tag;
 914
 915                                 /* Spitfire Errata #32 workaround */
 916                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 917                                                      "flush     %%g6"
 918                                                      : /* No outputs */
 919                                                      : "r" (0),
 920                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 921
 922                                 tag = spitfire_get_itlb_tag(i);
 923                                 if (save_p) {
 924                                         prom_itlb[itlb_seen].tlb_ent = i;
 925                                         prom_itlb[itlb_seen].tlb_tag = tag;
 926                                         prom_itlb[itlb_seen].tlb_data = data;
 927                                 }
 928                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 929                                                      "membar #Sync"
 930                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 931                                 spitfire_put_itlb_data(i, 0x0UL);
 932
 933                                 itlb_seen++;
 934                                 if (itlb_seen > 15)
 935                                         break;
 936                         }
 937                 }
 938         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 939                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 940
 941                 for (i = 0; i < high; i++) {
 942                         unsigned long data;
 943
 944                         data = cheetah_get_ldtlb_data(i);
 945                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 946                                 unsigned long tag;
 947
 948                                 tag = cheetah_get_ldtlb_tag(i);
 949                                 if (save_p) {
 950                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 951                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 952                                         prom_dtlb[dtlb_seen].tlb_data = data;
 953                                 }
 954                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 955                                                      "membar #Sync"
 956                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 957                                 cheetah_put_ldtlb_data(i, 0x0UL);
 958
 959                                 dtlb_seen++;
 960                                 if (dtlb_seen > 15)
 961                                         break;
 962                         }
 963                 }
 964
 965                 for (i = 0; i < high; i++) {
 966                         unsigned long data;
 967
 968                         data = cheetah_get_litlb_data(i);
 969                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 970                                 unsigned long tag;
 971
 972                                 tag = cheetah_get_litlb_tag(i);
 973                                 if (save_p) {
 974                                         prom_itlb[itlb_seen].tlb_ent = i;
 975                                         prom_itlb[itlb_seen].tlb_tag = tag;
 976                                         prom_itlb[itlb_seen].tlb_data = data;
 977                                 }
 978                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 979                                                      "membar #Sync"
 980                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 981                                 cheetah_put_litlb_data(i, 0x0UL);
 982
 983                                 itlb_seen++;
 984                                 if (itlb_seen > 15)
 985                                         break;
 986                         }
 987                 }
 988         } else {
 989                 /* Implement me :-) */
 990                 BUG();
 991         }
 992         if (save_p)
 993                 prom_ditlb_set = 1;
 994 }
 995
 996 /* Give PROM back his world, done during reboots... */
 997 void prom_reload_locked(void)
 998 {
 999         int i;
1000
1001         for (i = 0; i < 16; i++) {
1002                 if (prom_dtlb[i].tlb_ent != -1) {
1003                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1004                                              "membar #Sync"
1005                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
1006                                 "i" (ASI_DMMU));
1007                         if (tlb_type == spitfire)
1008                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
1009                                                        prom_dtlb[i].tlb_data);
1010                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1011                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
1012                                                       prom_dtlb[i].tlb_data);
1013                 }
1014
1015                 if (prom_itlb[i].tlb_ent != -1) {
1016                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1017                                              "membar #Sync"
1018                                              : : "r" (prom_itlb[i].tlb_tag),
1019                                              "r" (TLB_TAG_ACCESS),
1020                                              "i" (ASI_IMMU));
1021                         if (tlb_type == spitfire)
1022                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
1023                                                        prom_itlb[i].tlb_data);
1024                         else
1025                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
1026                                                        prom_itlb[i].tlb_data);
1027                 }
1028         }
1029 }
1030
1031 void __flush_dcache_range(unsigned long start, unsigned long end)
1032 {
1033         unsigned long va;
1034
1035         if (tlb_type == spitfire) {
1036                 int n = 0;
1037
1038                 for (va = start; va < end; va += 32) {
1039                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
1040                         if (++n >= 512)
1041                                 break;
1042                 }
1043         } else {
1044                 start = __pa(start);
1045                 end = __pa(end);
1046                 for (va = start; va < end; va += 32)
1047                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1048                                              "membar #Sync"
1049                                              : /* no outputs */
1050                                              : "r" (va),
1051                                                "i" (ASI_DCACHE_INVALIDATE));
1052         }
1053 }
1054
1055 /* If not locked, zap it. */
1056 void __flush_tlb_all(void)
1057 {
1058         unsigned long pstate;
1059         int i;
1060
1061         __asm__ __volatile__("flushw\n\t"
1062                              "rdpr      %%pstate, %0\n\t"
1063                              "wrpr      %0, %1, %%pstate"
1064                              : "=r" (pstate)
1065                              : "i" (PSTATE_IE));
1066         if (tlb_type == spitfire) {
1067                 for (i = 0; i < 64; i++) {
1068                         /* Spitfire Errata #32 workaround */
1069                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1070                                              "flush     %%g6"
1071                                              : /* No outputs */
1072                                              : "r" (0),
1073                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1074
1075                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1076                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1077                                                      "membar #Sync"
1078                                                      : /* no outputs */
1079                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1080                                 spitfire_put_dtlb_data(i, 0x0UL);
1081                         }
1082
1083                         /* Spitfire Errata #32 workaround */
1084                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1085                                              "flush     %%g6"
1086                                              : /* No outputs */
1087                                              : "r" (0),
1088                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1089
1090                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1091                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1092                                                      "membar #Sync"
1093                                                      : /* no outputs */
1094                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1095                                 spitfire_put_itlb_data(i, 0x0UL);
1096                         }
1097                 }
1098         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1099                 cheetah_flush_dtlb_all();
1100                 cheetah_flush_itlb_all();
1101         }
1102         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1103                              : : "r" (pstate));
1104 }
1105
1106 /* Caller does TLB context flushing on local CPU if necessary.
1107  * The caller also ensures that CTX_VALID(mm->context) is false.
1108  *
1109  * We must be careful about boundary cases so that we never
1110  * let the user have CTX 0 (nucleus) or we ever use a CTX
1111  * version of zero (and thus NO_CONTEXT would not be caught
1112  * by version mis-match tests in mmu_context.h).
1113  */
1114 void get_new_mmu_context(struct mm_struct *mm)
1115 {
1116         unsigned long ctx, new_ctx;
1117
1118         spin_lock(&ctx_alloc_lock);
1119         ctx = CTX_HWBITS(tlb_context_cache + 1);
1120         new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx);
1121         if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) {
1122                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1123                 if (new_ctx >= ctx) {
1124                         int i;
1125                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1126                                 CTX_FIRST_VERSION;
1127                         if (new_ctx == 1)
1128                                 new_ctx = CTX_FIRST_VERSION;
1129
1130                         /* Don't call memset, for 16 entries that's just
1131                          * plain silly...
1132                          */
1133                         mmu_context_bmap[0] = 3;
1134                         mmu_context_bmap[1] = 0;
1135                         mmu_context_bmap[2] = 0;
1136                         mmu_context_bmap[3] = 0;
1137                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1138                                 mmu_context_bmap[i + 0] = 0;
1139                                 mmu_context_bmap[i + 1] = 0;
1140                                 mmu_context_bmap[i + 2] = 0;
1141                                 mmu_context_bmap[i + 3] = 0;
1142                         }
1143                         goto out;
1144                 }
1145         }
1146         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1147         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1148 out:
1149         tlb_context_cache = new_ctx;
1150         spin_unlock(&ctx_alloc_lock);
1151
1152         mm->context = new_ctx;
1153 }
1154
1155 #ifndef CONFIG_SMP
1156 struct pgtable_cache_struct pgt_quicklists;
1157 #endif
1158
1159 /* OK, we have to color these pages. The page tables are accessed
1160  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1161  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1162  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1163  * fast handlers do not get data from old/garbage dcache lines that
1164  * correspond to an old/stale virtual address (user/kernel) that
1165  * previously mapped the pagetable page while accessing vpte range
1166  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1167  * color is the same, then when the kernel initializes the pagetable
1168  * using the later address range, accesses with the first address
1169  * range will see the newly initialized data rather than the garbage.
1170  */
1171 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1172 #define DC_ALIAS_SHIFT  1
1173 #else
1174 #define DC_ALIAS_SHIFT  0
1175 #endif
1176 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1177 {
1178         struct page *page;
1179         unsigned long color;
1180
1181         {
1182                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1183
1184                 if (ptep)
1185                         return ptep;
1186         }
1187
1188         color = VPTE_COLOR(address);
1189         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1190         if (page) {
1191                 unsigned long *to_free;
1192                 unsigned long paddr;
1193                 pte_t *pte;
1194
1195 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1196                 set_page_count(page, 1);
1197                 ClearPageCompound(page);
1198
1199                 set_page_count((page + 1), 1);
1200                 ClearPageCompound(page + 1);
1201 #endif
1202                 paddr = (unsigned long) page_address(page);
1203                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1204
1205                 if (!color) {
1206                         pte = (pte_t *) paddr;
1207                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1208                 } else {
1209                         pte = (pte_t *) (paddr + PAGE_SIZE);
1210                         to_free = (unsigned long *) paddr;
1211                 }
1212
1213 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1214                 /* Now free the other one up, adjust cache size. */
1215                 preempt_disable();
1216                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1217                 pte_quicklist[color ^ 0x1] = to_free;
1218                 pgtable_cache_size++;
1219                 preempt_enable();
1220 #endif
1221
1222                 return pte;
1223         }
1224         return NULL;
1225 }
1226
1227 void sparc_ultra_dump_itlb(void)
1228 {
1229         int slot;
1230
1231         if (tlb_type == spitfire) {
1232                 printk ("Contents of itlb: ");
1233                 for (slot = 0; slot < 14; slot++) printk ("    ");
1234                 printk ("%2x:%016lx,%016lx\n",
1235                         0,
1236                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1237                 for (slot = 1; slot < 64; slot+=3) {
1238                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1239                                 slot,
1240                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1241                                 slot+1,
1242                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1243                                 slot+2,
1244                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1245                 }
1246         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1247                 printk ("Contents of itlb0:\n");
1248                 for (slot = 0; slot < 16; slot+=2) {
1249                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1250                                 slot,
1251                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1252                                 slot+1,
1253                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1254                 }
1255                 printk ("Contents of itlb2:\n");
1256                 for (slot = 0; slot < 128; slot+=2) {
1257                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1258                                 slot,
1259                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1260                                 slot+1,
1261                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1262                 }
1263         }
1264 }
1265
1266 void sparc_ultra_dump_dtlb(void)
1267 {
1268         int slot;
1269
1270         if (tlb_type == spitfire) {
1271                 printk ("Contents of dtlb: ");
1272                 for (slot = 0; slot < 14; slot++) printk ("    ");
1273                 printk ("%2x:%016lx,%016lx\n", 0,
1274                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1275                 for (slot = 1; slot < 64; slot+=3) {
1276                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1277                                 slot,
1278                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1279                                 slot+1,
1280                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1281                                 slot+2,
1282                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1283                 }
1284         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1285                 printk ("Contents of dtlb0:\n");
1286                 for (slot = 0; slot < 16; slot+=2) {
1287                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1288                                 slot,
1289                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1290                                 slot+1,
1291                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1292                 }
1293                 printk ("Contents of dtlb2:\n");
1294                 for (slot = 0; slot < 512; slot+=2) {
1295                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1296                                 slot,
1297                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1298                                 slot+1,
1299                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1300                 }
1301                 if (tlb_type == cheetah_plus) {
1302                         printk ("Contents of dtlb3:\n");
1303                         for (slot = 0; slot < 512; slot+=2) {
1304                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1305                                         slot,
1306                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1307                                         slot+1,
1308                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1309                         }
1310                 }
1311         }
1312 }
1313
1314 extern unsigned long cmdline_memory_size;
1315
1316 unsigned long __init bootmem_init(unsigned long *pages_avail)
1317 {
1318         unsigned long bootmap_size, start_pfn, end_pfn;
1319         unsigned long end_of_phys_memory = 0UL;
1320         unsigned long bootmap_pfn, bytes_avail, size;
1321         int i;
1322
1323 #ifdef CONFIG_DEBUG_BOOTMEM
1324         prom_printf("bootmem_init: Scan sp_banks, ");
1325 #endif
1326
1327         bytes_avail = 0UL;
1328         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1329                 end_of_phys_memory = sp_banks[i].base_addr +
1330                         sp_banks[i].num_bytes;
1331                 bytes_avail += sp_banks[i].num_bytes;
1332                 if (cmdline_memory_size) {
1333                         if (bytes_avail > cmdline_memory_size) {
1334                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1335
1336                                 bytes_avail -= slack;
1337                                 end_of_phys_memory -= slack;
1338
1339                                 sp_banks[i].num_bytes -= slack;
1340                                 if (sp_banks[i].num_bytes == 0) {
1341                                         sp_banks[i].base_addr = 0xdeadbeef;
1342                                 } else {
1343                                         sp_banks[i+1].num_bytes = 0;
1344                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1345                                 }
1346                                 break;
1347                         }
1348                 }
1349         }
1350
1351         *pages_avail = bytes_avail >> PAGE_SHIFT;
1352
1353         /* Start with page aligned address of last symbol in kernel
1354          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1355          * 4MB locked TLB translation.
1356          */
1357         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1358
1359         bootmap_pfn = start_pfn;
1360
1361         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1362
1363 #ifdef CONFIG_BLK_DEV_INITRD
1364         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1365         if (sparc_ramdisk_image) {
1366                 if (sparc_ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1367                         sparc_ramdisk_image -= KERNBASE;
1368                 initrd_start = sparc_ramdisk_image + phys_base;
1369                 initrd_end = initrd_start + sparc_ramdisk_size;
1370                 if (initrd_end > end_of_phys_memory) {
1371                         printk(KERN_CRIT "initrd extends beyond end of memory "
1372                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1373                                initrd_end, end_of_phys_memory);
1374                         initrd_start = 0;
1375                 }
1376                 if (initrd_start) {
1377                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1378                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1379                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1380                 }
1381         }
1382 #endif
1383         /* Initialize the boot-time allocator. */
1384         max_pfn = max_low_pfn = end_pfn;
1385         min_low_pfn = pfn_base;
1386
1387 #ifdef CONFIG_DEBUG_BOOTMEM
1388         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1389                     min_low_pfn, bootmap_pfn, max_low_pfn);
1390 #endif
1391         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1392
1393         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1394
1395         /* Now register the available physical memory with the
1396          * allocator.
1397          */
1398         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1399 #ifdef CONFIG_DEBUG_BOOTMEM
1400                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1401                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1402 #endif
1403                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1404         }
1405
1406 #ifdef CONFIG_BLK_DEV_INITRD
1407         if (initrd_start) {
1408                 size = initrd_end - initrd_start;
1409
1410                 /* Resert the initrd image area. */
1411                 reserve_bootmem(initrd_start, size);
1412                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1413
1414                 initrd_start += PAGE_OFFSET;
1415                 initrd_end += PAGE_OFFSET;
1416         }
1417 #endif
1418         /* Reserve the kernel text/data/bss. */
1419 #ifdef CONFIG_DEBUG_BOOTMEM
1420         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1421 #endif
1422         reserve_bootmem(kern_base, kern_size);
1423         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1424
1425         /* Reserve the bootmem map.   We do not account for it
1426          * in pages_avail because we will release that memory
1427          * in free_all_bootmem.
1428          */
1429         size = bootmap_size;
1430 #ifdef CONFIG_DEBUG_BOOTMEM
1431         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1432                     (bootmap_pfn << PAGE_SHIFT), size);
1433 #endif
1434         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1435         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1436
1437         return end_pfn;
1438 }
1439
1440 /* paging_init() sets up the page tables */
1441
1442 extern void cheetah_ecache_flush_init(void);
1443
1444 static unsigned long last_valid_pfn;
1445
1446 void __init paging_init(void)
1447 {
1448         extern pmd_t swapper_pmd_dir[1024];
1449         extern unsigned int sparc64_vpte_patchme1[1];
1450         extern unsigned int sparc64_vpte_patchme2[1];
1451         unsigned long alias_base = kern_base + PAGE_OFFSET;
1452         unsigned long second_alias_page = 0;
1453         unsigned long pt, flags, end_pfn, pages_avail;
1454         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1455         unsigned long real_end;
1456
1457         set_bit(0, mmu_context_bmap);
1458
1459         real_end = (unsigned long)_end;
1460         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1461                 bigkernel = 1;
1462 #ifdef CONFIG_BLK_DEV_INITRD
1463         if (sparc_ramdisk_image)
1464                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1465 #endif
1466
1467         /* We assume physical memory starts at some 4mb multiple,
1468          * if this were not true we wouldn't boot up to this point
1469          * anyways.
1470          */
1471         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1472         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1473         local_irq_save(flags);
1474         if (tlb_type == spitfire) {
1475                 __asm__ __volatile__(
1476         "       stxa    %1, [%0] %3\n"
1477         "       stxa    %2, [%5] %4\n"
1478         "       membar  #Sync\n"
1479         "       flush   %%g6\n"
1480         "       nop\n"
1481         "       nop\n"
1482         "       nop\n"
1483                 : /* No outputs */
1484                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1485                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1486                 : "memory");
1487                 if (real_end >= KERNBASE + 0x340000) {
1488                         second_alias_page = alias_base + 0x400000;
1489                         __asm__ __volatile__(
1490                 "       stxa    %1, [%0] %3\n"
1491                 "       stxa    %2, [%5] %4\n"
1492                 "       membar  #Sync\n"
1493                 "       flush   %%g6\n"
1494                 "       nop\n"
1495                 "       nop\n"
1496                 "       nop\n"
1497                         : /* No outputs */
1498                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1499                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1500                         : "memory");
1501                 }
1502         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1503                 __asm__ __volatile__(
1504         "       stxa    %1, [%0] %3\n"
1505         "       stxa    %2, [%5] %4\n"
1506         "       membar  #Sync\n"
1507         "       flush   %%g6\n"
1508         "       nop\n"
1509         "       nop\n"
1510         "       nop\n"
1511                 : /* No outputs */
1512                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1513                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1514                 : "memory");
1515                 if (real_end >= KERNBASE + 0x340000) {
1516                         second_alias_page = alias_base + 0x400000;
1517                         __asm__ __volatile__(
1518                 "       stxa    %1, [%0] %3\n"
1519                 "       stxa    %2, [%5] %4\n"
1520                 "       membar  #Sync\n"
1521                 "       flush   %%g6\n"
1522                 "       nop\n"
1523                 "       nop\n"
1524                 "       nop\n"
1525                         : /* No outputs */
1526                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1527                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1528                         : "memory");
1529                 }
1530         }
1531         local_irq_restore(flags);
1532
1533         /* Now set kernel pgd to upper alias so physical page computations
1534          * work.
1535          */
1536         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1537
1538         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1539
1540         /* Now can init the kernel/bad page tables. */
1541         pgd_set(&swapper_pg_dir[0], swapper_pmd_dir + (shift / sizeof(pgd_t)));
1542
1543         sparc64_vpte_patchme1[0] |=
1544                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1545         sparc64_vpte_patchme2[0] |=
1546                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1547         flushi((long)&sparc64_vpte_patchme1[0]);
1548
1549         /* Setup bootmem... */
1550         pages_avail = 0;
1551         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1552
1553         /* Inherit non-locked OBP mappings. */
1554         inherit_prom_mappings();
1555
1556         /* Ok, we can use our TLB miss and window trap handlers safely.
1557          * We need to do a quick peek here to see if we are on StarFire
1558          * or not, so setup_tba can setup the IRQ globals correctly (it
1559          * needs to get the hard smp processor id correctly).
1560          */
1561         {
1562                 extern void setup_tba(int);
1563                 setup_tba(this_is_starfire);
1564         }
1565
1566         inherit_locked_prom_mappings(1);
1567
1568         /* We only created DTLB mapping of this stuff. */
1569         spitfire_flush_dtlb_nucleus_page(alias_base);
1570         if (second_alias_page)
1571                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1572
1573         __flush_tlb_all();
1574
1575         {
1576                 unsigned long zones_size[MAX_NR_ZONES];
1577                 unsigned long zholes_size[MAX_NR_ZONES];
1578                 unsigned long npages;
1579                 int znum;
1580
1581                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1582                         zones_size[znum] = zholes_size[znum] = 0;
1583
1584                 npages = end_pfn - pfn_base;
1585                 zones_size[ZONE_DMA] = npages;
1586                 zholes_size[ZONE_DMA] = npages - pages_avail;
1587
1588                 free_area_init_node(0, &contig_page_data, NULL, zones_size,
1589                                     phys_base >> PAGE_SHIFT, zholes_size);
1590                 mem_map = contig_page_data.node_mem_map;
1591         }
1592
1593         device_scan();
1594 }
1595
1596 /* Ok, it seems that the prom can allocate some more memory chunks
1597  * as a side effect of some prom calls we perform during the
1598  * boot sequence.  My most likely theory is that it is from the
1599  * prom_set_traptable() call, and OBP is allocating a scratchpad
1600  * for saving client program register state etc.
1601  */
1602 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1603 {
1604         int swapi = 0;
1605         int i, mitr;
1606         unsigned long tmpaddr, tmpsize;
1607         unsigned long lowest;
1608
1609         for (i = 0; thislist[i].theres_more != 0; i++) {
1610                 lowest = thislist[i].start_adr;
1611                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1612                         if (thislist[mitr].start_adr < lowest) {
1613                                 lowest = thislist[mitr].start_adr;
1614                                 swapi = mitr;
1615                         }
1616                 if (lowest == thislist[i].start_adr)
1617                         continue;
1618                 tmpaddr = thislist[swapi].start_adr;
1619                 tmpsize = thislist[swapi].num_bytes;
1620                 for (mitr = swapi; mitr > i; mitr--) {
1621                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1622                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1623                 }
1624                 thislist[i].start_adr = tmpaddr;
1625                 thislist[i].num_bytes = tmpsize;
1626         }
1627 }
1628
1629 void __init rescan_sp_banks(void)
1630 {
1631         struct linux_prom64_registers memlist[64];
1632         struct linux_mlist_p1275 avail[64], *mlist;
1633         unsigned long bytes, base_paddr;
1634         int num_regs, node = prom_finddevice("/memory");
1635         int i;
1636
1637         num_regs = prom_getproperty(node, "available",
1638                                     (char *) memlist, sizeof(memlist));
1639         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1640         for (i = 0; i < num_regs; i++) {
1641                 avail[i].start_adr = memlist[i].phys_addr;
1642                 avail[i].num_bytes = memlist[i].reg_size;
1643                 avail[i].theres_more = &avail[i + 1];
1644         }
1645         avail[i - 1].theres_more = NULL;
1646         sort_memlist(avail);
1647
1648         mlist = &avail[0];
1649         i = 0;
1650         bytes = mlist->num_bytes;
1651         base_paddr = mlist->start_adr;
1652
1653         sp_banks[0].base_addr = base_paddr;
1654         sp_banks[0].num_bytes = bytes;
1655
1656         while (mlist->theres_more != NULL){
1657                 i++;
1658                 mlist = mlist->theres_more;
1659                 bytes = mlist->num_bytes;
1660                 if (i >= SPARC_PHYS_BANKS-1) {
1661                         printk ("The machine has more banks than "
1662                                 "this kernel can support\n"
1663                                 "Increase the SPARC_PHYS_BANKS "
1664                                 "setting (currently %d)\n",
1665                                 SPARC_PHYS_BANKS);
1666                         i = SPARC_PHYS_BANKS-1;
1667                         break;
1668                 }
1669
1670                 sp_banks[i].base_addr = mlist->start_adr;
1671                 sp_banks[i].num_bytes = mlist->num_bytes;
1672         }
1673
1674         i++;
1675         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1676         sp_banks[i].num_bytes = 0;
1677
1678         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1679                 sp_banks[i].num_bytes &= PAGE_MASK;
1680 }
1681
1682 static void __init taint_real_pages(void)
1683 {
1684         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1685         int i;
1686
1687         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1688                 saved_sp_banks[i].base_addr =
1689                         sp_banks[i].base_addr;
1690                 saved_sp_banks[i].num_bytes =
1691                         sp_banks[i].num_bytes;
1692         }
1693
1694         rescan_sp_banks();
1695
1696         /* Find changes discovered in the sp_bank rescan and
1697          * reserve the lost portions in the bootmem maps.
1698          */
1699         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1700                 unsigned long old_start, old_end;
1701
1702                 old_start = saved_sp_banks[i].base_addr;
1703                 old_end = old_start +
1704                         saved_sp_banks[i].num_bytes;
1705                 while (old_start < old_end) {
1706                         int n;
1707
1708                         for (n = 0; sp_banks[n].num_bytes; n++) {
1709                                 unsigned long new_start, new_end;
1710
1711                                 new_start = sp_banks[n].base_addr;
1712                                 new_end = new_start + sp_banks[n].num_bytes;
1713
1714                                 if (new_start <= old_start &&
1715                                     new_end >= (old_start + PAGE_SIZE)) {
1716                                         set_bit (old_start >> 22,
1717                                                  sparc64_valid_addr_bitmap);
1718                                         goto do_next_page;
1719                                 }
1720                         }
1721                         reserve_bootmem(old_start, PAGE_SIZE);
1722
1723                 do_next_page:
1724                         old_start += PAGE_SIZE;
1725                 }
1726         }
1727 }
1728
1729 void __init mem_init(void)
1730 {
1731         unsigned long codepages, datapages, initpages;
1732         unsigned long addr, last;
1733         int i;
1734
1735         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1736         i += 1;
1737         sparc64_valid_addr_bitmap = (unsigned long *)
1738                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1739         if (sparc64_valid_addr_bitmap == NULL) {
1740                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1741                 prom_halt();
1742         }
1743         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1744
1745         addr = PAGE_OFFSET + kern_base;
1746         last = PAGE_ALIGN(kern_size) + addr;
1747         while (addr < last) {
1748                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1749                 addr += PAGE_SIZE;
1750         }
1751
1752         taint_real_pages();
1753
1754         max_mapnr = last_valid_pfn - pfn_base;
1755         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1756
1757 #ifdef CONFIG_DEBUG_BOOTMEM
1758         prom_printf("mem_init: Calling free_all_bootmem().\n");
1759 #endif
1760         totalram_pages = num_physpages = free_all_bootmem() - 1;
1761
1762         /*
1763          * Set up the zero page, mark it reserved, so that page count
1764          * is not manipulated when freeing the page from user ptes.
1765          */
1766         mem_map_zero = alloc_pages(GFP_KERNEL, 0);
1767         if (mem_map_zero == NULL) {
1768                 prom_printf("paging_init: Cannot alloc zero page.\n");
1769                 prom_halt();
1770         }
1771         SetPageReserved(mem_map_zero);
1772         clear_page(page_address(mem_map_zero));
1773
1774         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1775         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1776         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1777         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1778         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1779         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1780
1781 #ifndef CONFIG_SMP
1782         {
1783                 /* Put empty_pg_dir on pgd_quicklist */
1784                 extern pgd_t empty_pg_dir[1024];
1785                 unsigned long addr = (unsigned long)empty_pg_dir;
1786                 unsigned long alias_base = kern_base + PAGE_OFFSET -
1787                         (long)(KERNBASE);
1788
1789                 memset(empty_pg_dir, 0, sizeof(empty_pg_dir));
1790                 addr += alias_base;
1791                 free_pgd_fast((pgd_t *)addr);
1792                 num_physpages++;
1793                 totalram_pages++;
1794         }
1795 #endif
1796
1797         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1798                nr_free_pages() << (PAGE_SHIFT-10),
1799                codepages << (PAGE_SHIFT-10),
1800                datapages << (PAGE_SHIFT-10),
1801                initpages << (PAGE_SHIFT-10),
1802                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1803
1804         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1805                 cheetah_ecache_flush_init();
1806 }
1807
1808 void free_initmem (void)
1809 {
1810         unsigned long addr, initend;
1811
1812         /*
1813          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1814          */
1815         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1816         initend = (unsigned long)(__init_end) & PAGE_MASK;
1817         for (; addr < initend; addr += PAGE_SIZE) {
1818                 unsigned long page;
1819                 struct page *p;
1820
1821                 page = (addr +
1822                         ((unsigned long) __va(kern_base)) -
1823                         ((unsigned long) KERNBASE));
1824                 p = virt_to_page(page);
1825
1826                 ClearPageReserved(p);
1827                 set_page_count(p, 1);
1828                 __free_page(p);
1829                 num_physpages++;
1830                 totalram_pages++;
1831         }
1832 }
1833
1834 #ifdef CONFIG_BLK_DEV_INITRD
1835 void free_initrd_mem(unsigned long start, unsigned long end)
1836 {
1837         if (start < end)
1838                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1839         for (; start < end; start += PAGE_SIZE) {
1840                 struct page *p = virt_to_page(start);
1841
1842                 ClearPageReserved(p);
1843                 set_page_count(p, 1);
1844                 __free_page(p);
1845                 num_physpages++;
1846                 totalram_pages++;
1847         }
1848 }
1849 #endif