arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 extern void device_scan(void);
  41
  42 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  43
  44 unsigned long *sparc64_valid_addr_bitmap;
  45
  46 /* Ugly, but necessary... -DaveM */
  47 unsigned long phys_base;
  48 unsigned long kern_base;
  49 unsigned long kern_size;
  50 unsigned long pfn_base;
  51
  52 /* This is even uglier. We have a problem where the kernel may not be
  53  * located at phys_base. However, initial __alloc_bootmem() calls need to
  54  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  55  * those page mappings wont work. Things are ok after inherit_prom_mappings
  56  * is called though. Dave says he'll clean this up some other time.
  57  * -- BenC
  58  */
  59 static unsigned long bootmap_base;
  60
  61 /* get_new_mmu_context() uses "cache + 1".  */
  62 DEFINE_SPINLOCK(ctx_alloc_lock);
  63 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  64 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
  65 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  66
  67 /* References to special section boundaries */
  68 extern char  _start[], _end[];
  69
  70 /* Initial ramdisk setup */
  71 extern unsigned long sparc_ramdisk_image64;
  72 extern unsigned int sparc_ramdisk_image;
  73 extern unsigned int sparc_ramdisk_size;
  74
  75 struct page *mem_map_zero;
  76
  77 int bigkernel = 0;
  78
  79 /* XXX Tune this... */
  80 #define PGT_CACHE_LOW   25
  81 #define PGT_CACHE_HIGH  50
  82
  83 void check_pgt_cache(void)
  84 {
  85         preempt_disable();
  86         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  87                 do {
  88                         if (pgd_quicklist)
  89                                 free_pgd_slow(get_pgd_fast());
  90                         if (pte_quicklist[0])
  91                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  92                         if (pte_quicklist[1])
  93                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  94                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  95         }
  96         preempt_enable();
  97 }
  98
  99 #ifdef CONFIG_DEBUG_DCFLUSH
 100 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 101 #ifdef CONFIG_SMP
 102 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 103 #endif
 104 #endif
 105
 106 __inline__ void flush_dcache_page_impl(struct page *page)
 107 {
 108 #ifdef CONFIG_DEBUG_DCFLUSH
 109         atomic_inc(&dcpage_flushes);
 110 #endif
 111
 112 #ifdef DCACHE_ALIASING_POSSIBLE
 113         __flush_dcache_page(page_address(page),
 114                             ((tlb_type == spitfire) &&
 115                              page_mapping(page) != NULL));
 116 #else
 117         if (page_mapping(page) != NULL &&
 118             tlb_type == spitfire)
 119                 __flush_icache_page(__pa(page_address(page)));
 120 #endif
 121 }
 122
 123 #define PG_dcache_dirty         PG_arch_1
 124
 125 #define dcache_dirty_cpu(page) \
 126         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 127
 128 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 129 {
 130         unsigned long mask = this_cpu;
 131         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 132         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 133         __asm__ __volatile__("1:\n\t"
 134                              "ldx       [%2], %%g7\n\t"
 135                              "and       %%g7, %1, %%g1\n\t"
 136                              "or        %%g1, %0, %%g1\n\t"
 137                              "casx      [%2], %%g7, %%g1\n\t"
 138                              "cmp       %%g7, %%g1\n\t"
 139                              "bne,pn    %%xcc, 1b\n\t"
 140                              " membar   #StoreLoad | #StoreStore"
 141                              : /* no outputs */
 142                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 143                              : "g1", "g7");
 144 }
 145
 146 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 147 {
 148         unsigned long mask = (1UL << PG_dcache_dirty);
 149
 150         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 151                              "1:\n\t"
 152                              "ldx       [%2], %%g7\n\t"
 153                              "srlx      %%g7, 24, %%g1\n\t"
 154                              "and       %%g1, %3, %%g1\n\t"
 155                              "cmp       %%g1, %0\n\t"
 156                              "bne,pn    %%icc, 2f\n\t"
 157                              " andn     %%g7, %1, %%g1\n\t"
 158                              "casx      [%2], %%g7, %%g1\n\t"
 159                              "cmp       %%g7, %%g1\n\t"
 160                              "bne,pn    %%xcc, 1b\n\t"
 161                              " membar   #StoreLoad | #StoreStore\n"
 162                              "2:"
 163                              : /* no outputs */
 164                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 165                                "i" (NR_CPUS - 1UL)
 166                              : "g1", "g7");
 167 }
 168
 169 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 170
 171 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 172 {
 173         struct page *page;
 174         unsigned long pfn;
 175         unsigned long pg_flags;
 176
 177         pfn = pte_pfn(pte);
 178         if (pfn_valid(pfn) &&
 179             (page = pfn_to_page(pfn), page_mapping(page)) &&
 180             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 181                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 182                 int this_cpu = get_cpu();
 183
 184                 /* This is just to optimize away some function calls
 185                  * in the SMP case.
 186                  */
 187                 if (cpu == this_cpu)
 188                         flush_dcache_page_impl(page);
 189                 else
 190                         smp_flush_dcache_page_impl(page, cpu);
 191
 192                 clear_dcache_dirty_cpu(page, cpu);
 193
 194                 put_cpu();
 195         }
 196
 197         if (get_thread_fault_code())
 198                 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
 199                                    address, pte, get_thread_fault_code());
 200 }
 201
 202 void flush_dcache_page(struct page *page)
 203 {
 204         struct address_space *mapping;
 205         int this_cpu;
 206
 207         /* Do not bother with the expensive D-cache flush if it
 208          * is merely the zero page.  The 'bigcore' testcase in GDB
 209          * causes this case to run millions of times.
 210          */
 211         if (page == ZERO_PAGE(0))
 212                 return;
 213
 214         this_cpu = get_cpu();
 215
 216         mapping = page_mapping(page);
 217         if (mapping && !mapping_mapped(mapping)) {
 218                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 219                 if (dirty) {
 220                         int dirty_cpu = dcache_dirty_cpu(page);
 221
 222                         if (dirty_cpu == this_cpu)
 223                                 goto out;
 224                         smp_flush_dcache_page_impl(page, dirty_cpu);
 225                 }
 226                 set_dcache_dirty(page, this_cpu);
 227         } else {
 228                 /* We could delay the flush for the !page_mapping
 229                  * case too.  But that case is for exec env/arg
 230                  * pages and those are %99 certainly going to get
 231                  * faulted into the tlb (and thus flushed) anyways.
 232                  */
 233                 flush_dcache_page_impl(page);
 234         }
 235
 236 out:
 237         put_cpu();
 238 }
 239
 240 void flush_icache_range(unsigned long start, unsigned long end)
 241 {
 242         /* Cheetah has coherent I-cache. */
 243         if (tlb_type == spitfire) {
 244                 unsigned long kaddr;
 245
 246                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 247                         __flush_icache_page(__get_phys(kaddr));
 248         }
 249 }
 250
 251 unsigned long page_to_pfn(struct page *page)
 252 {
 253         return (unsigned long) ((page - mem_map) + pfn_base);
 254 }
 255
 256 struct page *pfn_to_page(unsigned long pfn)
 257 {
 258         return (mem_map + (pfn - pfn_base));
 259 }
 260
 261 void show_mem(void)
 262 {
 263         printk("Mem-info:\n");
 264         show_free_areas();
 265         printk("Free swap:       %6ldkB\n",
 266                nr_swap_pages << (PAGE_SHIFT-10));
 267         printk("%ld pages of RAM\n", num_physpages);
 268         printk("%d free pages\n", nr_free_pages());
 269         printk("%d pages in page table cache\n",pgtable_cache_size);
 270 }
 271
 272 void mmu_info(struct seq_file *m)
 273 {
 274         if (tlb_type == cheetah)
 275                 seq_printf(m, "MMU Type\t: Cheetah\n");
 276         else if (tlb_type == cheetah_plus)
 277                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 278         else if (tlb_type == spitfire)
 279                 seq_printf(m, "MMU Type\t: Spitfire\n");
 280         else
 281                 seq_printf(m, "MMU Type\t: ???\n");
 282
 283 #ifdef CONFIG_DEBUG_DCFLUSH
 284         seq_printf(m, "DCPageFlushes\t: %d\n",
 285                    atomic_read(&dcpage_flushes));
 286 #ifdef CONFIG_SMP
 287         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 288                    atomic_read(&dcpage_flushes_xcall));
 289 #endif /* CONFIG_SMP */
 290 #endif /* CONFIG_DEBUG_DCFLUSH */
 291 }
 292
 293 struct linux_prom_translation {
 294         unsigned long virt;
 295         unsigned long size;
 296         unsigned long data;
 297 };
 298
 299 extern unsigned long prom_boot_page;
 300 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 301 extern int prom_get_mmu_ihandle(void);
 302 extern void register_prom_callbacks(void);
 303
 304 /* Exported for SMP bootup purposes. */
 305 unsigned long kern_locked_tte_data;
 306
 307 void __init early_pgtable_allocfail(char *type)
 308 {
 309         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 310         prom_halt();
 311 }
 312
 313 #define BASE_PAGE_SIZE 8192
 314 static pmd_t *prompmd;
 315
 316 /*
 317  * Translate PROM's mapping we capture at boot time into physical address.
 318  * The second parameter is only set from prom_callback() invocations.
 319  */
 320 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 321 {
 322         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 323         pte_t *ptep;
 324         unsigned long base;
 325
 326         if (pmd_none(*pmdp)) {
 327                 if (error)
 328                         *error = 1;
 329                 return(0);
 330         }
 331         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 332         if (!pte_present(*ptep)) {
 333                 if (error)
 334                         *error = 1;
 335                 return(0);
 336         }
 337         if (error) {
 338                 *error = 0;
 339                 return(pte_val(*ptep));
 340         }
 341         base = pte_val(*ptep) & _PAGE_PADDR;
 342         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 343 }
 344
 345 static void inherit_prom_mappings(void)
 346 {
 347         struct linux_prom_translation *trans;
 348         unsigned long phys_page, tte_vaddr, tte_data;
 349         void (*remap_func)(unsigned long, unsigned long, int);
 350         pmd_t *pmdp;
 351         pte_t *ptep;
 352         int node, n, i, tsz;
 353         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 354
 355         node = prom_finddevice("/virtual-memory");
 356         n = prom_getproplen(node, "translations");
 357         if (n == 0 || n == -1) {
 358                 prom_printf("Couldn't get translation property\n");
 359                 prom_halt();
 360         }
 361         n += 5 * sizeof(struct linux_prom_translation);
 362         for (tsz = 1; tsz < n; tsz <<= 1)
 363                 /* empty */;
 364         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 365         if (trans == NULL) {
 366                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 367                 prom_halt();
 368         }
 369         memset(trans, 0, tsz);
 370
 371         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 372                 prom_printf("Couldn't get translation property\n");
 373                 prom_halt();
 374         }
 375         n = n / sizeof(*trans);
 376
 377         /*
 378          * The obp translations are saved based on 8k pagesize, since obp can
 379          * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
 380          * ie obp range, are handled in entry.S and do not use the vpte scheme
 381          * (see rant in inherit_locked_prom_mappings()).
 382          */
 383 #define OBP_PMD_SIZE 2048
 384         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 385         if (prompmd == NULL)
 386                 early_pgtable_allocfail("pmd");
 387         memset(prompmd, 0, OBP_PMD_SIZE);
 388         for (i = 0; i < n; i++) {
 389                 unsigned long vaddr;
 390
 391                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 392                         for (vaddr = trans[i].virt;
 393                              ((vaddr < trans[i].virt + trans[i].size) &&
 394                              (vaddr < HI_OBP_ADDRESS));
 395                              vaddr += BASE_PAGE_SIZE) {
 396                                 unsigned long val;
 397
 398                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 399                                 if (pmd_none(*pmdp)) {
 400                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 401                                                                BASE_PAGE_SIZE,
 402                                                                bootmap_base);
 403                                         if (ptep == NULL)
 404                                                 early_pgtable_allocfail("pte");
 405                                         memset(ptep, 0, BASE_PAGE_SIZE);
 406                                         pmd_set(pmdp, ptep);
 407                                 }
 408                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 409                                                 ((vaddr >> 13) & 0x3ff);
 410
 411                                 val = trans[i].data;
 412
 413                                 /* Clear diag TTE bits. */
 414                                 if (tlb_type == spitfire)
 415                                         val &= ~0x0003fe0000000000UL;
 416
 417                                 set_pte_at(&init_mm, vaddr,
 418                                            ptep, __pte(val | _PAGE_MODIFIED));
 419                                 trans[i].data += BASE_PAGE_SIZE;
 420                         }
 421                 }
 422         }
 423         phys_page = __pa(prompmd);
 424         obp_iaddr_patch[0] |= (phys_page >> 10);
 425         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 426         flushi((long)&obp_iaddr_patch[0]);
 427         obp_daddr_patch[0] |= (phys_page >> 10);
 428         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 429         flushi((long)&obp_daddr_patch[0]);
 430
 431         /* Now fixup OBP's idea about where we really are mapped. */
 432         prom_printf("Remapping the kernel... ");
 433
 434         /* Spitfire Errata #32 workaround */
 435         /* NOTE: Using plain zero for the context value is
 436          *       correct here, we are not using the Linux trap
 437          *       tables yet so we should not use the special
 438          *       UltraSPARC-III+ page size encodings yet.
 439          */
 440         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 441                              "flush     %%g6"
 442                              : /* No outputs */
 443                              : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 444
 445         switch (tlb_type) {
 446         default:
 447         case spitfire:
 448                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 449                 break;
 450
 451         case cheetah:
 452         case cheetah_plus:
 453                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 454                 break;
 455         };
 456
 457         phys_page &= _PAGE_PADDR;
 458         phys_page += ((unsigned long)&prom_boot_page -
 459                       (unsigned long)KERNBASE);
 460
 461         if (tlb_type == spitfire) {
 462                 /* Lock this into i/d tlb entry 59 */
 463                 __asm__ __volatile__(
 464                         "stxa   %%g0, [%2] %3\n\t"
 465                         "stxa   %0, [%1] %4\n\t"
 466                         "membar #Sync\n\t"
 467                         "flush  %%g6\n\t"
 468                         "stxa   %%g0, [%2] %5\n\t"
 469                         "stxa   %0, [%1] %6\n\t"
 470                         "membar #Sync\n\t"
 471                         "flush  %%g6"
 472                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 473                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 474                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 475                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 476                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 477                         : "memory");
 478         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 479                 /* Lock this into i/d tlb-0 entry 11 */
 480                 __asm__ __volatile__(
 481                         "stxa   %%g0, [%2] %3\n\t"
 482                         "stxa   %0, [%1] %4\n\t"
 483                         "membar #Sync\n\t"
 484                         "flush  %%g6\n\t"
 485                         "stxa   %%g0, [%2] %5\n\t"
 486                         "stxa   %0, [%1] %6\n\t"
 487                         "membar #Sync\n\t"
 488                         "flush  %%g6"
 489                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 490                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 491                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 492                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 493                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 494                         : "memory");
 495         } else {
 496                 /* Implement me :-) */
 497                 BUG();
 498         }
 499
 500         tte_vaddr = (unsigned long) KERNBASE;
 501
 502         /* Spitfire Errata #32 workaround */
 503         /* NOTE: Using plain zero for the context value is
 504          *       correct here, we are not using the Linux trap
 505          *       tables yet so we should not use the special
 506          *       UltraSPARC-III+ page size encodings yet.
 507          */
 508         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 509                              "flush     %%g6"
 510                              : /* No outputs */
 511                              : "r" (0),
 512                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 513
 514         if (tlb_type == spitfire)
 515                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 516         else
 517                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 518
 519         kern_locked_tte_data = tte_data;
 520
 521         remap_func = (void *)  ((unsigned long) &prom_remap -
 522                                 (unsigned long) &prom_boot_page);
 523
 524
 525         /* Spitfire Errata #32 workaround */
 526         /* NOTE: Using plain zero for the context value is
 527          *       correct here, we are not using the Linux trap
 528          *       tables yet so we should not use the special
 529          *       UltraSPARC-III+ page size encodings yet.
 530          */
 531         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 532                              "flush     %%g6"
 533                              : /* No outputs */
 534                              : "r" (0),
 535                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 536
 537         remap_func((tlb_type == spitfire ?
 538                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 539                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 540                    (unsigned long) KERNBASE,
 541                    prom_get_mmu_ihandle());
 542
 543         if (bigkernel)
 544                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 545                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 546
 547         /* Flush out that temporary mapping. */
 548         spitfire_flush_dtlb_nucleus_page(0x0);
 549         spitfire_flush_itlb_nucleus_page(0x0);
 550
 551         /* Now lock us back into the TLBs via OBP. */
 552         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 553         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 554         if (bigkernel) {
 555                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 556                                                                 tte_vaddr + 0x400000);
 557                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 558                                                                 tte_vaddr + 0x400000);
 559         }
 560
 561         /* Re-read translations property. */
 562         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 563                 prom_printf("Couldn't get translation property\n");
 564                 prom_halt();
 565         }
 566         n = n / sizeof(*trans);
 567
 568         for (i = 0; i < n; i++) {
 569                 unsigned long vaddr = trans[i].virt;
 570                 unsigned long size = trans[i].size;
 571
 572                 if (vaddr < 0xf0000000UL) {
 573                         unsigned long avoid_start = (unsigned long) KERNBASE;
 574                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 575
 576                         if (bigkernel)
 577                                 avoid_end += (4 * 1024 * 1024);
 578                         if (vaddr < avoid_start) {
 579                                 unsigned long top = vaddr + size;
 580
 581                                 if (top > avoid_start)
 582                                         top = avoid_start;
 583                                 prom_unmap(top - vaddr, vaddr);
 584                         }
 585                         if ((vaddr + size) > avoid_end) {
 586                                 unsigned long bottom = vaddr;
 587
 588                                 if (bottom < avoid_end)
 589                                         bottom = avoid_end;
 590                                 prom_unmap((vaddr + size) - bottom, bottom);
 591                         }
 592                 }
 593         }
 594
 595         prom_printf("done.\n");
 596
 597         register_prom_callbacks();
 598 }
 599
 600 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 601  * upwards as reserved for use by the firmware (I wonder if this
 602  * will be the same on Cheetah...).  We use this virtual address
 603  * range for the VPTE table mappings of the nucleus so we need
 604  * to zap them when we enter the PROM.  -DaveM
 605  */
 606 static void __flush_nucleus_vptes(void)
 607 {
 608         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 609         int i;
 610
 611         /* Only DTLB must be checked for VPTE entries. */
 612         if (tlb_type == spitfire) {
 613                 for (i = 0; i < 63; i++) {
 614                         unsigned long tag;
 615
 616                         /* Spitfire Errata #32 workaround */
 617                         /* NOTE: Always runs on spitfire, so no cheetah+
 618                          *       page size encodings.
 619                          */
 620                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 621                                              "flush     %%g6"
 622                                              : /* No outputs */
 623                                              : "r" (0),
 624                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 625
 626                         tag = spitfire_get_dtlb_tag(i);
 627                         if (((tag & ~(PAGE_MASK)) == 0) &&
 628                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 629                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 630                                                      "membar #Sync"
 631                                                      : /* no outputs */
 632                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 633                                 spitfire_put_dtlb_data(i, 0x0UL);
 634                         }
 635                 }
 636         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 637                 for (i = 0; i < 512; i++) {
 638                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 639
 640                         if ((tag & ~PAGE_MASK) == 0 &&
 641                             (tag & PAGE_MASK) >= prom_reserved_base) {
 642                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 643                                                      "membar #Sync"
 644                                                      : /* no outputs */
 645                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 646                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 647                         }
 648
 649                         if (tlb_type != cheetah_plus)
 650                                 continue;
 651
 652                         tag = cheetah_get_dtlb_tag(i, 3);
 653
 654                         if ((tag & ~PAGE_MASK) == 0 &&
 655                             (tag & PAGE_MASK) >= prom_reserved_base) {
 656                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 657                                                      "membar #Sync"
 658                                                      : /* no outputs */
 659                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 660                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 661                         }
 662                 }
 663         } else {
 664                 /* Implement me :-) */
 665                 BUG();
 666         }
 667 }
 668
 669 static int prom_ditlb_set;
 670 struct prom_tlb_entry {
 671         int             tlb_ent;
 672         unsigned long   tlb_tag;
 673         unsigned long   tlb_data;
 674 };
 675 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 676
 677 void prom_world(int enter)
 678 {
 679         unsigned long pstate;
 680         int i;
 681
 682         if (!enter)
 683                 set_fs((mm_segment_t) { get_thread_current_ds() });
 684
 685         if (!prom_ditlb_set)
 686                 return;
 687
 688         /* Make sure the following runs atomically. */
 689         __asm__ __volatile__("flushw\n\t"
 690                              "rdpr      %%pstate, %0\n\t"
 691                              "wrpr      %0, %1, %%pstate"
 692                              : "=r" (pstate)
 693                              : "i" (PSTATE_IE));
 694
 695         if (enter) {
 696                 /* Kick out nucleus VPTEs. */
 697                 __flush_nucleus_vptes();
 698
 699                 /* Install PROM world. */
 700                 for (i = 0; i < 16; i++) {
 701                         if (prom_dtlb[i].tlb_ent != -1) {
 702                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 703                                                      "membar #Sync"
 704                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 705                                         "i" (ASI_DMMU));
 706                                 if (tlb_type == spitfire)
 707                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 708                                                                prom_dtlb[i].tlb_data);
 709                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 710                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 711                                                                prom_dtlb[i].tlb_data);
 712                         }
 713                         if (prom_itlb[i].tlb_ent != -1) {
 714                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 715                                                      "membar #Sync"
 716                                                      : : "r" (prom_itlb[i].tlb_tag),
 717                                                      "r" (TLB_TAG_ACCESS),
 718                                                      "i" (ASI_IMMU));
 719                                 if (tlb_type == spitfire)
 720                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 721                                                                prom_itlb[i].tlb_data);
 722                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 723                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 724                                                                prom_itlb[i].tlb_data);
 725                         }
 726                 }
 727         } else {
 728                 for (i = 0; i < 16; i++) {
 729                         if (prom_dtlb[i].tlb_ent != -1) {
 730                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 731                                                      "membar #Sync"
 732                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 733                                 if (tlb_type == spitfire)
 734                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 735                                 else
 736                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 737                         }
 738                         if (prom_itlb[i].tlb_ent != -1) {
 739                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 740                                                      "membar #Sync"
 741                                                      : : "r" (TLB_TAG_ACCESS),
 742                                                      "i" (ASI_IMMU));
 743                                 if (tlb_type == spitfire)
 744                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 745                                 else
 746                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 747                         }
 748                 }
 749         }
 750         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 751                              : : "r" (pstate));
 752 }
 753
 754 void inherit_locked_prom_mappings(int save_p)
 755 {
 756         int i;
 757         int dtlb_seen = 0;
 758         int itlb_seen = 0;
 759
 760         /* Fucking losing PROM has more mappings in the TLB, but
 761          * it (conveniently) fails to mention any of these in the
 762          * translations property.  The only ones that matter are
 763          * the locked PROM tlb entries, so we impose the following
 764          * irrecovable rule on the PROM, it is allowed 8 locked
 765          * entries in the ITLB and 8 in the DTLB.
 766          *
 767          * Supposedly the upper 16GB of the address space is
 768          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 769          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 770          * used between the client program and the firmware on sun5
 771          * systems to coordinate mmu mappings is also COMPLETELY
 772          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 773          */
 774         if (save_p) {
 775                 for (i = 0; i < 16; i++) {
 776                         prom_itlb[i].tlb_ent = -1;
 777                         prom_dtlb[i].tlb_ent = -1;
 778                 }
 779         }
 780         if (tlb_type == spitfire) {
 781                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 782                 for (i = 0; i < high; i++) {
 783                         unsigned long data;
 784
 785                         /* Spitfire Errata #32 workaround */
 786                         /* NOTE: Always runs on spitfire, so no cheetah+
 787                          *       page size encodings.
 788                          */
 789                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 790                                              "flush     %%g6"
 791                                              : /* No outputs */
 792                                              : "r" (0),
 793                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 794
 795                         data = spitfire_get_dtlb_data(i);
 796                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 797                                 unsigned long tag;
 798
 799                                 /* Spitfire Errata #32 workaround */
 800                                 /* NOTE: Always runs on spitfire, so no
 801                                  *       cheetah+ page size encodings.
 802                                  */
 803                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 804                                                      "flush     %%g6"
 805                                                      : /* No outputs */
 806                                                      : "r" (0),
 807                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 808
 809                                 tag = spitfire_get_dtlb_tag(i);
 810                                 if (save_p) {
 811                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 812                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 813                                         prom_dtlb[dtlb_seen].tlb_data = data;
 814                                 }
 815                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 816                                                      "membar #Sync"
 817                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 818                                 spitfire_put_dtlb_data(i, 0x0UL);
 819
 820                                 dtlb_seen++;
 821                                 if (dtlb_seen > 15)
 822                                         break;
 823                         }
 824                 }
 825
 826                 for (i = 0; i < high; i++) {
 827                         unsigned long data;
 828
 829                         /* Spitfire Errata #32 workaround */
 830                         /* NOTE: Always runs on spitfire, so no
 831                          *       cheetah+ page size encodings.
 832                          */
 833                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 834                                              "flush     %%g6"
 835                                              : /* No outputs */
 836                                              : "r" (0),
 837                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 838
 839                         data = spitfire_get_itlb_data(i);
 840                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 841                                 unsigned long tag;
 842
 843                                 /* Spitfire Errata #32 workaround */
 844                                 /* NOTE: Always runs on spitfire, so no
 845                                  *       cheetah+ page size encodings.
 846                                  */
 847                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 848                                                      "flush     %%g6"
 849                                                      : /* No outputs */
 850                                                      : "r" (0),
 851                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 852
 853                                 tag = spitfire_get_itlb_tag(i);
 854                                 if (save_p) {
 855                                         prom_itlb[itlb_seen].tlb_ent = i;
 856                                         prom_itlb[itlb_seen].tlb_tag = tag;
 857                                         prom_itlb[itlb_seen].tlb_data = data;
 858                                 }
 859                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 860                                                      "membar #Sync"
 861                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 862                                 spitfire_put_itlb_data(i, 0x0UL);
 863
 864                                 itlb_seen++;
 865                                 if (itlb_seen > 15)
 866                                         break;
 867                         }
 868                 }
 869         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 870                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 871
 872                 for (i = 0; i < high; i++) {
 873                         unsigned long data;
 874
 875                         data = cheetah_get_ldtlb_data(i);
 876                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 877                                 unsigned long tag;
 878
 879                                 tag = cheetah_get_ldtlb_tag(i);
 880                                 if (save_p) {
 881                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 882                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 883                                         prom_dtlb[dtlb_seen].tlb_data = data;
 884                                 }
 885                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 886                                                      "membar #Sync"
 887                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 888                                 cheetah_put_ldtlb_data(i, 0x0UL);
 889
 890                                 dtlb_seen++;
 891                                 if (dtlb_seen > 15)
 892                                         break;
 893                         }
 894                 }
 895
 896                 for (i = 0; i < high; i++) {
 897                         unsigned long data;
 898
 899                         data = cheetah_get_litlb_data(i);
 900                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 901                                 unsigned long tag;
 902
 903                                 tag = cheetah_get_litlb_tag(i);
 904                                 if (save_p) {
 905                                         prom_itlb[itlb_seen].tlb_ent = i;
 906                                         prom_itlb[itlb_seen].tlb_tag = tag;
 907                                         prom_itlb[itlb_seen].tlb_data = data;
 908                                 }
 909                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 910                                                      "membar #Sync"
 911                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 912                                 cheetah_put_litlb_data(i, 0x0UL);
 913
 914                                 itlb_seen++;
 915                                 if (itlb_seen > 15)
 916                                         break;
 917                         }
 918                 }
 919         } else {
 920                 /* Implement me :-) */
 921                 BUG();
 922         }
 923         if (save_p)
 924                 prom_ditlb_set = 1;
 925 }
 926
 927 /* Give PROM back his world, done during reboots... */
 928 void prom_reload_locked(void)
 929 {
 930         int i;
 931
 932         for (i = 0; i < 16; i++) {
 933                 if (prom_dtlb[i].tlb_ent != -1) {
 934                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 935                                              "membar #Sync"
 936                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 937                                 "i" (ASI_DMMU));
 938                         if (tlb_type == spitfire)
 939                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 940                                                        prom_dtlb[i].tlb_data);
 941                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 942                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 943                                                       prom_dtlb[i].tlb_data);
 944                 }
 945
 946                 if (prom_itlb[i].tlb_ent != -1) {
 947                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 948                                              "membar #Sync"
 949                                              : : "r" (prom_itlb[i].tlb_tag),
 950                                              "r" (TLB_TAG_ACCESS),
 951                                              "i" (ASI_IMMU));
 952                         if (tlb_type == spitfire)
 953                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 954                                                        prom_itlb[i].tlb_data);
 955                         else
 956                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 957                                                        prom_itlb[i].tlb_data);
 958                 }
 959         }
 960 }
 961
 962 #ifdef DCACHE_ALIASING_POSSIBLE
 963 void __flush_dcache_range(unsigned long start, unsigned long end)
 964 {
 965         unsigned long va;
 966
 967         if (tlb_type == spitfire) {
 968                 int n = 0;
 969
 970                 for (va = start; va < end; va += 32) {
 971                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 972                         if (++n >= 512)
 973                                 break;
 974                 }
 975         } else {
 976                 start = __pa(start);
 977                 end = __pa(end);
 978                 for (va = start; va < end; va += 32)
 979                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 980                                              "membar #Sync"
 981                                              : /* no outputs */
 982                                              : "r" (va),
 983                                                "i" (ASI_DCACHE_INVALIDATE));
 984         }
 985 }
 986 #endif /* DCACHE_ALIASING_POSSIBLE */
 987
 988 /* If not locked, zap it. */
 989 void __flush_tlb_all(void)
 990 {
 991         unsigned long pstate;
 992         int i;
 993
 994         __asm__ __volatile__("flushw\n\t"
 995                              "rdpr      %%pstate, %0\n\t"
 996                              "wrpr      %0, %1, %%pstate"
 997                              : "=r" (pstate)
 998                              : "i" (PSTATE_IE));
 999         if (tlb_type == spitfire) {
1000                 for (i = 0; i < 64; i++) {
1001                         /* Spitfire Errata #32 workaround */
1002                         /* NOTE: Always runs on spitfire, so no
1003                          *       cheetah+ page size encodings.
1004                          */
1005                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1006                                              "flush     %%g6"
1007                                              : /* No outputs */
1008                                              : "r" (0),
1009                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1010
1011                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1012                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1013                                                      "membar #Sync"
1014                                                      : /* no outputs */
1015                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1016                                 spitfire_put_dtlb_data(i, 0x0UL);
1017                         }
1018
1019                         /* Spitfire Errata #32 workaround */
1020                         /* NOTE: Always runs on spitfire, so no
1021                          *       cheetah+ page size encodings.
1022                          */
1023                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1024                                              "flush     %%g6"
1025                                              : /* No outputs */
1026                                              : "r" (0),
1027                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1028
1029                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1030                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1031                                                      "membar #Sync"
1032                                                      : /* no outputs */
1033                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1034                                 spitfire_put_itlb_data(i, 0x0UL);
1035                         }
1036                 }
1037         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1038                 cheetah_flush_dtlb_all();
1039                 cheetah_flush_itlb_all();
1040         }
1041         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1042                              : : "r" (pstate));
1043 }
1044
1045 /* Caller does TLB context flushing on local CPU if necessary.
1046  * The caller also ensures that CTX_VALID(mm->context) is false.
1047  *
1048  * We must be careful about boundary cases so that we never
1049  * let the user have CTX 0 (nucleus) or we ever use a CTX
1050  * version of zero (and thus NO_CONTEXT would not be caught
1051  * by version mis-match tests in mmu_context.h).
1052  */
1053 void get_new_mmu_context(struct mm_struct *mm)
1054 {
1055         unsigned long ctx, new_ctx;
1056         unsigned long orig_pgsz_bits;
1057
1058
1059         spin_lock(&ctx_alloc_lock);
1060         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1061         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1062         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1063         if (new_ctx >= (1 << CTX_NR_BITS)) {
1064                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1065                 if (new_ctx >= ctx) {
1066                         int i;
1067                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1068                                 CTX_FIRST_VERSION;
1069                         if (new_ctx == 1)
1070                                 new_ctx = CTX_FIRST_VERSION;
1071
1072                         /* Don't call memset, for 16 entries that's just
1073                          * plain silly...
1074                          */
1075                         mmu_context_bmap[0] = 3;
1076                         mmu_context_bmap[1] = 0;
1077                         mmu_context_bmap[2] = 0;
1078                         mmu_context_bmap[3] = 0;
1079                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1080                                 mmu_context_bmap[i + 0] = 0;
1081                                 mmu_context_bmap[i + 1] = 0;
1082                                 mmu_context_bmap[i + 2] = 0;
1083                                 mmu_context_bmap[i + 3] = 0;
1084                         }
1085                         goto out;
1086                 }
1087         }
1088         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1089         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1090 out:
1091         tlb_context_cache = new_ctx;
1092         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1093         spin_unlock(&ctx_alloc_lock);
1094 }
1095
1096 #ifndef CONFIG_SMP
1097 struct pgtable_cache_struct pgt_quicklists;
1098 #endif
1099
1100 /* OK, we have to color these pages. The page tables are accessed
1101  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1102  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1103  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1104  * fast handlers do not get data from old/garbage dcache lines that
1105  * correspond to an old/stale virtual address (user/kernel) that
1106  * previously mapped the pagetable page while accessing vpte range
1107  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1108  * color is the same, then when the kernel initializes the pagetable
1109  * using the later address range, accesses with the first address
1110  * range will see the newly initialized data rather than the garbage.
1111  */
1112 #ifdef DCACHE_ALIASING_POSSIBLE
1113 #define DC_ALIAS_SHIFT  1
1114 #else
1115 #define DC_ALIAS_SHIFT  0
1116 #endif
1117 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1118 {
1119         struct page *page;
1120         unsigned long color;
1121
1122         {
1123                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1124
1125                 if (ptep)
1126                         return ptep;
1127         }
1128
1129         color = VPTE_COLOR(address);
1130         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1131         if (page) {
1132                 unsigned long *to_free;
1133                 unsigned long paddr;
1134                 pte_t *pte;
1135
1136 #ifdef DCACHE_ALIASING_POSSIBLE
1137                 set_page_count(page, 1);
1138                 ClearPageCompound(page);
1139
1140                 set_page_count((page + 1), 1);
1141                 ClearPageCompound(page + 1);
1142 #endif
1143                 paddr = (unsigned long) page_address(page);
1144                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1145
1146                 if (!color) {
1147                         pte = (pte_t *) paddr;
1148                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1149                 } else {
1150                         pte = (pte_t *) (paddr + PAGE_SIZE);
1151                         to_free = (unsigned long *) paddr;
1152                 }
1153
1154 #ifdef DCACHE_ALIASING_POSSIBLE
1155                 /* Now free the other one up, adjust cache size. */
1156                 preempt_disable();
1157                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1158                 pte_quicklist[color ^ 0x1] = to_free;
1159                 pgtable_cache_size++;
1160                 preempt_enable();
1161 #endif
1162
1163                 return pte;
1164         }
1165         return NULL;
1166 }
1167
1168 void sparc_ultra_dump_itlb(void)
1169 {
1170         int slot;
1171
1172         if (tlb_type == spitfire) {
1173                 printk ("Contents of itlb: ");
1174                 for (slot = 0; slot < 14; slot++) printk ("    ");
1175                 printk ("%2x:%016lx,%016lx\n",
1176                         0,
1177                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1178                 for (slot = 1; slot < 64; slot+=3) {
1179                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1180                                 slot,
1181                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1182                                 slot+1,
1183                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1184                                 slot+2,
1185                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1186                 }
1187         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1188                 printk ("Contents of itlb0:\n");
1189                 for (slot = 0; slot < 16; slot+=2) {
1190                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1191                                 slot,
1192                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1193                                 slot+1,
1194                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1195                 }
1196                 printk ("Contents of itlb2:\n");
1197                 for (slot = 0; slot < 128; slot+=2) {
1198                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1199                                 slot,
1200                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1201                                 slot+1,
1202                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1203                 }
1204         }
1205 }
1206
1207 void sparc_ultra_dump_dtlb(void)
1208 {
1209         int slot;
1210
1211         if (tlb_type == spitfire) {
1212                 printk ("Contents of dtlb: ");
1213                 for (slot = 0; slot < 14; slot++) printk ("    ");
1214                 printk ("%2x:%016lx,%016lx\n", 0,
1215                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1216                 for (slot = 1; slot < 64; slot+=3) {
1217                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1218                                 slot,
1219                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1220                                 slot+1,
1221                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1222                                 slot+2,
1223                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1224                 }
1225         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1226                 printk ("Contents of dtlb0:\n");
1227                 for (slot = 0; slot < 16; slot+=2) {
1228                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1229                                 slot,
1230                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1231                                 slot+1,
1232                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1233                 }
1234                 printk ("Contents of dtlb2:\n");
1235                 for (slot = 0; slot < 512; slot+=2) {
1236                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1237                                 slot,
1238                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1239                                 slot+1,
1240                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1241                 }
1242                 if (tlb_type == cheetah_plus) {
1243                         printk ("Contents of dtlb3:\n");
1244                         for (slot = 0; slot < 512; slot+=2) {
1245                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1246                                         slot,
1247                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1248                                         slot+1,
1249                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1250                         }
1251                 }
1252         }
1253 }
1254
1255 extern unsigned long cmdline_memory_size;
1256
1257 unsigned long __init bootmem_init(unsigned long *pages_avail)
1258 {
1259         unsigned long bootmap_size, start_pfn, end_pfn;
1260         unsigned long end_of_phys_memory = 0UL;
1261         unsigned long bootmap_pfn, bytes_avail, size;
1262         int i;
1263
1264 #ifdef CONFIG_DEBUG_BOOTMEM
1265         prom_printf("bootmem_init: Scan sp_banks, ");
1266 #endif
1267
1268         bytes_avail = 0UL;
1269         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1270                 end_of_phys_memory = sp_banks[i].base_addr +
1271                         sp_banks[i].num_bytes;
1272                 bytes_avail += sp_banks[i].num_bytes;
1273                 if (cmdline_memory_size) {
1274                         if (bytes_avail > cmdline_memory_size) {
1275                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1276
1277                                 bytes_avail -= slack;
1278                                 end_of_phys_memory -= slack;
1279
1280                                 sp_banks[i].num_bytes -= slack;
1281                                 if (sp_banks[i].num_bytes == 0) {
1282                                         sp_banks[i].base_addr = 0xdeadbeef;
1283                                 } else {
1284                                         sp_banks[i+1].num_bytes = 0;
1285                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1286                                 }
1287                                 break;
1288                         }
1289                 }
1290         }
1291
1292         *pages_avail = bytes_avail >> PAGE_SHIFT;
1293
1294         /* Start with page aligned address of last symbol in kernel
1295          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1296          * 4MB locked TLB translation.
1297          */
1298         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1299
1300         bootmap_pfn = start_pfn;
1301
1302         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1303
1304 #ifdef CONFIG_BLK_DEV_INITRD
1305         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1306         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1307                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1308                         sparc_ramdisk_image : sparc_ramdisk_image64;
1309                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1310                         ramdisk_image -= KERNBASE;
1311                 initrd_start = ramdisk_image + phys_base;
1312                 initrd_end = initrd_start + sparc_ramdisk_size;
1313                 if (initrd_end > end_of_phys_memory) {
1314                         printk(KERN_CRIT "initrd extends beyond end of memory "
1315                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1316                                initrd_end, end_of_phys_memory);
1317                         initrd_start = 0;
1318                 }
1319                 if (initrd_start) {
1320                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1321                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1322                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1323                 }
1324         }
1325 #endif
1326         /* Initialize the boot-time allocator. */
1327         max_pfn = max_low_pfn = end_pfn;
1328         min_low_pfn = pfn_base;
1329
1330 #ifdef CONFIG_DEBUG_BOOTMEM
1331         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1332                     min_low_pfn, bootmap_pfn, max_low_pfn);
1333 #endif
1334         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1335
1336         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1337
1338         /* Now register the available physical memory with the
1339          * allocator.
1340          */
1341         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1342 #ifdef CONFIG_DEBUG_BOOTMEM
1343                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1344                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1345 #endif
1346                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1347         }
1348
1349 #ifdef CONFIG_BLK_DEV_INITRD
1350         if (initrd_start) {
1351                 size = initrd_end - initrd_start;
1352
1353                 /* Resert the initrd image area. */
1354 #ifdef CONFIG_DEBUG_BOOTMEM
1355                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1356                         initrd_start, initrd_end);
1357 #endif
1358                 reserve_bootmem(initrd_start, size);
1359                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1360
1361                 initrd_start += PAGE_OFFSET;
1362                 initrd_end += PAGE_OFFSET;
1363         }
1364 #endif
1365         /* Reserve the kernel text/data/bss. */
1366 #ifdef CONFIG_DEBUG_BOOTMEM
1367         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1368 #endif
1369         reserve_bootmem(kern_base, kern_size);
1370         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1371
1372         /* Reserve the bootmem map.   We do not account for it
1373          * in pages_avail because we will release that memory
1374          * in free_all_bootmem.
1375          */
1376         size = bootmap_size;
1377 #ifdef CONFIG_DEBUG_BOOTMEM
1378         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1379                     (bootmap_pfn << PAGE_SHIFT), size);
1380 #endif
1381         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1382         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1383
1384         return end_pfn;
1385 }
1386
1387 /* paging_init() sets up the page tables */
1388
1389 extern void cheetah_ecache_flush_init(void);
1390
1391 static unsigned long last_valid_pfn;
1392
1393 void __init paging_init(void)
1394 {
1395         extern pmd_t swapper_pmd_dir[1024];
1396         extern unsigned int sparc64_vpte_patchme1[1];
1397         extern unsigned int sparc64_vpte_patchme2[1];
1398         unsigned long alias_base = kern_base + PAGE_OFFSET;
1399         unsigned long second_alias_page = 0;
1400         unsigned long pt, flags, end_pfn, pages_avail;
1401         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1402         unsigned long real_end;
1403
1404         set_bit(0, mmu_context_bmap);
1405
1406         real_end = (unsigned long)_end;
1407         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1408                 bigkernel = 1;
1409 #ifdef CONFIG_BLK_DEV_INITRD
1410         if (sparc_ramdisk_image || sparc_ramdisk_image64)
1411                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1412 #endif
1413
1414         /* We assume physical memory starts at some 4mb multiple,
1415          * if this were not true we wouldn't boot up to this point
1416          * anyways.
1417          */
1418         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1419         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1420         local_irq_save(flags);
1421         if (tlb_type == spitfire) {
1422                 __asm__ __volatile__(
1423         "       stxa    %1, [%0] %3\n"
1424         "       stxa    %2, [%5] %4\n"
1425         "       membar  #Sync\n"
1426         "       flush   %%g6\n"
1427         "       nop\n"
1428         "       nop\n"
1429         "       nop\n"
1430                 : /* No outputs */
1431                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1432                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1433                 : "memory");
1434                 if (real_end >= KERNBASE + 0x340000) {
1435                         second_alias_page = alias_base + 0x400000;
1436                         __asm__ __volatile__(
1437                 "       stxa    %1, [%0] %3\n"
1438                 "       stxa    %2, [%5] %4\n"
1439                 "       membar  #Sync\n"
1440                 "       flush   %%g6\n"
1441                 "       nop\n"
1442                 "       nop\n"
1443                 "       nop\n"
1444                         : /* No outputs */
1445                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1446                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1447                         : "memory");
1448                 }
1449         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1450                 __asm__ __volatile__(
1451         "       stxa    %1, [%0] %3\n"
1452         "       stxa    %2, [%5] %4\n"
1453         "       membar  #Sync\n"
1454         "       flush   %%g6\n"
1455         "       nop\n"
1456         "       nop\n"
1457         "       nop\n"
1458                 : /* No outputs */
1459                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1460                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1461                 : "memory");
1462                 if (real_end >= KERNBASE + 0x340000) {
1463                         second_alias_page = alias_base + 0x400000;
1464                         __asm__ __volatile__(
1465                 "       stxa    %1, [%0] %3\n"
1466                 "       stxa    %2, [%5] %4\n"
1467                 "       membar  #Sync\n"
1468                 "       flush   %%g6\n"
1469                 "       nop\n"
1470                 "       nop\n"
1471                 "       nop\n"
1472                         : /* No outputs */
1473                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1474                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1475                         : "memory");
1476                 }
1477         }
1478         local_irq_restore(flags);
1479
1480         /* Now set kernel pgd to upper alias so physical page computations
1481          * work.
1482          */
1483         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1484
1485         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1486
1487         /* Now can init the kernel/bad page tables. */
1488         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1489                 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1490
1491         sparc64_vpte_patchme1[0] |=
1492                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1493         sparc64_vpte_patchme2[0] |=
1494                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1495         flushi((long)&sparc64_vpte_patchme1[0]);
1496
1497         /* Setup bootmem... */
1498         pages_avail = 0;
1499         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1500
1501         /* Inherit non-locked OBP mappings. */
1502         inherit_prom_mappings();
1503
1504         /* Ok, we can use our TLB miss and window trap handlers safely.
1505          * We need to do a quick peek here to see if we are on StarFire
1506          * or not, so setup_tba can setup the IRQ globals correctly (it
1507          * needs to get the hard smp processor id correctly).
1508          */
1509         {
1510                 extern void setup_tba(int);
1511                 setup_tba(this_is_starfire);
1512         }
1513
1514         inherit_locked_prom_mappings(1);
1515
1516         /* We only created DTLB mapping of this stuff. */
1517         spitfire_flush_dtlb_nucleus_page(alias_base);
1518         if (second_alias_page)
1519                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1520
1521         __flush_tlb_all();
1522
1523         {
1524                 unsigned long zones_size[MAX_NR_ZONES];
1525                 unsigned long zholes_size[MAX_NR_ZONES];
1526                 unsigned long npages;
1527                 int znum;
1528
1529                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1530                         zones_size[znum] = zholes_size[znum] = 0;
1531
1532                 npages = end_pfn - pfn_base;
1533                 zones_size[ZONE_DMA] = npages;
1534                 zholes_size[ZONE_DMA] = npages - pages_avail;
1535
1536                 free_area_init_node(0, &contig_page_data, zones_size,
1537                                     phys_base >> PAGE_SHIFT, zholes_size);
1538         }
1539
1540         device_scan();
1541 }
1542
1543 /* Ok, it seems that the prom can allocate some more memory chunks
1544  * as a side effect of some prom calls we perform during the
1545  * boot sequence.  My most likely theory is that it is from the
1546  * prom_set_traptable() call, and OBP is allocating a scratchpad
1547  * for saving client program register state etc.
1548  */
1549 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1550 {
1551         int swapi = 0;
1552         int i, mitr;
1553         unsigned long tmpaddr, tmpsize;
1554         unsigned long lowest;
1555
1556         for (i = 0; thislist[i].theres_more != 0; i++) {
1557                 lowest = thislist[i].start_adr;
1558                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1559                         if (thislist[mitr].start_adr < lowest) {
1560                                 lowest = thislist[mitr].start_adr;
1561                                 swapi = mitr;
1562                         }
1563                 if (lowest == thislist[i].start_adr)
1564                         continue;
1565                 tmpaddr = thislist[swapi].start_adr;
1566                 tmpsize = thislist[swapi].num_bytes;
1567                 for (mitr = swapi; mitr > i; mitr--) {
1568                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1569                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1570                 }
1571                 thislist[i].start_adr = tmpaddr;
1572                 thislist[i].num_bytes = tmpsize;
1573         }
1574 }
1575
1576 void __init rescan_sp_banks(void)
1577 {
1578         struct linux_prom64_registers memlist[64];
1579         struct linux_mlist_p1275 avail[64], *mlist;
1580         unsigned long bytes, base_paddr;
1581         int num_regs, node = prom_finddevice("/memory");
1582         int i;
1583
1584         num_regs = prom_getproperty(node, "available",
1585                                     (char *) memlist, sizeof(memlist));
1586         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1587         for (i = 0; i < num_regs; i++) {
1588                 avail[i].start_adr = memlist[i].phys_addr;
1589                 avail[i].num_bytes = memlist[i].reg_size;
1590                 avail[i].theres_more = &avail[i + 1];
1591         }
1592         avail[i - 1].theres_more = NULL;
1593         sort_memlist(avail);
1594
1595         mlist = &avail[0];
1596         i = 0;
1597         bytes = mlist->num_bytes;
1598         base_paddr = mlist->start_adr;
1599
1600         sp_banks[0].base_addr = base_paddr;
1601         sp_banks[0].num_bytes = bytes;
1602
1603         while (mlist->theres_more != NULL){
1604                 i++;
1605                 mlist = mlist->theres_more;
1606                 bytes = mlist->num_bytes;
1607                 if (i >= SPARC_PHYS_BANKS-1) {
1608                         printk ("The machine has more banks than "
1609                                 "this kernel can support\n"
1610                                 "Increase the SPARC_PHYS_BANKS "
1611                                 "setting (currently %d)\n",
1612                                 SPARC_PHYS_BANKS);
1613                         i = SPARC_PHYS_BANKS-1;
1614                         break;
1615                 }
1616
1617                 sp_banks[i].base_addr = mlist->start_adr;
1618                 sp_banks[i].num_bytes = mlist->num_bytes;
1619         }
1620
1621         i++;
1622         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1623         sp_banks[i].num_bytes = 0;
1624
1625         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1626                 sp_banks[i].num_bytes &= PAGE_MASK;
1627 }
1628
1629 static void __init taint_real_pages(void)
1630 {
1631         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1632         int i;
1633
1634         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1635                 saved_sp_banks[i].base_addr =
1636                         sp_banks[i].base_addr;
1637                 saved_sp_banks[i].num_bytes =
1638                         sp_banks[i].num_bytes;
1639         }
1640
1641         rescan_sp_banks();
1642
1643         /* Find changes discovered in the sp_bank rescan and
1644          * reserve the lost portions in the bootmem maps.
1645          */
1646         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1647                 unsigned long old_start, old_end;
1648
1649                 old_start = saved_sp_banks[i].base_addr;
1650                 old_end = old_start +
1651                         saved_sp_banks[i].num_bytes;
1652                 while (old_start < old_end) {
1653                         int n;
1654
1655                         for (n = 0; sp_banks[n].num_bytes; n++) {
1656                                 unsigned long new_start, new_end;
1657
1658                                 new_start = sp_banks[n].base_addr;
1659                                 new_end = new_start + sp_banks[n].num_bytes;
1660
1661                                 if (new_start <= old_start &&
1662                                     new_end >= (old_start + PAGE_SIZE)) {
1663                                         set_bit (old_start >> 22,
1664                                                  sparc64_valid_addr_bitmap);
1665                                         goto do_next_page;
1666                                 }
1667                         }
1668                         reserve_bootmem(old_start, PAGE_SIZE);
1669
1670                 do_next_page:
1671                         old_start += PAGE_SIZE;
1672                 }
1673         }
1674 }
1675
1676 void __init mem_init(void)
1677 {
1678         unsigned long codepages, datapages, initpages;
1679         unsigned long addr, last;
1680         int i;
1681
1682         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1683         i += 1;
1684         sparc64_valid_addr_bitmap = (unsigned long *)
1685                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1686         if (sparc64_valid_addr_bitmap == NULL) {
1687                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1688                 prom_halt();
1689         }
1690         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1691
1692         addr = PAGE_OFFSET + kern_base;
1693         last = PAGE_ALIGN(kern_size) + addr;
1694         while (addr < last) {
1695                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1696                 addr += PAGE_SIZE;
1697         }
1698
1699         taint_real_pages();
1700
1701         max_mapnr = last_valid_pfn - pfn_base;
1702         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1703
1704 #ifdef CONFIG_DEBUG_BOOTMEM
1705         prom_printf("mem_init: Calling free_all_bootmem().\n");
1706 #endif
1707         totalram_pages = num_physpages = free_all_bootmem() - 1;
1708
1709         /*
1710          * Set up the zero page, mark it reserved, so that page count
1711          * is not manipulated when freeing the page from user ptes.
1712          */
1713         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1714         if (mem_map_zero == NULL) {
1715                 prom_printf("paging_init: Cannot alloc zero page.\n");
1716                 prom_halt();
1717         }
1718         SetPageReserved(mem_map_zero);
1719
1720         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1721         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1722         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1723         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1724         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1725         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1726
1727         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1728                nr_free_pages() << (PAGE_SHIFT-10),
1729                codepages << (PAGE_SHIFT-10),
1730                datapages << (PAGE_SHIFT-10),
1731                initpages << (PAGE_SHIFT-10),
1732                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1733
1734         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1735                 cheetah_ecache_flush_init();
1736 }
1737
1738 void free_initmem (void)
1739 {
1740         unsigned long addr, initend;
1741
1742         /*
1743          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1744          */
1745         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1746         initend = (unsigned long)(__init_end) & PAGE_MASK;
1747         for (; addr < initend; addr += PAGE_SIZE) {
1748                 unsigned long page;
1749                 struct page *p;
1750
1751                 page = (addr +
1752                         ((unsigned long) __va(kern_base)) -
1753                         ((unsigned long) KERNBASE));
1754                 memset((void *)addr, 0xcc, PAGE_SIZE);
1755                 p = virt_to_page(page);
1756
1757                 ClearPageReserved(p);
1758                 set_page_count(p, 1);
1759                 __free_page(p);
1760                 num_physpages++;
1761                 totalram_pages++;
1762         }
1763 }
1764
1765 #ifdef CONFIG_BLK_DEV_INITRD
1766 void free_initrd_mem(unsigned long start, unsigned long end)
1767 {
1768         if (start < end)
1769                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1770         for (; start < end; start += PAGE_SIZE) {
1771                 struct page *p = virt_to_page(start);
1772
1773                 ClearPageReserved(p);
1774                 set_page_count(p, 1);
1775                 __free_page(p);
1776                 num_physpages++;
1777                 totalram_pages++;
1778         }
1779 }
1780 #endif