arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  41
  42 extern void device_scan(void);
  43
  44 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  45
  46 unsigned long *sparc64_valid_addr_bitmap;
  47
  48 /* Ugly, but necessary... -DaveM */
  49 unsigned long phys_base;
  50 unsigned long kern_base;
  51 unsigned long kern_size;
  52 unsigned long pfn_base;
  53
  54 /* This is even uglier. We have a problem where the kernel may not be
  55  * located at phys_base. However, initial __alloc_bootmem() calls need to
  56  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  57  * those page mappings wont work. Things are ok after inherit_prom_mappings
  58  * is called though. Dave says he'll clean this up some other time.
  59  * -- BenC
  60  */
  61 static unsigned long bootmap_base;
  62
  63 /* get_new_mmu_context() uses "cache + 1".  */
  64 spinlock_t ctx_alloc_lock = SPIN_LOCK_UNLOCKED;
  65 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  66 #define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6))
  67 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  68
  69 /* References to special section boundaries */
  70 extern char  _start[], _end[];
  71
  72 /* Initial ramdisk setup */
  73 extern unsigned int sparc_ramdisk_image;
  74 extern unsigned int sparc_ramdisk_size;
  75
  76 struct page *mem_map_zero;
  77
  78 int bigkernel = 0;
  79
  80 /* XXX Tune this... */
  81 #define PGT_CACHE_LOW   25
  82 #define PGT_CACHE_HIGH  50
  83
  84 void check_pgt_cache(void)
  85 {
  86         preempt_disable();
  87         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  88                 do {
  89 #ifdef CONFIG_SMP
  90                         if (pgd_quicklist)
  91                                 free_pgd_slow(get_pgd_fast());
  92 #endif
  93                         if (pte_quicklist[0])
  94                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  95                         if (pte_quicklist[1])
  96                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  97                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  98         }
  99 #ifndef CONFIG_SMP
 100         if (pgd_cache_size > PGT_CACHE_HIGH / 4) {
 101                 struct page *page, *page2;
 102                 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
 103                         if ((unsigned long)page->lru.prev == 3) {
 104                                 if (page2)
 105                                         page2->lru.next = page->lru.next;
 106                                 else
 107                                         pgd_quicklist = (void *) page->lru.next;
 108                                 pgd_cache_size -= 2;
 109                                 __free_page(page);
 110                                 if (page2)
 111                                         page = (struct page *)page2->lru.next;
 112                                 else
 113                                         page = (struct page *)pgd_quicklist;
 114                                 if (pgd_cache_size <= PGT_CACHE_LOW / 4)
 115                                         break;
 116                                 continue;
 117                         }
 118                         page2 = page;
 119                         page = (struct page *)page->lru.next;
 120                 }
 121         }
 122 #endif
 123         preempt_enable();
 124 }
 125
 126 #ifdef CONFIG_DEBUG_DCFLUSH
 127 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 128 #ifdef CONFIG_SMP
 129 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 130 #endif
 131 #endif
 132
 133 __inline__ void flush_dcache_page_impl(struct page *page)
 134 {
 135 #ifdef CONFIG_DEBUG_DCFLUSH
 136         atomic_inc(&dcpage_flushes);
 137 #endif
 138
 139 #if (L1DCACHE_SIZE > PAGE_SIZE)
 140         __flush_dcache_page(page->virtual,
 141                             ((tlb_type == spitfire) &&
 142                              page_mapping(page) != NULL));
 143 #else
 144         if (page_mapping(page) != NULL &&
 145             tlb_type == spitfire)
 146                 __flush_icache_page(__pa(page->virtual));
 147 #endif
 148 }
 149
 150 #define PG_dcache_dirty         PG_arch_1
 151
 152 #define dcache_dirty_cpu(page) \
 153         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 154
 155 static __inline__ void set_dcache_dirty(struct page *page)
 156 {
 157         unsigned long mask = smp_processor_id();
 158         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 159         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 160         __asm__ __volatile__("1:\n\t"
 161                              "ldx       [%2], %%g7\n\t"
 162                              "and       %%g7, %1, %%g5\n\t"
 163                              "or        %%g5, %0, %%g5\n\t"
 164                              "casx      [%2], %%g7, %%g5\n\t"
 165                              "cmp       %%g7, %%g5\n\t"
 166                              "bne,pn    %%xcc, 1b\n\t"
 167                              " membar   #StoreLoad | #StoreStore"
 168                              : /* no outputs */
 169                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 170                              : "g5", "g7");
 171 }
 172
 173 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 174 {
 175         unsigned long mask = (1UL << PG_dcache_dirty);
 176
 177         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 178                              "1:\n\t"
 179                              "ldx       [%2], %%g7\n\t"
 180                              "srlx      %%g7, 24, %%g5\n\t"
 181                              "and       %%g5, %3, %%g5\n\t"
 182                              "cmp       %%g5, %0\n\t"
 183                              "bne,pn    %%icc, 2f\n\t"
 184                              " andn     %%g7, %1, %%g5\n\t"
 185                              "casx      [%2], %%g7, %%g5\n\t"
 186                              "cmp       %%g7, %%g5\n\t"
 187                              "bne,pn    %%xcc, 1b\n\t"
 188                              " membar   #StoreLoad | #StoreStore\n"
 189                              "2:"
 190                              : /* no outputs */
 191                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 192                                "i" (NR_CPUS - 1UL)
 193                              : "g5", "g7");
 194 }
 195
 196 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 197
 198 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 199 {
 200         struct page *page;
 201         unsigned long pfn;
 202         unsigned long pg_flags;
 203
 204         pfn = pte_pfn(pte);
 205         if (pfn_valid(pfn) &&
 206             (page = pfn_to_page(pfn), page_mapping(page)) &&
 207             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 208                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 209
 210                 /* This is just to optimize away some function calls
 211                  * in the SMP case.
 212                  */
 213                 if (cpu == smp_processor_id())
 214                         flush_dcache_page_impl(page);
 215                 else
 216                         smp_flush_dcache_page_impl(page, cpu);
 217
 218                 clear_dcache_dirty_cpu(page, cpu);
 219         }
 220         if (get_thread_fault_code())
 221                 __update_mmu_cache(vma->vm_mm->context & TAG_CONTEXT_BITS,
 222                                    address, pte, get_thread_fault_code());
 223 }
 224
 225 void flush_dcache_page(struct page *page)
 226 {
 227         struct address_space *mapping = page_mapping(page);
 228         int dirty = test_bit(PG_dcache_dirty, &page->flags);
 229         int dirty_cpu = dcache_dirty_cpu(page);
 230
 231         if (mapping && !mapping_mapped(mapping)) {
 232                 if (dirty) {
 233                         if (dirty_cpu == smp_processor_id())
 234                                 return;
 235                         smp_flush_dcache_page_impl(page, dirty_cpu);
 236                 }
 237                 set_dcache_dirty(page);
 238         } else {
 239                 /* We could delay the flush for the !page_mapping
 240                  * case too.  But that case is for exec env/arg
 241                  * pages and those are %99 certainly going to get
 242                  * faulted into the tlb (and thus flushed) anyways.
 243                  */
 244                 flush_dcache_page_impl(page);
 245         }
 246 }
 247
 248 /* When shared+writable mmaps of files go away, we lose all dirty
 249  * page state, so we have to deal with D-cache aliasing here.
 250  *
 251  * This code relies on the fact that flush_cache_range() is always
 252  * called for an area composed by a single VMA.  It also assumes that
 253  * the MM's page_table_lock is held.
 254  */
 255 static inline void flush_cache_pte_range(struct mm_struct *mm, pmd_t *pmd, unsigned long address, unsigned long size)
 256 {
 257         unsigned long offset;
 258         pte_t *ptep;
 259
 260         if (pmd_none(*pmd))
 261                 return;
 262         ptep = pte_offset_map(pmd, address);
 263         offset = address & ~PMD_MASK;
 264         if (offset + size > PMD_SIZE)
 265                 size = PMD_SIZE - offset;
 266         size &= PAGE_MASK;
 267         for (offset = 0; offset < size; ptep++, offset += PAGE_SIZE) {
 268                 pte_t pte = *ptep;
 269
 270                 if (pte_none(pte))
 271                         continue;
 272
 273                 if (pte_present(pte) && pte_dirty(pte)) {
 274                         struct page *page;
 275                         unsigned long pgaddr, uaddr;
 276                         unsigned long pfn = pte_pfn(pte);
 277
 278                         if (!pfn_valid(pfn))
 279                                 continue;
 280                         page = pfn_to_page(pfn);
 281                         if (PageReserved(page) || !page_mapping(page))
 282                                 continue;
 283                         pgaddr = (unsigned long) page_address(page);
 284                         uaddr = address + offset;
 285                         if ((pgaddr ^ uaddr) & (1 << 13))
 286                                 flush_dcache_page_all(mm, page);
 287                 }
 288         }
 289         pte_unmap(ptep - 1);
 290 }
 291
 292 static inline void flush_cache_pmd_range(struct mm_struct *mm, pgd_t *dir, unsigned long address, unsigned long size)
 293 {
 294         pmd_t *pmd;
 295         unsigned long end;
 296
 297         if (pgd_none(*dir))
 298                 return;
 299         pmd = pmd_offset(dir, address);
 300         end = address + size;
 301         if (end > ((address + PGDIR_SIZE) & PGDIR_MASK))
 302                 end = ((address + PGDIR_SIZE) & PGDIR_MASK);
 303         do {
 304                 flush_cache_pte_range(mm, pmd, address, end - address);
 305                 address = (address + PMD_SIZE) & PMD_MASK;
 306                 pmd++;
 307         } while (address < end);
 308 }
 309
 310 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 311 {
 312         struct mm_struct *mm = vma->vm_mm;
 313         pgd_t *dir = pgd_offset(mm, start);
 314
 315         if (mm == current->mm)
 316                 flushw_user();
 317
 318         if (vma->vm_file == NULL ||
 319             ((vma->vm_flags & (VM_SHARED|VM_WRITE)) != (VM_SHARED|VM_WRITE)))
 320                 return;
 321
 322         do {
 323                 flush_cache_pmd_range(mm, dir, start, end - start);
 324                 start = (start + PGDIR_SIZE) & PGDIR_MASK;
 325                 dir++;
 326         } while (start && (start < end));
 327 }
 328
 329 void flush_icache_range(unsigned long start, unsigned long end)
 330 {
 331         /* Cheetah has coherent I-cache. */
 332         if (tlb_type == spitfire) {
 333                 unsigned long kaddr;
 334
 335                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 336                         __flush_icache_page(__get_phys(kaddr));
 337         }
 338 }
 339
 340 void show_mem(void)
 341 {
 342         printk("Mem-info:\n");
 343         show_free_areas();
 344         printk("Free swap:       %6dkB\n",
 345                nr_swap_pages << (PAGE_SHIFT-10));
 346         printk("%ld pages of RAM\n", num_physpages);
 347         printk("%d free pages\n", nr_free_pages());
 348         printk("%d pages in page table cache\n",pgtable_cache_size);
 349 #ifndef CONFIG_SMP
 350         printk("%d entries in page dir cache\n",pgd_cache_size);
 351 #endif
 352 }
 353
 354 void mmu_info(struct seq_file *m)
 355 {
 356         if (tlb_type == cheetah)
 357                 seq_printf(m, "MMU Type\t: Cheetah\n");
 358         else if (tlb_type == cheetah_plus)
 359                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 360         else if (tlb_type == spitfire)
 361                 seq_printf(m, "MMU Type\t: Spitfire\n");
 362         else
 363                 seq_printf(m, "MMU Type\t: ???\n");
 364
 365 #ifdef CONFIG_DEBUG_DCFLUSH
 366         seq_printf(m, "DCPageFlushes\t: %d\n",
 367                    atomic_read(&dcpage_flushes));
 368 #ifdef CONFIG_SMP
 369         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 370                    atomic_read(&dcpage_flushes_xcall));
 371 #endif /* CONFIG_SMP */
 372 #endif /* CONFIG_DEBUG_DCFLUSH */
 373 }
 374
 375 struct linux_prom_translation {
 376         unsigned long virt;
 377         unsigned long size;
 378         unsigned long data;
 379 };
 380
 381 extern unsigned long prom_boot_page;
 382 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 383 extern int prom_get_mmu_ihandle(void);
 384 extern void register_prom_callbacks(void);
 385
 386 /* Exported for SMP bootup purposes. */
 387 unsigned long kern_locked_tte_data;
 388
 389 void __init early_pgtable_allocfail(char *type)
 390 {
 391         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 392         prom_halt();
 393 }
 394
 395 #define BASE_PAGE_SIZE 8192
 396 static pmd_t *prompmd;
 397
 398 /*
 399  * Translate PROM's mapping we capture at boot time into physical address.
 400  * The second parameter is only set from prom_callback() invocations.
 401  */
 402 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 403 {
 404         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 405         pte_t *ptep;
 406         unsigned long base;
 407
 408         if (pmd_none(*pmdp)) {
 409                 if (error)
 410                         *error = 1;
 411                 return(0);
 412         }
 413         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 414         if (!pte_present(*ptep)) {
 415                 if (error)
 416                         *error = 1;
 417                 return(0);
 418         }
 419         if (error) {
 420                 *error = 0;
 421                 return(pte_val(*ptep));
 422         }
 423         base = pte_val(*ptep) & _PAGE_PADDR;
 424         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 425 }
 426
 427 static void inherit_prom_mappings(void)
 428 {
 429         struct linux_prom_translation *trans;
 430         unsigned long phys_page, tte_vaddr, tte_data;
 431         void (*remap_func)(unsigned long, unsigned long, int);
 432         pmd_t *pmdp;
 433         pte_t *ptep;
 434         int node, n, i, tsz;
 435         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 436
 437         node = prom_finddevice("/virtual-memory");
 438         n = prom_getproplen(node, "translations");
 439         if (n == 0 || n == -1) {
 440                 prom_printf("Couldn't get translation property\n");
 441                 prom_halt();
 442         }
 443         n += 5 * sizeof(struct linux_prom_translation);
 444         for (tsz = 1; tsz < n; tsz <<= 1)
 445                 /* empty */;
 446         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 447         if (trans == NULL) {
 448                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 449                 prom_halt();
 450         }
 451         memset(trans, 0, tsz);
 452
 453         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 454                 prom_printf("Couldn't get translation property\n");
 455                 prom_halt();
 456         }
 457         n = n / sizeof(*trans);
 458
 459         /*
 460          * The obp translations are saved based on 8k pagesize, since obp can use
 461          * a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, ie obp
 462          * range, are handled in entry.S and do not use the vpte scheme (see rant
 463          * in inherit_locked_prom_mappings()).
 464          */
 465 #define OBP_PMD_SIZE 2048
 466         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 467         if (prompmd == NULL)
 468                 early_pgtable_allocfail("pmd");
 469         memset(prompmd, 0, OBP_PMD_SIZE);
 470         for (i = 0; i < n; i++) {
 471                 unsigned long vaddr;
 472
 473                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 474                         for (vaddr = trans[i].virt;
 475                              ((vaddr < trans[i].virt + trans[i].size) &&
 476                              (vaddr < HI_OBP_ADDRESS));
 477                              vaddr += BASE_PAGE_SIZE) {
 478                                 unsigned long val;
 479
 480                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 481                                 if (pmd_none(*pmdp)) {
 482                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 483                                                                BASE_PAGE_SIZE,
 484                                                                bootmap_base);
 485                                         if (ptep == NULL)
 486                                                 early_pgtable_allocfail("pte");
 487                                         memset(ptep, 0, BASE_PAGE_SIZE);
 488                                         pmd_set(pmdp, ptep);
 489                                 }
 490                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 491                                                 ((vaddr >> 13) & 0x3ff);
 492
 493                                 val = trans[i].data;
 494
 495                                 /* Clear diag TTE bits. */
 496                                 if (tlb_type == spitfire)
 497                                         val &= ~0x0003fe0000000000UL;
 498
 499                                 set_pte (ptep, __pte(val | _PAGE_MODIFIED));
 500                                 trans[i].data += BASE_PAGE_SIZE;
 501                         }
 502                 }
 503         }
 504         phys_page = __pa(prompmd);
 505         obp_iaddr_patch[0] |= (phys_page >> 10);
 506         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 507         flushi((long)&obp_iaddr_patch[0]);
 508         obp_daddr_patch[0] |= (phys_page >> 10);
 509         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 510         flushi((long)&obp_daddr_patch[0]);
 511
 512         /* Now fixup OBP's idea about where we really are mapped. */
 513         prom_printf("Remapping the kernel... ");
 514
 515         /* Spitfire Errata #32 workaround */
 516         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 517                              "flush     %%g6"
 518                              : /* No outputs */
 519                              : "r" (0),
 520                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 521
 522         switch (tlb_type) {
 523         default:
 524         case spitfire:
 525                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 526                 break;
 527
 528         case cheetah:
 529         case cheetah_plus:
 530                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 531                 break;
 532         };
 533
 534         phys_page &= _PAGE_PADDR;
 535         phys_page += ((unsigned long)&prom_boot_page -
 536                       (unsigned long)KERNBASE);
 537
 538         if (tlb_type == spitfire) {
 539                 /* Lock this into i/d tlb entry 59 */
 540                 __asm__ __volatile__(
 541                         "stxa   %%g0, [%2] %3\n\t"
 542                         "stxa   %0, [%1] %4\n\t"
 543                         "membar #Sync\n\t"
 544                         "flush  %%g6\n\t"
 545                         "stxa   %%g0, [%2] %5\n\t"
 546                         "stxa   %0, [%1] %6\n\t"
 547                         "membar #Sync\n\t"
 548                         "flush  %%g6"
 549                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 550                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 551                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 552                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 553                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 554                         : "memory");
 555         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 556                 /* Lock this into i/d tlb-0 entry 11 */
 557                 __asm__ __volatile__(
 558                         "stxa   %%g0, [%2] %3\n\t"
 559                         "stxa   %0, [%1] %4\n\t"
 560                         "membar #Sync\n\t"
 561                         "flush  %%g6\n\t"
 562                         "stxa   %%g0, [%2] %5\n\t"
 563                         "stxa   %0, [%1] %6\n\t"
 564                         "membar #Sync\n\t"
 565                         "flush  %%g6"
 566                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 567                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 568                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 569                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 570                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 571                         : "memory");
 572         } else {
 573                 /* Implement me :-) */
 574                 BUG();
 575         }
 576
 577         tte_vaddr = (unsigned long) KERNBASE;
 578
 579         /* Spitfire Errata #32 workaround */
 580         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 581                              "flush     %%g6"
 582                              : /* No outputs */
 583                              : "r" (0),
 584                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 585
 586         if (tlb_type == spitfire)
 587                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 588         else
 589                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 590
 591         kern_locked_tte_data = tte_data;
 592
 593         remap_func = (void *)  ((unsigned long) &prom_remap -
 594                                 (unsigned long) &prom_boot_page);
 595
 596
 597         /* Spitfire Errata #32 workaround */
 598         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 599                              "flush     %%g6"
 600                              : /* No outputs */
 601                              : "r" (0),
 602                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 603
 604         remap_func((tlb_type == spitfire ?
 605                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 606                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 607                    (unsigned long) KERNBASE,
 608                    prom_get_mmu_ihandle());
 609
 610         if (bigkernel)
 611                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 612                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 613
 614         /* Flush out that temporary mapping. */
 615         spitfire_flush_dtlb_nucleus_page(0x0);
 616         spitfire_flush_itlb_nucleus_page(0x0);
 617
 618         /* Now lock us back into the TLBs via OBP. */
 619         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 620         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 621         if (bigkernel) {
 622                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 623                                                                 tte_vaddr + 0x400000);
 624                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 625                                                                 tte_vaddr + 0x400000);
 626         }
 627
 628         /* Re-read translations property. */
 629         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 630                 prom_printf("Couldn't get translation property\n");
 631                 prom_halt();
 632         }
 633         n = n / sizeof(*trans);
 634
 635         for (i = 0; i < n; i++) {
 636                 unsigned long vaddr = trans[i].virt;
 637                 unsigned long size = trans[i].size;
 638
 639                 if (vaddr < 0xf0000000UL) {
 640                         unsigned long avoid_start = (unsigned long) KERNBASE;
 641                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 642
 643                         if (bigkernel)
 644                                 avoid_end += (4 * 1024 * 1024);
 645                         if (vaddr < avoid_start) {
 646                                 unsigned long top = vaddr + size;
 647
 648                                 if (top > avoid_start)
 649                                         top = avoid_start;
 650                                 prom_unmap(top - vaddr, vaddr);
 651                         }
 652                         if ((vaddr + size) > avoid_end) {
 653                                 unsigned long bottom = vaddr;
 654
 655                                 if (bottom < avoid_end)
 656                                         bottom = avoid_end;
 657                                 prom_unmap((vaddr + size) - bottom, bottom);
 658                         }
 659                 }
 660         }
 661
 662         prom_printf("done.\n");
 663
 664         register_prom_callbacks();
 665 }
 666
 667 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 668  * upwards as reserved for use by the firmware (I wonder if this
 669  * will be the same on Cheetah...).  We use this virtual address
 670  * range for the VPTE table mappings of the nucleus so we need
 671  * to zap them when we enter the PROM.  -DaveM
 672  */
 673 static void __flush_nucleus_vptes(void)
 674 {
 675         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 676         int i;
 677
 678         /* Only DTLB must be checked for VPTE entries. */
 679         if (tlb_type == spitfire) {
 680                 for (i = 0; i < 63; i++) {
 681                         unsigned long tag;
 682
 683                         /* Spitfire Errata #32 workaround */
 684                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 685                                              "flush     %%g6"
 686                                              : /* No outputs */
 687                                              : "r" (0),
 688                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 689
 690                         tag = spitfire_get_dtlb_tag(i);
 691                         if (((tag & ~(PAGE_MASK)) == 0) &&
 692                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 693                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 694                                                      "membar #Sync"
 695                                                      : /* no outputs */
 696                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 697                                 spitfire_put_dtlb_data(i, 0x0UL);
 698                         }
 699                 }
 700         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 701                 for (i = 0; i < 512; i++) {
 702                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 703
 704                         if ((tag & ~PAGE_MASK) == 0 &&
 705                             (tag & PAGE_MASK) >= prom_reserved_base) {
 706                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 707                                                      "membar #Sync"
 708                                                      : /* no outputs */
 709                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 710                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 711                         }
 712
 713                         if (tlb_type != cheetah_plus)
 714                                 continue;
 715
 716                         tag = cheetah_get_dtlb_tag(i, 3);
 717
 718                         if ((tag & ~PAGE_MASK) == 0 &&
 719                             (tag & PAGE_MASK) >= prom_reserved_base) {
 720                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 721                                                      "membar #Sync"
 722                                                      : /* no outputs */
 723                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 724                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 725                         }
 726                 }
 727         } else {
 728                 /* Implement me :-) */
 729                 BUG();
 730         }
 731 }
 732
 733 static int prom_ditlb_set;
 734 struct prom_tlb_entry {
 735         int             tlb_ent;
 736         unsigned long   tlb_tag;
 737         unsigned long   tlb_data;
 738 };
 739 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 740
 741 void prom_world(int enter)
 742 {
 743         unsigned long pstate;
 744         int i;
 745
 746         if (!enter)
 747                 set_fs((mm_segment_t) { get_thread_current_ds() });
 748
 749         if (!prom_ditlb_set)
 750                 return;
 751
 752         /* Make sure the following runs atomically. */
 753         __asm__ __volatile__("flushw\n\t"
 754                              "rdpr      %%pstate, %0\n\t"
 755                              "wrpr      %0, %1, %%pstate"
 756                              : "=r" (pstate)
 757                              : "i" (PSTATE_IE));
 758
 759         if (enter) {
 760                 /* Kick out nucleus VPTEs. */
 761                 __flush_nucleus_vptes();
 762
 763                 /* Install PROM world. */
 764                 for (i = 0; i < 16; i++) {
 765                         if (prom_dtlb[i].tlb_ent != -1) {
 766                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 767                                                      "membar #Sync"
 768                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 769                                         "i" (ASI_DMMU));
 770                                 if (tlb_type == spitfire)
 771                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 772                                                                prom_dtlb[i].tlb_data);
 773                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 774                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 775                                                                prom_dtlb[i].tlb_data);
 776                         }
 777                         if (prom_itlb[i].tlb_ent != -1) {
 778                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 779                                                      "membar #Sync"
 780                                                      : : "r" (prom_itlb[i].tlb_tag),
 781                                                      "r" (TLB_TAG_ACCESS),
 782                                                      "i" (ASI_IMMU));
 783                                 if (tlb_type == spitfire)
 784                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 785                                                                prom_itlb[i].tlb_data);
 786                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 787                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 788                                                                prom_itlb[i].tlb_data);
 789                         }
 790                 }
 791         } else {
 792                 for (i = 0; i < 16; i++) {
 793                         if (prom_dtlb[i].tlb_ent != -1) {
 794                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 795                                                      "membar #Sync"
 796                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 797                                 if (tlb_type == spitfire)
 798                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 799                                 else
 800                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 801                         }
 802                         if (prom_itlb[i].tlb_ent != -1) {
 803                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 804                                                      "membar #Sync"
 805                                                      : : "r" (TLB_TAG_ACCESS),
 806                                                      "i" (ASI_IMMU));
 807                                 if (tlb_type == spitfire)
 808                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 809                                 else
 810                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 811                         }
 812                 }
 813         }
 814         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 815                              : : "r" (pstate));
 816 }
 817
 818 void inherit_locked_prom_mappings(int save_p)
 819 {
 820         int i;
 821         int dtlb_seen = 0;
 822         int itlb_seen = 0;
 823
 824         /* Fucking losing PROM has more mappings in the TLB, but
 825          * it (conveniently) fails to mention any of these in the
 826          * translations property.  The only ones that matter are
 827          * the locked PROM tlb entries, so we impose the following
 828          * irrecovable rule on the PROM, it is allowed 8 locked
 829          * entries in the ITLB and 8 in the DTLB.
 830          *
 831          * Supposedly the upper 16GB of the address space is
 832          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 833          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 834          * used between the client program and the firmware on sun5
 835          * systems to coordinate mmu mappings is also COMPLETELY
 836          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 837          */
 838         if (save_p) {
 839                 for (i = 0; i < 16; i++) {
 840                         prom_itlb[i].tlb_ent = -1;
 841                         prom_dtlb[i].tlb_ent = -1;
 842                 }
 843         }
 844         if (tlb_type == spitfire) {
 845                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 846                 for (i = 0; i < high; i++) {
 847                         unsigned long data;
 848
 849                         /* Spitfire Errata #32 workaround */
 850                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 851                                              "flush     %%g6"
 852                                              : /* No outputs */
 853                                              : "r" (0),
 854                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 855
 856                         data = spitfire_get_dtlb_data(i);
 857                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 858                                 unsigned long tag;
 859
 860                                 /* Spitfire Errata #32 workaround */
 861                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 862                                                      "flush     %%g6"
 863                                                      : /* No outputs */
 864                                                      : "r" (0),
 865                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 866
 867                                 tag = spitfire_get_dtlb_tag(i);
 868                                 if (save_p) {
 869                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 870                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 871                                         prom_dtlb[dtlb_seen].tlb_data = data;
 872                                 }
 873                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 874                                                      "membar #Sync"
 875                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 876                                 spitfire_put_dtlb_data(i, 0x0UL);
 877
 878                                 dtlb_seen++;
 879                                 if (dtlb_seen > 15)
 880                                         break;
 881                         }
 882                 }
 883
 884                 for (i = 0; i < high; i++) {
 885                         unsigned long data;
 886
 887                         /* Spitfire Errata #32 workaround */
 888                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 889                                              "flush     %%g6"
 890                                              : /* No outputs */
 891                                              : "r" (0),
 892                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 893
 894                         data = spitfire_get_itlb_data(i);
 895                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 896                                 unsigned long tag;
 897
 898                                 /* Spitfire Errata #32 workaround */
 899                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 900                                                      "flush     %%g6"
 901                                                      : /* No outputs */
 902                                                      : "r" (0),
 903                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 904
 905                                 tag = spitfire_get_itlb_tag(i);
 906                                 if (save_p) {
 907                                         prom_itlb[itlb_seen].tlb_ent = i;
 908                                         prom_itlb[itlb_seen].tlb_tag = tag;
 909                                         prom_itlb[itlb_seen].tlb_data = data;
 910                                 }
 911                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 912                                                      "membar #Sync"
 913                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 914                                 spitfire_put_itlb_data(i, 0x0UL);
 915
 916                                 itlb_seen++;
 917                                 if (itlb_seen > 15)
 918                                         break;
 919                         }
 920                 }
 921         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 922                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 923
 924                 for (i = 0; i < high; i++) {
 925                         unsigned long data;
 926
 927                         data = cheetah_get_ldtlb_data(i);
 928                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 929                                 unsigned long tag;
 930
 931                                 tag = cheetah_get_ldtlb_tag(i);
 932                                 if (save_p) {
 933                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 934                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 935                                         prom_dtlb[dtlb_seen].tlb_data = data;
 936                                 }
 937                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 938                                                      "membar #Sync"
 939                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 940                                 cheetah_put_ldtlb_data(i, 0x0UL);
 941
 942                                 dtlb_seen++;
 943                                 if (dtlb_seen > 15)
 944                                         break;
 945                         }
 946                 }
 947
 948                 for (i = 0; i < high; i++) {
 949                         unsigned long data;
 950
 951                         data = cheetah_get_litlb_data(i);
 952                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 953                                 unsigned long tag;
 954
 955                                 tag = cheetah_get_litlb_tag(i);
 956                                 if (save_p) {
 957                                         prom_itlb[itlb_seen].tlb_ent = i;
 958                                         prom_itlb[itlb_seen].tlb_tag = tag;
 959                                         prom_itlb[itlb_seen].tlb_data = data;
 960                                 }
 961                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 962                                                      "membar #Sync"
 963                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 964                                 cheetah_put_litlb_data(i, 0x0UL);
 965
 966                                 itlb_seen++;
 967                                 if (itlb_seen > 15)
 968                                         break;
 969                         }
 970                 }
 971         } else {
 972                 /* Implement me :-) */
 973                 BUG();
 974         }
 975         if (save_p)
 976                 prom_ditlb_set = 1;
 977 }
 978
 979 /* Give PROM back his world, done during reboots... */
 980 void prom_reload_locked(void)
 981 {
 982         int i;
 983
 984         for (i = 0; i < 16; i++) {
 985                 if (prom_dtlb[i].tlb_ent != -1) {
 986                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 987                                              "membar #Sync"
 988                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 989                                 "i" (ASI_DMMU));
 990                         if (tlb_type == spitfire)
 991                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 992                                                        prom_dtlb[i].tlb_data);
 993                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 994                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 995                                                       prom_dtlb[i].tlb_data);
 996                 }
 997
 998                 if (prom_itlb[i].tlb_ent != -1) {
 999                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1000                                              "membar #Sync"
1001                                              : : "r" (prom_itlb[i].tlb_tag),
1002                                              "r" (TLB_TAG_ACCESS),
1003                                              "i" (ASI_IMMU));
1004                         if (tlb_type == spitfire)
1005                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
1006                                                        prom_itlb[i].tlb_data);
1007                         else
1008                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
1009                                                        prom_itlb[i].tlb_data);
1010                 }
1011         }
1012 }
1013
1014 void __flush_dcache_range(unsigned long start, unsigned long end)
1015 {
1016         unsigned long va;
1017
1018         if (tlb_type == spitfire) {
1019                 int n = 0;
1020
1021                 for (va = start; va < end; va += 32) {
1022                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
1023                         if (++n >= 512)
1024                                 break;
1025                 }
1026         } else {
1027                 start = __pa(start);
1028                 end = __pa(end);
1029                 for (va = start; va < end; va += 32)
1030                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1031                                              "membar #Sync"
1032                                              : /* no outputs */
1033                                              : "r" (va),
1034                                                "i" (ASI_DCACHE_INVALIDATE));
1035         }
1036 }
1037
1038 /* If not locked, zap it. */
1039 void __flush_tlb_all(void)
1040 {
1041         unsigned long pstate;
1042         int i;
1043
1044         __asm__ __volatile__("flushw\n\t"
1045                              "rdpr      %%pstate, %0\n\t"
1046                              "wrpr      %0, %1, %%pstate"
1047                              : "=r" (pstate)
1048                              : "i" (PSTATE_IE));
1049         if (tlb_type == spitfire) {
1050                 for (i = 0; i < 64; i++) {
1051                         /* Spitfire Errata #32 workaround */
1052                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1053                                              "flush     %%g6"
1054                                              : /* No outputs */
1055                                              : "r" (0),
1056                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1057
1058                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1059                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1060                                                      "membar #Sync"
1061                                                      : /* no outputs */
1062                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1063                                 spitfire_put_dtlb_data(i, 0x0UL);
1064                         }
1065
1066                         /* Spitfire Errata #32 workaround */
1067                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1068                                              "flush     %%g6"
1069                                              : /* No outputs */
1070                                              : "r" (0),
1071                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1072
1073                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1074                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1075                                                      "membar #Sync"
1076                                                      : /* no outputs */
1077                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1078                                 spitfire_put_itlb_data(i, 0x0UL);
1079                         }
1080                 }
1081         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1082                 cheetah_flush_dtlb_all();
1083                 cheetah_flush_itlb_all();
1084         }
1085         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1086                              : : "r" (pstate));
1087 }
1088
1089 /* Caller does TLB context flushing on local CPU if necessary.
1090  * The caller also ensures that CTX_VALID(mm->context) is false.
1091  *
1092  * We must be careful about boundary cases so that we never
1093  * let the user have CTX 0 (nucleus) or we ever use a CTX
1094  * version of zero (and thus NO_CONTEXT would not be caught
1095  * by version mis-match tests in mmu_context.h).
1096  */
1097 void get_new_mmu_context(struct mm_struct *mm)
1098 {
1099         unsigned long ctx, new_ctx;
1100
1101         spin_lock(&ctx_alloc_lock);
1102         ctx = CTX_HWBITS(tlb_context_cache + 1);
1103         new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx);
1104         if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) {
1105                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1106                 if (new_ctx >= ctx) {
1107                         int i;
1108                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1109                                 CTX_FIRST_VERSION;
1110                         if (new_ctx == 1)
1111                                 new_ctx = CTX_FIRST_VERSION;
1112
1113                         /* Don't call memset, for 16 entries that's just
1114                          * plain silly...
1115                          */
1116                         mmu_context_bmap[0] = 3;
1117                         mmu_context_bmap[1] = 0;
1118                         mmu_context_bmap[2] = 0;
1119                         mmu_context_bmap[3] = 0;
1120                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1121                                 mmu_context_bmap[i + 0] = 0;
1122                                 mmu_context_bmap[i + 1] = 0;
1123                                 mmu_context_bmap[i + 2] = 0;
1124                                 mmu_context_bmap[i + 3] = 0;
1125                         }
1126                         goto out;
1127                 }
1128         }
1129         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1130         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1131 out:
1132         tlb_context_cache = new_ctx;
1133         spin_unlock(&ctx_alloc_lock);
1134
1135         mm->context = new_ctx;
1136 }
1137
1138 #ifndef CONFIG_SMP
1139 struct pgtable_cache_struct pgt_quicklists;
1140 #endif
1141
1142 /* OK, we have to color these pages. The page tables are accessed
1143  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1144  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1145  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1146  * fast handlers do not get data from old/garbage dcache lines that
1147  * correspond to an old/stale virtual address (user/kernel) that
1148  * previously mapped the pagetable page while accessing vpte range
1149  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1150  * color is the same, then when the kernel initializes the pagetable
1151  * using the later address range, accesses with the first address
1152  * range will see the newly initialized data rather than the garbage.
1153  */
1154 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1155 #define DC_ALIAS_SHIFT  1
1156 #else
1157 #define DC_ALIAS_SHIFT  0
1158 #endif
1159 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1160 {
1161         struct page *page;
1162         unsigned long color;
1163
1164         {
1165                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1166
1167                 if (ptep)
1168                         return ptep;
1169         }
1170
1171         color = VPTE_COLOR(address);
1172         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1173         if (page) {
1174                 unsigned long *to_free;
1175                 unsigned long paddr;
1176                 pte_t *pte;
1177
1178 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1179                 set_page_count(page, 1);
1180                 ClearPageCompound(page);
1181
1182                 set_page_count((page + 1), 1);
1183                 ClearPageCompound(page + 1);
1184 #endif
1185                 paddr = (unsigned long) page_address(page);
1186                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1187
1188                 if (!color) {
1189                         pte = (pte_t *) paddr;
1190                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1191                 } else {
1192                         pte = (pte_t *) (paddr + PAGE_SIZE);
1193                         to_free = (unsigned long *) paddr;
1194                 }
1195
1196 #if (L1DCACHE_SIZE > PAGE_SIZE)                 /* is there D$ aliasing problem */
1197                 /* Now free the other one up, adjust cache size. */
1198                 preempt_disable();
1199                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1200                 pte_quicklist[color ^ 0x1] = to_free;
1201                 pgtable_cache_size++;
1202                 preempt_enable();
1203 #endif
1204
1205                 return pte;
1206         }
1207         return NULL;
1208 }
1209
1210 void sparc_ultra_dump_itlb(void)
1211 {
1212         int slot;
1213
1214         if (tlb_type == spitfire) {
1215                 printk ("Contents of itlb: ");
1216                 for (slot = 0; slot < 14; slot++) printk ("    ");
1217                 printk ("%2x:%016lx,%016lx\n",
1218                         0,
1219                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1220                 for (slot = 1; slot < 64; slot+=3) {
1221                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1222                                 slot,
1223                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1224                                 slot+1,
1225                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1226                                 slot+2,
1227                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1228                 }
1229         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1230                 printk ("Contents of itlb0:\n");
1231                 for (slot = 0; slot < 16; slot+=2) {
1232                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1233                                 slot,
1234                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1235                                 slot+1,
1236                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1237                 }
1238                 printk ("Contents of itlb2:\n");
1239                 for (slot = 0; slot < 128; slot+=2) {
1240                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1241                                 slot,
1242                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1243                                 slot+1,
1244                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1245                 }
1246         }
1247 }
1248
1249 void sparc_ultra_dump_dtlb(void)
1250 {
1251         int slot;
1252
1253         if (tlb_type == spitfire) {
1254                 printk ("Contents of dtlb: ");
1255                 for (slot = 0; slot < 14; slot++) printk ("    ");
1256                 printk ("%2x:%016lx,%016lx\n", 0,
1257                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1258                 for (slot = 1; slot < 64; slot+=3) {
1259                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1260                                 slot,
1261                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1262                                 slot+1,
1263                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1264                                 slot+2,
1265                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1266                 }
1267         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1268                 printk ("Contents of dtlb0:\n");
1269                 for (slot = 0; slot < 16; slot+=2) {
1270                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1271                                 slot,
1272                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1273                                 slot+1,
1274                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1275                 }
1276                 printk ("Contents of dtlb2:\n");
1277                 for (slot = 0; slot < 512; slot+=2) {
1278                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1279                                 slot,
1280                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1281                                 slot+1,
1282                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1283                 }
1284                 if (tlb_type == cheetah_plus) {
1285                         printk ("Contents of dtlb3:\n");
1286                         for (slot = 0; slot < 512; slot+=2) {
1287                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1288                                         slot,
1289                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1290                                         slot+1,
1291                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1292                         }
1293                 }
1294         }
1295 }
1296
1297 extern unsigned long cmdline_memory_size;
1298
1299 unsigned long __init bootmem_init(unsigned long *pages_avail)
1300 {
1301         unsigned long bootmap_size, start_pfn, end_pfn;
1302         unsigned long end_of_phys_memory = 0UL;
1303         unsigned long bootmap_pfn, bytes_avail, size;
1304         int i;
1305
1306 #ifdef CONFIG_DEBUG_BOOTMEM
1307         prom_printf("bootmem_init: Scan sp_banks, ");
1308 #endif
1309
1310         bytes_avail = 0UL;
1311         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1312                 end_of_phys_memory = sp_banks[i].base_addr +
1313                         sp_banks[i].num_bytes;
1314                 bytes_avail += sp_banks[i].num_bytes;
1315                 if (cmdline_memory_size) {
1316                         if (bytes_avail > cmdline_memory_size) {
1317                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1318
1319                                 bytes_avail -= slack;
1320                                 end_of_phys_memory -= slack;
1321
1322                                 sp_banks[i].num_bytes -= slack;
1323                                 if (sp_banks[i].num_bytes == 0) {
1324                                         sp_banks[i].base_addr = 0xdeadbeef;
1325                                 } else {
1326                                         sp_banks[i+1].num_bytes = 0;
1327                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1328                                 }
1329                                 break;
1330                         }
1331                 }
1332         }
1333
1334         *pages_avail = bytes_avail >> PAGE_SHIFT;
1335
1336         /* Start with page aligned address of last symbol in kernel
1337          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1338          * 4MB locked TLB translation.
1339          */
1340         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1341
1342         bootmap_pfn = start_pfn;
1343
1344         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1345
1346 #ifdef CONFIG_BLK_DEV_INITRD
1347         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1348         if (sparc_ramdisk_image) {
1349                 if (sparc_ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1350                         sparc_ramdisk_image -= KERNBASE;
1351                 initrd_start = sparc_ramdisk_image + phys_base;
1352                 initrd_end = initrd_start + sparc_ramdisk_size;
1353                 if (initrd_end > end_of_phys_memory) {
1354                         printk(KERN_CRIT "initrd extends beyond end of memory "
1355                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1356                                initrd_end, end_of_phys_memory);
1357                         initrd_start = 0;
1358                 }
1359                 if (initrd_start) {
1360                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1361                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1362                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1363                 }
1364         }
1365 #endif
1366         /* Initialize the boot-time allocator. */
1367         max_pfn = max_low_pfn = end_pfn;
1368         min_low_pfn = pfn_base;
1369
1370 #ifdef CONFIG_DEBUG_BOOTMEM
1371         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1372                     min_low_pfn, bootmap_pfn, max_low_pfn);
1373 #endif
1374         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1375
1376         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1377
1378         /* Now register the available physical memory with the
1379          * allocator.
1380          */
1381         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1382 #ifdef CONFIG_DEBUG_BOOTMEM
1383                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1384                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1385 #endif
1386                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1387         }
1388
1389 #ifdef CONFIG_BLK_DEV_INITRD
1390         if (initrd_start) {
1391                 size = initrd_end - initrd_start;
1392
1393                 /* Resert the initrd image area. */
1394                 reserve_bootmem(initrd_start, size);
1395                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1396
1397                 initrd_start += PAGE_OFFSET;
1398                 initrd_end += PAGE_OFFSET;
1399         }
1400 #endif
1401         /* Reserve the kernel text/data/bss. */
1402 #ifdef CONFIG_DEBUG_BOOTMEM
1403         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1404 #endif
1405         reserve_bootmem(kern_base, kern_size);
1406         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1407
1408         /* Reserve the bootmem map.   We do not account for it
1409          * in pages_avail because we will release that memory
1410          * in free_all_bootmem.
1411          */
1412         size = bootmap_size;
1413 #ifdef CONFIG_DEBUG_BOOTMEM
1414         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1415                     (bootmap_pfn << PAGE_SHIFT), size);
1416 #endif
1417         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1418         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1419
1420         return end_pfn;
1421 }
1422
1423 /* paging_init() sets up the page tables */
1424
1425 extern void cheetah_ecache_flush_init(void);
1426
1427 static unsigned long last_valid_pfn;
1428
1429 void __init paging_init(void)
1430 {
1431         extern pmd_t swapper_pmd_dir[1024];
1432         extern unsigned int sparc64_vpte_patchme1[1];
1433         extern unsigned int sparc64_vpte_patchme2[1];
1434         unsigned long alias_base = kern_base + PAGE_OFFSET;
1435         unsigned long second_alias_page = 0;
1436         unsigned long pt, flags, end_pfn, pages_avail;
1437         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1438         unsigned long real_end;
1439
1440         set_bit(0, mmu_context_bmap);
1441
1442         real_end = (unsigned long)_end;
1443         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1444                 bigkernel = 1;
1445 #ifdef CONFIG_BLK_DEV_INITRD
1446         if (sparc_ramdisk_image)
1447                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1448 #endif
1449
1450         /* We assume physical memory starts at some 4mb multiple,
1451          * if this were not true we wouldn't boot up to this point
1452          * anyways.
1453          */
1454         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1455         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1456         local_irq_save(flags);
1457         if (tlb_type == spitfire) {
1458                 __asm__ __volatile__(
1459         "       stxa    %1, [%0] %3\n"
1460         "       stxa    %2, [%5] %4\n"
1461         "       membar  #Sync\n"
1462         "       flush   %%g6\n"
1463         "       nop\n"
1464         "       nop\n"
1465         "       nop\n"
1466                 : /* No outputs */
1467                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1468                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1469                 : "memory");
1470                 if (real_end >= KERNBASE + 0x340000) {
1471                         second_alias_page = alias_base + 0x400000;
1472                         __asm__ __volatile__(
1473                 "       stxa    %1, [%0] %3\n"
1474                 "       stxa    %2, [%5] %4\n"
1475                 "       membar  #Sync\n"
1476                 "       flush   %%g6\n"
1477                 "       nop\n"
1478                 "       nop\n"
1479                 "       nop\n"
1480                         : /* No outputs */
1481                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1482                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1483                         : "memory");
1484                 }
1485         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1486                 __asm__ __volatile__(
1487         "       stxa    %1, [%0] %3\n"
1488         "       stxa    %2, [%5] %4\n"
1489         "       membar  #Sync\n"
1490         "       flush   %%g6\n"
1491         "       nop\n"
1492         "       nop\n"
1493         "       nop\n"
1494                 : /* No outputs */
1495                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1496                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1497                 : "memory");
1498                 if (real_end >= KERNBASE + 0x340000) {
1499                         second_alias_page = alias_base + 0x400000;
1500                         __asm__ __volatile__(
1501                 "       stxa    %1, [%0] %3\n"
1502                 "       stxa    %2, [%5] %4\n"
1503                 "       membar  #Sync\n"
1504                 "       flush   %%g6\n"
1505                 "       nop\n"
1506                 "       nop\n"
1507                 "       nop\n"
1508                         : /* No outputs */
1509                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1510                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1511                         : "memory");
1512                 }
1513         }
1514         local_irq_restore(flags);
1515
1516         /* Now set kernel pgd to upper alias so physical page computations
1517          * work.
1518          */
1519         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1520
1521         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1522
1523         /* Now can init the kernel/bad page tables. */
1524         pgd_set(&swapper_pg_dir[0], swapper_pmd_dir + (shift / sizeof(pgd_t)));
1525
1526         sparc64_vpte_patchme1[0] |=
1527                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1528         sparc64_vpte_patchme2[0] |=
1529                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1530         flushi((long)&sparc64_vpte_patchme1[0]);
1531
1532         /* Setup bootmem... */
1533         pages_avail = 0;
1534         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1535
1536         /* Inherit non-locked OBP mappings. */
1537         inherit_prom_mappings();
1538
1539         /* Ok, we can use our TLB miss and window trap handlers safely.
1540          * We need to do a quick peek here to see if we are on StarFire
1541          * or not, so setup_tba can setup the IRQ globals correctly (it
1542          * needs to get the hard smp processor id correctly).
1543          */
1544         {
1545                 extern void setup_tba(int);
1546                 setup_tba(this_is_starfire);
1547         }
1548
1549         inherit_locked_prom_mappings(1);
1550
1551         /* We only created DTLB mapping of this stuff. */
1552         spitfire_flush_dtlb_nucleus_page(alias_base);
1553         if (second_alias_page)
1554                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1555
1556         __flush_tlb_all();
1557
1558         {
1559                 unsigned long zones_size[MAX_NR_ZONES];
1560                 unsigned long zholes_size[MAX_NR_ZONES];
1561                 unsigned long npages;
1562                 int znum;
1563
1564                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1565                         zones_size[znum] = zholes_size[znum] = 0;
1566
1567                 npages = end_pfn - pfn_base;
1568                 zones_size[ZONE_DMA] = npages;
1569                 zholes_size[ZONE_DMA] = npages - pages_avail;
1570
1571                 free_area_init_node(0, &contig_page_data, NULL, zones_size,
1572                                     phys_base >> PAGE_SHIFT, zholes_size);
1573                 mem_map = contig_page_data.node_mem_map;
1574         }
1575
1576         device_scan();
1577 }
1578
1579 /* Ok, it seems that the prom can allocate some more memory chunks
1580  * as a side effect of some prom calls we perform during the
1581  * boot sequence.  My most likely theory is that it is from the
1582  * prom_set_traptable() call, and OBP is allocating a scratchpad
1583  * for saving client program register state etc.
1584  */
1585 void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1586 {
1587         int swapi = 0;
1588         int i, mitr;
1589         unsigned long tmpaddr, tmpsize;
1590         unsigned long lowest;
1591
1592         for (i = 0; thislist[i].theres_more != 0; i++) {
1593                 lowest = thislist[i].start_adr;
1594                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1595                         if (thislist[mitr].start_adr < lowest) {
1596                                 lowest = thislist[mitr].start_adr;
1597                                 swapi = mitr;
1598                         }
1599                 if (lowest == thislist[i].start_adr)
1600                         continue;
1601                 tmpaddr = thislist[swapi].start_adr;
1602                 tmpsize = thislist[swapi].num_bytes;
1603                 for (mitr = swapi; mitr > i; mitr--) {
1604                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1605                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1606                 }
1607                 thislist[i].start_adr = tmpaddr;
1608                 thislist[i].num_bytes = tmpsize;
1609         }
1610 }
1611
1612 void __init rescan_sp_banks(void)
1613 {
1614         struct linux_prom64_registers memlist[64];
1615         struct linux_mlist_p1275 avail[64], *mlist;
1616         unsigned long bytes, base_paddr;
1617         int num_regs, node = prom_finddevice("/memory");
1618         int i;
1619
1620         num_regs = prom_getproperty(node, "available",
1621                                     (char *) memlist, sizeof(memlist));
1622         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1623         for (i = 0; i < num_regs; i++) {
1624                 avail[i].start_adr = memlist[i].phys_addr;
1625                 avail[i].num_bytes = memlist[i].reg_size;
1626                 avail[i].theres_more = &avail[i + 1];
1627         }
1628         avail[i - 1].theres_more = NULL;
1629         sort_memlist(avail);
1630
1631         mlist = &avail[0];
1632         i = 0;
1633         bytes = mlist->num_bytes;
1634         base_paddr = mlist->start_adr;
1635
1636         sp_banks[0].base_addr = base_paddr;
1637         sp_banks[0].num_bytes = bytes;
1638
1639         while (mlist->theres_more != NULL){
1640                 i++;
1641                 mlist = mlist->theres_more;
1642                 bytes = mlist->num_bytes;
1643                 if (i >= SPARC_PHYS_BANKS-1) {
1644                         printk ("The machine has more banks than "
1645                                 "this kernel can support\n"
1646                                 "Increase the SPARC_PHYS_BANKS "
1647                                 "setting (currently %d)\n",
1648                                 SPARC_PHYS_BANKS);
1649                         i = SPARC_PHYS_BANKS-1;
1650                         break;
1651                 }
1652
1653                 sp_banks[i].base_addr = mlist->start_adr;
1654                 sp_banks[i].num_bytes = mlist->num_bytes;
1655         }
1656
1657         i++;
1658         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1659         sp_banks[i].num_bytes = 0;
1660
1661         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1662                 sp_banks[i].num_bytes &= PAGE_MASK;
1663 }
1664
1665 static void __init taint_real_pages(void)
1666 {
1667         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1668         int i;
1669
1670         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1671                 saved_sp_banks[i].base_addr =
1672                         sp_banks[i].base_addr;
1673                 saved_sp_banks[i].num_bytes =
1674                         sp_banks[i].num_bytes;
1675         }
1676
1677         rescan_sp_banks();
1678
1679         /* Find changes discovered in the sp_bank rescan and
1680          * reserve the lost portions in the bootmem maps.
1681          */
1682         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1683                 unsigned long old_start, old_end;
1684
1685                 old_start = saved_sp_banks[i].base_addr;
1686                 old_end = old_start +
1687                         saved_sp_banks[i].num_bytes;
1688                 while (old_start < old_end) {
1689                         int n;
1690
1691                         for (n = 0; sp_banks[n].num_bytes; n++) {
1692                                 unsigned long new_start, new_end;
1693
1694                                 new_start = sp_banks[n].base_addr;
1695                                 new_end = new_start + sp_banks[n].num_bytes;
1696
1697                                 if (new_start <= old_start &&
1698                                     new_end >= (old_start + PAGE_SIZE)) {
1699                                         set_bit (old_start >> 22,
1700                                                  sparc64_valid_addr_bitmap);
1701                                         goto do_next_page;
1702                                 }
1703                         }
1704                         reserve_bootmem(old_start, PAGE_SIZE);
1705
1706                 do_next_page:
1707                         old_start += PAGE_SIZE;
1708                 }
1709         }
1710 }
1711
1712 void __init mem_init(void)
1713 {
1714         unsigned long codepages, datapages, initpages;
1715         unsigned long addr, last;
1716         int i;
1717
1718         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1719         i += 1;
1720         sparc64_valid_addr_bitmap = (unsigned long *)
1721                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1722         if (sparc64_valid_addr_bitmap == NULL) {
1723                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1724                 prom_halt();
1725         }
1726         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1727
1728         addr = PAGE_OFFSET + kern_base;
1729         last = PAGE_ALIGN(kern_size) + addr;
1730         while (addr < last) {
1731                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1732                 addr += PAGE_SIZE;
1733         }
1734
1735         taint_real_pages();
1736
1737         max_mapnr = last_valid_pfn - pfn_base;
1738         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1739
1740 #ifdef CONFIG_DEBUG_BOOTMEM
1741         prom_printf("mem_init: Calling free_all_bootmem().\n");
1742 #endif
1743         totalram_pages = num_physpages = free_all_bootmem() - 1;
1744
1745         /*
1746          * Set up the zero page, mark it reserved, so that page count
1747          * is not manipulated when freeing the page from user ptes.
1748          */
1749         mem_map_zero = alloc_pages(GFP_KERNEL, 0);
1750         if (mem_map_zero == NULL) {
1751                 prom_printf("paging_init: Cannot alloc zero page.\n");
1752                 prom_halt();
1753         }
1754         SetPageReserved(mem_map_zero);
1755         clear_page(page_address(mem_map_zero));
1756
1757         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1758         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1759         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1760         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1761         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1762         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1763
1764 #ifndef CONFIG_SMP
1765         {
1766                 /* Put empty_pg_dir on pgd_quicklist */
1767                 extern pgd_t empty_pg_dir[1024];
1768                 unsigned long addr = (unsigned long)empty_pg_dir;
1769                 unsigned long alias_base = kern_base + PAGE_OFFSET -
1770                         (long)(KERNBASE);
1771
1772                 memset(empty_pg_dir, 0, sizeof(empty_pg_dir));
1773                 addr += alias_base;
1774                 free_pgd_fast((pgd_t *)addr);
1775                 num_physpages++;
1776                 totalram_pages++;
1777         }
1778 #endif
1779
1780         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1781                nr_free_pages() << (PAGE_SHIFT-10),
1782                codepages << (PAGE_SHIFT-10),
1783                datapages << (PAGE_SHIFT-10),
1784                initpages << (PAGE_SHIFT-10),
1785                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1786
1787         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1788                 cheetah_ecache_flush_init();
1789 }
1790
1791 void free_initmem (void)
1792 {
1793         unsigned long addr, initend;
1794
1795         /*
1796          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1797          */
1798         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1799         initend = (unsigned long)(__init_end) & PAGE_MASK;
1800         for (; addr < initend; addr += PAGE_SIZE) {
1801                 unsigned long page;
1802                 struct page *p;
1803
1804                 page = (addr +
1805                         ((unsigned long) __va(kern_base)) -
1806                         ((unsigned long) KERNBASE));
1807                 p = virt_to_page(page);
1808
1809                 ClearPageReserved(p);
1810                 set_page_count(p, 1);
1811                 __free_page(p);
1812                 num_physpages++;
1813                 totalram_pages++;
1814         }
1815 }
1816
1817 #ifdef CONFIG_BLK_DEV_INITRD
1818 void free_initrd_mem(unsigned long start, unsigned long end)
1819 {
1820         if (start < end)
1821                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1822         for (; start < end; start += PAGE_SIZE) {
1823                 struct page *p = virt_to_page(start);
1824
1825                 ClearPageReserved(p);
1826                 set_page_count(p, 1);
1827                 __free_page(p);
1828                 num_physpages++;
1829                 totalram_pages++;
1830         }
1831 }
1832 #endif