1 /* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $
2 * ultra.S: Don't expand these all over the place...
4 * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com)
7 #include <linux/config.h>
9 #include <asm/pgtable.h>
11 #include <asm/spitfire.h>
12 #include <asm/mmu_context.h>
15 #include <asm/thread_info.h>
17 /* Basically, most of the Spitfire vs. Cheetah madness
18 * has to do with the fact that Cheetah does not support
19 * IMMU flushes out of the secondary context. Someone needs
20 * to throw a south lake birthday party for the folks
21 * in Microelectronics who refused to fix this shit.
24 /* This file is meant to be read efficiently by the CPU, not humans.
25 * Staraj sie tego nikomu nie pierdolnac...
30 __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
31 ldxa [%o1] ASI_DMMU, %g2
33 bne,pn %icc, __spitfire_flush_tlb_mm_slow
35 stxa %g0, [%g3] ASI_DMMU_DEMAP
36 stxa %g0, [%g3] ASI_IMMU_DEMAP
49 .globl __flush_tlb_pending
51 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
54 andn %g5, PSTATE_IE, %g2
56 mov SECONDARY_CONTEXT, %o4
57 ldxa [%o4] ASI_DMMU, %g2
58 stxa %o0, [%o4] ASI_DMMU
59 1: sub %o1, (1 << 3), %o1
65 stxa %g0, [%o3] ASI_IMMU_DEMAP
66 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
70 stxa %g2, [%o4] ASI_DMMU
73 wrpr %g5, 0x0, %pstate
76 .globl __flush_tlb_kernel_range
77 __flush_tlb_kernel_range: /* %o0=start, %o1=end */
80 sethi %hi(PAGE_SIZE), %o4
83 or %o0, 0x20, %o0 ! Nucleus
84 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
85 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
92 __spitfire_flush_tlb_mm_slow:
94 wrpr %g1, PSTATE_IE, %pstate
95 stxa %o0, [%o1] ASI_DMMU
96 stxa %g0, [%g3] ASI_DMMU_DEMAP
97 stxa %g0, [%g3] ASI_IMMU_DEMAP
99 stxa %g2, [%o1] ASI_DMMU
105 * The following code flushes one page_size worth.
107 #if (PAGE_SHIFT == 13)
108 #define ITAG_MASK 0xfe
109 #elif (PAGE_SHIFT == 16)
110 #define ITAG_MASK 0x7fe
112 #error unsupported PAGE_SIZE
115 .globl __flush_icache_page
116 __flush_icache_page: /* %o0 = phys_page */
117 sethi %hi(1 << 13), %o2 ! IC_set bit
122 ldda [%o1] ASI_IC_TAG, %o4
124 or %o0, %g1, %o0 ! VALID+phys-addr comparitor
127 andn %g2, ITAG_MASK, %g2 ! IC_tag mask
135 1: addx %g0, %g0, %g0
136 ldda [%o1 + %o2] ASI_IC_TAG, %g4
141 ldda [%o1] ASI_IC_TAG, %o4
154 ldx [%g6 + TI_TASK], %g4
156 iflush1:sub %o1, 0x20, %g3
157 stxa %g0, [%g3] ASI_IC_TAG
160 iflush2:sub %o1, 0x20, %g3
161 stxa %g0, [%o1 + %o2] ASI_IC_TAG
165 #if (PAGE_SHIFT == 13)
166 #define DTAG_MASK 0x3
167 #elif (PAGE_SHIFT == 16)
168 #define DTAG_MASK 0x1f
169 #elif (PAGE_SHIFT == 19)
170 #define DTAG_MASK 0xff
171 #elif (PAGE_SHIFT == 22)
172 #define DTAG_MASK 0x3ff
176 .globl __flush_dcache_page
177 __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
178 sethi %uhi(PAGE_OFFSET), %g1
183 sethi %hi(1 << 14), %o2
184 1: ldxa [%o4] ASI_DCACHE_TAG, %o3 ! LSU Group
185 add %o4, (1 << 5), %o4 ! IEU0
186 ldxa [%o4] ASI_DCACHE_TAG, %g1 ! LSU Group
187 add %o4, (1 << 5), %o4 ! IEU0
188 ldxa [%o4] ASI_DCACHE_TAG, %g2 ! LSU Group o3 available
189 add %o4, (1 << 5), %o4 ! IEU0
190 andn %o3, DTAG_MASK, %o3 ! IEU1
191 ldxa [%o4] ASI_DCACHE_TAG, %g3 ! LSU Group
192 add %o4, (1 << 5), %o4 ! IEU0
193 andn %g1, DTAG_MASK, %g1 ! IEU1
194 cmp %o0, %o3 ! IEU1 Group
195 be,a,pn %xcc, dflush1 ! CTI
196 sub %o4, (4 << 5), %o4 ! IEU0 (Group)
197 cmp %o0, %g1 ! IEU1 Group
198 andn %g2, DTAG_MASK, %g2 ! IEU0
199 be,a,pn %xcc, dflush2 ! CTI
200 sub %o4, (3 << 5), %o4 ! IEU0 (Group)
201 cmp %o0, %g2 ! IEU1 Group
202 andn %g3, DTAG_MASK, %g3 ! IEU0
203 be,a,pn %xcc, dflush3 ! CTI
204 sub %o4, (2 << 5), %o4 ! IEU0 (Group)
205 cmp %o0, %g3 ! IEU1 Group
206 be,a,pn %xcc, dflush4 ! CTI
207 sub %o4, (1 << 5), %o4 ! IEU0
208 2: cmp %o4, %o2 ! IEU1 Group
209 bne,pt %xcc, 1b ! CTI
212 /* The I-cache does not snoop local stores so we
213 * better flush that too when necessary.
215 brnz,pt %o1, __flush_icache_page
220 dflush1:stxa %g0, [%o4] ASI_DCACHE_TAG
221 add %o4, (1 << 5), %o4
222 dflush2:stxa %g0, [%o4] ASI_DCACHE_TAG
223 add %o4, (1 << 5), %o4
224 dflush3:stxa %g0, [%o4] ASI_DCACHE_TAG
225 add %o4, (1 << 5), %o4
226 dflush4:stxa %g0, [%o4] ASI_DCACHE_TAG
227 add %o4, (1 << 5), %o4
235 wrpr %g7, PSTATE_IE, %pstate
236 mov TLB_TAG_ACCESS, %g1
237 stxa %o5, [%g1] ASI_DMMU
238 stxa %o2, [%g0] ASI_DTLB_DATA_IN
244 wrpr %g7, PSTATE_IE, %pstate
245 mov TLB_TAG_ACCESS, %g1
246 stxa %o5, [%g1] ASI_IMMU
247 stxa %o2, [%g0] ASI_ITLB_DATA_IN
252 .globl __update_mmu_cache
253 __update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
254 srlx %o1, PAGE_SHIFT, %o1
255 andcc %o3, FAULT_CODE_DTLB, %g0
256 sllx %o1, PAGE_SHIFT, %o5
257 bne,pt %xcc, __prefill_dtlb
259 ba,a,pt %xcc, __prefill_itlb
261 /* Cheetah specific versions, patched at boot time. */
262 __cheetah_flush_tlb_mm: /* 15 insns */
264 andn %g5, PSTATE_IE, %g2
265 wrpr %g2, 0x0, %pstate
267 mov PRIMARY_CONTEXT, %o2
269 ldxa [%o2] ASI_DMMU, %g2
270 stxa %o0, [%o2] ASI_DMMU
271 stxa %g0, [%g3] ASI_DMMU_DEMAP
272 stxa %g0, [%g3] ASI_IMMU_DEMAP
273 stxa %g2, [%o2] ASI_DMMU
277 wrpr %g5, 0x0, %pstate
279 __cheetah_flush_tlb_pending: /* 22 insns */
280 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
283 andn %g5, PSTATE_IE, %g2
284 wrpr %g2, 0x0, %pstate
286 mov PRIMARY_CONTEXT, %o4
287 ldxa [%o4] ASI_DMMU, %g2
288 stxa %o0, [%o4] ASI_DMMU
289 1: sub %o1, (1 << 3), %o1
294 stxa %g0, [%o3] ASI_IMMU_DEMAP
295 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
298 stxa %g2, [%o4] ASI_DMMU
302 wrpr %g5, 0x0, %pstate
304 flush_dcpage_cheetah: /* 11 insns */
305 sethi %uhi(PAGE_OFFSET), %g1
308 sethi %hi(PAGE_SIZE), %o4
309 1: subcc %o4, (1 << 5), %o4
310 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
314 retl /* I-cache flush never needed on Cheetah, see callers. */
328 .globl cheetah_patch_cachetlbops
329 cheetah_patch_cachetlbops:
332 sethi %hi(__flush_tlb_mm), %o0
333 or %o0, %lo(__flush_tlb_mm), %o0
334 sethi %hi(__cheetah_flush_tlb_mm), %o1
335 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
336 call cheetah_patch_one
339 sethi %hi(__flush_tlb_pending), %o0
340 or %o0, %lo(__flush_tlb_pending), %o0
341 sethi %hi(__cheetah_flush_tlb_pending), %o1
342 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
343 call cheetah_patch_one
346 sethi %hi(__flush_dcache_page), %o0
347 or %o0, %lo(__flush_dcache_page), %o0
348 sethi %hi(flush_dcpage_cheetah), %o1
349 or %o1, %lo(flush_dcpage_cheetah), %o1
350 call cheetah_patch_one
357 /* These are all called by the slaves of a cross call, at
358 * trap level 1, with interrupts fully disabled.
361 * %g5 mm->context (all tlb flushes)
362 * %g1 address arg 1 (tlb page and range flushes)
363 * %g7 address arg 2 (tlb range flush only)
365 * %g6 ivector table, don't touch
370 * TODO: Make xcall TLB range flushes use the tricks above... -DaveM
373 .globl xcall_flush_tlb_mm
375 mov PRIMARY_CONTEXT, %g2
377 ldxa [%g2] ASI_DMMU, %g3
378 stxa %g5, [%g2] ASI_DMMU
379 stxa %g0, [%g4] ASI_DMMU_DEMAP
380 stxa %g0, [%g4] ASI_IMMU_DEMAP
381 stxa %g3, [%g2] ASI_DMMU
384 .globl xcall_flush_tlb_pending
385 xcall_flush_tlb_pending:
386 /* %g5=context, %g1=nr, %g7=vaddrs[] */
388 mov PRIMARY_CONTEXT, %g4
389 ldxa [%g4] ASI_DMMU, %g2
390 stxa %g5, [%g4] ASI_DMMU
391 1: sub %g1, (1 << 3), %g1
397 stxa %g0, [%g5] ASI_IMMU_DEMAP
398 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
402 stxa %g2, [%g4] ASI_DMMU
405 .globl xcall_flush_tlb_kernel_range
406 xcall_flush_tlb_kernel_range:
407 sethi %hi(PAGE_SIZE - 1), %g2
408 or %g2, %lo(PAGE_SIZE - 1), %g2
414 or %g1, 0x20, %g1 ! Nucleus
415 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
416 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
424 /* This runs in a very controlled environment, so we do
425 * not need to worry about BH races etc.
427 .globl xcall_sync_tick
430 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
435 109: or %g7, %lo(109b), %g7
436 call smp_synchronize_tick_client
440 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
442 /* NOTE: This is SPECIAL!! We do etrap/rtrap however
443 * we choose to deal with the "BH's run with
444 * %pil==15" problem (described in asm/pil.h)
445 * by just invoking rtrap directly past where
446 * BH's are checked for.
448 * We do it like this because we do not want %pil==15
449 * lockups to prevent regs being reported.
451 .globl xcall_report_regs
454 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
459 109: or %g7, %lo(109b), %g7
461 add %sp, PTREGS_OFF, %o0
463 /* Has to be a non-v9 branch due to the large distance. */
465 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
468 .globl xcall_flush_dcache_page_cheetah
469 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
470 sethi %hi(PAGE_SIZE), %g3
471 1: subcc %g3, (1 << 5), %g3
472 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
479 .globl xcall_flush_dcache_page_spitfire
480 xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
481 %g7 == kernel page virtual address
482 %g5 == (page->mapping != NULL) */
483 #if (L1DCACHE_SIZE > PAGE_SIZE)
484 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
485 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
486 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
487 1: ldxa [%g3] ASI_DCACHE_TAG, %g2
495 stxa %g0, [%g3] ASI_DCACHE_TAG
499 sub %g3, (1 << 5), %g3
502 #endif /* L1DCACHE_SIZE > PAGE_SIZE */
503 sethi %hi(PAGE_SIZE), %g3
506 subcc %g3, (1 << 5), %g3
508 add %g7, (1 << 5), %g7
514 .globl xcall_promstop
517 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
522 109: or %g7, %lo(109b), %g7
526 /* We should not return, just spin if we do... */
537 /* These two are not performance critical... */
538 .globl xcall_flush_tlb_all_spitfire
539 xcall_flush_tlb_all_spitfire:
540 /* Spitfire Errata #32 workaround. */
541 sethi %hi(errata32_hwbug), %g4
542 stx %g0, [%g4 + %lo(errata32_hwbug)]
546 1: ldxa [%g3] ASI_DTLB_DATA_ACCESS, %g4
547 and %g4, _PAGE_L, %g5
549 mov TLB_TAG_ACCESS, %g7
551 stxa %g0, [%g7] ASI_DMMU
553 stxa %g0, [%g3] ASI_DTLB_DATA_ACCESS
556 /* Spitfire Errata #32 workaround. */
557 sethi %hi(errata32_hwbug), %g4
558 stx %g0, [%g4 + %lo(errata32_hwbug)]
560 2: ldxa [%g3] ASI_ITLB_DATA_ACCESS, %g4
561 and %g4, _PAGE_L, %g5
563 mov TLB_TAG_ACCESS, %g7
565 stxa %g0, [%g7] ASI_IMMU
567 stxa %g0, [%g3] ASI_ITLB_DATA_ACCESS
570 /* Spitfire Errata #32 workaround. */
571 sethi %hi(errata32_hwbug), %g4
572 stx %g0, [%g4 + %lo(errata32_hwbug)]
575 cmp %g2, SPITFIRE_HIGHEST_LOCKED_TLBENT
581 .globl xcall_flush_tlb_all_cheetah
582 xcall_flush_tlb_all_cheetah:
584 stxa %g0, [%g2] ASI_DMMU_DEMAP
585 stxa %g0, [%g2] ASI_IMMU_DEMAP
588 /* These just get rescheduled to PIL vectors. */
589 .globl xcall_call_function
591 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
594 .globl xcall_receive_signal
595 xcall_receive_signal:
596 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
601 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
604 #endif /* CONFIG_SMP */