2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
51 [0 ... FIRST_EXTERNAL_VECTOR - 1] = -1,
52 [FIRST_EXTERNAL_VECTOR + 0] = 0,
53 [FIRST_EXTERNAL_VECTOR + 1] = 1,
54 [FIRST_EXTERNAL_VECTOR + 2] = 2,
55 [FIRST_EXTERNAL_VECTOR + 3] = 3,
56 [FIRST_EXTERNAL_VECTOR + 4] = 4,
57 [FIRST_EXTERNAL_VECTOR + 5] = 5,
58 [FIRST_EXTERNAL_VECTOR + 6] = 6,
59 [FIRST_EXTERNAL_VECTOR + 7] = 7,
60 [FIRST_EXTERNAL_VECTOR + 8] = 8,
61 [FIRST_EXTERNAL_VECTOR + 9] = 9,
62 [FIRST_EXTERNAL_VECTOR + 10] = 10,
63 [FIRST_EXTERNAL_VECTOR + 11] = 11,
64 [FIRST_EXTERNAL_VECTOR + 12] = 12,
65 [FIRST_EXTERNAL_VECTOR + 13] = 13,
66 [FIRST_EXTERNAL_VECTOR + 14] = 14,
67 [FIRST_EXTERNAL_VECTOR + 15] = 15,
68 [FIRST_EXTERNAL_VECTOR + 16 ... NR_VECTORS - 1] = -1
71 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
73 #define __apicdebuginit __init
75 int sis_apic_bug; /* not actually supported, dummy for compile */
77 static int no_timer_check;
79 static int disable_timer_pin_1 __initdata;
81 int timer_over_8254 __initdata = 1;
84 /* Where if anywhere is the i8259 connect in external int mode */
85 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
88 static DEFINE_SPINLOCK(ioapic_lock);
89 DEFINE_SPINLOCK(vector_lock);
92 * # of IRQ routing registers
94 int nr_ioapic_registers[MAX_IO_APICS];
97 * Rough estimation of how many shared IRQs there are, can
100 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
101 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
104 * This is performance-critical, we want to do it O(1)
106 * the indexing order of this array favors 1:1 mappings
107 * between pins and IRQs.
110 static struct irq_pin_list {
111 short apic, pin, next;
112 } irq_2_pin[PIN_MAP_SIZE];
116 unsigned int unused[3];
120 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
122 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
123 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
126 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
128 struct io_apic __iomem *io_apic = io_apic_base(apic);
129 writel(reg, &io_apic->index);
130 return readl(&io_apic->data);
133 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
135 struct io_apic __iomem *io_apic = io_apic_base(apic);
136 writel(reg, &io_apic->index);
137 writel(value, &io_apic->data);
141 * Re-write a value: to be used for read-modify-write
142 * cycles where the read already set up the index register.
144 static inline void io_apic_modify(unsigned int apic, unsigned int value)
146 struct io_apic __iomem *io_apic = io_apic_base(apic);
147 writel(value, &io_apic->data);
151 * Synchronize the IO-APIC and the CPU by doing
152 * a dummy read from the IO-APIC
154 static inline void io_apic_sync(unsigned int apic)
156 struct io_apic __iomem *io_apic = io_apic_base(apic);
157 readl(&io_apic->data);
162 #include <xen/interface/xen.h>
163 #include <xen/interface/physdev.h>
166 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
167 #define disable_8259A_irq(_irq) ((void)0)
168 #define i8259A_irq_pending(_irq) (0)
170 unsigned long io_apic_irqs;
172 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
174 struct physdev_apic apic_op;
177 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
179 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
182 return apic_op.value;
185 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
187 struct physdev_apic apic_op;
189 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
191 apic_op.value = value;
192 HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
195 #define io_apic_read(a,r) xen_io_apic_read(a,r)
196 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
198 #define clear_IO_APIC() ((void)0)
202 #define __DO_ACTION(R, ACTION, FINAL) \
206 struct irq_pin_list *entry = irq_2_pin + irq; \
208 BUG_ON(irq >= NR_IRQS); \
214 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
216 io_apic_modify(entry->apic, reg); \
219 entry = irq_2_pin + entry->next; \
223 #endif /* !CONFIG_XEN */
226 struct { u32 w1, w2; };
227 struct IO_APIC_route_entry entry;
230 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
232 union entry_union eu;
234 spin_lock_irqsave(&ioapic_lock, flags);
235 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
236 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
237 spin_unlock_irqrestore(&ioapic_lock, flags);
242 * When we write a new IO APIC routing entry, we need to write the high
243 * word first! If the mask bit in the low word is clear, we will enable
244 * the interrupt, and we need to make sure the entry is fully populated
245 * before that happens.
248 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
250 union entry_union eu;
252 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
253 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
256 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
259 spin_lock_irqsave(&ioapic_lock, flags);
260 __ioapic_write_entry(apic, pin, e);
261 spin_unlock_irqrestore(&ioapic_lock, flags);
265 * When we mask an IO APIC routing entry, we need to write the low
266 * word first, in order to set the mask bit before we change the
270 static void ioapic_mask_entry(int apic, int pin)
273 union entry_union eu = { .entry.mask = 1 };
275 spin_lock_irqsave(&ioapic_lock, flags);
276 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
277 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
278 spin_unlock_irqrestore(&ioapic_lock, flags);
282 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
285 struct irq_pin_list *entry = irq_2_pin + irq;
287 BUG_ON(irq >= NR_IRQS);
294 io_apic_write(apic, 0x11 + pin*2, dest);
295 reg = io_apic_read(apic, 0x10 + pin*2);
298 io_apic_modify(apic, reg);
301 entry = irq_2_pin + entry->next;
305 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
312 cpus_and(tmp, mask, cpu_online_map);
316 cpus_and(mask, tmp, CPU_MASK_ALL);
318 vector = assign_irq_vector(irq, mask, &tmp);
322 dest = cpu_mask_to_apicid(tmp);
325 * Only the high 8 bits are valid.
327 dest = SET_APIC_LOGICAL_ID(dest);
329 spin_lock_irqsave(&ioapic_lock, flags);
330 __target_IO_APIC_irq(irq, dest, vector);
331 set_native_irq_info(irq, mask);
332 spin_unlock_irqrestore(&ioapic_lock, flags);
335 #endif /* !CONFIG_XEN */
338 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
339 * shared ISA-space IRQs, so we have to support them. We are super
340 * fast in the common case, and fast for shared ISA-space IRQs.
342 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
344 static int first_free_entry = NR_IRQS;
345 struct irq_pin_list *entry = irq_2_pin + irq;
347 BUG_ON(irq >= NR_IRQS);
349 entry = irq_2_pin + entry->next;
351 if (entry->pin != -1) {
352 entry->next = first_free_entry;
353 entry = irq_2_pin + entry->next;
354 if (++first_free_entry >= PIN_MAP_SIZE)
355 panic("io_apic.c: ran out of irq_2_pin entries!");
363 #define DO_ACTION(name,R,ACTION, FINAL) \
365 static void name##_IO_APIC_irq (unsigned int irq) \
366 __DO_ACTION(R, ACTION, FINAL)
368 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
370 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
373 static void mask_IO_APIC_irq (unsigned int irq)
377 spin_lock_irqsave(&ioapic_lock, flags);
378 __mask_IO_APIC_irq(irq);
379 spin_unlock_irqrestore(&ioapic_lock, flags);
382 static void unmask_IO_APIC_irq (unsigned int irq)
386 spin_lock_irqsave(&ioapic_lock, flags);
387 __unmask_IO_APIC_irq(irq);
388 spin_unlock_irqrestore(&ioapic_lock, flags);
391 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
393 struct IO_APIC_route_entry entry;
395 /* Check delivery_mode to be sure we're not clearing an SMI pin */
396 entry = ioapic_read_entry(apic, pin);
397 if (entry.delivery_mode == dest_SMI)
400 * Disable it in the IO-APIC irq-routing table:
402 ioapic_mask_entry(apic, pin);
405 static void clear_IO_APIC (void)
409 for (apic = 0; apic < nr_ioapics; apic++)
410 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
411 clear_IO_APIC_pin(apic, pin);
414 #endif /* !CONFIG_XEN */
415 int skip_ioapic_setup;
418 /* dummy parsing: see setup.c */
420 static int __init disable_ioapic_setup(char *str)
422 skip_ioapic_setup = 1;
425 early_param("noapic", disable_ioapic_setup);
427 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
428 static int __init disable_timer_pin_setup(char *arg)
430 disable_timer_pin_1 = 1;
433 __setup("disable_timer_pin_1", disable_timer_pin_setup);
435 static int __init setup_disable_8254_timer(char *s)
437 timer_over_8254 = -1;
440 static int __init setup_enable_8254_timer(char *s)
446 __setup("disable_8254_timer", setup_disable_8254_timer);
447 __setup("enable_8254_timer", setup_enable_8254_timer);
451 * Find the IRQ entry number of a certain pin.
453 static int find_irq_entry(int apic, int pin, int type)
457 for (i = 0; i < mp_irq_entries; i++)
458 if (mp_irqs[i].mpc_irqtype == type &&
459 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
460 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
461 mp_irqs[i].mpc_dstirq == pin)
469 * Find the pin to which IRQ[irq] (ISA) is connected
471 static int __init find_isa_irq_pin(int irq, int type)
475 for (i = 0; i < mp_irq_entries; i++) {
476 int lbus = mp_irqs[i].mpc_srcbus;
478 if (test_bit(lbus, mp_bus_not_pci) &&
479 (mp_irqs[i].mpc_irqtype == type) &&
480 (mp_irqs[i].mpc_srcbusirq == irq))
482 return mp_irqs[i].mpc_dstirq;
487 static int __init find_isa_irq_apic(int irq, int type)
491 for (i = 0; i < mp_irq_entries; i++) {
492 int lbus = mp_irqs[i].mpc_srcbus;
494 if (test_bit(lbus, mp_bus_not_pci) &&
495 (mp_irqs[i].mpc_irqtype == type) &&
496 (mp_irqs[i].mpc_srcbusirq == irq))
499 if (i < mp_irq_entries) {
501 for(apic = 0; apic < nr_ioapics; apic++) {
502 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
512 * Find a specific PCI IRQ entry.
513 * Not an __init, possibly needed by modules
515 static int pin_2_irq(int idx, int apic, int pin);
517 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
519 int apic, i, best_guess = -1;
521 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
523 if (mp_bus_id_to_pci_bus[bus] == -1) {
524 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
527 for (i = 0; i < mp_irq_entries; i++) {
528 int lbus = mp_irqs[i].mpc_srcbus;
530 for (apic = 0; apic < nr_ioapics; apic++)
531 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
532 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
535 if (!test_bit(lbus, mp_bus_not_pci) &&
536 !mp_irqs[i].mpc_irqtype &&
538 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
539 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
541 if (!(apic || IO_APIC_IRQ(irq)))
544 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
547 * Use the first all-but-pin matching entry as a
548 * best-guess fuzzy result for broken mptables.
554 BUG_ON(best_guess >= NR_IRQS);
558 /* ISA interrupts are always polarity zero edge triggered,
559 * when listed as conforming in the MP table. */
561 #define default_ISA_trigger(idx) (0)
562 #define default_ISA_polarity(idx) (0)
564 /* PCI interrupts are always polarity one level triggered,
565 * when listed as conforming in the MP table. */
567 #define default_PCI_trigger(idx) (1)
568 #define default_PCI_polarity(idx) (1)
570 static int __init MPBIOS_polarity(int idx)
572 int bus = mp_irqs[idx].mpc_srcbus;
576 * Determine IRQ line polarity (high active or low active):
578 switch (mp_irqs[idx].mpc_irqflag & 3)
580 case 0: /* conforms, ie. bus-type dependent polarity */
581 if (test_bit(bus, mp_bus_not_pci))
582 polarity = default_ISA_polarity(idx);
584 polarity = default_PCI_polarity(idx);
586 case 1: /* high active */
591 case 2: /* reserved */
593 printk(KERN_WARNING "broken BIOS!!\n");
597 case 3: /* low active */
602 default: /* invalid */
604 printk(KERN_WARNING "broken BIOS!!\n");
612 static int MPBIOS_trigger(int idx)
614 int bus = mp_irqs[idx].mpc_srcbus;
618 * Determine IRQ trigger mode (edge or level sensitive):
620 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
622 case 0: /* conforms, ie. bus-type dependent */
623 if (test_bit(bus, mp_bus_not_pci))
624 trigger = default_ISA_trigger(idx);
626 trigger = default_PCI_trigger(idx);
633 case 2: /* reserved */
635 printk(KERN_WARNING "broken BIOS!!\n");
644 default: /* invalid */
646 printk(KERN_WARNING "broken BIOS!!\n");
654 static inline int irq_polarity(int idx)
656 return MPBIOS_polarity(idx);
659 static inline int irq_trigger(int idx)
661 return MPBIOS_trigger(idx);
664 static int pin_2_irq(int idx, int apic, int pin)
667 int bus = mp_irqs[idx].mpc_srcbus;
670 * Debugging check, we are in big trouble if this message pops up!
672 if (mp_irqs[idx].mpc_dstirq != pin)
673 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
675 if (test_bit(bus, mp_bus_not_pci)) {
676 irq = mp_irqs[idx].mpc_srcbusirq;
679 * PCI IRQs are mapped in order
683 irq += nr_ioapic_registers[i++];
686 BUG_ON(irq >= NR_IRQS);
690 static inline int IO_APIC_irq_trigger(int irq)
694 for (apic = 0; apic < nr_ioapics; apic++) {
695 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
696 idx = find_irq_entry(apic,pin,mp_INT);
697 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
698 return irq_trigger(idx);
702 * nonexistent IRQs are edge default
707 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
708 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
710 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
730 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
732 struct physdev_irq irq_op;
735 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
737 if (irq_vector[irq] > 0) {
738 cpus_and(*result, irq_domain[irq], mask);
739 return irq_vector[irq];
742 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
745 vector = irq_op.vector;
746 per_cpu(vector_irq,0)[vector] = irq;
747 irq_vector[irq] = vector;
748 cpus_and(*result, irq_domain[irq], mask);
753 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
758 spin_lock_irqsave(&vector_lock, flags);
759 vector = __assign_irq_vector(irq, mask, result);
760 spin_unlock_irqrestore(&vector_lock, flags);
764 static void __clear_irq_vector(int irq)
769 BUG_ON(!irq_vector[irq]);
771 vector = irq_vector[irq];
772 cpus_and(mask, irq_domain[irq], cpu_online_map);
773 for_each_cpu_mask(cpu, mask)
774 per_cpu(vector_irq, cpu)[vector] = -1;
777 irq_domain[irq] = CPU_MASK_NONE;
780 void __setup_vector_irq(int cpu)
782 /* Initialize vector_irq on a new cpu */
783 /* This function must be called with vector_lock held */
786 /* Mark the inuse vectors */
787 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
788 if (!cpu_isset(cpu, irq_domain[irq]))
790 vector = irq_vector[irq];
791 per_cpu(vector_irq, cpu)[vector] = irq;
793 /* Mark the free vectors */
794 for (vector = 0; vector < NR_VECTORS; ++vector) {
795 irq = per_cpu(vector_irq, cpu)[vector];
798 if (!cpu_isset(cpu, irq_domain[irq]))
799 per_cpu(vector_irq, cpu)[vector] = -1;
804 extern void (*interrupt[NR_IRQS])(void);
807 static struct irq_chip ioapic_chip;
809 #define IOAPIC_AUTO -1
810 #define IOAPIC_EDGE 0
811 #define IOAPIC_LEVEL 1
813 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
815 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
816 trigger == IOAPIC_LEVEL)
817 set_irq_chip_and_handler_name(irq, &ioapic_chip,
818 handle_fasteoi_irq, "fasteoi");
820 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
821 set_irq_chip_and_handler_name(irq, &ioapic_chip,
822 handle_edge_irq, "edge");
826 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
827 #endif /* !CONFIG_XEN */
829 static void __init setup_IO_APIC_irq(int apic, int pin, int idx, int irq)
831 struct IO_APIC_route_entry entry;
837 * add it to the IO-APIC irq-routing table:
839 memset(&entry,0,sizeof(entry));
841 entry.delivery_mode = INT_DELIVERY_MODE;
842 entry.dest_mode = INT_DEST_MODE;
843 entry.mask = 0; /* enable IRQ */
844 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
846 entry.trigger = irq_trigger(idx);
847 entry.polarity = irq_polarity(idx);
849 if (irq_trigger(idx)) {
852 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
855 if (!apic && !IO_APIC_IRQ(irq))
858 if (IO_APIC_IRQ(irq)) {
860 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
864 entry.dest = cpu_mask_to_apicid(mask);
865 entry.vector = vector;
867 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
868 if (!apic && (irq < 16))
869 disable_8259A_irq(irq);
872 ioapic_write_entry(apic, pin, entry);
874 spin_lock_irqsave(&ioapic_lock, flags);
875 set_native_irq_info(irq, TARGET_CPUS);
876 spin_unlock_irqrestore(&ioapic_lock, flags);
880 static void __init setup_IO_APIC_irqs(void)
882 int apic, pin, idx, irq, first_notcon = 1;
884 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
886 for (apic = 0; apic < nr_ioapics; apic++) {
887 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
889 idx = find_irq_entry(apic,pin,mp_INT);
892 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
895 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
899 irq = pin_2_irq(idx, apic, pin);
900 add_pin_to_irq(irq, apic, pin);
902 setup_IO_APIC_irq(apic, pin, idx, irq);
908 apic_printk(APIC_VERBOSE," not connected.\n");
913 * Set up the 8259A-master output pin as broadcast to all
916 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
918 struct IO_APIC_route_entry entry;
921 memset(&entry,0,sizeof(entry));
923 disable_8259A_irq(0);
926 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
929 * We use logical delivery to get the timer IRQ
932 entry.dest_mode = INT_DEST_MODE;
933 entry.mask = 0; /* unmask IRQ now */
934 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
935 entry.delivery_mode = INT_DELIVERY_MODE;
938 entry.vector = vector;
941 * The timer IRQ doesn't have to know that behind the
942 * scene we have a 8259A-master in AEOI mode ...
944 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
947 * Add it to the IO-APIC irq-routing table:
949 spin_lock_irqsave(&ioapic_lock, flags);
950 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
951 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
952 spin_unlock_irqrestore(&ioapic_lock, flags);
957 void __init UNEXPECTED_IO_APIC(void)
961 void __apicdebuginit print_IO_APIC(void)
964 union IO_APIC_reg_00 reg_00;
965 union IO_APIC_reg_01 reg_01;
966 union IO_APIC_reg_02 reg_02;
969 if (apic_verbosity == APIC_QUIET)
972 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
973 for (i = 0; i < nr_ioapics; i++)
974 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
975 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
978 * We are a bit conservative about what we expect. We have to
979 * know about every hardware change ASAP.
981 printk(KERN_INFO "testing the IO APIC.......................\n");
983 for (apic = 0; apic < nr_ioapics; apic++) {
985 spin_lock_irqsave(&ioapic_lock, flags);
986 reg_00.raw = io_apic_read(apic, 0);
987 reg_01.raw = io_apic_read(apic, 1);
988 if (reg_01.bits.version >= 0x10)
989 reg_02.raw = io_apic_read(apic, 2);
990 spin_unlock_irqrestore(&ioapic_lock, flags);
993 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
994 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
995 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
996 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
997 UNEXPECTED_IO_APIC();
999 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1000 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1001 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1002 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1003 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1004 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1005 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1006 (reg_01.bits.entries != 0x2E) &&
1007 (reg_01.bits.entries != 0x3F) &&
1008 (reg_01.bits.entries != 0x03)
1010 UNEXPECTED_IO_APIC();
1012 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1013 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1014 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1015 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1016 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1017 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1018 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1019 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1021 UNEXPECTED_IO_APIC();
1022 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1023 UNEXPECTED_IO_APIC();
1025 if (reg_01.bits.version >= 0x10) {
1026 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1027 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1028 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1029 UNEXPECTED_IO_APIC();
1032 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1034 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1035 " Stat Dmod Deli Vect: \n");
1037 for (i = 0; i <= reg_01.bits.entries; i++) {
1038 struct IO_APIC_route_entry entry;
1040 entry = ioapic_read_entry(apic, i);
1042 printk(KERN_DEBUG " %02x %03X ",
1047 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1052 entry.delivery_status,
1054 entry.delivery_mode,
1059 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1060 for (i = 0; i < NR_IRQS; i++) {
1061 struct irq_pin_list *entry = irq_2_pin + i;
1064 printk(KERN_DEBUG "IRQ%d ", i);
1066 printk("-> %d:%d", entry->apic, entry->pin);
1069 entry = irq_2_pin + entry->next;
1074 printk(KERN_INFO ".................................... done.\n");
1081 static __apicdebuginit void print_APIC_bitfield (int base)
1086 if (apic_verbosity == APIC_QUIET)
1089 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1090 for (i = 0; i < 8; i++) {
1091 v = apic_read(base + i*0x10);
1092 for (j = 0; j < 32; j++) {
1102 void __apicdebuginit print_local_APIC(void * dummy)
1104 unsigned int v, ver, maxlvt;
1106 if (apic_verbosity == APIC_QUIET)
1109 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1110 smp_processor_id(), hard_smp_processor_id());
1111 v = apic_read(APIC_ID);
1112 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1113 v = apic_read(APIC_LVR);
1114 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1115 ver = GET_APIC_VERSION(v);
1116 maxlvt = get_maxlvt();
1118 v = apic_read(APIC_TASKPRI);
1119 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1121 v = apic_read(APIC_ARBPRI);
1122 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1123 v & APIC_ARBPRI_MASK);
1124 v = apic_read(APIC_PROCPRI);
1125 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1127 v = apic_read(APIC_EOI);
1128 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1129 v = apic_read(APIC_RRR);
1130 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1131 v = apic_read(APIC_LDR);
1132 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1133 v = apic_read(APIC_DFR);
1134 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1135 v = apic_read(APIC_SPIV);
1136 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1138 printk(KERN_DEBUG "... APIC ISR field:\n");
1139 print_APIC_bitfield(APIC_ISR);
1140 printk(KERN_DEBUG "... APIC TMR field:\n");
1141 print_APIC_bitfield(APIC_TMR);
1142 printk(KERN_DEBUG "... APIC IRR field:\n");
1143 print_APIC_bitfield(APIC_IRR);
1145 v = apic_read(APIC_ESR);
1146 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1148 v = apic_read(APIC_ICR);
1149 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1150 v = apic_read(APIC_ICR2);
1151 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1153 v = apic_read(APIC_LVTT);
1154 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1156 if (maxlvt > 3) { /* PC is LVT#4. */
1157 v = apic_read(APIC_LVTPC);
1158 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1160 v = apic_read(APIC_LVT0);
1161 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1162 v = apic_read(APIC_LVT1);
1163 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1165 if (maxlvt > 2) { /* ERR is LVT#3. */
1166 v = apic_read(APIC_LVTERR);
1167 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1170 v = apic_read(APIC_TMICT);
1171 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1172 v = apic_read(APIC_TMCCT);
1173 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1174 v = apic_read(APIC_TDCR);
1175 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1179 void print_all_local_APICs (void)
1181 on_each_cpu(print_local_APIC, NULL, 1, 1);
1184 void __apicdebuginit print_PIC(void)
1187 unsigned long flags;
1189 if (apic_verbosity == APIC_QUIET)
1192 printk(KERN_DEBUG "\nprinting PIC contents\n");
1194 spin_lock_irqsave(&i8259A_lock, flags);
1196 v = inb(0xa1) << 8 | inb(0x21);
1197 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1199 v = inb(0xa0) << 8 | inb(0x20);
1200 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1204 v = inb(0xa0) << 8 | inb(0x20);
1208 spin_unlock_irqrestore(&i8259A_lock, flags);
1210 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1212 v = inb(0x4d1) << 8 | inb(0x4d0);
1213 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1219 void __init print_IO_APIC(void) { }
1220 #endif /* !CONFIG_XEN */
1222 static void __init enable_IO_APIC(void)
1224 union IO_APIC_reg_01 reg_01;
1226 int i8259_apic, i8259_pin;
1229 unsigned long flags;
1231 for (i = 0; i < PIN_MAP_SIZE; i++) {
1232 irq_2_pin[i].pin = -1;
1233 irq_2_pin[i].next = 0;
1237 * The number of IO-APIC IRQ registers (== #pins):
1239 for (apic = 0; apic < nr_ioapics; apic++) {
1240 spin_lock_irqsave(&ioapic_lock, flags);
1241 reg_01.raw = io_apic_read(apic, 1);
1242 spin_unlock_irqrestore(&ioapic_lock, flags);
1243 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1246 for(apic = 0; apic < nr_ioapics; apic++) {
1248 /* See if any of the pins is in ExtINT mode */
1249 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1250 struct IO_APIC_route_entry entry;
1251 entry = ioapic_read_entry(apic, pin);
1253 /* If the interrupt line is enabled and in ExtInt mode
1254 * I have found the pin where the i8259 is connected.
1256 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1257 ioapic_i8259.apic = apic;
1258 ioapic_i8259.pin = pin;
1264 /* Look to see what if the MP table has reported the ExtINT */
1265 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1266 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1267 /* Trust the MP table if nothing is setup in the hardware */
1268 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1269 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1270 ioapic_i8259.pin = i8259_pin;
1271 ioapic_i8259.apic = i8259_apic;
1273 /* Complain if the MP table and the hardware disagree */
1274 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1275 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1277 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1282 * Do not trust the IO-APIC being empty at bootup
1288 * Not an __init, needed by the reboot code
1290 void disable_IO_APIC(void)
1293 * Clear the IO-APIC before rebooting:
1299 * If the i8259 is routed through an IOAPIC
1300 * Put that IOAPIC in virtual wire mode
1301 * so legacy interrupts can be delivered.
1303 if (ioapic_i8259.pin != -1) {
1304 struct IO_APIC_route_entry entry;
1306 memset(&entry, 0, sizeof(entry));
1307 entry.mask = 0; /* Enabled */
1308 entry.trigger = 0; /* Edge */
1310 entry.polarity = 0; /* High */
1311 entry.delivery_status = 0;
1312 entry.dest_mode = 0; /* Physical */
1313 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1316 GET_APIC_ID(apic_read(APIC_ID));
1319 * Add it to the IO-APIC irq-routing table:
1321 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1324 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1329 * There is a nasty bug in some older SMP boards, their mptable lies
1330 * about the timer IRQ. We do the following to work around the situation:
1332 * - timer IRQ defaults to IO-APIC IRQ
1333 * - if this function detects that timer IRQs are defunct, then we fall
1334 * back to ISA timer IRQs
1337 static int __init timer_irq_works(void)
1339 unsigned long t1 = jiffies;
1342 /* Let ten ticks pass... */
1343 mdelay((10 * 1000) / HZ);
1346 * Expect a few ticks at least, to be sure some possible
1347 * glue logic does not lock up after one or two first
1348 * ticks in a non-ExtINT mode. Also the local APIC
1349 * might have cached one ExtINT interrupt. Finally, at
1350 * least one tick may be lost due to delays.
1354 if (jiffies - t1 > 4)
1360 * In the SMP+IOAPIC case it might happen that there are an unspecified
1361 * number of pending IRQ events unhandled. These cases are very rare,
1362 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1363 * better to do it this way as thus we do not have to be aware of
1364 * 'pending' interrupts in the IRQ path, except at this point.
1367 * Edge triggered needs to resend any interrupt
1368 * that was delayed but this is now handled in the device
1373 * Starting up a edge-triggered IO-APIC interrupt is
1374 * nasty - we need to make sure that we get the edge.
1375 * If it is already asserted for some reason, we need
1376 * return 1 to indicate that is was pending.
1378 * This is not complete - we should be able to fake
1379 * an edge even if it isn't on the 8259A...
1382 static unsigned int startup_ioapic_irq(unsigned int irq)
1384 int was_pending = 0;
1385 unsigned long flags;
1387 spin_lock_irqsave(&ioapic_lock, flags);
1389 disable_8259A_irq(irq);
1390 if (i8259A_irq_pending(irq))
1393 __unmask_IO_APIC_irq(irq);
1394 spin_unlock_irqrestore(&ioapic_lock, flags);
1399 static int ioapic_retrigger_irq(unsigned int irq)
1403 unsigned long flags;
1405 spin_lock_irqsave(&vector_lock, flags);
1406 vector = irq_vector[irq];
1408 cpu_set(first_cpu(irq_domain[irq]), mask);
1410 send_IPI_mask(mask, vector);
1411 spin_unlock_irqrestore(&vector_lock, flags);
1417 * Level and edge triggered IO-APIC interrupts need different handling,
1418 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1419 * handled with the level-triggered descriptor, but that one has slightly
1420 * more overhead. Level-triggered interrupts cannot be handled with the
1421 * edge-triggered handler, without risking IRQ storms and other ugly
1425 static void ack_apic_edge(unsigned int irq)
1427 move_native_irq(irq);
1431 static void ack_apic_level(unsigned int irq)
1433 int do_unmask_irq = 0;
1435 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1436 /* If we are moving the irq we need to mask it */
1437 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1439 mask_IO_APIC_irq(irq);
1444 * We must acknowledge the irq before we move it or the acknowledge will
1445 * not propogate properly.
1449 /* Now we can move and renable the irq */
1450 move_masked_irq(irq);
1451 if (unlikely(do_unmask_irq))
1452 unmask_IO_APIC_irq(irq);
1455 static struct irq_chip ioapic_chip __read_mostly = {
1457 .startup = startup_ioapic_irq,
1458 .mask = mask_IO_APIC_irq,
1459 .unmask = unmask_IO_APIC_irq,
1460 .ack = ack_apic_edge,
1461 .eoi = ack_apic_level,
1463 .set_affinity = set_ioapic_affinity_irq,
1465 .retrigger = ioapic_retrigger_irq,
1467 #endif /* !CONFIG_XEN */
1469 static inline void init_IO_APIC_traps(void)
1474 * NOTE! The local APIC isn't very good at handling
1475 * multiple interrupts at the same interrupt level.
1476 * As the interrupt level is determined by taking the
1477 * vector number and shifting that right by 4, we
1478 * want to spread these out a bit so that they don't
1479 * all fall in the same interrupt level.
1481 * Also, we've got to be careful not to trash gate
1482 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1484 for (irq = 0; irq < NR_IRQS ; irq++) {
1486 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1488 * Hmm.. We don't have an entry for this,
1489 * so default to an old-fashioned 8259
1490 * interrupt if we can..
1493 make_8259A_irq(irq);
1496 /* Strange. Oh, well.. */
1497 irq_desc[irq].chip = &no_irq_chip;
1504 static void enable_lapic_irq (unsigned int irq)
1508 v = apic_read(APIC_LVT0);
1509 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1512 static void disable_lapic_irq (unsigned int irq)
1516 v = apic_read(APIC_LVT0);
1517 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1520 static void ack_lapic_irq (unsigned int irq)
1525 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1527 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1528 .typename = "local-APIC-edge",
1529 .startup = NULL, /* startup_irq() not used for IRQ0 */
1530 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1531 .enable = enable_lapic_irq,
1532 .disable = disable_lapic_irq,
1533 .ack = ack_lapic_irq,
1534 .end = end_lapic_irq,
1537 static void setup_nmi (void)
1540 * Dirty trick to enable the NMI watchdog ...
1541 * We put the 8259A master into AEOI mode and
1542 * unmask on all local APICs LVT0 as NMI.
1544 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1545 * is from Maciej W. Rozycki - so we do not have to EOI from
1546 * the NMI handler or the timer interrupt.
1548 printk(KERN_INFO "activating NMI Watchdog ...");
1550 enable_NMI_through_LVT0(NULL);
1556 * This looks a bit hackish but it's about the only one way of sending
1557 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1558 * not support the ExtINT mode, unfortunately. We need to send these
1559 * cycles as some i82489DX-based boards have glue logic that keeps the
1560 * 8259A interrupt line asserted until INTA. --macro
1562 static inline void unlock_ExtINT_logic(void)
1565 struct IO_APIC_route_entry entry0, entry1;
1566 unsigned char save_control, save_freq_select;
1567 unsigned long flags;
1569 pin = find_isa_irq_pin(8, mp_INT);
1570 apic = find_isa_irq_apic(8, mp_INT);
1574 spin_lock_irqsave(&ioapic_lock, flags);
1575 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1576 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1577 spin_unlock_irqrestore(&ioapic_lock, flags);
1578 clear_IO_APIC_pin(apic, pin);
1580 memset(&entry1, 0, sizeof(entry1));
1582 entry1.dest_mode = 0; /* physical delivery */
1583 entry1.mask = 0; /* unmask IRQ now */
1584 entry1.dest = hard_smp_processor_id();
1585 entry1.delivery_mode = dest_ExtINT;
1586 entry1.polarity = entry0.polarity;
1590 spin_lock_irqsave(&ioapic_lock, flags);
1591 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1592 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1593 spin_unlock_irqrestore(&ioapic_lock, flags);
1595 save_control = CMOS_READ(RTC_CONTROL);
1596 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1597 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1599 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1604 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1608 CMOS_WRITE(save_control, RTC_CONTROL);
1609 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1610 clear_IO_APIC_pin(apic, pin);
1612 spin_lock_irqsave(&ioapic_lock, flags);
1613 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1614 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1615 spin_unlock_irqrestore(&ioapic_lock, flags);
1619 * This code may look a bit paranoid, but it's supposed to cooperate with
1620 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1621 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1622 * fanatically on his truly buggy board.
1624 * FIXME: really need to revamp this for modern platforms only.
1626 static inline void check_timer(void)
1628 int apic1, pin1, apic2, pin2;
1633 * get/set the timer IRQ vector:
1635 disable_8259A_irq(0);
1636 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1639 * Subtle, code in do_timer_interrupt() expects an AEOI
1640 * mode for the 8259A whenever interrupts are routed
1641 * through I/O APICs. Also IRQ0 has to be enabled in
1642 * the 8259A which implies the virtual wire has to be
1643 * disabled in the local APIC.
1645 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1647 if (timer_over_8254 > 0)
1648 enable_8259A_irq(0);
1650 pin1 = find_isa_irq_pin(0, mp_INT);
1651 apic1 = find_isa_irq_apic(0, mp_INT);
1652 pin2 = ioapic_i8259.pin;
1653 apic2 = ioapic_i8259.apic;
1655 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1656 vector, apic1, pin1, apic2, pin2);
1660 * Ok, does IRQ0 through the IOAPIC work?
1662 unmask_IO_APIC_irq(0);
1663 if (!no_timer_check && timer_irq_works()) {
1664 nmi_watchdog_default();
1665 if (nmi_watchdog == NMI_IO_APIC) {
1666 disable_8259A_irq(0);
1668 enable_8259A_irq(0);
1670 if (disable_timer_pin_1 > 0)
1671 clear_IO_APIC_pin(0, pin1);
1674 clear_IO_APIC_pin(apic1, pin1);
1675 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1676 "connected to IO-APIC\n");
1679 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1680 "through the 8259A ... ");
1682 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1685 * legacy devices should be connected to IO APIC #0
1687 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1688 if (timer_irq_works()) {
1689 apic_printk(APIC_VERBOSE," works.\n");
1690 nmi_watchdog_default();
1691 if (nmi_watchdog == NMI_IO_APIC) {
1697 * Cleanup, just in case ...
1699 clear_IO_APIC_pin(apic2, pin2);
1701 apic_printk(APIC_VERBOSE," failed.\n");
1703 if (nmi_watchdog == NMI_IO_APIC) {
1704 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1708 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1710 disable_8259A_irq(0);
1711 irq_desc[0].chip = &lapic_irq_type;
1712 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1713 enable_8259A_irq(0);
1715 if (timer_irq_works()) {
1716 apic_printk(APIC_VERBOSE," works.\n");
1719 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1720 apic_printk(APIC_VERBOSE," failed.\n");
1722 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1726 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1728 unlock_ExtINT_logic();
1730 if (timer_irq_works()) {
1731 apic_printk(APIC_VERBOSE," works.\n");
1734 apic_printk(APIC_VERBOSE," failed :(.\n");
1735 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1738 #define check_timer() ((void)0)
1739 #endif /* !CONFIG_XEN */
1741 static int __init notimercheck(char *s)
1746 __setup("no_timer_check", notimercheck);
1750 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1751 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1752 * Linux doesn't really care, as it's not actually used
1753 * for any interrupt handling anyway.
1755 #define PIC_IRQS (1<<2)
1757 void __init setup_IO_APIC(void)
1762 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1764 io_apic_irqs = ~PIC_IRQS;
1766 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1770 #endif /* !CONFIG_XEN */
1771 setup_IO_APIC_irqs();
1772 init_IO_APIC_traps();
1778 struct sysfs_ioapic_data {
1779 struct sys_device dev;
1780 struct IO_APIC_route_entry entry[0];
1782 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1784 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1786 struct IO_APIC_route_entry *entry;
1787 struct sysfs_ioapic_data *data;
1790 data = container_of(dev, struct sysfs_ioapic_data, dev);
1791 entry = data->entry;
1792 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1793 *entry = ioapic_read_entry(dev->id, i);
1798 static int ioapic_resume(struct sys_device *dev)
1800 struct IO_APIC_route_entry *entry;
1801 struct sysfs_ioapic_data *data;
1802 unsigned long flags;
1803 union IO_APIC_reg_00 reg_00;
1806 data = container_of(dev, struct sysfs_ioapic_data, dev);
1807 entry = data->entry;
1809 spin_lock_irqsave(&ioapic_lock, flags);
1810 reg_00.raw = io_apic_read(dev->id, 0);
1811 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1812 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1813 io_apic_write(dev->id, 0, reg_00.raw);
1815 spin_unlock_irqrestore(&ioapic_lock, flags);
1816 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1817 ioapic_write_entry(dev->id, i, entry[i]);
1822 static struct sysdev_class ioapic_sysdev_class = {
1823 set_kset_name("ioapic"),
1824 .suspend = ioapic_suspend,
1825 .resume = ioapic_resume,
1828 static int __init ioapic_init_sysfs(void)
1830 struct sys_device * dev;
1831 int i, size, error = 0;
1833 error = sysdev_class_register(&ioapic_sysdev_class);
1837 for (i = 0; i < nr_ioapics; i++ ) {
1838 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1839 * sizeof(struct IO_APIC_route_entry);
1840 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1841 if (!mp_ioapic_data[i]) {
1842 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1845 memset(mp_ioapic_data[i], 0, size);
1846 dev = &mp_ioapic_data[i]->dev;
1848 dev->cls = &ioapic_sysdev_class;
1849 error = sysdev_register(dev);
1851 kfree(mp_ioapic_data[i]);
1852 mp_ioapic_data[i] = NULL;
1853 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1861 device_initcall(ioapic_init_sysfs);
1864 * Dynamic irq allocate and deallocation
1866 int create_irq(void)
1868 /* Allocate an unused irq */
1872 unsigned long flags;
1876 spin_lock_irqsave(&vector_lock, flags);
1877 for (new = (NR_IRQS - 1); new >= 0; new--) {
1878 if (platform_legacy_irq(new))
1880 if (irq_vector[new] != 0)
1882 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1883 if (likely(vector > 0))
1887 spin_unlock_irqrestore(&vector_lock, flags);
1890 dynamic_irq_init(irq);
1895 void destroy_irq(unsigned int irq)
1897 unsigned long flags;
1899 dynamic_irq_cleanup(irq);
1901 spin_lock_irqsave(&vector_lock, flags);
1902 __clear_irq_vector(irq);
1903 spin_unlock_irqrestore(&vector_lock, flags);
1907 * MSI mesage composition
1910 #ifdef CONFIG_PCI_MSI
1911 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1917 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1919 dest = cpu_mask_to_apicid(tmp);
1921 msg->address_hi = MSI_ADDR_BASE_HI;
1924 ((INT_DEST_MODE == 0) ?
1925 MSI_ADDR_DEST_MODE_PHYSICAL:
1926 MSI_ADDR_DEST_MODE_LOGICAL) |
1927 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1928 MSI_ADDR_REDIRECTION_CPU:
1929 MSI_ADDR_REDIRECTION_LOWPRI) |
1930 MSI_ADDR_DEST_ID(dest);
1933 MSI_DATA_TRIGGER_EDGE |
1934 MSI_DATA_LEVEL_ASSERT |
1935 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1936 MSI_DATA_DELIVERY_FIXED:
1937 MSI_DATA_DELIVERY_LOWPRI) |
1938 MSI_DATA_VECTOR(vector);
1944 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1951 cpus_and(tmp, mask, cpu_online_map);
1952 if (cpus_empty(tmp))
1955 cpus_and(mask, tmp, CPU_MASK_ALL);
1957 vector = assign_irq_vector(irq, mask, &tmp);
1961 dest = cpu_mask_to_apicid(tmp);
1963 read_msi_msg(irq, &msg);
1965 msg.data &= ~MSI_DATA_VECTOR_MASK;
1966 msg.data |= MSI_DATA_VECTOR(vector);
1967 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1968 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1970 write_msi_msg(irq, &msg);
1971 set_native_irq_info(irq, mask);
1973 #endif /* CONFIG_SMP */
1976 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1977 * which implement the MSI or MSI-X Capability Structure.
1979 static struct irq_chip msi_chip = {
1981 .unmask = unmask_msi_irq,
1982 .mask = mask_msi_irq,
1983 .ack = ack_apic_edge,
1985 .set_affinity = set_msi_irq_affinity,
1987 .retrigger = ioapic_retrigger_irq,
1990 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1994 ret = msi_compose_msg(dev, irq, &msg);
1998 write_msi_msg(irq, &msg);
2000 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2005 void arch_teardown_msi_irq(unsigned int irq)
2010 #endif /* CONFIG_PCI_MSI */
2011 #endif /* !CONFIG_XEN */
2013 * Hypertransport interrupt support
2015 #ifdef CONFIG_HT_IRQ
2019 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2021 struct ht_irq_msg msg;
2022 fetch_ht_irq_msg(irq, &msg);
2024 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2025 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2027 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2028 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2030 write_ht_irq_msg(irq, &msg);
2033 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2039 cpus_and(tmp, mask, cpu_online_map);
2040 if (cpus_empty(tmp))
2043 cpus_and(mask, tmp, CPU_MASK_ALL);
2045 vector = assign_irq_vector(irq, mask, &tmp);
2049 dest = cpu_mask_to_apicid(tmp);
2051 target_ht_irq(irq, dest, vector);
2052 set_native_irq_info(irq, mask);
2056 static struct irq_chip ht_irq_chip = {
2058 .mask = mask_ht_irq,
2059 .unmask = unmask_ht_irq,
2060 .ack = ack_apic_edge,
2062 .set_affinity = set_ht_irq_affinity,
2064 .retrigger = ioapic_retrigger_irq,
2067 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2072 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2074 struct ht_irq_msg msg;
2077 dest = cpu_mask_to_apicid(tmp);
2079 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2083 HT_IRQ_LOW_DEST_ID(dest) |
2084 HT_IRQ_LOW_VECTOR(vector) |
2085 ((INT_DEST_MODE == 0) ?
2086 HT_IRQ_LOW_DM_PHYSICAL :
2087 HT_IRQ_LOW_DM_LOGICAL) |
2088 HT_IRQ_LOW_RQEOI_EDGE |
2089 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2090 HT_IRQ_LOW_MT_FIXED :
2091 HT_IRQ_LOW_MT_ARBITRATED) |
2092 HT_IRQ_LOW_IRQ_MASKED;
2094 write_ht_irq_msg(irq, &msg);
2096 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2097 handle_edge_irq, "edge");
2101 #endif /* CONFIG_HT_IRQ */
2103 /* --------------------------------------------------------------------------
2104 ACPI-based IOAPIC Configuration
2105 -------------------------------------------------------------------------- */
2109 #define IO_APIC_MAX_ID 0xFE
2111 int __init io_apic_get_redir_entries (int ioapic)
2113 union IO_APIC_reg_01 reg_01;
2114 unsigned long flags;
2116 spin_lock_irqsave(&ioapic_lock, flags);
2117 reg_01.raw = io_apic_read(ioapic, 1);
2118 spin_unlock_irqrestore(&ioapic_lock, flags);
2120 return reg_01.bits.entries;
2124 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2126 struct IO_APIC_route_entry entry;
2127 unsigned long flags;
2131 if (!IO_APIC_IRQ(irq)) {
2132 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2138 * IRQs < 16 are already in the irq_2_pin[] map
2141 add_pin_to_irq(irq, ioapic, pin);
2144 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2149 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2150 * Note that we mask (disable) IRQs now -- these get enabled when the
2151 * corresponding device driver registers for this IRQ.
2154 memset(&entry,0,sizeof(entry));
2156 entry.delivery_mode = INT_DELIVERY_MODE;
2157 entry.dest_mode = INT_DEST_MODE;
2158 entry.dest = cpu_mask_to_apicid(mask);
2159 entry.trigger = triggering;
2160 entry.polarity = polarity;
2161 entry.mask = 1; /* Disabled (masked) */
2162 entry.vector = vector & 0xff;
2164 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2165 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2166 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2167 triggering, polarity);
2169 ioapic_register_intr(irq, entry.vector, triggering);
2171 if (!ioapic && (irq < 16))
2172 disable_8259A_irq(irq);
2174 ioapic_write_entry(ioapic, pin, entry);
2176 spin_lock_irqsave(&ioapic_lock, flags);
2177 set_native_irq_info(irq, TARGET_CPUS);
2178 spin_unlock_irqrestore(&ioapic_lock, flags);
2183 #endif /* CONFIG_ACPI */
2188 * This function currently is only a helper for the i386 smp boot process where
2189 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2190 * so mask in all cases should simply be TARGET_CPUS
2193 void __init setup_ioapic_dest(void)
2195 int pin, ioapic, irq, irq_entry;
2197 if (skip_ioapic_setup == 1)
2200 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2201 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2202 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2203 if (irq_entry == -1)
2205 irq = pin_2_irq(irq_entry, ioapic, pin);
2207 /* setup_IO_APIC_irqs could fail to get vector for some device
2208 * when you have too many devices, because at that time only boot
2211 if(!irq_vector[irq])
2212 setup_IO_APIC_irq(ioapic, pin, irq_entry, irq);
2214 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2220 #endif /* !CONFIG_XEN */