arch/x86_64/kernel/io_apic-xen.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 #ifndef CONFIG_XEN
  54 int timer_over_8254 __initdata = 0;
  55
  56 /* Where if anywhere is the i8259 connect in external int mode */
  57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  58 #endif
  59
  60 static DEFINE_SPINLOCK(ioapic_lock);
  61 static DEFINE_SPINLOCK(vector_lock);
  62
  63 /*
  64  * # of IRQ routing registers
  65  */
  66 int nr_ioapic_registers[MAX_IO_APICS];
  67
  68 /*
  69  * Rough estimation of how many shared IRQs there are, can
  70  * be changed anytime.
  71  */
  72 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  73 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  74
  75 /*
  76  * This is performance-critical, we want to do it O(1)
  77  *
  78  * the indexing order of this array favors 1:1 mappings
  79  * between pins and IRQs.
  80  */
  81
  82 static struct irq_pin_list {
  83         short apic, pin, next;
  84 } irq_2_pin[PIN_MAP_SIZE];
  85
  86 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  87 #ifdef CONFIG_PCI_MSI
  88 #define vector_to_irq(vector)   \
  89         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  90 #else
  91 #define vector_to_irq(vector)   (vector)
  92 #endif
  93
  94 #ifdef CONFIG_XEN
  95
  96 #include <xen/interface/xen.h>
  97 #include <xen/interface/physdev.h>
  98
  99 /* Fake i8259 */
 100 #define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
 101 #define disable_8259A_irq(_irq)  ((void)0)
 102 #define i8259A_irq_pending(_irq) (0)
 103
 104 unsigned long io_apic_irqs;
 105
 106 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
 107 {
 108         struct physdev_apic apic_op;
 109         int ret;
 110
 111         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
 112         apic_op.reg = reg;
 113         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
 114         if (ret)
 115                 return ret;
 116         return apic_op.value;
 117 }
 118
 119 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 120 {
 121         struct physdev_apic apic_op;
 122
 123         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
 124         apic_op.reg = reg;
 125         apic_op.value = value;
 126         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
 127 }
 128
 129 #define io_apic_read(a,r)    xen_io_apic_read(a,r)
 130 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
 131
 132 #define clear_IO_APIC() ((void)0)
 133
 134 #else
 135
 136 #ifdef CONFIG_SMP
 137 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 138 {
 139         unsigned long flags;
 140         unsigned int dest;
 141         cpumask_t tmp;
 142
 143         cpus_and(tmp, mask, cpu_online_map);
 144         if (cpus_empty(tmp))
 145                 tmp = TARGET_CPUS;
 146
 147         cpus_and(mask, tmp, CPU_MASK_ALL);
 148
 149         dest = cpu_mask_to_apicid(mask);
 150
 151         /*
 152          * Only the high 8 bits are valid.
 153          */
 154         dest = SET_APIC_LOGICAL_ID(dest);
 155
 156         spin_lock_irqsave(&ioapic_lock, flags);
 157         __DO_ACTION(1, = dest, )
 158         set_irq_info(irq, mask);
 159         spin_unlock_irqrestore(&ioapic_lock, flags);
 160 }
 161 #endif
 162
 163 #endif /* !CONFIG_XEN */
 164
 165 /*
 166  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 167  * shared ISA-space IRQs, so we have to support them. We are super
 168  * fast in the common case, and fast for shared ISA-space IRQs.
 169  */
 170 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 171 {
 172         static int first_free_entry = NR_IRQS;
 173         struct irq_pin_list *entry = irq_2_pin + irq;
 174
 175         BUG_ON(irq >= NR_IRQS);
 176         while (entry->next)
 177                 entry = irq_2_pin + entry->next;
 178
 179         if (entry->pin != -1) {
 180                 entry->next = first_free_entry;
 181                 entry = irq_2_pin + entry->next;
 182                 if (++first_free_entry >= PIN_MAP_SIZE)
 183                         panic("io_apic.c: ran out of irq_2_pin entries!");
 184         }
 185         entry->apic = apic;
 186         entry->pin = pin;
 187 }
 188
 189 #ifndef CONFIG_XEN
 190 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 191                                                                         \
 192 {                                                                       \
 193         int pin;                                                        \
 194         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 195                                                                         \
 196         BUG_ON(irq >= NR_IRQS);                                         \
 197         for (;;) {                                                      \
 198                 unsigned int reg;                                       \
 199                 pin = entry->pin;                                       \
 200                 if (pin == -1)                                          \
 201                         break;                                          \
 202                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 203                 reg ACTION;                                             \
 204                 io_apic_modify(entry->apic, reg);                       \
 205                 if (!entry->next)                                       \
 206                         break;                                          \
 207                 entry = irq_2_pin + entry->next;                        \
 208         }                                                               \
 209         FINAL;                                                          \
 210 }
 211
 212 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 213                                                                         \
 214         static void name##_IO_APIC_irq (unsigned int irq)               \
 215         __DO_ACTION(R, ACTION, FINAL)
 216
 217 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 218                                                 /* mask = 1 */
 219 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 220                                                 /* mask = 0 */
 221
 222 static void mask_IO_APIC_irq (unsigned int irq)
 223 {
 224         unsigned long flags;
 225
 226         spin_lock_irqsave(&ioapic_lock, flags);
 227         __mask_IO_APIC_irq(irq);
 228         spin_unlock_irqrestore(&ioapic_lock, flags);
 229 }
 230
 231 static void unmask_IO_APIC_irq (unsigned int irq)
 232 {
 233         unsigned long flags;
 234
 235         spin_lock_irqsave(&ioapic_lock, flags);
 236         __unmask_IO_APIC_irq(irq);
 237         spin_unlock_irqrestore(&ioapic_lock, flags);
 238 }
 239
 240 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 241 {
 242         struct IO_APIC_route_entry entry;
 243         unsigned long flags;
 244
 245         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 246         spin_lock_irqsave(&ioapic_lock, flags);
 247         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 248         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 249         spin_unlock_irqrestore(&ioapic_lock, flags);
 250         if (entry.delivery_mode == dest_SMI)
 251                 return;
 252         /*
 253          * Disable it in the IO-APIC irq-routing table:
 254          */
 255         memset(&entry, 0, sizeof(entry));
 256         entry.mask = 1;
 257         spin_lock_irqsave(&ioapic_lock, flags);
 258         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 259         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 260         spin_unlock_irqrestore(&ioapic_lock, flags);
 261 }
 262
 263 static void clear_IO_APIC (void)
 264 {
 265         int apic, pin;
 266
 267         for (apic = 0; apic < nr_ioapics; apic++)
 268                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 269                         clear_IO_APIC_pin(apic, pin);
 270 }
 271
 272 #endif /* !CONFIG_XEN */
 273
 274 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 275
 276 /*
 277  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 278  * specific CPU-side IRQs.
 279  */
 280
 281 #define MAX_PIRQS 8
 282 static int pirq_entries [MAX_PIRQS];
 283 static int pirqs_enabled;
 284 int skip_ioapic_setup;
 285 int ioapic_force;
 286
 287 /* dummy parsing: see setup.c */
 288
 289 static int __init disable_ioapic_setup(char *str)
 290 {
 291         skip_ioapic_setup = 1;
 292         return 1;
 293 }
 294
 295 static int __init enable_ioapic_setup(char *str)
 296 {
 297         ioapic_force = 1;
 298         skip_ioapic_setup = 0;
 299         return 1;
 300 }
 301
 302 __setup("noapic", disable_ioapic_setup);
 303 __setup("apic", enable_ioapic_setup);
 304
 305 #ifndef CONFIG_XEN
 306 static int __init setup_disable_8254_timer(char *s)
 307 {
 308         timer_over_8254 = -1;
 309         return 1;
 310 }
 311 static int __init setup_enable_8254_timer(char *s)
 312 {
 313         timer_over_8254 = 2;
 314         return 1;
 315 }
 316
 317 __setup("disable_8254_timer", setup_disable_8254_timer);
 318 __setup("enable_8254_timer", setup_enable_8254_timer);
 319 #endif /* !CONFIG_XEN */
 320
 321 #include <asm/pci-direct.h>
 322 #include <linux/pci_ids.h>
 323 #include <linux/pci.h>
 324
 325
 326 #ifdef CONFIG_ACPI
 327
 328 static int nvidia_hpet_detected __initdata;
 329
 330 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 331 {
 332         nvidia_hpet_detected = 1;
 333         return 0;
 334 }
 335 #endif
 336
 337 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 338    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 339    Use pci direct infrastructure because this runs before the PCI subsystem.
 340
 341    Can be overwritten with "apic"
 342
 343    And another hack to disable the IOMMU on VIA chipsets.
 344
 345    ... and others. Really should move this somewhere else.
 346
 347    Kludge-O-Rama. */
 348 void __init check_ioapic(void)
 349 {
 350         int num,slot,func;
 351         /* Poor man's PCI discovery */
 352         for (num = 0; num < 32; num++) {
 353                 for (slot = 0; slot < 32; slot++) {
 354                         for (func = 0; func < 8; func++) {
 355                                 u32 class;
 356                                 u32 vendor;
 357                                 u8 type;
 358                                 class = read_pci_config(num,slot,func,
 359                                                         PCI_CLASS_REVISION);
 360                                 if (class == 0xffffffff)
 361                                         break;
 362
 363                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 364                                         continue;
 365
 366                                 vendor = read_pci_config(num, slot, func,
 367                                                          PCI_VENDOR_ID);
 368                                 vendor &= 0xffff;
 369                                 switch (vendor) {
 370                                 case PCI_VENDOR_ID_VIA:
 371 #ifdef CONFIG_IOMMU
 372                                         if ((end_pfn > MAX_DMA32_PFN ||
 373                                              force_iommu) &&
 374                                             !iommu_aperture_allowed) {
 375                                                 printk(KERN_INFO
 376     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 377                                                 iommu_aperture_disabled = 1;
 378                                         }
 379 #endif
 380                                         return;
 381                                 case PCI_VENDOR_ID_NVIDIA:
 382 #ifdef CONFIG_ACPI
 383                                         /*
 384                                          * All timer overrides on Nvidia are
 385                                          * wrong unless HPET is enabled.
 386                                          */
 387                                         nvidia_hpet_detected = 0;
 388                                         acpi_table_parse(ACPI_HPET,
 389                                                         nvidia_hpet_check);
 390                                         if (nvidia_hpet_detected == 0) {
 391                                                 acpi_skip_timer_override = 1;
 392                                                 printk(KERN_INFO "Nvidia board "
 393                                                     "detected. Ignoring ACPI "
 394                                                     "timer override.\n");
 395                                         }
 396 #endif
 397                                         /* RED-PEN skip them on mptables too? */
 398                                         return;
 399                                 case PCI_VENDOR_ID_ATI:
 400
 401                                 /* This should be actually default, but
 402                                    for 2.6.16 let's do it for ATI only where
 403                                    it's really needed. */
 404 #ifndef CONFIG_XEN
 405                                         if (timer_over_8254 == 1) {
 406                                                 timer_over_8254 = 0;
 407                                         printk(KERN_INFO
 408                 "ATI board detected. Disabling timer routing over 8254.\n");
 409                                         }
 410 #endif
 411                                         return;
 412                                 }
 413
 414
 415                                 /* No multi-function device? */
 416                                 type = read_pci_config_byte(num,slot,func,
 417                                                             PCI_HEADER_TYPE);
 418                                 if (!(type & 0x80))
 419                                         break;
 420                         }
 421                 }
 422         }
 423 }
 424
 425 static int __init ioapic_pirq_setup(char *str)
 426 {
 427         int i, max;
 428         int ints[MAX_PIRQS+1];
 429
 430         get_options(str, ARRAY_SIZE(ints), ints);
 431
 432         for (i = 0; i < MAX_PIRQS; i++)
 433                 pirq_entries[i] = -1;
 434
 435         pirqs_enabled = 1;
 436         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 437         max = MAX_PIRQS;
 438         if (ints[0] < MAX_PIRQS)
 439                 max = ints[0];
 440
 441         for (i = 0; i < max; i++) {
 442                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 443                 /*
 444                  * PIRQs are mapped upside down, usually.
 445                  */
 446                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 447         }
 448         return 1;
 449 }
 450
 451 __setup("pirq=", ioapic_pirq_setup);
 452
 453 /*
 454  * Find the IRQ entry number of a certain pin.
 455  */
 456 static int find_irq_entry(int apic, int pin, int type)
 457 {
 458         int i;
 459
 460         for (i = 0; i < mp_irq_entries; i++)
 461                 if (mp_irqs[i].mpc_irqtype == type &&
 462                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 463                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 464                     mp_irqs[i].mpc_dstirq == pin)
 465                         return i;
 466
 467         return -1;
 468 }
 469
 470 #ifndef CONFIG_XEN
 471 /*
 472  * Find the pin to which IRQ[irq] (ISA) is connected
 473  */
 474 static int __init find_isa_irq_pin(int irq, int type)
 475 {
 476         int i;
 477
 478         for (i = 0; i < mp_irq_entries; i++) {
 479                 int lbus = mp_irqs[i].mpc_srcbus;
 480
 481                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 482                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 483                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 484                     (mp_irqs[i].mpc_irqtype == type) &&
 485                     (mp_irqs[i].mpc_srcbusirq == irq))
 486
 487                         return mp_irqs[i].mpc_dstirq;
 488         }
 489         return -1;
 490 }
 491
 492 static int __init find_isa_irq_apic(int irq, int type)
 493 {
 494         int i;
 495
 496         for (i = 0; i < mp_irq_entries; i++) {
 497                 int lbus = mp_irqs[i].mpc_srcbus;
 498
 499                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 500                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 501                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 502                     (mp_irqs[i].mpc_irqtype == type) &&
 503                     (mp_irqs[i].mpc_srcbusirq == irq))
 504                         break;
 505         }
 506         if (i < mp_irq_entries) {
 507                 int apic;
 508                 for(apic = 0; apic < nr_ioapics; apic++) {
 509                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 510                                 return apic;
 511                 }
 512         }
 513
 514         return -1;
 515 }
 516 #endif
 517
 518 /*
 519  * Find a specific PCI IRQ entry.
 520  * Not an __init, possibly needed by modules
 521  */
 522 static int pin_2_irq(int idx, int apic, int pin);
 523
 524 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 525 {
 526         int apic, i, best_guess = -1;
 527
 528         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 529                 bus, slot, pin);
 530         if (mp_bus_id_to_pci_bus[bus] == -1) {
 531                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 532                 return -1;
 533         }
 534         for (i = 0; i < mp_irq_entries; i++) {
 535                 int lbus = mp_irqs[i].mpc_srcbus;
 536
 537                 for (apic = 0; apic < nr_ioapics; apic++)
 538                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 539                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 540                                 break;
 541
 542                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 543                     !mp_irqs[i].mpc_irqtype &&
 544                     (bus == lbus) &&
 545                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 546                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 547
 548                         if (!(apic || IO_APIC_IRQ(irq)))
 549                                 continue;
 550
 551                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 552                                 return irq;
 553                         /*
 554                          * Use the first all-but-pin matching entry as a
 555                          * best-guess fuzzy result for broken mptables.
 556                          */
 557                         if (best_guess < 0)
 558                                 best_guess = irq;
 559                 }
 560         }
 561         BUG_ON(best_guess >= NR_IRQS);
 562         return best_guess;
 563 }
 564
 565 /*
 566  * EISA Edge/Level control register, ELCR
 567  */
 568 static int EISA_ELCR(unsigned int irq)
 569 {
 570         if (irq < 16) {
 571                 unsigned int port = 0x4d0 + (irq >> 3);
 572                 return (inb(port) >> (irq & 7)) & 1;
 573         }
 574         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 575         return 0;
 576 }
 577
 578 /* EISA interrupts are always polarity zero and can be edge or level
 579  * trigger depending on the ELCR value.  If an interrupt is listed as
 580  * EISA conforming in the MP table, that means its trigger type must
 581  * be read in from the ELCR */
 582
 583 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 584 #define default_EISA_polarity(idx)      (0)
 585
 586 /* ISA interrupts are always polarity zero edge triggered,
 587  * when listed as conforming in the MP table. */
 588
 589 #define default_ISA_trigger(idx)        (0)
 590 #define default_ISA_polarity(idx)       (0)
 591
 592 /* PCI interrupts are always polarity one level triggered,
 593  * when listed as conforming in the MP table. */
 594
 595 #define default_PCI_trigger(idx)        (1)
 596 #define default_PCI_polarity(idx)       (1)
 597
 598 /* MCA interrupts are always polarity zero level triggered,
 599  * when listed as conforming in the MP table. */
 600
 601 #define default_MCA_trigger(idx)        (1)
 602 #define default_MCA_polarity(idx)       (0)
 603
 604 static int __init MPBIOS_polarity(int idx)
 605 {
 606         int bus = mp_irqs[idx].mpc_srcbus;
 607         int polarity;
 608
 609         /*
 610          * Determine IRQ line polarity (high active or low active):
 611          */
 612         switch (mp_irqs[idx].mpc_irqflag & 3)
 613         {
 614                 case 0: /* conforms, ie. bus-type dependent polarity */
 615                 {
 616                         switch (mp_bus_id_to_type[bus])
 617                         {
 618                                 case MP_BUS_ISA: /* ISA pin */
 619                                 {
 620                                         polarity = default_ISA_polarity(idx);
 621                                         break;
 622                                 }
 623                                 case MP_BUS_EISA: /* EISA pin */
 624                                 {
 625                                         polarity = default_EISA_polarity(idx);
 626                                         break;
 627                                 }
 628                                 case MP_BUS_PCI: /* PCI pin */
 629                                 {
 630                                         polarity = default_PCI_polarity(idx);
 631                                         break;
 632                                 }
 633                                 case MP_BUS_MCA: /* MCA pin */
 634                                 {
 635                                         polarity = default_MCA_polarity(idx);
 636                                         break;
 637                                 }
 638                                 default:
 639                                 {
 640                                         printk(KERN_WARNING "broken BIOS!!\n");
 641                                         polarity = 1;
 642                                         break;
 643                                 }
 644                         }
 645                         break;
 646                 }
 647                 case 1: /* high active */
 648                 {
 649                         polarity = 0;
 650                         break;
 651                 }
 652                 case 2: /* reserved */
 653                 {
 654                         printk(KERN_WARNING "broken BIOS!!\n");
 655                         polarity = 1;
 656                         break;
 657                 }
 658                 case 3: /* low active */
 659                 {
 660                         polarity = 1;
 661                         break;
 662                 }
 663                 default: /* invalid */
 664                 {
 665                         printk(KERN_WARNING "broken BIOS!!\n");
 666                         polarity = 1;
 667                         break;
 668                 }
 669         }
 670         return polarity;
 671 }
 672
 673 static int MPBIOS_trigger(int idx)
 674 {
 675         int bus = mp_irqs[idx].mpc_srcbus;
 676         int trigger;
 677
 678         /*
 679          * Determine IRQ trigger mode (edge or level sensitive):
 680          */
 681         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 682         {
 683                 case 0: /* conforms, ie. bus-type dependent */
 684                 {
 685                         switch (mp_bus_id_to_type[bus])
 686                         {
 687                                 case MP_BUS_ISA: /* ISA pin */
 688                                 {
 689                                         trigger = default_ISA_trigger(idx);
 690                                         break;
 691                                 }
 692                                 case MP_BUS_EISA: /* EISA pin */
 693                                 {
 694                                         trigger = default_EISA_trigger(idx);
 695                                         break;
 696                                 }
 697                                 case MP_BUS_PCI: /* PCI pin */
 698                                 {
 699                                         trigger = default_PCI_trigger(idx);
 700                                         break;
 701                                 }
 702                                 case MP_BUS_MCA: /* MCA pin */
 703                                 {
 704                                         trigger = default_MCA_trigger(idx);
 705                                         break;
 706                                 }
 707                                 default:
 708                                 {
 709                                         printk(KERN_WARNING "broken BIOS!!\n");
 710                                         trigger = 1;
 711                                         break;
 712                                 }
 713                         }
 714                         break;
 715                 }
 716                 case 1: /* edge */
 717                 {
 718                         trigger = 0;
 719                         break;
 720                 }
 721                 case 2: /* reserved */
 722                 {
 723                         printk(KERN_WARNING "broken BIOS!!\n");
 724                         trigger = 1;
 725                         break;
 726                 }
 727                 case 3: /* level */
 728                 {
 729                         trigger = 1;
 730                         break;
 731                 }
 732                 default: /* invalid */
 733                 {
 734                         printk(KERN_WARNING "broken BIOS!!\n");
 735                         trigger = 0;
 736                         break;
 737                 }
 738         }
 739         return trigger;
 740 }
 741
 742 static inline int irq_polarity(int idx)
 743 {
 744         return MPBIOS_polarity(idx);
 745 }
 746
 747 static inline int irq_trigger(int idx)
 748 {
 749         return MPBIOS_trigger(idx);
 750 }
 751
 752 static int next_irq = 16;
 753
 754 /*
 755  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 756  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 757  * from ACPI, which can reach 800 in large boxen.
 758  *
 759  * Compact the sparse GSI space into a sequential IRQ series and reuse
 760  * vectors if possible.
 761  */
 762 int gsi_irq_sharing(int gsi)
 763 {
 764         int i, tries, vector;
 765
 766         BUG_ON(gsi >= NR_IRQ_VECTORS);
 767
 768         if (platform_legacy_irq(gsi))
 769                 return gsi;
 770
 771         if (gsi_2_irq[gsi] != 0xFF)
 772                 return (int)gsi_2_irq[gsi];
 773
 774         tries = NR_IRQS;
 775   try_again:
 776         vector = assign_irq_vector(gsi);
 777
 778         /*
 779          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 780          * use of vector and if found, return that IRQ.  However, we never want
 781          * to share legacy IRQs, which usually have a different trigger mode
 782          * than PCI.
 783          */
 784         for (i = 0; i < NR_IRQS; i++)
 785                 if (IO_APIC_VECTOR(i) == vector)
 786                         break;
 787         if (platform_legacy_irq(i)) {
 788                 if (--tries >= 0) {
 789                         IO_APIC_VECTOR(i) = 0;
 790                         goto try_again;
 791                 }
 792                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 793         }
 794         if (i < NR_IRQS) {
 795                 gsi_2_irq[gsi] = i;
 796                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 797                                 gsi, vector, i);
 798                 return i;
 799         }
 800
 801         i = next_irq++;
 802         BUG_ON(i >= NR_IRQS);
 803         gsi_2_irq[gsi] = i;
 804         IO_APIC_VECTOR(i) = vector;
 805         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 806                         gsi, vector, i);
 807         return i;
 808 }
 809
 810 static int pin_2_irq(int idx, int apic, int pin)
 811 {
 812         int irq, i;
 813         int bus = mp_irqs[idx].mpc_srcbus;
 814
 815         /*
 816          * Debugging check, we are in big trouble if this message pops up!
 817          */
 818         if (mp_irqs[idx].mpc_dstirq != pin)
 819                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 820
 821         switch (mp_bus_id_to_type[bus])
 822         {
 823                 case MP_BUS_ISA: /* ISA pin */
 824                 case MP_BUS_EISA:
 825                 case MP_BUS_MCA:
 826                 {
 827                         irq = mp_irqs[idx].mpc_srcbusirq;
 828                         break;
 829                 }
 830                 case MP_BUS_PCI: /* PCI pin */
 831                 {
 832                         /*
 833                          * PCI IRQs are mapped in order
 834                          */
 835                         i = irq = 0;
 836                         while (i < apic)
 837                                 irq += nr_ioapic_registers[i++];
 838                         irq += pin;
 839                         irq = gsi_irq_sharing(irq);
 840                         break;
 841                 }
 842                 default:
 843                 {
 844                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 845                         irq = 0;
 846                         break;
 847                 }
 848         }
 849         BUG_ON(irq >= NR_IRQS);
 850
 851         /*
 852          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 853          */
 854         if ((pin >= 16) && (pin <= 23)) {
 855                 if (pirq_entries[pin-16] != -1) {
 856                         if (!pirq_entries[pin-16]) {
 857                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 858                         } else {
 859                                 irq = pirq_entries[pin-16];
 860                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 861                                                 pin-16, irq);
 862                         }
 863                 }
 864         }
 865         BUG_ON(irq >= NR_IRQS);
 866         return irq;
 867 }
 868
 869 static inline int IO_APIC_irq_trigger(int irq)
 870 {
 871         int apic, idx, pin;
 872
 873         for (apic = 0; apic < nr_ioapics; apic++) {
 874                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 875                         idx = find_irq_entry(apic,pin,mp_INT);
 876                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 877                                 return irq_trigger(idx);
 878                 }
 879         }
 880         /*
 881          * nonexistent IRQs are edge default
 882          */
 883         return 0;
 884 }
 885
 886 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 887 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
 888
 889 int assign_irq_vector(int irq)
 890 {
 891         struct physdev_irq irq_op;
 892         unsigned long flags;
 893
 894         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 895
 896         spin_lock_irqsave(&vector_lock, flags);
 897
 898         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 899                 spin_unlock_irqrestore(&vector_lock, flags);
 900                 return IO_APIC_VECTOR(irq);
 901         }
 902         irq_op.irq = irq;
 903         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
 904                 return -ENOSPC;
 905
 906         vector_irq[irq_op.vector] = irq;
 907         if (irq != AUTO_ASSIGN)
 908                 IO_APIC_VECTOR(irq) = irq_op.vector;
 909
 910         spin_unlock_irqrestore(&vector_lock, flags);
 911         return irq_op.vector;
 912 }
 913
 914 extern void (*interrupt[NR_IRQS])(void);
 915 #ifndef CONFIG_XEN
 916 static struct hw_interrupt_type ioapic_level_type;
 917 static struct hw_interrupt_type ioapic_edge_type;
 918
 919 #define IOAPIC_AUTO     -1
 920 #define IOAPIC_EDGE     0
 921 #define IOAPIC_LEVEL    1
 922
 923 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 924 {
 925         unsigned idx;
 926
 927         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 928
 929         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 930                         trigger == IOAPIC_LEVEL)
 931                 irq_desc[idx].chip = &ioapic_level_type;
 932         else
 933                 irq_desc[idx].chip = &ioapic_edge_type;
 934         set_intr_gate(vector, interrupt[idx]);
 935 }
 936 #else
 937 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
 938 #endif /* !CONFIG_XEN */
 939
 940 static void __init setup_IO_APIC_irqs(void)
 941 {
 942         struct IO_APIC_route_entry entry;
 943         int apic, pin, idx, irq, first_notcon = 1, vector;
 944         unsigned long flags;
 945
 946         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 947
 948         for (apic = 0; apic < nr_ioapics; apic++) {
 949         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 950
 951                 /*
 952                  * add it to the IO-APIC irq-routing table:
 953                  */
 954                 memset(&entry,0,sizeof(entry));
 955
 956                 entry.delivery_mode = INT_DELIVERY_MODE;
 957                 entry.dest_mode = INT_DEST_MODE;
 958                 entry.mask = 0;                         /* enable IRQ */
 959                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 960
 961                 idx = find_irq_entry(apic,pin,mp_INT);
 962                 if (idx == -1) {
 963                         if (first_notcon) {
 964                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 965                                 first_notcon = 0;
 966                         } else
 967                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 968                         continue;
 969                 }
 970
 971                 entry.trigger = irq_trigger(idx);
 972                 entry.polarity = irq_polarity(idx);
 973
 974                 if (irq_trigger(idx)) {
 975                         entry.trigger = 1;
 976                         entry.mask = 1;
 977                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 978                 }
 979
 980                 irq = pin_2_irq(idx, apic, pin);
 981                 add_pin_to_irq(irq, apic, pin);
 982
 983                 if (/* !apic && */ !IO_APIC_IRQ(irq))
 984                         continue;
 985
 986                 if (IO_APIC_IRQ(irq)) {
 987                         vector = assign_irq_vector(irq);
 988                         entry.vector = vector;
 989
 990                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 991                         if (!apic && (irq < 16))
 992                                 disable_8259A_irq(irq);
 993                 }
 994                 spin_lock_irqsave(&ioapic_lock, flags);
 995                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 996                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 997                 set_native_irq_info(irq, TARGET_CPUS);
 998                 spin_unlock_irqrestore(&ioapic_lock, flags);
 999         }
1000         }
1001
1002         if (!first_notcon)
1003                 apic_printk(APIC_VERBOSE," not connected.\n");
1004 }
1005
1006 #ifndef CONFIG_XEN
1007 /*
1008  * Set up the 8259A-master output pin as broadcast to all
1009  * CPUs.
1010  */
1011 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1012 {
1013         struct IO_APIC_route_entry entry;
1014         unsigned long flags;
1015
1016         memset(&entry,0,sizeof(entry));
1017
1018         disable_8259A_irq(0);
1019
1020         /* mask LVT0 */
1021         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1022
1023         /*
1024          * We use logical delivery to get the timer IRQ
1025          * to the first CPU.
1026          */
1027         entry.dest_mode = INT_DEST_MODE;
1028         entry.mask = 0;                                 /* unmask IRQ now */
1029         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1030         entry.delivery_mode = INT_DELIVERY_MODE;
1031         entry.polarity = 0;
1032         entry.trigger = 0;
1033         entry.vector = vector;
1034
1035         /*
1036          * The timer IRQ doesn't have to know that behind the
1037          * scene we have a 8259A-master in AEOI mode ...
1038          */
1039         irq_desc[0].chip = &ioapic_edge_type;
1040
1041         /*
1042          * Add it to the IO-APIC irq-routing table:
1043          */
1044         spin_lock_irqsave(&ioapic_lock, flags);
1045         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1046         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1047         spin_unlock_irqrestore(&ioapic_lock, flags);
1048
1049         enable_8259A_irq(0);
1050 }
1051
1052 void __init UNEXPECTED_IO_APIC(void)
1053 {
1054 }
1055
1056 void __apicdebuginit print_IO_APIC(void)
1057 {
1058         int apic, i;
1059         union IO_APIC_reg_00 reg_00;
1060         union IO_APIC_reg_01 reg_01;
1061         union IO_APIC_reg_02 reg_02;
1062         unsigned long flags;
1063
1064         if (apic_verbosity == APIC_QUIET)
1065                 return;
1066
1067         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1068         for (i = 0; i < nr_ioapics; i++)
1069                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1070                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1071
1072         /*
1073          * We are a bit conservative about what we expect.  We have to
1074          * know about every hardware change ASAP.
1075          */
1076         printk(KERN_INFO "testing the IO APIC.......................\n");
1077
1078         for (apic = 0; apic < nr_ioapics; apic++) {
1079
1080         spin_lock_irqsave(&ioapic_lock, flags);
1081         reg_00.raw = io_apic_read(apic, 0);
1082         reg_01.raw = io_apic_read(apic, 1);
1083         if (reg_01.bits.version >= 0x10)
1084                 reg_02.raw = io_apic_read(apic, 2);
1085         spin_unlock_irqrestore(&ioapic_lock, flags);
1086
1087         printk("\n");
1088         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1089         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1090         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1091         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1092                 UNEXPECTED_IO_APIC();
1093
1094         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1095         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1096         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1097                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1098                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1099                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1100                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1101                 (reg_01.bits.entries != 0x2E) &&
1102                 (reg_01.bits.entries != 0x3F) &&
1103                 (reg_01.bits.entries != 0x03)
1104         )
1105                 UNEXPECTED_IO_APIC();
1106
1107         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1108         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1109         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1110                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1111                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1112                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1113                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1114                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1115         )
1116                 UNEXPECTED_IO_APIC();
1117         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1118                 UNEXPECTED_IO_APIC();
1119
1120         if (reg_01.bits.version >= 0x10) {
1121                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1122                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1123                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1124                         UNEXPECTED_IO_APIC();
1125         }
1126
1127         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1128
1129         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1130                           " Stat Dest Deli Vect:   \n");
1131
1132         for (i = 0; i <= reg_01.bits.entries; i++) {
1133                 struct IO_APIC_route_entry entry;
1134
1135                 spin_lock_irqsave(&ioapic_lock, flags);
1136                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1137                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1138                 spin_unlock_irqrestore(&ioapic_lock, flags);
1139
1140                 printk(KERN_DEBUG " %02x %03X %02X  ",
1141                         i,
1142                         entry.dest.logical.logical_dest,
1143                         entry.dest.physical.physical_dest
1144                 );
1145
1146                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1147                         entry.mask,
1148                         entry.trigger,
1149                         entry.irr,
1150                         entry.polarity,
1151                         entry.delivery_status,
1152                         entry.dest_mode,
1153                         entry.delivery_mode,
1154                         entry.vector
1155                 );
1156         }
1157         }
1158         if (use_pci_vector())
1159                 printk(KERN_INFO "Using vector-based indexing\n");
1160         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1161         for (i = 0; i < NR_IRQS; i++) {
1162                 struct irq_pin_list *entry = irq_2_pin + i;
1163                 if (entry->pin < 0)
1164                         continue;
1165                 if (use_pci_vector() && !platform_legacy_irq(i))
1166                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1167                 else
1168                         printk(KERN_DEBUG "IRQ%d ", i);
1169                 for (;;) {
1170                         printk("-> %d:%d", entry->apic, entry->pin);
1171                         if (!entry->next)
1172                                 break;
1173                         entry = irq_2_pin + entry->next;
1174                 }
1175                 printk("\n");
1176         }
1177
1178         printk(KERN_INFO ".................................... done.\n");
1179
1180         return;
1181 }
1182
1183 #if 0
1184
1185 static __apicdebuginit void print_APIC_bitfield (int base)
1186 {
1187         unsigned int v;
1188         int i, j;
1189
1190         if (apic_verbosity == APIC_QUIET)
1191                 return;
1192
1193         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1194         for (i = 0; i < 8; i++) {
1195                 v = apic_read(base + i*0x10);
1196                 for (j = 0; j < 32; j++) {
1197                         if (v & (1<<j))
1198                                 printk("1");
1199                         else
1200                                 printk("0");
1201                 }
1202                 printk("\n");
1203         }
1204 }
1205
1206 void __apicdebuginit print_local_APIC(void * dummy)
1207 {
1208         unsigned int v, ver, maxlvt;
1209
1210         if (apic_verbosity == APIC_QUIET)
1211                 return;
1212
1213         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1214                 smp_processor_id(), hard_smp_processor_id());
1215         v = apic_read(APIC_ID);
1216         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1217         v = apic_read(APIC_LVR);
1218         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1219         ver = GET_APIC_VERSION(v);
1220         maxlvt = get_maxlvt();
1221
1222         v = apic_read(APIC_TASKPRI);
1223         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1224
1225         v = apic_read(APIC_ARBPRI);
1226         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1227                 v & APIC_ARBPRI_MASK);
1228         v = apic_read(APIC_PROCPRI);
1229         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1230
1231         v = apic_read(APIC_EOI);
1232         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1233         v = apic_read(APIC_RRR);
1234         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1235         v = apic_read(APIC_LDR);
1236         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1237         v = apic_read(APIC_DFR);
1238         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1239         v = apic_read(APIC_SPIV);
1240         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1241
1242         printk(KERN_DEBUG "... APIC ISR field:\n");
1243         print_APIC_bitfield(APIC_ISR);
1244         printk(KERN_DEBUG "... APIC TMR field:\n");
1245         print_APIC_bitfield(APIC_TMR);
1246         printk(KERN_DEBUG "... APIC IRR field:\n");
1247         print_APIC_bitfield(APIC_IRR);
1248
1249         v = apic_read(APIC_ESR);
1250         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1251
1252         v = apic_read(APIC_ICR);
1253         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1254         v = apic_read(APIC_ICR2);
1255         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1256
1257         v = apic_read(APIC_LVTT);
1258         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1259
1260         if (maxlvt > 3) {                       /* PC is LVT#4. */
1261                 v = apic_read(APIC_LVTPC);
1262                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1263         }
1264         v = apic_read(APIC_LVT0);
1265         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1266         v = apic_read(APIC_LVT1);
1267         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1268
1269         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1270                 v = apic_read(APIC_LVTERR);
1271                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1272         }
1273
1274         v = apic_read(APIC_TMICT);
1275         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1276         v = apic_read(APIC_TMCCT);
1277         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1278         v = apic_read(APIC_TDCR);
1279         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1280         printk("\n");
1281 }
1282
1283 void print_all_local_APICs (void)
1284 {
1285         on_each_cpu(print_local_APIC, NULL, 1, 1);
1286 }
1287
1288 void __apicdebuginit print_PIC(void)
1289 {
1290         unsigned int v;
1291         unsigned long flags;
1292
1293         if (apic_verbosity == APIC_QUIET)
1294                 return;
1295
1296         printk(KERN_DEBUG "\nprinting PIC contents\n");
1297
1298         spin_lock_irqsave(&i8259A_lock, flags);
1299
1300         v = inb(0xa1) << 8 | inb(0x21);
1301         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1302
1303         v = inb(0xa0) << 8 | inb(0x20);
1304         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1305
1306         outb(0x0b,0xa0);
1307         outb(0x0b,0x20);
1308         v = inb(0xa0) << 8 | inb(0x20);
1309         outb(0x0a,0xa0);
1310         outb(0x0a,0x20);
1311
1312         spin_unlock_irqrestore(&i8259A_lock, flags);
1313
1314         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1315
1316         v = inb(0x4d1) << 8 | inb(0x4d0);
1317         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1318 }
1319
1320 #endif  /*  0  */
1321
1322 #else
1323 void __init print_IO_APIC(void) { }
1324 #endif /* !CONFIG_XEN */
1325
1326 static void __init enable_IO_APIC(void)
1327 {
1328         union IO_APIC_reg_01 reg_01;
1329 #ifndef CONFIG_XEN
1330         int i8259_apic, i8259_pin;
1331 #endif
1332         int i, apic;
1333         unsigned long flags;
1334
1335         for (i = 0; i < PIN_MAP_SIZE; i++) {
1336                 irq_2_pin[i].pin = -1;
1337                 irq_2_pin[i].next = 0;
1338         }
1339         if (!pirqs_enabled)
1340                 for (i = 0; i < MAX_PIRQS; i++)
1341                         pirq_entries[i] = -1;
1342
1343         /*
1344          * The number of IO-APIC IRQ registers (== #pins):
1345          */
1346         for (apic = 0; apic < nr_ioapics; apic++) {
1347                 spin_lock_irqsave(&ioapic_lock, flags);
1348                 reg_01.raw = io_apic_read(apic, 1);
1349                 spin_unlock_irqrestore(&ioapic_lock, flags);
1350                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1351         }
1352 #ifndef CONFIG_XEN
1353         for(apic = 0; apic < nr_ioapics; apic++) {
1354                 int pin;
1355                 /* See if any of the pins is in ExtINT mode */
1356                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1357                         struct IO_APIC_route_entry entry;
1358                         spin_lock_irqsave(&ioapic_lock, flags);
1359                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1360                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1361                         spin_unlock_irqrestore(&ioapic_lock, flags);
1362
1363
1364                         /* If the interrupt line is enabled and in ExtInt mode
1365                          * I have found the pin where the i8259 is connected.
1366                          */
1367                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1368                                 ioapic_i8259.apic = apic;
1369                                 ioapic_i8259.pin  = pin;
1370                                 goto found_i8259;
1371                         }
1372                 }
1373         }
1374  found_i8259:
1375         /* Look to see what if the MP table has reported the ExtINT */
1376         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1377         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1378         /* Trust the MP table if nothing is setup in the hardware */
1379         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1380                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1381                 ioapic_i8259.pin  = i8259_pin;
1382                 ioapic_i8259.apic = i8259_apic;
1383         }
1384         /* Complain if the MP table and the hardware disagree */
1385         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1386                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1387         {
1388                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1389         }
1390 #endif
1391
1392         /*
1393          * Do not trust the IO-APIC being empty at bootup
1394          */
1395         clear_IO_APIC();
1396 }
1397
1398 /*
1399  * Not an __init, needed by the reboot code
1400  */
1401 void disable_IO_APIC(void)
1402 {
1403         /*
1404          * Clear the IO-APIC before rebooting:
1405          */
1406         clear_IO_APIC();
1407
1408 #ifndef CONFIG_XEN
1409         /*
1410          * If the i8259 is routed through an IOAPIC
1411          * Put that IOAPIC in virtual wire mode
1412          * so legacy interrupts can be delivered.
1413          */
1414         if (ioapic_i8259.pin != -1) {
1415                 struct IO_APIC_route_entry entry;
1416                 unsigned long flags;
1417
1418                 memset(&entry, 0, sizeof(entry));
1419                 entry.mask            = 0; /* Enabled */
1420                 entry.trigger         = 0; /* Edge */
1421                 entry.irr             = 0;
1422                 entry.polarity        = 0; /* High */
1423                 entry.delivery_status = 0;
1424                 entry.dest_mode       = 0; /* Physical */
1425                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1426                 entry.vector          = 0;
1427                 entry.dest.physical.physical_dest =
1428                                         GET_APIC_ID(apic_read(APIC_ID));
1429
1430                 /*
1431                  * Add it to the IO-APIC irq-routing table:
1432                  */
1433                 spin_lock_irqsave(&ioapic_lock, flags);
1434                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1435                         *(((int *)&entry)+1));
1436                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1437                         *(((int *)&entry)+0));
1438                 spin_unlock_irqrestore(&ioapic_lock, flags);
1439         }
1440
1441         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1442 #endif
1443 }
1444
1445 /*
1446  * function to set the IO-APIC physical IDs based on the
1447  * values stored in the MPC table.
1448  *
1449  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1450  */
1451
1452 #ifndef CONFIG_XEN
1453 static void __init setup_ioapic_ids_from_mpc (void)
1454 {
1455         union IO_APIC_reg_00 reg_00;
1456         int apic;
1457         int i;
1458         unsigned char old_id;
1459         unsigned long flags;
1460
1461         /*
1462          * Set the IOAPIC ID to the value stored in the MPC table.
1463          */
1464         for (apic = 0; apic < nr_ioapics; apic++) {
1465
1466                 /* Read the register 0 value */
1467                 spin_lock_irqsave(&ioapic_lock, flags);
1468                 reg_00.raw = io_apic_read(apic, 0);
1469                 spin_unlock_irqrestore(&ioapic_lock, flags);
1470
1471                 old_id = mp_ioapics[apic].mpc_apicid;
1472
1473
1474                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1475
1476
1477                 /*
1478                  * We need to adjust the IRQ routing table
1479                  * if the ID changed.
1480                  */
1481                 if (old_id != mp_ioapics[apic].mpc_apicid)
1482                         for (i = 0; i < mp_irq_entries; i++)
1483                                 if (mp_irqs[i].mpc_dstapic == old_id)
1484                                         mp_irqs[i].mpc_dstapic
1485                                                 = mp_ioapics[apic].mpc_apicid;
1486
1487                 /*
1488                  * Read the right value from the MPC table and
1489                  * write it into the ID register.
1490                  */
1491                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1492                                 mp_ioapics[apic].mpc_apicid);
1493
1494                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1495                 spin_lock_irqsave(&ioapic_lock, flags);
1496                 io_apic_write(apic, 0, reg_00.raw);
1497                 spin_unlock_irqrestore(&ioapic_lock, flags);
1498
1499                 /*
1500                  * Sanity check
1501                  */
1502                 spin_lock_irqsave(&ioapic_lock, flags);
1503                 reg_00.raw = io_apic_read(apic, 0);
1504                 spin_unlock_irqrestore(&ioapic_lock, flags);
1505                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1506                         printk("could not set ID!\n");
1507                 else
1508                         apic_printk(APIC_VERBOSE," ok.\n");
1509         }
1510 }
1511 #else
1512 static void __init setup_ioapic_ids_from_mpc(void) { }
1513 #endif
1514
1515 /*
1516  * There is a nasty bug in some older SMP boards, their mptable lies
1517  * about the timer IRQ. We do the following to work around the situation:
1518  *
1519  *      - timer IRQ defaults to IO-APIC IRQ
1520  *      - if this function detects that timer IRQs are defunct, then we fall
1521  *        back to ISA timer IRQs
1522  */
1523 #ifndef CONFIG_XEN
1524 static int __init timer_irq_works(void)
1525 {
1526         unsigned long t1 = jiffies;
1527
1528         local_irq_enable();
1529         /* Let ten ticks pass... */
1530         mdelay((10 * 1000) / HZ);
1531
1532         /*
1533          * Expect a few ticks at least, to be sure some possible
1534          * glue logic does not lock up after one or two first
1535          * ticks in a non-ExtINT mode.  Also the local APIC
1536          * might have cached one ExtINT interrupt.  Finally, at
1537          * least one tick may be lost due to delays.
1538          */
1539
1540         /* jiffies wrap? */
1541         if (jiffies - t1 > 4)
1542                 return 1;
1543         return 0;
1544 }
1545
1546 /*
1547  * In the SMP+IOAPIC case it might happen that there are an unspecified
1548  * number of pending IRQ events unhandled. These cases are very rare,
1549  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1550  * better to do it this way as thus we do not have to be aware of
1551  * 'pending' interrupts in the IRQ path, except at this point.
1552  */
1553 /*
1554  * Edge triggered needs to resend any interrupt
1555  * that was delayed but this is now handled in the device
1556  * independent code.
1557  */
1558
1559 /*
1560  * Starting up a edge-triggered IO-APIC interrupt is
1561  * nasty - we need to make sure that we get the edge.
1562  * If it is already asserted for some reason, we need
1563  * return 1 to indicate that is was pending.
1564  *
1565  * This is not complete - we should be able to fake
1566  * an edge even if it isn't on the 8259A...
1567  */
1568
1569 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1570 {
1571         int was_pending = 0;
1572         unsigned long flags;
1573
1574         spin_lock_irqsave(&ioapic_lock, flags);
1575         if (irq < 16) {
1576                 disable_8259A_irq(irq);
1577                 if (i8259A_irq_pending(irq))
1578                         was_pending = 1;
1579         }
1580         __unmask_IO_APIC_irq(irq);
1581         spin_unlock_irqrestore(&ioapic_lock, flags);
1582
1583         return was_pending;
1584 }
1585
1586 /*
1587  * Once we have recorded IRQ_PENDING already, we can mask the
1588  * interrupt for real. This prevents IRQ storms from unhandled
1589  * devices.
1590  */
1591 static void ack_edge_ioapic_irq(unsigned int irq)
1592 {
1593         move_irq(irq);
1594         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1595                                         == (IRQ_PENDING | IRQ_DISABLED))
1596                 mask_IO_APIC_irq(irq);
1597         ack_APIC_irq();
1598 }
1599
1600 /*
1601  * Level triggered interrupts can just be masked,
1602  * and shutting down and starting up the interrupt
1603  * is the same as enabling and disabling them -- except
1604  * with a startup need to return a "was pending" value.
1605  *
1606  * Level triggered interrupts are special because we
1607  * do not touch any IO-APIC register while handling
1608  * them. We ack the APIC in the end-IRQ handler, not
1609  * in the start-IRQ-handler. Protection against reentrance
1610  * from the same interrupt is still provided, both by the
1611  * generic IRQ layer and by the fact that an unacked local
1612  * APIC does not accept IRQs.
1613  */
1614 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1615 {
1616         unmask_IO_APIC_irq(irq);
1617
1618         return 0; /* don't check for pending */
1619 }
1620
1621 static void end_level_ioapic_irq (unsigned int irq)
1622 {
1623         move_irq(irq);
1624         ack_APIC_irq();
1625 }
1626
1627 #ifdef CONFIG_PCI_MSI
1628 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1629 {
1630         int irq = vector_to_irq(vector);
1631
1632         return startup_edge_ioapic_irq(irq);
1633 }
1634
1635 static void ack_edge_ioapic_vector(unsigned int vector)
1636 {
1637         int irq = vector_to_irq(vector);
1638
1639         move_native_irq(vector);
1640         ack_edge_ioapic_irq(irq);
1641 }
1642
1643 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1644 {
1645         int irq = vector_to_irq(vector);
1646
1647         return startup_level_ioapic_irq (irq);
1648 }
1649
1650 static void end_level_ioapic_vector (unsigned int vector)
1651 {
1652         int irq = vector_to_irq(vector);
1653
1654         move_native_irq(vector);
1655         end_level_ioapic_irq(irq);
1656 }
1657
1658 static void mask_IO_APIC_vector (unsigned int vector)
1659 {
1660         int irq = vector_to_irq(vector);
1661
1662         mask_IO_APIC_irq(irq);
1663 }
1664
1665 static void unmask_IO_APIC_vector (unsigned int vector)
1666 {
1667         int irq = vector_to_irq(vector);
1668
1669         unmask_IO_APIC_irq(irq);
1670 }
1671
1672 #ifdef CONFIG_SMP
1673 static void set_ioapic_affinity_vector (unsigned int vector,
1674                                         cpumask_t cpu_mask)
1675 {
1676         int irq = vector_to_irq(vector);
1677
1678         set_native_irq_info(vector, cpu_mask);
1679         set_ioapic_affinity_irq(irq, cpu_mask);
1680 }
1681 #endif // CONFIG_SMP
1682 #endif // CONFIG_PCI_MSI
1683
1684 static int ioapic_retrigger(unsigned int irq)
1685 {
1686         send_IPI_self(IO_APIC_VECTOR(irq));
1687
1688         return 1;
1689 }
1690
1691 /*
1692  * Level and edge triggered IO-APIC interrupts need different handling,
1693  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1694  * handled with the level-triggered descriptor, but that one has slightly
1695  * more overhead. Level-triggered interrupts cannot be handled with the
1696  * edge-triggered handler, without risking IRQ storms and other ugly
1697  * races.
1698  */
1699
1700 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1701         .typename = "IO-APIC-edge",
1702         .startup        = startup_edge_ioapic,
1703         .shutdown       = shutdown_edge_ioapic,
1704         .enable         = enable_edge_ioapic,
1705         .disable        = disable_edge_ioapic,
1706         .ack            = ack_edge_ioapic,
1707         .end            = end_edge_ioapic,
1708 #ifdef CONFIG_SMP
1709         .set_affinity = set_ioapic_affinity,
1710 #endif
1711         .retrigger      = ioapic_retrigger,
1712 };
1713
1714 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1715         .typename = "IO-APIC-level",
1716         .startup        = startup_level_ioapic,
1717         .shutdown       = shutdown_level_ioapic,
1718         .enable         = enable_level_ioapic,
1719         .disable        = disable_level_ioapic,
1720         .ack            = mask_and_ack_level_ioapic,
1721         .end            = end_level_ioapic,
1722 #ifdef CONFIG_SMP
1723         .set_affinity = set_ioapic_affinity,
1724 #endif
1725         .retrigger      = ioapic_retrigger,
1726 };
1727 #endif /* !CONFIG_XEN */
1728
1729 static inline void init_IO_APIC_traps(void)
1730 {
1731         int irq;
1732
1733         /*
1734          * NOTE! The local APIC isn't very good at handling
1735          * multiple interrupts at the same interrupt level.
1736          * As the interrupt level is determined by taking the
1737          * vector number and shifting that right by 4, we
1738          * want to spread these out a bit so that they don't
1739          * all fall in the same interrupt level.
1740          *
1741          * Also, we've got to be careful not to trash gate
1742          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1743          */
1744         for (irq = 0; irq < NR_IRQS ; irq++) {
1745                 int tmp = irq;
1746                 if (use_pci_vector()) {
1747                         if (!platform_legacy_irq(tmp))
1748                                 if ((tmp = vector_to_irq(tmp)) == -1)
1749                                         continue;
1750                 }
1751                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1752                         /*
1753                          * Hmm.. We don't have an entry for this,
1754                          * so default to an old-fashioned 8259
1755                          * interrupt if we can..
1756                          */
1757                         if (irq < 16)
1758                                 make_8259A_irq(irq);
1759 #ifndef CONFIG_XEN
1760                         else
1761                                 /* Strange. Oh, well.. */
1762                                 irq_desc[irq].chip = &no_irq_type;
1763 #endif
1764                 }
1765         }
1766 }
1767
1768 #ifndef CONFIG_XEN
1769 static void enable_lapic_irq (unsigned int irq)
1770 {
1771         unsigned long v;
1772
1773         v = apic_read(APIC_LVT0);
1774         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1775 }
1776
1777 static void disable_lapic_irq (unsigned int irq)
1778 {
1779         unsigned long v;
1780
1781         v = apic_read(APIC_LVT0);
1782         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1783 }
1784
1785 static void ack_lapic_irq (unsigned int irq)
1786 {
1787         ack_APIC_irq();
1788 }
1789
1790 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1791
1792 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1793         .typename = "local-APIC-edge",
1794         .startup = NULL, /* startup_irq() not used for IRQ0 */
1795         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1796         .enable = enable_lapic_irq,
1797         .disable = disable_lapic_irq,
1798         .ack = ack_lapic_irq,
1799         .end = end_lapic_irq,
1800 };
1801
1802 static void setup_nmi (void)
1803 {
1804         /*
1805          * Dirty trick to enable the NMI watchdog ...
1806          * We put the 8259A master into AEOI mode and
1807          * unmask on all local APICs LVT0 as NMI.
1808          *
1809          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1810          * is from Maciej W. Rozycki - so we do not have to EOI from
1811          * the NMI handler or the timer interrupt.
1812          */
1813         printk(KERN_INFO "activating NMI Watchdog ...");
1814
1815         enable_NMI_through_LVT0(NULL);
1816
1817         printk(" done.\n");
1818 }
1819
1820 /*
1821  * This looks a bit hackish but it's about the only one way of sending
1822  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1823  * not support the ExtINT mode, unfortunately.  We need to send these
1824  * cycles as some i82489DX-based boards have glue logic that keeps the
1825  * 8259A interrupt line asserted until INTA.  --macro
1826  */
1827 static inline void unlock_ExtINT_logic(void)
1828 {
1829         int apic, pin, i;
1830         struct IO_APIC_route_entry entry0, entry1;
1831         unsigned char save_control, save_freq_select;
1832         unsigned long flags;
1833
1834         pin  = find_isa_irq_pin(8, mp_INT);
1835         apic = find_isa_irq_apic(8, mp_INT);
1836         if (pin == -1)
1837                 return;
1838
1839         spin_lock_irqsave(&ioapic_lock, flags);
1840         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1841         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1842         spin_unlock_irqrestore(&ioapic_lock, flags);
1843         clear_IO_APIC_pin(apic, pin);
1844
1845         memset(&entry1, 0, sizeof(entry1));
1846
1847         entry1.dest_mode = 0;                   /* physical delivery */
1848         entry1.mask = 0;                        /* unmask IRQ now */
1849         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1850         entry1.delivery_mode = dest_ExtINT;
1851         entry1.polarity = entry0.polarity;
1852         entry1.trigger = 0;
1853         entry1.vector = 0;
1854
1855         spin_lock_irqsave(&ioapic_lock, flags);
1856         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1857         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1858         spin_unlock_irqrestore(&ioapic_lock, flags);
1859
1860         save_control = CMOS_READ(RTC_CONTROL);
1861         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1862         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1863                    RTC_FREQ_SELECT);
1864         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1865
1866         i = 100;
1867         while (i-- > 0) {
1868                 mdelay(10);
1869                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1870                         i -= 10;
1871         }
1872
1873         CMOS_WRITE(save_control, RTC_CONTROL);
1874         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1875         clear_IO_APIC_pin(apic, pin);
1876
1877         spin_lock_irqsave(&ioapic_lock, flags);
1878         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1879         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1880         spin_unlock_irqrestore(&ioapic_lock, flags);
1881 }
1882
1883 int timer_uses_ioapic_pin_0;
1884
1885 /*
1886  * This code may look a bit paranoid, but it's supposed to cooperate with
1887  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1888  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1889  * fanatically on his truly buggy board.
1890  *
1891  * FIXME: really need to revamp this for modern platforms only.
1892  */
1893 static inline void check_timer(void)
1894 {
1895         int apic1, pin1, apic2, pin2;
1896         int vector;
1897
1898         /*
1899          * get/set the timer IRQ vector:
1900          */
1901         disable_8259A_irq(0);
1902         vector = assign_irq_vector(0);
1903         set_intr_gate(vector, interrupt[0]);
1904
1905         /*
1906          * Subtle, code in do_timer_interrupt() expects an AEOI
1907          * mode for the 8259A whenever interrupts are routed
1908          * through I/O APICs.  Also IRQ0 has to be enabled in
1909          * the 8259A which implies the virtual wire has to be
1910          * disabled in the local APIC.
1911          */
1912         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1913         init_8259A(1);
1914         if (timer_over_8254 > 0)
1915                 enable_8259A_irq(0);
1916
1917         pin1  = find_isa_irq_pin(0, mp_INT);
1918         apic1 = find_isa_irq_apic(0, mp_INT);
1919         pin2  = ioapic_i8259.pin;
1920         apic2 = ioapic_i8259.apic;
1921
1922         if (pin1 == 0)
1923                 timer_uses_ioapic_pin_0 = 1;
1924
1925         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1926                 vector, apic1, pin1, apic2, pin2);
1927
1928         if (pin1 != -1) {
1929                 /*
1930                  * Ok, does IRQ0 through the IOAPIC work?
1931                  */
1932                 unmask_IO_APIC_irq(0);
1933                 if (!no_timer_check && timer_irq_works()) {
1934                         nmi_watchdog_default();
1935                         if (nmi_watchdog == NMI_IO_APIC) {
1936                                 disable_8259A_irq(0);
1937                                 setup_nmi();
1938                                 enable_8259A_irq(0);
1939                         }
1940                         if (disable_timer_pin_1 > 0)
1941                                 clear_IO_APIC_pin(0, pin1);
1942                         return;
1943                 }
1944                 clear_IO_APIC_pin(apic1, pin1);
1945                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1946                                 "connected to IO-APIC\n");
1947         }
1948
1949         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1950                                 "through the 8259A ... ");
1951         if (pin2 != -1) {
1952                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1953                         apic2, pin2);
1954                 /*
1955                  * legacy devices should be connected to IO APIC #0
1956                  */
1957                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1958                 if (timer_irq_works()) {
1959                         apic_printk(APIC_VERBOSE," works.\n");
1960                         nmi_watchdog_default();
1961                         if (nmi_watchdog == NMI_IO_APIC) {
1962                                 setup_nmi();
1963                         }
1964                         return;
1965                 }
1966                 /*
1967                  * Cleanup, just in case ...
1968                  */
1969                 clear_IO_APIC_pin(apic2, pin2);
1970         }
1971         apic_printk(APIC_VERBOSE," failed.\n");
1972
1973         if (nmi_watchdog == NMI_IO_APIC) {
1974                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1975                 nmi_watchdog = 0;
1976         }
1977
1978         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1979
1980         disable_8259A_irq(0);
1981         irq_desc[0].chip = &lapic_irq_type;
1982         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1983         enable_8259A_irq(0);
1984
1985         if (timer_irq_works()) {
1986                 apic_printk(APIC_VERBOSE," works.\n");
1987                 return;
1988         }
1989         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1990         apic_printk(APIC_VERBOSE," failed.\n");
1991
1992         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1993
1994         init_8259A(0);
1995         make_8259A_irq(0);
1996         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1997
1998         unlock_ExtINT_logic();
1999
2000         if (timer_irq_works()) {
2001                 apic_printk(APIC_VERBOSE," works.\n");
2002                 return;
2003         }
2004         apic_printk(APIC_VERBOSE," failed :(.\n");
2005         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2006 }
2007 #else
2008 int timer_uses_ioapic_pin_0;
2009 #define check_timer() ((void)0)
2010 #endif /* !CONFIG_XEN */
2011
2012 static int __init notimercheck(char *s)
2013 {
2014         no_timer_check = 1;
2015         return 1;
2016 }
2017 __setup("no_timer_check", notimercheck);
2018
2019 /*
2020  *
2021  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2022  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2023  *   Linux doesn't really care, as it's not actually used
2024  *   for any interrupt handling anyway.
2025  */
2026 #define PIC_IRQS        (1<<2)
2027
2028 void __init setup_IO_APIC(void)
2029 {
2030         enable_IO_APIC();
2031
2032         if (acpi_ioapic)
2033                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2034         else
2035                 io_apic_irqs = ~PIC_IRQS;
2036
2037         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2038
2039         /*
2040          * Set up the IO-APIC IRQ routing table.
2041          */
2042         if (!acpi_ioapic)
2043                 setup_ioapic_ids_from_mpc();
2044 #ifndef CONFIG_XEN
2045         sync_Arb_IDs();
2046 #endif /* !CONFIG_XEN */
2047         setup_IO_APIC_irqs();
2048         init_IO_APIC_traps();
2049         check_timer();
2050         if (!acpi_ioapic)
2051                 print_IO_APIC();
2052 }
2053
2054 struct sysfs_ioapic_data {
2055         struct sys_device dev;
2056         struct IO_APIC_route_entry entry[0];
2057 };
2058 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2059
2060 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2061 {
2062         struct IO_APIC_route_entry *entry;
2063         struct sysfs_ioapic_data *data;
2064         unsigned long flags;
2065         int i;
2066
2067         data = container_of(dev, struct sysfs_ioapic_data, dev);
2068         entry = data->entry;
2069         spin_lock_irqsave(&ioapic_lock, flags);
2070         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2071                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2072                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2073         }
2074         spin_unlock_irqrestore(&ioapic_lock, flags);
2075
2076         return 0;
2077 }
2078
2079 static int ioapic_resume(struct sys_device *dev)
2080 {
2081         struct IO_APIC_route_entry *entry;
2082         struct sysfs_ioapic_data *data;
2083         unsigned long flags;
2084         union IO_APIC_reg_00 reg_00;
2085         int i;
2086
2087         data = container_of(dev, struct sysfs_ioapic_data, dev);
2088         entry = data->entry;
2089
2090         spin_lock_irqsave(&ioapic_lock, flags);
2091         reg_00.raw = io_apic_read(dev->id, 0);
2092         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2093                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2094                 io_apic_write(dev->id, 0, reg_00.raw);
2095         }
2096         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2097                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2098                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2099         }
2100         spin_unlock_irqrestore(&ioapic_lock, flags);
2101
2102         return 0;
2103 }
2104
2105 static struct sysdev_class ioapic_sysdev_class = {
2106         set_kset_name("ioapic"),
2107         .suspend = ioapic_suspend,
2108         .resume = ioapic_resume,
2109 };
2110
2111 static int __init ioapic_init_sysfs(void)
2112 {
2113         struct sys_device * dev;
2114         int i, size, error = 0;
2115
2116         error = sysdev_class_register(&ioapic_sysdev_class);
2117         if (error)
2118                 return error;
2119
2120         for (i = 0; i < nr_ioapics; i++ ) {
2121                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2122                         * sizeof(struct IO_APIC_route_entry);
2123                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2124                 if (!mp_ioapic_data[i]) {
2125                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2126                         continue;
2127                 }
2128                 memset(mp_ioapic_data[i], 0, size);
2129                 dev = &mp_ioapic_data[i]->dev;
2130                 dev->id = i;
2131                 dev->cls = &ioapic_sysdev_class;
2132                 error = sysdev_register(dev);
2133                 if (error) {
2134                         kfree(mp_ioapic_data[i]);
2135                         mp_ioapic_data[i] = NULL;
2136                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2137                         continue;
2138                 }
2139         }
2140
2141         return 0;
2142 }
2143
2144 device_initcall(ioapic_init_sysfs);
2145
2146 /* --------------------------------------------------------------------------
2147                           ACPI-based IOAPIC Configuration
2148    -------------------------------------------------------------------------- */
2149
2150 #ifdef CONFIG_ACPI
2151
2152 #define IO_APIC_MAX_ID          0xFE
2153
2154 int __init io_apic_get_version (int ioapic)
2155 {
2156         union IO_APIC_reg_01    reg_01;
2157         unsigned long flags;
2158
2159         spin_lock_irqsave(&ioapic_lock, flags);
2160         reg_01.raw = io_apic_read(ioapic, 1);
2161         spin_unlock_irqrestore(&ioapic_lock, flags);
2162
2163         return reg_01.bits.version;
2164 }
2165
2166
2167 int __init io_apic_get_redir_entries (int ioapic)
2168 {
2169         union IO_APIC_reg_01    reg_01;
2170         unsigned long flags;
2171
2172         spin_lock_irqsave(&ioapic_lock, flags);
2173         reg_01.raw = io_apic_read(ioapic, 1);
2174         spin_unlock_irqrestore(&ioapic_lock, flags);
2175
2176         return reg_01.bits.entries;
2177 }
2178
2179
2180 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2181 {
2182         struct IO_APIC_route_entry entry;
2183         unsigned long flags;
2184
2185         if (!IO_APIC_IRQ(irq)) {
2186                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2187                         ioapic);
2188                 return -EINVAL;
2189         }
2190
2191         /*
2192          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2193          * Note that we mask (disable) IRQs now -- these get enabled when the
2194          * corresponding device driver registers for this IRQ.
2195          */
2196
2197         memset(&entry,0,sizeof(entry));
2198
2199         entry.delivery_mode = INT_DELIVERY_MODE;
2200         entry.dest_mode = INT_DEST_MODE;
2201         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2202         entry.trigger = edge_level;
2203         entry.polarity = active_high_low;
2204         entry.mask = 1;                                  /* Disabled (masked) */
2205
2206         irq = gsi_irq_sharing(irq);
2207         /*
2208          * IRQs < 16 are already in the irq_2_pin[] map
2209          */
2210         if (irq >= 16)
2211                 add_pin_to_irq(irq, ioapic, pin);
2212
2213         entry.vector = assign_irq_vector(irq);
2214
2215         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2216                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2217                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2218                edge_level, active_high_low);
2219
2220         ioapic_register_intr(irq, entry.vector, edge_level);
2221
2222         if (!ioapic && (irq < 16))
2223                 disable_8259A_irq(irq);
2224
2225         spin_lock_irqsave(&ioapic_lock, flags);
2226         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2227         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2228         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2229         spin_unlock_irqrestore(&ioapic_lock, flags);
2230
2231         return 0;
2232 }
2233
2234 #endif /* CONFIG_ACPI */
2235
2236
2237 #ifndef CONFIG_XEN
2238 /*
2239  * This function currently is only a helper for the i386 smp boot process where
2240  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2241  * so mask in all cases should simply be TARGET_CPUS
2242  */
2243 #ifdef CONFIG_SMP
2244 void __init setup_ioapic_dest(void)
2245 {
2246         int pin, ioapic, irq, irq_entry;
2247
2248         if (skip_ioapic_setup == 1)
2249                 return;
2250
2251         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2252                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2253                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2254                         if (irq_entry == -1)
2255                                 continue;
2256                         irq = pin_2_irq(irq_entry, ioapic, pin);
2257                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2258                 }
2259
2260         }
2261 }
2262 #endif
2263 #endif /* !CONFIG_XEN */