arch/x86_64/kernel/io_apic-xen.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #ifdef CONFIG_ACPI
  34 #include <acpi/acpi_bus.h>
  35 #endif
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/proto.h>
  41 #include <asm/mach_apic.h>
  42 #include <asm/acpi.h>
  43 #include <asm/dma.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 #ifndef CONFIG_XEN
  54 int timer_over_8254 __initdata = 0;
  55
  56 /* Where if anywhere is the i8259 connect in external int mode */
  57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  58 #endif
  59
  60 static DEFINE_SPINLOCK(ioapic_lock);
  61
  62 /*
  63  * # of IRQ routing registers
  64  */
  65 int nr_ioapic_registers[MAX_IO_APICS];
  66
  67 /*
  68  * Rough estimation of how many shared IRQs there are, can
  69  * be changed anytime.
  70  */
  71 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  72 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  73
  74 /*
  75  * This is performance-critical, we want to do it O(1)
  76  *
  77  * the indexing order of this array favors 1:1 mappings
  78  * between pins and IRQs.
  79  */
  80
  81 static struct irq_pin_list {
  82         short apic, pin, next;
  83 } irq_2_pin[PIN_MAP_SIZE];
  84
  85 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  86 #ifdef CONFIG_PCI_MSI
  87 #define vector_to_irq(vector)   \
  88         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  89 #else
  90 #define vector_to_irq(vector)   (vector)
  91 #endif
  92
  93 #ifdef CONFIG_XEN
  94
  95 #include <xen/interface/xen.h>
  96 #include <xen/interface/physdev.h>
  97
  98 /* Fake i8259 */
  99 #define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
 100 #define disable_8259A_irq(_irq)  ((void)0)
 101 #define i8259A_irq_pending(_irq) (0)
 102
 103 unsigned long io_apic_irqs;
 104
 105 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
 106 {
 107         struct physdev_apic apic_op;
 108         int ret;
 109
 110         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
 111         apic_op.reg = reg;
 112         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
 113         if (ret)
 114                 return ret;
 115         return apic_op.value;
 116 }
 117
 118 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 119 {
 120         struct physdev_apic apic_op;
 121
 122         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
 123         apic_op.reg = reg;
 124         apic_op.value = value;
 125         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
 126 }
 127
 128 #define io_apic_read(a,r)    xen_io_apic_read(a,r)
 129 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
 130
 131 #define clear_IO_APIC() ((void)0)
 132
 133 #else
 134
 135 #ifdef CONFIG_SMP
 136 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 137 {
 138         unsigned long flags;
 139         unsigned int dest;
 140         cpumask_t tmp;
 141
 142         cpus_and(tmp, mask, cpu_online_map);
 143         if (cpus_empty(tmp))
 144                 tmp = TARGET_CPUS;
 145
 146         cpus_and(mask, tmp, CPU_MASK_ALL);
 147
 148         dest = cpu_mask_to_apicid(mask);
 149
 150         /*
 151          * Only the high 8 bits are valid.
 152          */
 153         dest = SET_APIC_LOGICAL_ID(dest);
 154
 155         spin_lock_irqsave(&ioapic_lock, flags);
 156         __DO_ACTION(1, = dest, )
 157         set_irq_info(irq, mask);
 158         spin_unlock_irqrestore(&ioapic_lock, flags);
 159 }
 160 #endif
 161
 162 #endif /* !CONFIG_XEN */
 163
 164 /*
 165  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 166  * shared ISA-space IRQs, so we have to support them. We are super
 167  * fast in the common case, and fast for shared ISA-space IRQs.
 168  */
 169 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 170 {
 171         static int first_free_entry = NR_IRQS;
 172         struct irq_pin_list *entry = irq_2_pin + irq;
 173
 174         BUG_ON(irq >= NR_IRQS);
 175         while (entry->next)
 176                 entry = irq_2_pin + entry->next;
 177
 178         if (entry->pin != -1) {
 179                 entry->next = first_free_entry;
 180                 entry = irq_2_pin + entry->next;
 181                 if (++first_free_entry >= PIN_MAP_SIZE)
 182                         panic("io_apic.c: ran out of irq_2_pin entries!");
 183         }
 184         entry->apic = apic;
 185         entry->pin = pin;
 186 }
 187
 188 #ifndef CONFIG_XEN
 189 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 190                                                                         \
 191 {                                                                       \
 192         int pin;                                                        \
 193         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 194                                                                         \
 195         BUG_ON(irq >= NR_IRQS);                                         \
 196         for (;;) {                                                      \
 197                 unsigned int reg;                                       \
 198                 pin = entry->pin;                                       \
 199                 if (pin == -1)                                          \
 200                         break;                                          \
 201                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 202                 reg ACTION;                                             \
 203                 io_apic_modify(entry->apic, reg);                       \
 204                 if (!entry->next)                                       \
 205                         break;                                          \
 206                 entry = irq_2_pin + entry->next;                        \
 207         }                                                               \
 208         FINAL;                                                          \
 209 }
 210
 211 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 212                                                                         \
 213         static void name##_IO_APIC_irq (unsigned int irq)               \
 214         __DO_ACTION(R, ACTION, FINAL)
 215
 216 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 217                                                 /* mask = 1 */
 218 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 219                                                 /* mask = 0 */
 220
 221 static void mask_IO_APIC_irq (unsigned int irq)
 222 {
 223         unsigned long flags;
 224
 225         spin_lock_irqsave(&ioapic_lock, flags);
 226         __mask_IO_APIC_irq(irq);
 227         spin_unlock_irqrestore(&ioapic_lock, flags);
 228 }
 229
 230 static void unmask_IO_APIC_irq (unsigned int irq)
 231 {
 232         unsigned long flags;
 233
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         __unmask_IO_APIC_irq(irq);
 236         spin_unlock_irqrestore(&ioapic_lock, flags);
 237 }
 238
 239 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 240 {
 241         struct IO_APIC_route_entry entry;
 242         unsigned long flags;
 243
 244         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 245         spin_lock_irqsave(&ioapic_lock, flags);
 246         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 247         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 248         spin_unlock_irqrestore(&ioapic_lock, flags);
 249         if (entry.delivery_mode == dest_SMI)
 250                 return;
 251         /*
 252          * Disable it in the IO-APIC irq-routing table:
 253          */
 254         memset(&entry, 0, sizeof(entry));
 255         entry.mask = 1;
 256         spin_lock_irqsave(&ioapic_lock, flags);
 257         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 258         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 259         spin_unlock_irqrestore(&ioapic_lock, flags);
 260 }
 261
 262 static void clear_IO_APIC (void)
 263 {
 264         int apic, pin;
 265
 266         for (apic = 0; apic < nr_ioapics; apic++)
 267                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 268                         clear_IO_APIC_pin(apic, pin);
 269 }
 270
 271 #endif /* !CONFIG_XEN */
 272
 273 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 274
 275 /*
 276  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 277  * specific CPU-side IRQs.
 278  */
 279
 280 #define MAX_PIRQS 8
 281 static int pirq_entries [MAX_PIRQS];
 282 static int pirqs_enabled;
 283 int skip_ioapic_setup;
 284 int ioapic_force;
 285
 286 /* dummy parsing: see setup.c */
 287
 288 static int __init disable_ioapic_setup(char *str)
 289 {
 290         skip_ioapic_setup = 1;
 291         return 1;
 292 }
 293
 294 static int __init enable_ioapic_setup(char *str)
 295 {
 296         ioapic_force = 1;
 297         skip_ioapic_setup = 0;
 298         return 1;
 299 }
 300
 301 __setup("noapic", disable_ioapic_setup);
 302 __setup("apic", enable_ioapic_setup);
 303
 304 #ifndef CONFIG_XEN
 305 static int __init setup_disable_8254_timer(char *s)
 306 {
 307         timer_over_8254 = -1;
 308         return 1;
 309 }
 310 static int __init setup_enable_8254_timer(char *s)
 311 {
 312         timer_over_8254 = 2;
 313         return 1;
 314 }
 315
 316 __setup("disable_8254_timer", setup_disable_8254_timer);
 317 __setup("enable_8254_timer", setup_enable_8254_timer);
 318 #endif /* !CONFIG_XEN */
 319
 320 #include <asm/pci-direct.h>
 321 #include <linux/pci_ids.h>
 322 #include <linux/pci.h>
 323
 324 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 325    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 326    Use pci direct infrastructure because this runs before the PCI subsystem.
 327
 328    Can be overwritten with "apic"
 329
 330    And another hack to disable the IOMMU on VIA chipsets.
 331
 332    ... and others. Really should move this somewhere else.
 333
 334    Kludge-O-Rama. */
 335 void __init check_ioapic(void)
 336 {
 337         int num,slot,func;
 338         /* Poor man's PCI discovery */
 339         for (num = 0; num < 32; num++) {
 340                 for (slot = 0; slot < 32; slot++) {
 341                         for (func = 0; func < 8; func++) {
 342                                 u32 class;
 343                                 u32 vendor;
 344                                 u8 type;
 345                                 class = read_pci_config(num,slot,func,
 346                                                         PCI_CLASS_REVISION);
 347                                 if (class == 0xffffffff)
 348                                         break;
 349
 350                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 351                                         continue;
 352
 353                                 vendor = read_pci_config(num, slot, func,
 354                                                          PCI_VENDOR_ID);
 355                                 vendor &= 0xffff;
 356                                 switch (vendor) {
 357                                 case PCI_VENDOR_ID_VIA:
 358 #ifdef CONFIG_GART_IOMMU
 359                                         if ((end_pfn > MAX_DMA32_PFN ||
 360                                              force_iommu) &&
 361                                             !iommu_aperture_allowed) {
 362                                                 printk(KERN_INFO
 363     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 364                                                 iommu_aperture_disabled = 1;
 365                                         }
 366 #endif
 367                                         return;
 368                                 case PCI_VENDOR_ID_NVIDIA:
 369 #ifdef CONFIG_ACPI
 370                                         /* All timer overrides on Nvidia
 371                                            seem to be wrong. Skip them. */
 372                                         acpi_skip_timer_override = 1;
 373                                         printk(KERN_INFO
 374              "Nvidia board detected. Ignoring ACPI timer override.\n");
 375 #endif
 376                                         /* RED-PEN skip them on mptables too? */
 377                                         return;
 378                                 case PCI_VENDOR_ID_ATI:
 379
 380                                 /* This should be actually default, but
 381                                    for 2.6.16 let's do it for ATI only where
 382                                    it's really needed. */
 383 #ifndef CONFIG_XEN
 384                                         if (timer_over_8254 == 1) {
 385                                                 timer_over_8254 = 0;
 386                                         printk(KERN_INFO
 387                 "ATI board detected. Disabling timer routing over 8254.\n");
 388                                         }
 389 #endif
 390                                         return;
 391                                 }
 392
 393
 394                                 /* No multi-function device? */
 395                                 type = read_pci_config_byte(num,slot,func,
 396                                                             PCI_HEADER_TYPE);
 397                                 if (!(type & 0x80))
 398                                         break;
 399                         }
 400                 }
 401         }
 402 }
 403
 404 static int __init ioapic_pirq_setup(char *str)
 405 {
 406         int i, max;
 407         int ints[MAX_PIRQS+1];
 408
 409         get_options(str, ARRAY_SIZE(ints), ints);
 410
 411         for (i = 0; i < MAX_PIRQS; i++)
 412                 pirq_entries[i] = -1;
 413
 414         pirqs_enabled = 1;
 415         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 416         max = MAX_PIRQS;
 417         if (ints[0] < MAX_PIRQS)
 418                 max = ints[0];
 419
 420         for (i = 0; i < max; i++) {
 421                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 422                 /*
 423                  * PIRQs are mapped upside down, usually.
 424                  */
 425                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 426         }
 427         return 1;
 428 }
 429
 430 __setup("pirq=", ioapic_pirq_setup);
 431
 432 /*
 433  * Find the IRQ entry number of a certain pin.
 434  */
 435 static int find_irq_entry(int apic, int pin, int type)
 436 {
 437         int i;
 438
 439         for (i = 0; i < mp_irq_entries; i++)
 440                 if (mp_irqs[i].mpc_irqtype == type &&
 441                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 442                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 443                     mp_irqs[i].mpc_dstirq == pin)
 444                         return i;
 445
 446         return -1;
 447 }
 448
 449 #ifndef CONFIG_XEN
 450 /*
 451  * Find the pin to which IRQ[irq] (ISA) is connected
 452  */
 453 static int __init find_isa_irq_pin(int irq, int type)
 454 {
 455         int i;
 456
 457         for (i = 0; i < mp_irq_entries; i++) {
 458                 int lbus = mp_irqs[i].mpc_srcbus;
 459
 460                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 461                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 462                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 463                     (mp_irqs[i].mpc_irqtype == type) &&
 464                     (mp_irqs[i].mpc_srcbusirq == irq))
 465
 466                         return mp_irqs[i].mpc_dstirq;
 467         }
 468         return -1;
 469 }
 470
 471 static int __init find_isa_irq_apic(int irq, int type)
 472 {
 473         int i;
 474
 475         for (i = 0; i < mp_irq_entries; i++) {
 476                 int lbus = mp_irqs[i].mpc_srcbus;
 477
 478                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 479                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 480                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 481                     (mp_irqs[i].mpc_irqtype == type) &&
 482                     (mp_irqs[i].mpc_srcbusirq == irq))
 483                         break;
 484         }
 485         if (i < mp_irq_entries) {
 486                 int apic;
 487                 for(apic = 0; apic < nr_ioapics; apic++) {
 488                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 489                                 return apic;
 490                 }
 491         }
 492
 493         return -1;
 494 }
 495 #endif
 496
 497 /*
 498  * Find a specific PCI IRQ entry.
 499  * Not an __init, possibly needed by modules
 500  */
 501 static int pin_2_irq(int idx, int apic, int pin);
 502
 503 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 504 {
 505         int apic, i, best_guess = -1;
 506
 507         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 508                 bus, slot, pin);
 509         if (mp_bus_id_to_pci_bus[bus] == -1) {
 510                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 511                 return -1;
 512         }
 513         for (i = 0; i < mp_irq_entries; i++) {
 514                 int lbus = mp_irqs[i].mpc_srcbus;
 515
 516                 for (apic = 0; apic < nr_ioapics; apic++)
 517                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 518                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 519                                 break;
 520
 521                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 522                     !mp_irqs[i].mpc_irqtype &&
 523                     (bus == lbus) &&
 524                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 525                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 526
 527                         if (!(apic || IO_APIC_IRQ(irq)))
 528                                 continue;
 529
 530                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 531                                 return irq;
 532                         /*
 533                          * Use the first all-but-pin matching entry as a
 534                          * best-guess fuzzy result for broken mptables.
 535                          */
 536                         if (best_guess < 0)
 537                                 best_guess = irq;
 538                 }
 539         }
 540         BUG_ON(best_guess >= NR_IRQS);
 541         return best_guess;
 542 }
 543
 544 /*
 545  * EISA Edge/Level control register, ELCR
 546  */
 547 static int EISA_ELCR(unsigned int irq)
 548 {
 549         if (irq < 16) {
 550                 unsigned int port = 0x4d0 + (irq >> 3);
 551                 return (inb(port) >> (irq & 7)) & 1;
 552         }
 553         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 554         return 0;
 555 }
 556
 557 /* EISA interrupts are always polarity zero and can be edge or level
 558  * trigger depending on the ELCR value.  If an interrupt is listed as
 559  * EISA conforming in the MP table, that means its trigger type must
 560  * be read in from the ELCR */
 561
 562 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 563 #define default_EISA_polarity(idx)      (0)
 564
 565 /* ISA interrupts are always polarity zero edge triggered,
 566  * when listed as conforming in the MP table. */
 567
 568 #define default_ISA_trigger(idx)        (0)
 569 #define default_ISA_polarity(idx)       (0)
 570
 571 /* PCI interrupts are always polarity one level triggered,
 572  * when listed as conforming in the MP table. */
 573
 574 #define default_PCI_trigger(idx)        (1)
 575 #define default_PCI_polarity(idx)       (1)
 576
 577 /* MCA interrupts are always polarity zero level triggered,
 578  * when listed as conforming in the MP table. */
 579
 580 #define default_MCA_trigger(idx)        (1)
 581 #define default_MCA_polarity(idx)       (0)
 582
 583 static int __init MPBIOS_polarity(int idx)
 584 {
 585         int bus = mp_irqs[idx].mpc_srcbus;
 586         int polarity;
 587
 588         /*
 589          * Determine IRQ line polarity (high active or low active):
 590          */
 591         switch (mp_irqs[idx].mpc_irqflag & 3)
 592         {
 593                 case 0: /* conforms, ie. bus-type dependent polarity */
 594                 {
 595                         switch (mp_bus_id_to_type[bus])
 596                         {
 597                                 case MP_BUS_ISA: /* ISA pin */
 598                                 {
 599                                         polarity = default_ISA_polarity(idx);
 600                                         break;
 601                                 }
 602                                 case MP_BUS_EISA: /* EISA pin */
 603                                 {
 604                                         polarity = default_EISA_polarity(idx);
 605                                         break;
 606                                 }
 607                                 case MP_BUS_PCI: /* PCI pin */
 608                                 {
 609                                         polarity = default_PCI_polarity(idx);
 610                                         break;
 611                                 }
 612                                 case MP_BUS_MCA: /* MCA pin */
 613                                 {
 614                                         polarity = default_MCA_polarity(idx);
 615                                         break;
 616                                 }
 617                                 default:
 618                                 {
 619                                         printk(KERN_WARNING "broken BIOS!!\n");
 620                                         polarity = 1;
 621                                         break;
 622                                 }
 623                         }
 624                         break;
 625                 }
 626                 case 1: /* high active */
 627                 {
 628                         polarity = 0;
 629                         break;
 630                 }
 631                 case 2: /* reserved */
 632                 {
 633                         printk(KERN_WARNING "broken BIOS!!\n");
 634                         polarity = 1;
 635                         break;
 636                 }
 637                 case 3: /* low active */
 638                 {
 639                         polarity = 1;
 640                         break;
 641                 }
 642                 default: /* invalid */
 643                 {
 644                         printk(KERN_WARNING "broken BIOS!!\n");
 645                         polarity = 1;
 646                         break;
 647                 }
 648         }
 649         return polarity;
 650 }
 651
 652 static int MPBIOS_trigger(int idx)
 653 {
 654         int bus = mp_irqs[idx].mpc_srcbus;
 655         int trigger;
 656
 657         /*
 658          * Determine IRQ trigger mode (edge or level sensitive):
 659          */
 660         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 661         {
 662                 case 0: /* conforms, ie. bus-type dependent */
 663                 {
 664                         switch (mp_bus_id_to_type[bus])
 665                         {
 666                                 case MP_BUS_ISA: /* ISA pin */
 667                                 {
 668                                         trigger = default_ISA_trigger(idx);
 669                                         break;
 670                                 }
 671                                 case MP_BUS_EISA: /* EISA pin */
 672                                 {
 673                                         trigger = default_EISA_trigger(idx);
 674                                         break;
 675                                 }
 676                                 case MP_BUS_PCI: /* PCI pin */
 677                                 {
 678                                         trigger = default_PCI_trigger(idx);
 679                                         break;
 680                                 }
 681                                 case MP_BUS_MCA: /* MCA pin */
 682                                 {
 683                                         trigger = default_MCA_trigger(idx);
 684                                         break;
 685                                 }
 686                                 default:
 687                                 {
 688                                         printk(KERN_WARNING "broken BIOS!!\n");
 689                                         trigger = 1;
 690                                         break;
 691                                 }
 692                         }
 693                         break;
 694                 }
 695                 case 1: /* edge */
 696                 {
 697                         trigger = 0;
 698                         break;
 699                 }
 700                 case 2: /* reserved */
 701                 {
 702                         printk(KERN_WARNING "broken BIOS!!\n");
 703                         trigger = 1;
 704                         break;
 705                 }
 706                 case 3: /* level */
 707                 {
 708                         trigger = 1;
 709                         break;
 710                 }
 711                 default: /* invalid */
 712                 {
 713                         printk(KERN_WARNING "broken BIOS!!\n");
 714                         trigger = 0;
 715                         break;
 716                 }
 717         }
 718         return trigger;
 719 }
 720
 721 static inline int irq_polarity(int idx)
 722 {
 723         return MPBIOS_polarity(idx);
 724 }
 725
 726 static inline int irq_trigger(int idx)
 727 {
 728         return MPBIOS_trigger(idx);
 729 }
 730
 731 static int next_irq = 16;
 732
 733 /*
 734  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 735  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 736  * from ACPI, which can reach 800 in large boxen.
 737  *
 738  * Compact the sparse GSI space into a sequential IRQ series and reuse
 739  * vectors if possible.
 740  */
 741 int gsi_irq_sharing(int gsi)
 742 {
 743         int i, tries, vector;
 744
 745         BUG_ON(gsi >= NR_IRQ_VECTORS);
 746
 747         if (platform_legacy_irq(gsi))
 748                 return gsi;
 749
 750         if (gsi_2_irq[gsi] != 0xFF)
 751                 return (int)gsi_2_irq[gsi];
 752
 753         tries = NR_IRQS;
 754   try_again:
 755         vector = assign_irq_vector(gsi);
 756
 757         /*
 758          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 759          * use of vector and if found, return that IRQ.  However, we never want
 760          * to share legacy IRQs, which usually have a different trigger mode
 761          * than PCI.
 762          */
 763         for (i = 0; i < NR_IRQS; i++)
 764                 if (IO_APIC_VECTOR(i) == vector)
 765                         break;
 766         if (platform_legacy_irq(i)) {
 767                 if (--tries >= 0) {
 768                         IO_APIC_VECTOR(i) = 0;
 769                         goto try_again;
 770                 }
 771                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 772         }
 773         if (i < NR_IRQS) {
 774                 gsi_2_irq[gsi] = i;
 775                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 776                                 gsi, vector, i);
 777                 return i;
 778         }
 779
 780         i = next_irq++;
 781         BUG_ON(i >= NR_IRQS);
 782         gsi_2_irq[gsi] = i;
 783         IO_APIC_VECTOR(i) = vector;
 784         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 785                         gsi, vector, i);
 786         return i;
 787 }
 788
 789 static int pin_2_irq(int idx, int apic, int pin)
 790 {
 791         int irq, i;
 792         int bus = mp_irqs[idx].mpc_srcbus;
 793
 794         /*
 795          * Debugging check, we are in big trouble if this message pops up!
 796          */
 797         if (mp_irqs[idx].mpc_dstirq != pin)
 798                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 799
 800         switch (mp_bus_id_to_type[bus])
 801         {
 802                 case MP_BUS_ISA: /* ISA pin */
 803                 case MP_BUS_EISA:
 804                 case MP_BUS_MCA:
 805                 {
 806                         irq = mp_irqs[idx].mpc_srcbusirq;
 807                         break;
 808                 }
 809                 case MP_BUS_PCI: /* PCI pin */
 810                 {
 811                         /*
 812                          * PCI IRQs are mapped in order
 813                          */
 814                         i = irq = 0;
 815                         while (i < apic)
 816                                 irq += nr_ioapic_registers[i++];
 817                         irq += pin;
 818                         irq = gsi_irq_sharing(irq);
 819                         break;
 820                 }
 821                 default:
 822                 {
 823                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 824                         irq = 0;
 825                         break;
 826                 }
 827         }
 828         BUG_ON(irq >= NR_IRQS);
 829
 830         /*
 831          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 832          */
 833         if ((pin >= 16) && (pin <= 23)) {
 834                 if (pirq_entries[pin-16] != -1) {
 835                         if (!pirq_entries[pin-16]) {
 836                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 837                         } else {
 838                                 irq = pirq_entries[pin-16];
 839                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 840                                                 pin-16, irq);
 841                         }
 842                 }
 843         }
 844         BUG_ON(irq >= NR_IRQS);
 845         return irq;
 846 }
 847
 848 static inline int IO_APIC_irq_trigger(int irq)
 849 {
 850         int apic, idx, pin;
 851
 852         for (apic = 0; apic < nr_ioapics; apic++) {
 853                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 854                         idx = find_irq_entry(apic,pin,mp_INT);
 855                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 856                                 return irq_trigger(idx);
 857                 }
 858         }
 859         /*
 860          * nonexistent IRQs are edge default
 861          */
 862         return 0;
 863 }
 864
 865 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 866 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
 867
 868 int assign_irq_vector(int irq)
 869 {
 870         struct physdev_irq irq_op;
 871
 872         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 873         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
 874                 return IO_APIC_VECTOR(irq);
 875
 876         irq_op.irq = irq;
 877         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
 878                 return -ENOSPC;
 879
 880         vector_irq[irq_op.vector] = irq;
 881         if (irq != AUTO_ASSIGN)
 882                 IO_APIC_VECTOR(irq) = irq_op.vector;
 883
 884         return irq_op.vector;
 885 }
 886
 887 extern void (*interrupt[NR_IRQS])(void);
 888 #ifndef CONFIG_XEN
 889 static struct hw_interrupt_type ioapic_level_type;
 890 static struct hw_interrupt_type ioapic_edge_type;
 891
 892 #define IOAPIC_AUTO     -1
 893 #define IOAPIC_EDGE     0
 894 #define IOAPIC_LEVEL    1
 895
 896 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 897 {
 898         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 899                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 900                                 trigger == IOAPIC_LEVEL)
 901                         irq_desc[vector].handler = &ioapic_level_type;
 902                 else
 903                         irq_desc[vector].handler = &ioapic_edge_type;
 904                 set_intr_gate(vector, interrupt[vector]);
 905         } else  {
 906                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 907                                 trigger == IOAPIC_LEVEL)
 908                         irq_desc[irq].handler = &ioapic_level_type;
 909                 else
 910                         irq_desc[irq].handler = &ioapic_edge_type;
 911                 set_intr_gate(vector, interrupt[irq]);
 912         }
 913 }
 914 #else
 915 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
 916 #endif /* !CONFIG_XEN */
 917
 918 static void __init setup_IO_APIC_irqs(void)
 919 {
 920         struct IO_APIC_route_entry entry;
 921         int apic, pin, idx, irq, first_notcon = 1, vector;
 922         unsigned long flags;
 923
 924         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 925
 926         for (apic = 0; apic < nr_ioapics; apic++) {
 927         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 928
 929                 /*
 930                  * add it to the IO-APIC irq-routing table:
 931                  */
 932                 memset(&entry,0,sizeof(entry));
 933
 934                 entry.delivery_mode = INT_DELIVERY_MODE;
 935                 entry.dest_mode = INT_DEST_MODE;
 936                 entry.mask = 0;                         /* enable IRQ */
 937                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 938
 939                 idx = find_irq_entry(apic,pin,mp_INT);
 940                 if (idx == -1) {
 941                         if (first_notcon) {
 942                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 943                                 first_notcon = 0;
 944                         } else
 945                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 946                         continue;
 947                 }
 948
 949                 entry.trigger = irq_trigger(idx);
 950                 entry.polarity = irq_polarity(idx);
 951
 952                 if (irq_trigger(idx)) {
 953                         entry.trigger = 1;
 954                         entry.mask = 1;
 955                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 956                 }
 957
 958                 irq = pin_2_irq(idx, apic, pin);
 959                 add_pin_to_irq(irq, apic, pin);
 960
 961                 if (/* !apic && */ !IO_APIC_IRQ(irq))
 962                         continue;
 963
 964                 if (IO_APIC_IRQ(irq)) {
 965                         vector = assign_irq_vector(irq);
 966                         entry.vector = vector;
 967
 968                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 969                         if (!apic && (irq < 16))
 970                                 disable_8259A_irq(irq);
 971                 }
 972                 spin_lock_irqsave(&ioapic_lock, flags);
 973                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 974                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 975                 set_native_irq_info(irq, TARGET_CPUS);
 976                 spin_unlock_irqrestore(&ioapic_lock, flags);
 977         }
 978         }
 979
 980         if (!first_notcon)
 981                 apic_printk(APIC_VERBOSE," not connected.\n");
 982 }
 983
 984 #ifndef CONFIG_XEN
 985 /*
 986  * Set up the 8259A-master output pin as broadcast to all
 987  * CPUs.
 988  */
 989 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 990 {
 991         struct IO_APIC_route_entry entry;
 992         unsigned long flags;
 993
 994         memset(&entry,0,sizeof(entry));
 995
 996         disable_8259A_irq(0);
 997
 998         /* mask LVT0 */
 999         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1000
1001         /*
1002          * We use logical delivery to get the timer IRQ
1003          * to the first CPU.
1004          */
1005         entry.dest_mode = INT_DEST_MODE;
1006         entry.mask = 0;                                 /* unmask IRQ now */
1007         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1008         entry.delivery_mode = INT_DELIVERY_MODE;
1009         entry.polarity = 0;
1010         entry.trigger = 0;
1011         entry.vector = vector;
1012
1013         /*
1014          * The timer IRQ doesn't have to know that behind the
1015          * scene we have a 8259A-master in AEOI mode ...
1016          */
1017         irq_desc[0].handler = &ioapic_edge_type;
1018
1019         /*
1020          * Add it to the IO-APIC irq-routing table:
1021          */
1022         spin_lock_irqsave(&ioapic_lock, flags);
1023         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1024         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1025         spin_unlock_irqrestore(&ioapic_lock, flags);
1026
1027         enable_8259A_irq(0);
1028 }
1029
1030 void __init UNEXPECTED_IO_APIC(void)
1031 {
1032 }
1033
1034 void __apicdebuginit print_IO_APIC(void)
1035 {
1036         int apic, i;
1037         union IO_APIC_reg_00 reg_00;
1038         union IO_APIC_reg_01 reg_01;
1039         union IO_APIC_reg_02 reg_02;
1040         unsigned long flags;
1041
1042         if (apic_verbosity == APIC_QUIET)
1043                 return;
1044
1045         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1046         for (i = 0; i < nr_ioapics; i++)
1047                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1048                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1049
1050         /*
1051          * We are a bit conservative about what we expect.  We have to
1052          * know about every hardware change ASAP.
1053          */
1054         printk(KERN_INFO "testing the IO APIC.......................\n");
1055
1056         for (apic = 0; apic < nr_ioapics; apic++) {
1057
1058         spin_lock_irqsave(&ioapic_lock, flags);
1059         reg_00.raw = io_apic_read(apic, 0);
1060         reg_01.raw = io_apic_read(apic, 1);
1061         if (reg_01.bits.version >= 0x10)
1062                 reg_02.raw = io_apic_read(apic, 2);
1063         spin_unlock_irqrestore(&ioapic_lock, flags);
1064
1065         printk("\n");
1066         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1067         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1068         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1069         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1070                 UNEXPECTED_IO_APIC();
1071
1072         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1073         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1074         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1075                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1076                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1077                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1078                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1079                 (reg_01.bits.entries != 0x2E) &&
1080                 (reg_01.bits.entries != 0x3F) &&
1081                 (reg_01.bits.entries != 0x03)
1082         )
1083                 UNEXPECTED_IO_APIC();
1084
1085         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1086         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1087         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1088                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1089                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1090                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1091                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1092                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1093         )
1094                 UNEXPECTED_IO_APIC();
1095         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1096                 UNEXPECTED_IO_APIC();
1097
1098         if (reg_01.bits.version >= 0x10) {
1099                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1100                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1101                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1102                         UNEXPECTED_IO_APIC();
1103         }
1104
1105         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1106
1107         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1108                           " Stat Dest Deli Vect:   \n");
1109
1110         for (i = 0; i <= reg_01.bits.entries; i++) {
1111                 struct IO_APIC_route_entry entry;
1112
1113                 spin_lock_irqsave(&ioapic_lock, flags);
1114                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1115                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1116                 spin_unlock_irqrestore(&ioapic_lock, flags);
1117
1118                 printk(KERN_DEBUG " %02x %03X %02X  ",
1119                         i,
1120                         entry.dest.logical.logical_dest,
1121                         entry.dest.physical.physical_dest
1122                 );
1123
1124                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1125                         entry.mask,
1126                         entry.trigger,
1127                         entry.irr,
1128                         entry.polarity,
1129                         entry.delivery_status,
1130                         entry.dest_mode,
1131                         entry.delivery_mode,
1132                         entry.vector
1133                 );
1134         }
1135         }
1136         if (use_pci_vector())
1137                 printk(KERN_INFO "Using vector-based indexing\n");
1138         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1139         for (i = 0; i < NR_IRQS; i++) {
1140                 struct irq_pin_list *entry = irq_2_pin + i;
1141                 if (entry->pin < 0)
1142                         continue;
1143                 if (use_pci_vector() && !platform_legacy_irq(i))
1144                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1145                 else
1146                         printk(KERN_DEBUG "IRQ%d ", i);
1147                 for (;;) {
1148                         printk("-> %d:%d", entry->apic, entry->pin);
1149                         if (!entry->next)
1150                                 break;
1151                         entry = irq_2_pin + entry->next;
1152                 }
1153                 printk("\n");
1154         }
1155
1156         printk(KERN_INFO ".................................... done.\n");
1157
1158         return;
1159 }
1160
1161 #if 0
1162
1163 static __apicdebuginit void print_APIC_bitfield (int base)
1164 {
1165         unsigned int v;
1166         int i, j;
1167
1168         if (apic_verbosity == APIC_QUIET)
1169                 return;
1170
1171         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1172         for (i = 0; i < 8; i++) {
1173                 v = apic_read(base + i*0x10);
1174                 for (j = 0; j < 32; j++) {
1175                         if (v & (1<<j))
1176                                 printk("1");
1177                         else
1178                                 printk("0");
1179                 }
1180                 printk("\n");
1181         }
1182 }
1183
1184 void __apicdebuginit print_local_APIC(void * dummy)
1185 {
1186         unsigned int v, ver, maxlvt;
1187
1188         if (apic_verbosity == APIC_QUIET)
1189                 return;
1190
1191         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1192                 smp_processor_id(), hard_smp_processor_id());
1193         v = apic_read(APIC_ID);
1194         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1195         v = apic_read(APIC_LVR);
1196         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1197         ver = GET_APIC_VERSION(v);
1198         maxlvt = get_maxlvt();
1199
1200         v = apic_read(APIC_TASKPRI);
1201         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1202
1203         v = apic_read(APIC_ARBPRI);
1204         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1205                 v & APIC_ARBPRI_MASK);
1206         v = apic_read(APIC_PROCPRI);
1207         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1208
1209         v = apic_read(APIC_EOI);
1210         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1211         v = apic_read(APIC_RRR);
1212         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1213         v = apic_read(APIC_LDR);
1214         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1215         v = apic_read(APIC_DFR);
1216         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1217         v = apic_read(APIC_SPIV);
1218         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1219
1220         printk(KERN_DEBUG "... APIC ISR field:\n");
1221         print_APIC_bitfield(APIC_ISR);
1222         printk(KERN_DEBUG "... APIC TMR field:\n");
1223         print_APIC_bitfield(APIC_TMR);
1224         printk(KERN_DEBUG "... APIC IRR field:\n");
1225         print_APIC_bitfield(APIC_IRR);
1226
1227         v = apic_read(APIC_ESR);
1228         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1229
1230         v = apic_read(APIC_ICR);
1231         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1232         v = apic_read(APIC_ICR2);
1233         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1234
1235         v = apic_read(APIC_LVTT);
1236         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1237
1238         if (maxlvt > 3) {                       /* PC is LVT#4. */
1239                 v = apic_read(APIC_LVTPC);
1240                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1241         }
1242         v = apic_read(APIC_LVT0);
1243         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1244         v = apic_read(APIC_LVT1);
1245         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1246
1247         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1248                 v = apic_read(APIC_LVTERR);
1249                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1250         }
1251
1252         v = apic_read(APIC_TMICT);
1253         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1254         v = apic_read(APIC_TMCCT);
1255         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1256         v = apic_read(APIC_TDCR);
1257         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1258         printk("\n");
1259 }
1260
1261 void print_all_local_APICs (void)
1262 {
1263         on_each_cpu(print_local_APIC, NULL, 1, 1);
1264 }
1265
1266 void __apicdebuginit print_PIC(void)
1267 {
1268         unsigned int v;
1269         unsigned long flags;
1270
1271         if (apic_verbosity == APIC_QUIET)
1272                 return;
1273
1274         printk(KERN_DEBUG "\nprinting PIC contents\n");
1275
1276         spin_lock_irqsave(&i8259A_lock, flags);
1277
1278         v = inb(0xa1) << 8 | inb(0x21);
1279         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1280
1281         v = inb(0xa0) << 8 | inb(0x20);
1282         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1283
1284         outb(0x0b,0xa0);
1285         outb(0x0b,0x20);
1286         v = inb(0xa0) << 8 | inb(0x20);
1287         outb(0x0a,0xa0);
1288         outb(0x0a,0x20);
1289
1290         spin_unlock_irqrestore(&i8259A_lock, flags);
1291
1292         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1293
1294         v = inb(0x4d1) << 8 | inb(0x4d0);
1295         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1296 }
1297
1298 #endif  /*  0  */
1299
1300 #else
1301 void __init print_IO_APIC(void) { }
1302 #endif /* !CONFIG_XEN */
1303
1304 static void __init enable_IO_APIC(void)
1305 {
1306         union IO_APIC_reg_01 reg_01;
1307 #ifndef CONFIG_XEN
1308         int i8259_apic, i8259_pin;
1309 #endif
1310         int i, apic;
1311         unsigned long flags;
1312
1313         for (i = 0; i < PIN_MAP_SIZE; i++) {
1314                 irq_2_pin[i].pin = -1;
1315                 irq_2_pin[i].next = 0;
1316         }
1317         if (!pirqs_enabled)
1318                 for (i = 0; i < MAX_PIRQS; i++)
1319                         pirq_entries[i] = -1;
1320
1321         /*
1322          * The number of IO-APIC IRQ registers (== #pins):
1323          */
1324         for (apic = 0; apic < nr_ioapics; apic++) {
1325                 spin_lock_irqsave(&ioapic_lock, flags);
1326                 reg_01.raw = io_apic_read(apic, 1);
1327                 spin_unlock_irqrestore(&ioapic_lock, flags);
1328                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1329         }
1330 #ifndef CONFIG_XEN
1331         for(apic = 0; apic < nr_ioapics; apic++) {
1332                 int pin;
1333                 /* See if any of the pins is in ExtINT mode */
1334                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1335                         struct IO_APIC_route_entry entry;
1336                         spin_lock_irqsave(&ioapic_lock, flags);
1337                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1338                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1339                         spin_unlock_irqrestore(&ioapic_lock, flags);
1340
1341
1342                         /* If the interrupt line is enabled and in ExtInt mode
1343                          * I have found the pin where the i8259 is connected.
1344                          */
1345                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1346                                 ioapic_i8259.apic = apic;
1347                                 ioapic_i8259.pin  = pin;
1348                                 goto found_i8259;
1349                         }
1350                 }
1351         }
1352  found_i8259:
1353         /* Look to see what if the MP table has reported the ExtINT */
1354         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1355         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1356         /* Trust the MP table if nothing is setup in the hardware */
1357         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1358                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1359                 ioapic_i8259.pin  = i8259_pin;
1360                 ioapic_i8259.apic = i8259_apic;
1361         }
1362         /* Complain if the MP table and the hardware disagree */
1363         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1364                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1365         {
1366                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1367         }
1368 #endif
1369
1370         /*
1371          * Do not trust the IO-APIC being empty at bootup
1372          */
1373         clear_IO_APIC();
1374 }
1375
1376 /*
1377  * Not an __init, needed by the reboot code
1378  */
1379 void disable_IO_APIC(void)
1380 {
1381         /*
1382          * Clear the IO-APIC before rebooting:
1383          */
1384         clear_IO_APIC();
1385
1386 #ifndef CONFIG_XEN
1387         /*
1388          * If the i8259 is routed through an IOAPIC
1389          * Put that IOAPIC in virtual wire mode
1390          * so legacy interrupts can be delivered.
1391          */
1392         if (ioapic_i8259.pin != -1) {
1393                 struct IO_APIC_route_entry entry;
1394                 unsigned long flags;
1395
1396                 memset(&entry, 0, sizeof(entry));
1397                 entry.mask            = 0; /* Enabled */
1398                 entry.trigger         = 0; /* Edge */
1399                 entry.irr             = 0;
1400                 entry.polarity        = 0; /* High */
1401                 entry.delivery_status = 0;
1402                 entry.dest_mode       = 0; /* Physical */
1403                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1404                 entry.vector          = 0;
1405                 entry.dest.physical.physical_dest =
1406                                         GET_APIC_ID(apic_read(APIC_ID));
1407
1408                 /*
1409                  * Add it to the IO-APIC irq-routing table:
1410                  */
1411                 spin_lock_irqsave(&ioapic_lock, flags);
1412                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1413                         *(((int *)&entry)+1));
1414                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1415                         *(((int *)&entry)+0));
1416                 spin_unlock_irqrestore(&ioapic_lock, flags);
1417         }
1418
1419         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1420 #endif
1421 }
1422
1423 /*
1424  * function to set the IO-APIC physical IDs based on the
1425  * values stored in the MPC table.
1426  *
1427  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1428  */
1429
1430 #ifndef CONFIG_XEN
1431 static void __init setup_ioapic_ids_from_mpc (void)
1432 {
1433         union IO_APIC_reg_00 reg_00;
1434         int apic;
1435         int i;
1436         unsigned char old_id;
1437         unsigned long flags;
1438
1439         /*
1440          * Set the IOAPIC ID to the value stored in the MPC table.
1441          */
1442         for (apic = 0; apic < nr_ioapics; apic++) {
1443
1444                 /* Read the register 0 value */
1445                 spin_lock_irqsave(&ioapic_lock, flags);
1446                 reg_00.raw = io_apic_read(apic, 0);
1447                 spin_unlock_irqrestore(&ioapic_lock, flags);
1448
1449                 old_id = mp_ioapics[apic].mpc_apicid;
1450
1451
1452                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1453
1454
1455                 /*
1456                  * We need to adjust the IRQ routing table
1457                  * if the ID changed.
1458                  */
1459                 if (old_id != mp_ioapics[apic].mpc_apicid)
1460                         for (i = 0; i < mp_irq_entries; i++)
1461                                 if (mp_irqs[i].mpc_dstapic == old_id)
1462                                         mp_irqs[i].mpc_dstapic
1463                                                 = mp_ioapics[apic].mpc_apicid;
1464
1465                 /*
1466                  * Read the right value from the MPC table and
1467                  * write it into the ID register.
1468                  */
1469                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1470                                 mp_ioapics[apic].mpc_apicid);
1471
1472                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1473                 spin_lock_irqsave(&ioapic_lock, flags);
1474                 io_apic_write(apic, 0, reg_00.raw);
1475                 spin_unlock_irqrestore(&ioapic_lock, flags);
1476
1477                 /*
1478                  * Sanity check
1479                  */
1480                 spin_lock_irqsave(&ioapic_lock, flags);
1481                 reg_00.raw = io_apic_read(apic, 0);
1482                 spin_unlock_irqrestore(&ioapic_lock, flags);
1483                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1484                         printk("could not set ID!\n");
1485                 else
1486                         apic_printk(APIC_VERBOSE," ok.\n");
1487         }
1488 }
1489 #else
1490 static void __init setup_ioapic_ids_from_mpc(void) { }
1491 #endif
1492
1493 /*
1494  * There is a nasty bug in some older SMP boards, their mptable lies
1495  * about the timer IRQ. We do the following to work around the situation:
1496  *
1497  *      - timer IRQ defaults to IO-APIC IRQ
1498  *      - if this function detects that timer IRQs are defunct, then we fall
1499  *        back to ISA timer IRQs
1500  */
1501 #ifndef CONFIG_XEN
1502 static int __init timer_irq_works(void)
1503 {
1504         unsigned long t1 = jiffies;
1505
1506         local_irq_enable();
1507         /* Let ten ticks pass... */
1508         mdelay((10 * 1000) / HZ);
1509
1510         /*
1511          * Expect a few ticks at least, to be sure some possible
1512          * glue logic does not lock up after one or two first
1513          * ticks in a non-ExtINT mode.  Also the local APIC
1514          * might have cached one ExtINT interrupt.  Finally, at
1515          * least one tick may be lost due to delays.
1516          */
1517
1518         /* jiffies wrap? */
1519         if (jiffies - t1 > 4)
1520                 return 1;
1521         return 0;
1522 }
1523
1524 /*
1525  * In the SMP+IOAPIC case it might happen that there are an unspecified
1526  * number of pending IRQ events unhandled. These cases are very rare,
1527  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1528  * better to do it this way as thus we do not have to be aware of
1529  * 'pending' interrupts in the IRQ path, except at this point.
1530  */
1531 /*
1532  * Edge triggered needs to resend any interrupt
1533  * that was delayed but this is now handled in the device
1534  * independent code.
1535  */
1536
1537 /*
1538  * Starting up a edge-triggered IO-APIC interrupt is
1539  * nasty - we need to make sure that we get the edge.
1540  * If it is already asserted for some reason, we need
1541  * return 1 to indicate that is was pending.
1542  *
1543  * This is not complete - we should be able to fake
1544  * an edge even if it isn't on the 8259A...
1545  */
1546
1547 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1548 {
1549         int was_pending = 0;
1550         unsigned long flags;
1551
1552         spin_lock_irqsave(&ioapic_lock, flags);
1553         if (irq < 16) {
1554                 disable_8259A_irq(irq);
1555                 if (i8259A_irq_pending(irq))
1556                         was_pending = 1;
1557         }
1558         __unmask_IO_APIC_irq(irq);
1559         spin_unlock_irqrestore(&ioapic_lock, flags);
1560
1561         return was_pending;
1562 }
1563
1564 /*
1565  * Once we have recorded IRQ_PENDING already, we can mask the
1566  * interrupt for real. This prevents IRQ storms from unhandled
1567  * devices.
1568  */
1569 static void ack_edge_ioapic_irq(unsigned int irq)
1570 {
1571         move_irq(irq);
1572         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1573                                         == (IRQ_PENDING | IRQ_DISABLED))
1574                 mask_IO_APIC_irq(irq);
1575         ack_APIC_irq();
1576 }
1577
1578 /*
1579  * Level triggered interrupts can just be masked,
1580  * and shutting down and starting up the interrupt
1581  * is the same as enabling and disabling them -- except
1582  * with a startup need to return a "was pending" value.
1583  *
1584  * Level triggered interrupts are special because we
1585  * do not touch any IO-APIC register while handling
1586  * them. We ack the APIC in the end-IRQ handler, not
1587  * in the start-IRQ-handler. Protection against reentrance
1588  * from the same interrupt is still provided, both by the
1589  * generic IRQ layer and by the fact that an unacked local
1590  * APIC does not accept IRQs.
1591  */
1592 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1593 {
1594         unmask_IO_APIC_irq(irq);
1595
1596         return 0; /* don't check for pending */
1597 }
1598
1599 static void end_level_ioapic_irq (unsigned int irq)
1600 {
1601         move_irq(irq);
1602         ack_APIC_irq();
1603 }
1604
1605 #ifdef CONFIG_PCI_MSI
1606 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1607 {
1608         int irq = vector_to_irq(vector);
1609
1610         return startup_edge_ioapic_irq(irq);
1611 }
1612
1613 static void ack_edge_ioapic_vector(unsigned int vector)
1614 {
1615         int irq = vector_to_irq(vector);
1616
1617         move_native_irq(vector);
1618         ack_edge_ioapic_irq(irq);
1619 }
1620
1621 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1622 {
1623         int irq = vector_to_irq(vector);
1624
1625         return startup_level_ioapic_irq (irq);
1626 }
1627
1628 static void end_level_ioapic_vector (unsigned int vector)
1629 {
1630         int irq = vector_to_irq(vector);
1631
1632         move_native_irq(vector);
1633         end_level_ioapic_irq(irq);
1634 }
1635
1636 static void mask_IO_APIC_vector (unsigned int vector)
1637 {
1638         int irq = vector_to_irq(vector);
1639
1640         mask_IO_APIC_irq(irq);
1641 }
1642
1643 static void unmask_IO_APIC_vector (unsigned int vector)
1644 {
1645         int irq = vector_to_irq(vector);
1646
1647         unmask_IO_APIC_irq(irq);
1648 }
1649
1650 #ifdef CONFIG_SMP
1651 static void set_ioapic_affinity_vector (unsigned int vector,
1652                                         cpumask_t cpu_mask)
1653 {
1654         int irq = vector_to_irq(vector);
1655
1656         set_native_irq_info(vector, cpu_mask);
1657         set_ioapic_affinity_irq(irq, cpu_mask);
1658 }
1659 #endif // CONFIG_SMP
1660 #endif // CONFIG_PCI_MSI
1661
1662 /*
1663  * Level and edge triggered IO-APIC interrupts need different handling,
1664  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1665  * handled with the level-triggered descriptor, but that one has slightly
1666  * more overhead. Level-triggered interrupts cannot be handled with the
1667  * edge-triggered handler, without risking IRQ storms and other ugly
1668  * races.
1669  */
1670
1671 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1672         .typename = "IO-APIC-edge",
1673         .startup        = startup_edge_ioapic,
1674         .shutdown       = shutdown_edge_ioapic,
1675         .enable         = enable_edge_ioapic,
1676         .disable        = disable_edge_ioapic,
1677         .ack            = ack_edge_ioapic,
1678         .end            = end_edge_ioapic,
1679 #ifdef CONFIG_SMP
1680         .set_affinity = set_ioapic_affinity,
1681 #endif
1682 };
1683
1684 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1685         .typename = "IO-APIC-level",
1686         .startup        = startup_level_ioapic,
1687         .shutdown       = shutdown_level_ioapic,
1688         .enable         = enable_level_ioapic,
1689         .disable        = disable_level_ioapic,
1690         .ack            = mask_and_ack_level_ioapic,
1691         .end            = end_level_ioapic,
1692 #ifdef CONFIG_SMP
1693         .set_affinity = set_ioapic_affinity,
1694 #endif
1695 };
1696 #endif /* !CONFIG_XEN */
1697
1698 static inline void init_IO_APIC_traps(void)
1699 {
1700         int irq;
1701
1702         /*
1703          * NOTE! The local APIC isn't very good at handling
1704          * multiple interrupts at the same interrupt level.
1705          * As the interrupt level is determined by taking the
1706          * vector number and shifting that right by 4, we
1707          * want to spread these out a bit so that they don't
1708          * all fall in the same interrupt level.
1709          *
1710          * Also, we've got to be careful not to trash gate
1711          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1712          */
1713         for (irq = 0; irq < NR_IRQS ; irq++) {
1714                 int tmp = irq;
1715                 if (use_pci_vector()) {
1716                         if (!platform_legacy_irq(tmp))
1717                                 if ((tmp = vector_to_irq(tmp)) == -1)
1718                                         continue;
1719                 }
1720                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1721                         /*
1722                          * Hmm.. We don't have an entry for this,
1723                          * so default to an old-fashioned 8259
1724                          * interrupt if we can..
1725                          */
1726                         if (irq < 16)
1727                                 make_8259A_irq(irq);
1728 #ifndef CONFIG_XEN
1729                         else
1730                                 /* Strange. Oh, well.. */
1731                                 irq_desc[irq].handler = &no_irq_type;
1732 #endif
1733                 }
1734         }
1735 }
1736
1737 #ifndef CONFIG_XEN
1738 static void enable_lapic_irq (unsigned int irq)
1739 {
1740         unsigned long v;
1741
1742         v = apic_read(APIC_LVT0);
1743         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1744 }
1745
1746 static void disable_lapic_irq (unsigned int irq)
1747 {
1748         unsigned long v;
1749
1750         v = apic_read(APIC_LVT0);
1751         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1752 }
1753
1754 static void ack_lapic_irq (unsigned int irq)
1755 {
1756         ack_APIC_irq();
1757 }
1758
1759 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1760
1761 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1762         .typename = "local-APIC-edge",
1763         .startup = NULL, /* startup_irq() not used for IRQ0 */
1764         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1765         .enable = enable_lapic_irq,
1766         .disable = disable_lapic_irq,
1767         .ack = ack_lapic_irq,
1768         .end = end_lapic_irq,
1769 };
1770
1771 static void setup_nmi (void)
1772 {
1773         /*
1774          * Dirty trick to enable the NMI watchdog ...
1775          * We put the 8259A master into AEOI mode and
1776          * unmask on all local APICs LVT0 as NMI.
1777          *
1778          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1779          * is from Maciej W. Rozycki - so we do not have to EOI from
1780          * the NMI handler or the timer interrupt.
1781          */
1782         printk(KERN_INFO "activating NMI Watchdog ...");
1783
1784         enable_NMI_through_LVT0(NULL);
1785
1786         printk(" done.\n");
1787 }
1788
1789 /*
1790  * This looks a bit hackish but it's about the only one way of sending
1791  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1792  * not support the ExtINT mode, unfortunately.  We need to send these
1793  * cycles as some i82489DX-based boards have glue logic that keeps the
1794  * 8259A interrupt line asserted until INTA.  --macro
1795  */
1796 static inline void unlock_ExtINT_logic(void)
1797 {
1798         int apic, pin, i;
1799         struct IO_APIC_route_entry entry0, entry1;
1800         unsigned char save_control, save_freq_select;
1801         unsigned long flags;
1802
1803         pin  = find_isa_irq_pin(8, mp_INT);
1804         apic = find_isa_irq_apic(8, mp_INT);
1805         if (pin == -1)
1806                 return;
1807
1808         spin_lock_irqsave(&ioapic_lock, flags);
1809         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1810         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1811         spin_unlock_irqrestore(&ioapic_lock, flags);
1812         clear_IO_APIC_pin(apic, pin);
1813
1814         memset(&entry1, 0, sizeof(entry1));
1815
1816         entry1.dest_mode = 0;                   /* physical delivery */
1817         entry1.mask = 0;                        /* unmask IRQ now */
1818         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1819         entry1.delivery_mode = dest_ExtINT;
1820         entry1.polarity = entry0.polarity;
1821         entry1.trigger = 0;
1822         entry1.vector = 0;
1823
1824         spin_lock_irqsave(&ioapic_lock, flags);
1825         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1826         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1827         spin_unlock_irqrestore(&ioapic_lock, flags);
1828
1829         save_control = CMOS_READ(RTC_CONTROL);
1830         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1831         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1832                    RTC_FREQ_SELECT);
1833         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1834
1835         i = 100;
1836         while (i-- > 0) {
1837                 mdelay(10);
1838                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1839                         i -= 10;
1840         }
1841
1842         CMOS_WRITE(save_control, RTC_CONTROL);
1843         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1844         clear_IO_APIC_pin(apic, pin);
1845
1846         spin_lock_irqsave(&ioapic_lock, flags);
1847         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1848         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1849         spin_unlock_irqrestore(&ioapic_lock, flags);
1850 }
1851
1852 int timer_uses_ioapic_pin_0;
1853
1854 /*
1855  * This code may look a bit paranoid, but it's supposed to cooperate with
1856  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1857  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1858  * fanatically on his truly buggy board.
1859  *
1860  * FIXME: really need to revamp this for modern platforms only.
1861  */
1862 static inline void check_timer(void)
1863 {
1864         int apic1, pin1, apic2, pin2;
1865         int vector;
1866
1867         /*
1868          * get/set the timer IRQ vector:
1869          */
1870         disable_8259A_irq(0);
1871         vector = assign_irq_vector(0);
1872         set_intr_gate(vector, interrupt[0]);
1873
1874         /*
1875          * Subtle, code in do_timer_interrupt() expects an AEOI
1876          * mode for the 8259A whenever interrupts are routed
1877          * through I/O APICs.  Also IRQ0 has to be enabled in
1878          * the 8259A which implies the virtual wire has to be
1879          * disabled in the local APIC.
1880          */
1881         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1882         init_8259A(1);
1883         if (timer_over_8254 > 0)
1884                 enable_8259A_irq(0);
1885
1886         pin1  = find_isa_irq_pin(0, mp_INT);
1887         apic1 = find_isa_irq_apic(0, mp_INT);
1888         pin2  = ioapic_i8259.pin;
1889         apic2 = ioapic_i8259.apic;
1890
1891         if (pin1 == 0)
1892                 timer_uses_ioapic_pin_0 = 1;
1893
1894         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1895                 vector, apic1, pin1, apic2, pin2);
1896
1897         if (pin1 != -1) {
1898                 /*
1899                  * Ok, does IRQ0 through the IOAPIC work?
1900                  */
1901                 unmask_IO_APIC_irq(0);
1902                 if (!no_timer_check && timer_irq_works()) {
1903                         nmi_watchdog_default();
1904                         if (nmi_watchdog == NMI_IO_APIC) {
1905                                 disable_8259A_irq(0);
1906                                 setup_nmi();
1907                                 enable_8259A_irq(0);
1908                         }
1909                         if (disable_timer_pin_1 > 0)
1910                                 clear_IO_APIC_pin(0, pin1);
1911                         return;
1912                 }
1913                 clear_IO_APIC_pin(apic1, pin1);
1914                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1915                                 "connected to IO-APIC\n");
1916         }
1917
1918         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1919                                 "through the 8259A ... ");
1920         if (pin2 != -1) {
1921                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1922                         apic2, pin2);
1923                 /*
1924                  * legacy devices should be connected to IO APIC #0
1925                  */
1926                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1927                 if (timer_irq_works()) {
1928                         apic_printk(APIC_VERBOSE," works.\n");
1929                         nmi_watchdog_default();
1930                         if (nmi_watchdog == NMI_IO_APIC) {
1931                                 setup_nmi();
1932                         }
1933                         return;
1934                 }
1935                 /*
1936                  * Cleanup, just in case ...
1937                  */
1938                 clear_IO_APIC_pin(apic2, pin2);
1939         }
1940         apic_printk(APIC_VERBOSE," failed.\n");
1941
1942         if (nmi_watchdog == NMI_IO_APIC) {
1943                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1944                 nmi_watchdog = 0;
1945         }
1946
1947         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1948
1949         disable_8259A_irq(0);
1950         irq_desc[0].handler = &lapic_irq_type;
1951         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1952         enable_8259A_irq(0);
1953
1954         if (timer_irq_works()) {
1955                 apic_printk(APIC_VERBOSE," works.\n");
1956                 return;
1957         }
1958         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1959         apic_printk(APIC_VERBOSE," failed.\n");
1960
1961         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1962
1963         init_8259A(0);
1964         make_8259A_irq(0);
1965         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1966
1967         unlock_ExtINT_logic();
1968
1969         if (timer_irq_works()) {
1970                 apic_printk(APIC_VERBOSE," works.\n");
1971                 return;
1972         }
1973         apic_printk(APIC_VERBOSE," failed :(.\n");
1974         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1975 }
1976 #else
1977 int timer_uses_ioapic_pin_0;
1978 #define check_timer() ((void)0)
1979 #endif /* !CONFIG_XEN */
1980
1981 static int __init notimercheck(char *s)
1982 {
1983         no_timer_check = 1;
1984         return 1;
1985 }
1986 __setup("no_timer_check", notimercheck);
1987
1988 /*
1989  *
1990  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1991  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1992  *   Linux doesn't really care, as it's not actually used
1993  *   for any interrupt handling anyway.
1994  */
1995 #define PIC_IRQS        (1<<2)
1996
1997 void __init setup_IO_APIC(void)
1998 {
1999         enable_IO_APIC();
2000
2001         if (acpi_ioapic)
2002                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2003         else
2004                 io_apic_irqs = ~PIC_IRQS;
2005
2006         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2007
2008         /*
2009          * Set up the IO-APIC IRQ routing table.
2010          */
2011         if (!acpi_ioapic)
2012                 setup_ioapic_ids_from_mpc();
2013 #ifndef CONFIG_XEN
2014         sync_Arb_IDs();
2015 #endif /* !CONFIG_XEN */
2016         setup_IO_APIC_irqs();
2017         init_IO_APIC_traps();
2018         check_timer();
2019         if (!acpi_ioapic)
2020                 print_IO_APIC();
2021 }
2022
2023 struct sysfs_ioapic_data {
2024         struct sys_device dev;
2025         struct IO_APIC_route_entry entry[0];
2026 };
2027 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2028
2029 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2030 {
2031         struct IO_APIC_route_entry *entry;
2032         struct sysfs_ioapic_data *data;
2033         unsigned long flags;
2034         int i;
2035
2036         data = container_of(dev, struct sysfs_ioapic_data, dev);
2037         entry = data->entry;
2038         spin_lock_irqsave(&ioapic_lock, flags);
2039         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2040                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2041                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2042         }
2043         spin_unlock_irqrestore(&ioapic_lock, flags);
2044
2045         return 0;
2046 }
2047
2048 static int ioapic_resume(struct sys_device *dev)
2049 {
2050         struct IO_APIC_route_entry *entry;
2051         struct sysfs_ioapic_data *data;
2052         unsigned long flags;
2053         union IO_APIC_reg_00 reg_00;
2054         int i;
2055
2056         data = container_of(dev, struct sysfs_ioapic_data, dev);
2057         entry = data->entry;
2058
2059         spin_lock_irqsave(&ioapic_lock, flags);
2060         reg_00.raw = io_apic_read(dev->id, 0);
2061         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2062                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2063                 io_apic_write(dev->id, 0, reg_00.raw);
2064         }
2065         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2066                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2067                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2068         }
2069         spin_unlock_irqrestore(&ioapic_lock, flags);
2070
2071         return 0;
2072 }
2073
2074 static struct sysdev_class ioapic_sysdev_class = {
2075         set_kset_name("ioapic"),
2076         .suspend = ioapic_suspend,
2077         .resume = ioapic_resume,
2078 };
2079
2080 static int __init ioapic_init_sysfs(void)
2081 {
2082         struct sys_device * dev;
2083         int i, size, error = 0;
2084
2085         error = sysdev_class_register(&ioapic_sysdev_class);
2086         if (error)
2087                 return error;
2088
2089         for (i = 0; i < nr_ioapics; i++ ) {
2090                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2091                         * sizeof(struct IO_APIC_route_entry);
2092                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2093                 if (!mp_ioapic_data[i]) {
2094                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2095                         continue;
2096                 }
2097                 memset(mp_ioapic_data[i], 0, size);
2098                 dev = &mp_ioapic_data[i]->dev;
2099                 dev->id = i;
2100                 dev->cls = &ioapic_sysdev_class;
2101                 error = sysdev_register(dev);
2102                 if (error) {
2103                         kfree(mp_ioapic_data[i]);
2104                         mp_ioapic_data[i] = NULL;
2105                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2106                         continue;
2107                 }
2108         }
2109
2110         return 0;
2111 }
2112
2113 device_initcall(ioapic_init_sysfs);
2114
2115 /* --------------------------------------------------------------------------
2116                           ACPI-based IOAPIC Configuration
2117    -------------------------------------------------------------------------- */
2118
2119 #ifdef CONFIG_ACPI
2120
2121 #define IO_APIC_MAX_ID          0xFE
2122
2123 int __init io_apic_get_version (int ioapic)
2124 {
2125         union IO_APIC_reg_01    reg_01;
2126         unsigned long flags;
2127
2128         spin_lock_irqsave(&ioapic_lock, flags);
2129         reg_01.raw = io_apic_read(ioapic, 1);
2130         spin_unlock_irqrestore(&ioapic_lock, flags);
2131
2132         return reg_01.bits.version;
2133 }
2134
2135
2136 int __init io_apic_get_redir_entries (int ioapic)
2137 {
2138         union IO_APIC_reg_01    reg_01;
2139         unsigned long flags;
2140
2141         spin_lock_irqsave(&ioapic_lock, flags);
2142         reg_01.raw = io_apic_read(ioapic, 1);
2143         spin_unlock_irqrestore(&ioapic_lock, flags);
2144
2145         return reg_01.bits.entries;
2146 }
2147
2148
2149 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2150 {
2151         struct IO_APIC_route_entry entry;
2152         unsigned long flags;
2153
2154         if (!IO_APIC_IRQ(irq)) {
2155                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2156                         ioapic);
2157                 return -EINVAL;
2158         }
2159
2160         /*
2161          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2162          * Note that we mask (disable) IRQs now -- these get enabled when the
2163          * corresponding device driver registers for this IRQ.
2164          */
2165
2166         memset(&entry,0,sizeof(entry));
2167
2168         entry.delivery_mode = INT_DELIVERY_MODE;
2169         entry.dest_mode = INT_DEST_MODE;
2170         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2171         entry.trigger = edge_level;
2172         entry.polarity = active_high_low;
2173         entry.mask = 1;                                  /* Disabled (masked) */
2174
2175         irq = gsi_irq_sharing(irq);
2176         /*
2177          * IRQs < 16 are already in the irq_2_pin[] map
2178          */
2179         if (irq >= 16)
2180                 add_pin_to_irq(irq, ioapic, pin);
2181
2182         entry.vector = assign_irq_vector(irq);
2183
2184         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2185                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2186                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2187                edge_level, active_high_low);
2188
2189         ioapic_register_intr(irq, entry.vector, edge_level);
2190
2191         if (!ioapic && (irq < 16))
2192                 disable_8259A_irq(irq);
2193
2194         spin_lock_irqsave(&ioapic_lock, flags);
2195         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2196         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2197         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2198         spin_unlock_irqrestore(&ioapic_lock, flags);
2199
2200         return 0;
2201 }
2202
2203 #endif /* CONFIG_ACPI */
2204
2205
2206 #ifndef CONFIG_XEN
2207 /*
2208  * This function currently is only a helper for the i386 smp boot process where
2209  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2210  * so mask in all cases should simply be TARGET_CPUS
2211  */
2212 #ifdef CONFIG_SMP
2213 void __init setup_ioapic_dest(void)
2214 {
2215         int pin, ioapic, irq, irq_entry;
2216
2217         if (skip_ioapic_setup == 1)
2218                 return;
2219
2220         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2221                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2222                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2223                         if (irq_entry == -1)
2224                                 continue;
2225                         irq = pin_2_irq(irq_entry, ioapic, pin);
2226                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2227                 }
2228
2229         }
2230 }
2231 #endif
2232 #endif /* !CONFIG_XEN */