arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/smp.h>
  36 #include <asm/desc.h>
  37 #include <asm/proto.h>
  38
  39 int sis_apic_bug; /* not actually supported, dummy for compile */
  40
  41 #undef APIC_LOCKUP_DEBUG
  42
  43 #define APIC_LOCKUP_DEBUG
  44
  45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  46
  47 /*
  48  * # of IRQ routing registers
  49  */
  50 int nr_ioapic_registers[MAX_IO_APICS];
  51
  52 /*
  53  * Rough estimation of how many shared IRQs there are, can
  54  * be changed anytime.
  55  */
  56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  58
  59 /*
  60  * This is performance-critical, we want to do it O(1)
  61  *
  62  * the indexing order of this array favors 1:1 mappings
  63  * between pins and IRQs.
  64  */
  65
  66 static struct irq_pin_list {
  67         short apic, pin, next;
  68 } irq_2_pin[PIN_MAP_SIZE];
  69
  70 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  71 #ifdef CONFIG_PCI_MSI
  72 #define vector_to_irq(vector)   \
  73         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  74 #else
  75 #define vector_to_irq(vector)   (vector)
  76 #endif
  77
  78 /*
  79  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  80  * shared ISA-space IRQs, so we have to support them. We are super
  81  * fast in the common case, and fast for shared ISA-space IRQs.
  82  */
  83 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  84 {
  85         static int first_free_entry = NR_IRQS;
  86         struct irq_pin_list *entry = irq_2_pin + irq;
  87
  88         while (entry->next)
  89                 entry = irq_2_pin + entry->next;
  90
  91         if (entry->pin != -1) {
  92                 entry->next = first_free_entry;
  93                 entry = irq_2_pin + entry->next;
  94                 if (++first_free_entry >= PIN_MAP_SIZE)
  95                         panic("io_apic.c: whoops");
  96         }
  97         entry->apic = apic;
  98         entry->pin = pin;
  99 }
 100
 101 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 102                                                                         \
 103 {                                                                       \
 104         int pin;                                                        \
 105         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 106                                                                         \
 107         for (;;) {                                                      \
 108                 unsigned int reg;                                       \
 109                 pin = entry->pin;                                       \
 110                 if (pin == -1)                                          \
 111                         break;                                          \
 112                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 113                 reg ACTION;                                             \
 114                 io_apic_modify(entry->apic, reg);                       \
 115                 if (!entry->next)                                       \
 116                         break;                                          \
 117                 entry = irq_2_pin + entry->next;                        \
 118         }                                                               \
 119         FINAL;                                                          \
 120 }
 121
 122 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 123                                                                         \
 124         static void name##_IO_APIC_irq (unsigned int irq)               \
 125         __DO_ACTION(R, ACTION, FINAL)
 126
 127 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 128                                                 /* mask = 1 */
 129 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 130                                                 /* mask = 0 */
 131 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
 132                                                 /* mask = 1, trigger = 0 */
 133 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
 134                                                 /* mask = 0, trigger = 1 */
 135
 136 static void mask_IO_APIC_irq (unsigned int irq)
 137 {
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&ioapic_lock, flags);
 141         __mask_IO_APIC_irq(irq);
 142         spin_unlock_irqrestore(&ioapic_lock, flags);
 143 }
 144
 145 static void unmask_IO_APIC_irq (unsigned int irq)
 146 {
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&ioapic_lock, flags);
 150         __unmask_IO_APIC_irq(irq);
 151         spin_unlock_irqrestore(&ioapic_lock, flags);
 152 }
 153
 154 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 155 {
 156         struct IO_APIC_route_entry entry;
 157         unsigned long flags;
 158
 159         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 160         spin_lock_irqsave(&ioapic_lock, flags);
 161         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 162         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 163         spin_unlock_irqrestore(&ioapic_lock, flags);
 164         if (entry.delivery_mode == dest_SMI)
 165                 return;
 166         /*
 167          * Disable it in the IO-APIC irq-routing table:
 168          */
 169         memset(&entry, 0, sizeof(entry));
 170         entry.mask = 1;
 171         spin_lock_irqsave(&ioapic_lock, flags);
 172         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 173         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 174         spin_unlock_irqrestore(&ioapic_lock, flags);
 175 }
 176
 177 static void clear_IO_APIC (void)
 178 {
 179         int apic, pin;
 180
 181         for (apic = 0; apic < nr_ioapics; apic++)
 182                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 183                         clear_IO_APIC_pin(apic, pin);
 184 }
 185
 186 /*
 187  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 188  * specific CPU-side IRQs.
 189  */
 190
 191 #define MAX_PIRQS 8
 192 int pirq_entries [MAX_PIRQS];
 193 int pirqs_enabled;
 194 int skip_ioapic_setup;
 195 int ioapic_force;
 196
 197 /* dummy parsing: see setup.c */
 198
 199 static int __init disable_ioapic_setup(char *str)
 200 {
 201         skip_ioapic_setup = 1;
 202         return 1;
 203 }
 204
 205 static int __init enable_ioapic_setup(char *str)
 206 {
 207         ioapic_force = 1;
 208         skip_ioapic_setup = 0;
 209         return 1;
 210 }
 211
 212 __setup("noapic", disable_ioapic_setup);
 213 __setup("apic", enable_ioapic_setup);
 214
 215 #include <asm/pci-direct.h>
 216 #include <linux/pci_ids.h>
 217 #include <linux/pci.h>
 218
 219 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 220    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 221    Use pci direct infrastructure because this runs before the PCI subsystem.
 222
 223    Can be overwritten with "apic"
 224
 225    And another hack to disable the IOMMU on VIA chipsets.
 226
 227    Kludge-O-Rama. */
 228 void __init check_ioapic(void)
 229 {
 230         int num,slot,func;
 231         if (ioapic_force)
 232                 return;
 233
 234         /* Poor man's PCI discovery */
 235         for (num = 0; num < 32; num++) {
 236                 for (slot = 0; slot < 32; slot++) {
 237                         for (func = 0; func < 8; func++) {
 238                                 u32 class;
 239                                 u32 vendor;
 240                                 u8 type;
 241                                 class = read_pci_config(num,slot,func,
 242                                                         PCI_CLASS_REVISION);
 243                                 if (class == 0xffffffff)
 244                                         break;
 245
 246                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 247                                         continue;
 248
 249                                 vendor = read_pci_config(num, slot, func,
 250                                                          PCI_VENDOR_ID);
 251                                 vendor &= 0xffff;
 252                                 switch (vendor) {
 253                                 case PCI_VENDOR_ID_VIA:
 254 #ifdef CONFIG_GART_IOMMU
 255                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 256                                              force_iommu) &&
 257                                             !iommu_aperture_allowed) {
 258                                                 printk(KERN_INFO
 259     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 260                                                 iommu_aperture_disabled = 1;
 261                                         }
 262 #endif
 263                                         return;
 264                                 case PCI_VENDOR_ID_NVIDIA:
 265 #ifndef CONFIG_SMP
 266                                         printk(KERN_INFO
 267      "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
 268                                                num,slot,vendor);
 269                                         skip_ioapic_setup = 1;
 270 #endif
 271                                         return;
 272                                 }
 273
 274                                 /* No multi-function device? */
 275                                 type = read_pci_config_byte(num,slot,func,
 276                                                             PCI_HEADER_TYPE);
 277                                 if (!(type & 0x80))
 278                                         break;
 279                         }
 280                 }
 281         }
 282 }
 283
 284 static int __init ioapic_pirq_setup(char *str)
 285 {
 286         int i, max;
 287         int ints[MAX_PIRQS+1];
 288
 289         get_options(str, ARRAY_SIZE(ints), ints);
 290
 291         for (i = 0; i < MAX_PIRQS; i++)
 292                 pirq_entries[i] = -1;
 293
 294         pirqs_enabled = 1;
 295         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
 296         max = MAX_PIRQS;
 297         if (ints[0] < MAX_PIRQS)
 298                 max = ints[0];
 299
 300         for (i = 0; i < max; i++) {
 301                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 302                 /*
 303                  * PIRQs are mapped upside down, usually.
 304                  */
 305                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 306         }
 307         return 1;
 308 }
 309
 310 __setup("pirq=", ioapic_pirq_setup);
 311
 312 /*
 313  * Find the IRQ entry number of a certain pin.
 314  */
 315 static int __init find_irq_entry(int apic, int pin, int type)
 316 {
 317         int i;
 318
 319         for (i = 0; i < mp_irq_entries; i++)
 320                 if (mp_irqs[i].mpc_irqtype == type &&
 321                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 322                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 323                     mp_irqs[i].mpc_dstirq == pin)
 324                         return i;
 325
 326         return -1;
 327 }
 328
 329 /*
 330  * Find the pin to which IRQ[irq] (ISA) is connected
 331  */
 332 static int __init find_isa_irq_pin(int irq, int type)
 333 {
 334         int i;
 335
 336         for (i = 0; i < mp_irq_entries; i++) {
 337                 int lbus = mp_irqs[i].mpc_srcbus;
 338
 339                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 340                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 341                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 342                     (mp_irqs[i].mpc_irqtype == type) &&
 343                     (mp_irqs[i].mpc_srcbusirq == irq))
 344
 345                         return mp_irqs[i].mpc_dstirq;
 346         }
 347         return -1;
 348 }
 349
 350 /*
 351  * Find a specific PCI IRQ entry.
 352  * Not an __init, possibly needed by modules
 353  */
 354 static int pin_2_irq(int idx, int apic, int pin);
 355
 356 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 357 {
 358         int apic, i, best_guess = -1;
 359
 360         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 361                 bus, slot, pin);
 362         if (mp_bus_id_to_pci_bus[bus] == -1) {
 363                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 364                 return -1;
 365         }
 366         for (i = 0; i < mp_irq_entries; i++) {
 367                 int lbus = mp_irqs[i].mpc_srcbus;
 368
 369                 for (apic = 0; apic < nr_ioapics; apic++)
 370                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 371                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 372                                 break;
 373
 374                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 375                     !mp_irqs[i].mpc_irqtype &&
 376                     (bus == lbus) &&
 377                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 378                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 379
 380                         if (!(apic || IO_APIC_IRQ(irq)))
 381                                 continue;
 382
 383                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 384                                 return irq;
 385                         /*
 386                          * Use the first all-but-pin matching entry as a
 387                          * best-guess fuzzy result for broken mptables.
 388                          */
 389                         if (best_guess < 0)
 390                                 best_guess = irq;
 391                 }
 392         }
 393         return best_guess;
 394 }
 395
 396 /*
 397  * EISA Edge/Level control register, ELCR
 398  */
 399 static int __init EISA_ELCR(unsigned int irq)
 400 {
 401         if (irq < 16) {
 402                 unsigned int port = 0x4d0 + (irq >> 3);
 403                 return (inb(port) >> (irq & 7)) & 1;
 404         }
 405         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
 406         return 0;
 407 }
 408
 409 /* EISA interrupts are always polarity zero and can be edge or level
 410  * trigger depending on the ELCR value.  If an interrupt is listed as
 411  * EISA conforming in the MP table, that means its trigger type must
 412  * be read in from the ELCR */
 413
 414 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 415 #define default_EISA_polarity(idx)      (0)
 416
 417 /* ISA interrupts are always polarity zero edge triggered,
 418  * when listed as conforming in the MP table. */
 419
 420 #define default_ISA_trigger(idx)        (0)
 421 #define default_ISA_polarity(idx)       (0)
 422
 423 /* PCI interrupts are always polarity one level triggered,
 424  * when listed as conforming in the MP table. */
 425
 426 #define default_PCI_trigger(idx)        (1)
 427 #define default_PCI_polarity(idx)       (1)
 428
 429 /* MCA interrupts are always polarity zero level triggered,
 430  * when listed as conforming in the MP table. */
 431
 432 #define default_MCA_trigger(idx)        (1)
 433 #define default_MCA_polarity(idx)       (0)
 434
 435 static int __init MPBIOS_polarity(int idx)
 436 {
 437         int bus = mp_irqs[idx].mpc_srcbus;
 438         int polarity;
 439
 440         /*
 441          * Determine IRQ line polarity (high active or low active):
 442          */
 443         switch (mp_irqs[idx].mpc_irqflag & 3)
 444         {
 445                 case 0: /* conforms, ie. bus-type dependent polarity */
 446                 {
 447                         switch (mp_bus_id_to_type[bus])
 448                         {
 449                                 case MP_BUS_ISA: /* ISA pin */
 450                                 {
 451                                         polarity = default_ISA_polarity(idx);
 452                                         break;
 453                                 }
 454                                 case MP_BUS_EISA: /* EISA pin */
 455                                 {
 456                                         polarity = default_EISA_polarity(idx);
 457                                         break;
 458                                 }
 459                                 case MP_BUS_PCI: /* PCI pin */
 460                                 {
 461                                         polarity = default_PCI_polarity(idx);
 462                                         break;
 463                                 }
 464                                 case MP_BUS_MCA: /* MCA pin */
 465                                 {
 466                                         polarity = default_MCA_polarity(idx);
 467                                         break;
 468                                 }
 469                                 default:
 470                                 {
 471                                         printk(KERN_WARNING "broken BIOS!!\n");
 472                                         polarity = 1;
 473                                         break;
 474                                 }
 475                         }
 476                         break;
 477                 }
 478                 case 1: /* high active */
 479                 {
 480                         polarity = 0;
 481                         break;
 482                 }
 483                 case 2: /* reserved */
 484                 {
 485                         printk(KERN_WARNING "broken BIOS!!\n");
 486                         polarity = 1;
 487                         break;
 488                 }
 489                 case 3: /* low active */
 490                 {
 491                         polarity = 1;
 492                         break;
 493                 }
 494                 default: /* invalid */
 495                 {
 496                         printk(KERN_WARNING "broken BIOS!!\n");
 497                         polarity = 1;
 498                         break;
 499                 }
 500         }
 501         return polarity;
 502 }
 503
 504 static int __init MPBIOS_trigger(int idx)
 505 {
 506         int bus = mp_irqs[idx].mpc_srcbus;
 507         int trigger;
 508
 509         /*
 510          * Determine IRQ trigger mode (edge or level sensitive):
 511          */
 512         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 513         {
 514                 case 0: /* conforms, ie. bus-type dependent */
 515                 {
 516                         switch (mp_bus_id_to_type[bus])
 517                         {
 518                                 case MP_BUS_ISA: /* ISA pin */
 519                                 {
 520                                         trigger = default_ISA_trigger(idx);
 521                                         break;
 522                                 }
 523                                 case MP_BUS_EISA: /* EISA pin */
 524                                 {
 525                                         trigger = default_EISA_trigger(idx);
 526                                         break;
 527                                 }
 528                                 case MP_BUS_PCI: /* PCI pin */
 529                                 {
 530                                         trigger = default_PCI_trigger(idx);
 531                                         break;
 532                                 }
 533                                 case MP_BUS_MCA: /* MCA pin */
 534                                 {
 535                                         trigger = default_MCA_trigger(idx);
 536                                         break;
 537                                 }
 538                                 default:
 539                                 {
 540                                         printk(KERN_WARNING "broken BIOS!!\n");
 541                                         trigger = 1;
 542                                         break;
 543                                 }
 544                         }
 545                         break;
 546                 }
 547                 case 1: /* edge */
 548                 {
 549                         trigger = 0;
 550                         break;
 551                 }
 552                 case 2: /* reserved */
 553                 {
 554                         printk(KERN_WARNING "broken BIOS!!\n");
 555                         trigger = 1;
 556                         break;
 557                 }
 558                 case 3: /* level */
 559                 {
 560                         trigger = 1;
 561                         break;
 562                 }
 563                 default: /* invalid */
 564                 {
 565                         printk(KERN_WARNING "broken BIOS!!\n");
 566                         trigger = 0;
 567                         break;
 568                 }
 569         }
 570         return trigger;
 571 }
 572
 573 static inline int irq_polarity(int idx)
 574 {
 575         return MPBIOS_polarity(idx);
 576 }
 577
 578 static inline int irq_trigger(int idx)
 579 {
 580         return MPBIOS_trigger(idx);
 581 }
 582
 583 static int pin_2_irq(int idx, int apic, int pin)
 584 {
 585         int irq, i;
 586         int bus = mp_irqs[idx].mpc_srcbus;
 587
 588         /*
 589          * Debugging check, we are in big trouble if this message pops up!
 590          */
 591         if (mp_irqs[idx].mpc_dstirq != pin)
 592                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 593
 594         switch (mp_bus_id_to_type[bus])
 595         {
 596                 case MP_BUS_ISA: /* ISA pin */
 597                 case MP_BUS_EISA:
 598                 case MP_BUS_MCA:
 599                 {
 600                         irq = mp_irqs[idx].mpc_srcbusirq;
 601                         break;
 602                 }
 603                 case MP_BUS_PCI: /* PCI pin */
 604                 {
 605                         /*
 606                          * PCI IRQs are mapped in order
 607                          */
 608                         i = irq = 0;
 609                         while (i < apic)
 610                                 irq += nr_ioapic_registers[i++];
 611                         irq += pin;
 612                         break;
 613                 }
 614                 default:
 615                 {
 616                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 617                         irq = 0;
 618                         break;
 619                 }
 620         }
 621
 622         /*
 623          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 624          */
 625         if ((pin >= 16) && (pin <= 23)) {
 626                 if (pirq_entries[pin-16] != -1) {
 627                         if (!pirq_entries[pin-16]) {
 628                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
 629                         } else {
 630                                 irq = pirq_entries[pin-16];
 631                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
 632                                                 pin-16, irq);
 633                         }
 634                 }
 635         }
 636         return irq;
 637 }
 638
 639 static inline int IO_APIC_irq_trigger(int irq)
 640 {
 641         int apic, idx, pin;
 642
 643         for (apic = 0; apic < nr_ioapics; apic++) {
 644                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 645                         idx = find_irq_entry(apic,pin,mp_INT);
 646                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 647                                 return irq_trigger(idx);
 648                 }
 649         }
 650         /*
 651          * nonexistent IRQs are edge default
 652          */
 653         return 0;
 654 }
 655
 656 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 657 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 658
 659 #ifdef CONFIG_PCI_MSI
 660 int assign_irq_vector(int irq)
 661 #else
 662 int __init assign_irq_vector(int irq)
 663 #endif
 664 {
 665         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 666
 667         BUG_ON(irq >= NR_IRQ_VECTORS);
 668         if (IO_APIC_VECTOR(irq) > 0)
 669                 return IO_APIC_VECTOR(irq);
 670 next:
 671         current_vector += 8;
 672         if (current_vector == IA32_SYSCALL_VECTOR)
 673                 goto next;
 674
 675         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 676                 offset++;
 677                 if (!(offset%8))
 678                         return -ENOSPC;
 679                 current_vector = FIRST_DEVICE_VECTOR + offset;
 680         }
 681
 682         vector_irq[current_vector] = irq;
 683         if (irq != AUTO_ASSIGN)
 684                 IO_APIC_VECTOR(irq) = current_vector;
 685
 686         return current_vector;
 687 }
 688
 689 extern void (*interrupt[NR_IRQS])(void);
 690 static struct hw_interrupt_type ioapic_level_type;
 691 static struct hw_interrupt_type ioapic_edge_type;
 692
 693 #define IOAPIC_AUTO     -1
 694 #define IOAPIC_EDGE     0
 695 #define IOAPIC_LEVEL    1
 696
 697 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 698 {
 699         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 700                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 701                                 trigger == IOAPIC_LEVEL)
 702                         irq_desc[vector].handler = &ioapic_level_type;
 703                 else
 704                         irq_desc[vector].handler = &ioapic_edge_type;
 705                 set_intr_gate(vector, interrupt[vector]);
 706         } else  {
 707                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 708                                 trigger == IOAPIC_LEVEL)
 709                         irq_desc[irq].handler = &ioapic_level_type;
 710                 else
 711                         irq_desc[irq].handler = &ioapic_edge_type;
 712                 set_intr_gate(vector, interrupt[irq]);
 713         }
 714 }
 715
 716 void __init setup_IO_APIC_irqs(void)
 717 {
 718         struct IO_APIC_route_entry entry;
 719         int apic, pin, idx, irq, first_notcon = 1, vector;
 720         unsigned long flags;
 721
 722         printk(KERN_DEBUG "init IO_APIC IRQs\n");
 723
 724         for (apic = 0; apic < nr_ioapics; apic++) {
 725         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 726
 727                 /*
 728                  * add it to the IO-APIC irq-routing table:
 729                  */
 730                 memset(&entry,0,sizeof(entry));
 731
 732                 entry.delivery_mode = dest_LowestPrio;
 733                 entry.dest_mode = INT_DELIVERY_MODE;
 734                 entry.mask = 0;                         /* enable IRQ */
 735                 entry.dest.logical.logical_dest = TARGET_CPUS;
 736
 737                 idx = find_irq_entry(apic,pin,mp_INT);
 738                 if (idx == -1) {
 739                         if (first_notcon) {
 740                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 741                                 first_notcon = 0;
 742                         } else
 743                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 744                         continue;
 745                 }
 746
 747                 entry.trigger = irq_trigger(idx);
 748                 entry.polarity = irq_polarity(idx);
 749
 750                 if (irq_trigger(idx)) {
 751                         entry.trigger = 1;
 752                         entry.mask = 1;
 753                         entry.dest.logical.logical_dest = TARGET_CPUS;
 754                 }
 755
 756                 irq = pin_2_irq(idx, apic, pin);
 757                 add_pin_to_irq(irq, apic, pin);
 758
 759                 if (!apic && !IO_APIC_IRQ(irq))
 760                         continue;
 761
 762                 if (IO_APIC_IRQ(irq)) {
 763                         vector = assign_irq_vector(irq);
 764                         entry.vector = vector;
 765
 766                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 767                         if (!apic && (irq < 16))
 768                                 disable_8259A_irq(irq);
 769                 }
 770                 spin_lock_irqsave(&ioapic_lock, flags);
 771                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 772                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 773                 spin_unlock_irqrestore(&ioapic_lock, flags);
 774         }
 775         }
 776
 777         if (!first_notcon)
 778                 printk(" not connected.\n");
 779 }
 780
 781 /*
 782  * Set up the 8259A-master output pin as broadcast to all
 783  * CPUs.
 784  */
 785 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 786 {
 787         struct IO_APIC_route_entry entry;
 788         unsigned long flags;
 789
 790         memset(&entry,0,sizeof(entry));
 791
 792         disable_8259A_irq(0);
 793
 794         /* mask LVT0 */
 795         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 796
 797         /*
 798          * We use logical delivery to get the timer IRQ
 799          * to the first CPU.
 800          */
 801         entry.dest_mode = INT_DELIVERY_MODE;
 802         entry.mask = 0;                                 /* unmask IRQ now */
 803         entry.dest.logical.logical_dest = TARGET_CPUS;
 804         entry.delivery_mode = dest_LowestPrio;
 805         entry.polarity = 0;
 806         entry.trigger = 0;
 807         entry.vector = vector;
 808
 809         /*
 810          * The timer IRQ doesn't have to know that behind the
 811          * scene we have a 8259A-master in AEOI mode ...
 812          */
 813         irq_desc[0].handler = &ioapic_edge_type;
 814
 815         /*
 816          * Add it to the IO-APIC irq-routing table:
 817          */
 818         spin_lock_irqsave(&ioapic_lock, flags);
 819         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 820         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 821         spin_unlock_irqrestore(&ioapic_lock, flags);
 822
 823         enable_8259A_irq(0);
 824 }
 825
 826 void __init UNEXPECTED_IO_APIC(void)
 827 {
 828 #if 0
 829         printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
 830         printk(KERN_WARNING "          to linux-smp@vger.kernel.org\n");
 831 #endif
 832 }
 833
 834 void __init print_IO_APIC(void)
 835 {
 836         int apic, i;
 837         union IO_APIC_reg_00 reg_00;
 838         union IO_APIC_reg_01 reg_01;
 839         union IO_APIC_reg_02 reg_02;
 840         unsigned long flags;
 841
 842         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 843         for (i = 0; i < nr_ioapics; i++)
 844                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 845                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 846
 847         /*
 848          * We are a bit conservative about what we expect.  We have to
 849          * know about every hardware change ASAP.
 850          */
 851         printk(KERN_INFO "testing the IO APIC.......................\n");
 852
 853         for (apic = 0; apic < nr_ioapics; apic++) {
 854
 855         spin_lock_irqsave(&ioapic_lock, flags);
 856         reg_00.raw = io_apic_read(apic, 0);
 857         reg_01.raw = io_apic_read(apic, 1);
 858         if (reg_01.bits.version >= 0x10)
 859                 reg_02.raw = io_apic_read(apic, 2);
 860         spin_unlock_irqrestore(&ioapic_lock, flags);
 861
 862         printk("\n");
 863         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 864         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 865         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 866         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 867                 UNEXPECTED_IO_APIC();
 868
 869         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 870         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 871         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 872                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 873                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 874                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 875                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 876                 (reg_01.bits.entries != 0x2E) &&
 877                 (reg_01.bits.entries != 0x3F) &&
 878                 (reg_01.bits.entries != 0x03)
 879         )
 880                 UNEXPECTED_IO_APIC();
 881
 882         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 883         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 884         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 885                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 886                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 887                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 888                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 889                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 890         )
 891                 UNEXPECTED_IO_APIC();
 892         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 893                 UNEXPECTED_IO_APIC();
 894
 895         if (reg_01.bits.version >= 0x10) {
 896                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 897                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 898                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 899                         UNEXPECTED_IO_APIC();
 900         }
 901
 902         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 903
 904         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 905                           " Stat Dest Deli Vect:   \n");
 906
 907         for (i = 0; i <= reg_01.bits.entries; i++) {
 908                 struct IO_APIC_route_entry entry;
 909
 910                 spin_lock_irqsave(&ioapic_lock, flags);
 911                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 912                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 913                 spin_unlock_irqrestore(&ioapic_lock, flags);
 914
 915                 printk(KERN_DEBUG " %02x %03X %02X  ",
 916                         i,
 917                         entry.dest.logical.logical_dest,
 918                         entry.dest.physical.physical_dest
 919                 );
 920
 921                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 922                         entry.mask,
 923                         entry.trigger,
 924                         entry.irr,
 925                         entry.polarity,
 926                         entry.delivery_status,
 927                         entry.dest_mode,
 928                         entry.delivery_mode,
 929                         entry.vector
 930                 );
 931         }
 932         }
 933         if (use_pci_vector())
 934                 printk(KERN_INFO "Using vector-based indexing\n");
 935         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 936         for (i = 0; i < NR_IRQS; i++) {
 937                 struct irq_pin_list *entry = irq_2_pin + i;
 938                 if (entry->pin < 0)
 939                         continue;
 940                 if (use_pci_vector() && !platform_legacy_irq(i))
 941                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 942                 else
 943                         printk(KERN_DEBUG "IRQ%d ", i);
 944                 for (;;) {
 945                         printk("-> %d:%d", entry->apic, entry->pin);
 946                         if (!entry->next)
 947                                 break;
 948                         entry = irq_2_pin + entry->next;
 949                 }
 950                 printk("\n");
 951         }
 952
 953         printk(KERN_INFO ".................................... done.\n");
 954
 955         return;
 956 }
 957
 958 static void print_APIC_bitfield (int base)
 959 {
 960         unsigned int v;
 961         int i, j;
 962
 963         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 964         for (i = 0; i < 8; i++) {
 965                 v = apic_read(base + i*0x10);
 966                 for (j = 0; j < 32; j++) {
 967                         if (v & (1<<j))
 968                                 printk("1");
 969                         else
 970                                 printk("0");
 971                 }
 972                 printk("\n");
 973         }
 974 }
 975
 976 void /*__init*/ print_local_APIC(void * dummy)
 977 {
 978         unsigned int v, ver, maxlvt;
 979
 980         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 981                 smp_processor_id(), hard_smp_processor_id());
 982         v = apic_read(APIC_ID);
 983         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 984         v = apic_read(APIC_LVR);
 985         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 986         ver = GET_APIC_VERSION(v);
 987         maxlvt = get_maxlvt();
 988
 989         v = apic_read(APIC_TASKPRI);
 990         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 991
 992         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
 993                 v = apic_read(APIC_ARBPRI);
 994                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 995                         v & APIC_ARBPRI_MASK);
 996                 v = apic_read(APIC_PROCPRI);
 997                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 998         }
 999
1000         v = apic_read(APIC_EOI);
1001         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1002         v = apic_read(APIC_RRR);
1003         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1004         v = apic_read(APIC_LDR);
1005         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1006         v = apic_read(APIC_DFR);
1007         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1008         v = apic_read(APIC_SPIV);
1009         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1010
1011         printk(KERN_DEBUG "... APIC ISR field:\n");
1012         print_APIC_bitfield(APIC_ISR);
1013         printk(KERN_DEBUG "... APIC TMR field:\n");
1014         print_APIC_bitfield(APIC_TMR);
1015         printk(KERN_DEBUG "... APIC IRR field:\n");
1016         print_APIC_bitfield(APIC_IRR);
1017
1018         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1019                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1020                         apic_write(APIC_ESR, 0);
1021                 v = apic_read(APIC_ESR);
1022                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1023         }
1024
1025         v = apic_read(APIC_ICR);
1026         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1027         v = apic_read(APIC_ICR2);
1028         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1029
1030         v = apic_read(APIC_LVTT);
1031         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1032
1033         if (maxlvt > 3) {                       /* PC is LVT#4. */
1034                 v = apic_read(APIC_LVTPC);
1035                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1036         }
1037         v = apic_read(APIC_LVT0);
1038         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1039         v = apic_read(APIC_LVT1);
1040         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1041
1042         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1043                 v = apic_read(APIC_LVTERR);
1044                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1045         }
1046
1047         v = apic_read(APIC_TMICT);
1048         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1049         v = apic_read(APIC_TMCCT);
1050         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1051         v = apic_read(APIC_TDCR);
1052         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1053         printk("\n");
1054 }
1055
1056 void print_all_local_APICs (void)
1057 {
1058         on_each_cpu(print_local_APIC, NULL, 1, 1);
1059 }
1060
1061 void /*__init*/ print_PIC(void)
1062 {
1063         extern spinlock_t i8259A_lock;
1064         unsigned int v;
1065         unsigned long flags;
1066
1067         printk(KERN_DEBUG "\nprinting PIC contents\n");
1068
1069         spin_lock_irqsave(&i8259A_lock, flags);
1070
1071         v = inb(0xa1) << 8 | inb(0x21);
1072         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1073
1074         v = inb(0xa0) << 8 | inb(0x20);
1075         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1076
1077         outb(0x0b,0xa0);
1078         outb(0x0b,0x20);
1079         v = inb(0xa0) << 8 | inb(0x20);
1080         outb(0x0a,0xa0);
1081         outb(0x0a,0x20);
1082
1083         spin_unlock_irqrestore(&i8259A_lock, flags);
1084
1085         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1086
1087         v = inb(0x4d1) << 8 | inb(0x4d0);
1088         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1089 }
1090
1091 static void __init enable_IO_APIC(void)
1092 {
1093         union IO_APIC_reg_01 reg_01;
1094         int i;
1095         unsigned long flags;
1096
1097         for (i = 0; i < PIN_MAP_SIZE; i++) {
1098                 irq_2_pin[i].pin = -1;
1099                 irq_2_pin[i].next = 0;
1100         }
1101         if (!pirqs_enabled)
1102                 for (i = 0; i < MAX_PIRQS; i++)
1103                         pirq_entries[i] = -1;
1104
1105         /*
1106          * The number of IO-APIC IRQ registers (== #pins):
1107          */
1108         for (i = 0; i < nr_ioapics; i++) {
1109                 spin_lock_irqsave(&ioapic_lock, flags);
1110                 reg_01.raw = io_apic_read(i, 1);
1111                 spin_unlock_irqrestore(&ioapic_lock, flags);
1112                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1113         }
1114
1115         /*
1116          * Do not trust the IO-APIC being empty at bootup
1117          */
1118         clear_IO_APIC();
1119 }
1120
1121 /*
1122  * Not an __init, needed by the reboot code
1123  */
1124 void disable_IO_APIC(void)
1125 {
1126         /*
1127          * Clear the IO-APIC before rebooting:
1128          */
1129         clear_IO_APIC();
1130
1131         disconnect_bsp_APIC();
1132 }
1133
1134 /*
1135  * function to set the IO-APIC physical IDs based on the
1136  * values stored in the MPC table.
1137  *
1138  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1139  */
1140
1141 static void __init setup_ioapic_ids_from_mpc (void)
1142 {
1143         union IO_APIC_reg_00 reg_00;
1144         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1145         int apic;
1146         int i;
1147         unsigned char old_id;
1148         unsigned long flags;
1149
1150         /*
1151          * Set the IOAPIC ID to the value stored in the MPC table.
1152          */
1153         for (apic = 0; apic < nr_ioapics; apic++) {
1154
1155                 /* Read the register 0 value */
1156                 spin_lock_irqsave(&ioapic_lock, flags);
1157                 reg_00.raw = io_apic_read(apic, 0);
1158                 spin_unlock_irqrestore(&ioapic_lock, flags);
1159
1160                 old_id = mp_ioapics[apic].mpc_apicid;
1161
1162                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1163                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1164                                 apic, mp_ioapics[apic].mpc_apicid);
1165                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1166                                 reg_00.bits.ID);
1167                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1168                 }
1169
1170                 /*
1171                  * Sanity check, is the ID really free? Every APIC in a
1172                  * system must have a unique ID or we get lots of nice
1173                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1174                  */
1175                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1176                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1177                                 apic, mp_ioapics[apic].mpc_apicid);
1178                         for (i = 0; i < 0xf; i++)
1179                                 if (!physid_isset(i, phys_id_present_map))
1180                                         break;
1181                         if (i >= 0xf)
1182                                 panic("Max APIC ID exceeded!\n");
1183                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1184                                 i);
1185                         physid_set(i, phys_id_present_map);
1186                         mp_ioapics[apic].mpc_apicid = i;
1187                 } else {
1188                         printk(KERN_INFO
1189                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1190                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1191                 }
1192
1193
1194                 /*
1195                  * We need to adjust the IRQ routing table
1196                  * if the ID changed.
1197                  */
1198                 if (old_id != mp_ioapics[apic].mpc_apicid)
1199                         for (i = 0; i < mp_irq_entries; i++)
1200                                 if (mp_irqs[i].mpc_dstapic == old_id)
1201                                         mp_irqs[i].mpc_dstapic
1202                                                 = mp_ioapics[apic].mpc_apicid;
1203
1204                 /*
1205                  * Read the right value from the MPC table and
1206                  * write it into the ID register.
1207                  */
1208                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1209                                 mp_ioapics[apic].mpc_apicid);
1210
1211                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1212                 spin_lock_irqsave(&ioapic_lock, flags);
1213                 io_apic_write(apic, 0, reg_00.raw);
1214                 spin_unlock_irqrestore(&ioapic_lock, flags);
1215
1216                 /*
1217                  * Sanity check
1218                  */
1219                 spin_lock_irqsave(&ioapic_lock, flags);
1220                 reg_00.raw = io_apic_read(apic, 0);
1221                 spin_unlock_irqrestore(&ioapic_lock, flags);
1222                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1223                         panic("could not set ID!\n");
1224                 else
1225                         printk(" ok.\n");
1226         }
1227 }
1228
1229 /*
1230  * There is a nasty bug in some older SMP boards, their mptable lies
1231  * about the timer IRQ. We do the following to work around the situation:
1232  *
1233  *      - timer IRQ defaults to IO-APIC IRQ
1234  *      - if this function detects that timer IRQs are defunct, then we fall
1235  *        back to ISA timer IRQs
1236  */
1237 static int __init timer_irq_works(void)
1238 {
1239         unsigned long t1 = jiffies;
1240
1241         local_irq_enable();
1242         /* Let ten ticks pass... */
1243         mdelay((10 * 1000) / HZ);
1244
1245         /*
1246          * Expect a few ticks at least, to be sure some possible
1247          * glue logic does not lock up after one or two first
1248          * ticks in a non-ExtINT mode.  Also the local APIC
1249          * might have cached one ExtINT interrupt.  Finally, at
1250          * least one tick may be lost due to delays.
1251          */
1252
1253         /* jiffies wrap? */
1254         if (jiffies - t1 > 4)
1255                 return 1;
1256         return 0;
1257 }
1258
1259 /*
1260  * In the SMP+IOAPIC case it might happen that there are an unspecified
1261  * number of pending IRQ events unhandled. These cases are very rare,
1262  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1263  * better to do it this way as thus we do not have to be aware of
1264  * 'pending' interrupts in the IRQ path, except at this point.
1265  */
1266 /*
1267  * Edge triggered needs to resend any interrupt
1268  * that was delayed but this is now handled in the device
1269  * independent code.
1270  */
1271
1272 /*
1273  * Starting up a edge-triggered IO-APIC interrupt is
1274  * nasty - we need to make sure that we get the edge.
1275  * If it is already asserted for some reason, we need
1276  * return 1 to indicate that is was pending.
1277  *
1278  * This is not complete - we should be able to fake
1279  * an edge even if it isn't on the 8259A...
1280  */
1281
1282 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1283 {
1284         int was_pending = 0;
1285         unsigned long flags;
1286
1287         spin_lock_irqsave(&ioapic_lock, flags);
1288         if (irq < 16) {
1289                 disable_8259A_irq(irq);
1290                 if (i8259A_irq_pending(irq))
1291                         was_pending = 1;
1292         }
1293         __unmask_IO_APIC_irq(irq);
1294         spin_unlock_irqrestore(&ioapic_lock, flags);
1295
1296         return was_pending;
1297 }
1298
1299 /*
1300  * Once we have recorded IRQ_PENDING already, we can mask the
1301  * interrupt for real. This prevents IRQ storms from unhandled
1302  * devices.
1303  */
1304 static void ack_edge_ioapic_irq(unsigned int irq)
1305 {
1306         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1307                                         == (IRQ_PENDING | IRQ_DISABLED))
1308                 mask_IO_APIC_irq(irq);
1309         ack_APIC_irq();
1310 }
1311
1312 /*
1313  * Level triggered interrupts can just be masked,
1314  * and shutting down and starting up the interrupt
1315  * is the same as enabling and disabling them -- except
1316  * with a startup need to return a "was pending" value.
1317  *
1318  * Level triggered interrupts are special because we
1319  * do not touch any IO-APIC register while handling
1320  * them. We ack the APIC in the end-IRQ handler, not
1321  * in the start-IRQ-handler. Protection against reentrance
1322  * from the same interrupt is still provided, both by the
1323  * generic IRQ layer and by the fact that an unacked local
1324  * APIC does not accept IRQs.
1325  */
1326 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1327 {
1328         unmask_IO_APIC_irq(irq);
1329
1330         return 0; /* don't check for pending */
1331 }
1332
1333 static void end_level_ioapic_irq (unsigned int irq)
1334 {
1335         unsigned long v;
1336         int i;
1337
1338 /*
1339  * It appears there is an erratum which affects at least version 0x11
1340  * of I/O APIC (that's the 82093AA and cores integrated into various
1341  * chipsets).  Under certain conditions a level-triggered interrupt is
1342  * erroneously delivered as edge-triggered one but the respective IRR
1343  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1344  * message but it will never arrive and further interrupts are blocked
1345  * from the source.  The exact reason is so far unknown, but the
1346  * phenomenon was observed when two consecutive interrupt requests
1347  * from a given source get delivered to the same CPU and the source is
1348  * temporarily disabled in between.
1349  *
1350  * A workaround is to simulate an EOI message manually.  We achieve it
1351  * by setting the trigger mode to edge and then to level when the edge
1352  * trigger mode gets detected in the TMR of a local APIC for a
1353  * level-triggered interrupt.  We mask the source for the time of the
1354  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1355  * The idea is from Manfred Spraul.  --macro
1356  */
1357         i = IO_APIC_VECTOR(irq);
1358         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1359
1360         ack_APIC_irq();
1361
1362         if (!(v & (1 << (i & 0x1f)))) {
1363 #ifdef APIC_LOCKUP_DEBUG
1364                 struct irq_pin_list *entry;
1365 #endif
1366
1367 #ifdef APIC_MISMATCH_DEBUG
1368                 atomic_inc(&irq_mis_count);
1369 #endif
1370                 spin_lock(&ioapic_lock);
1371                 __mask_and_edge_IO_APIC_irq(irq);
1372 #ifdef APIC_LOCKUP_DEBUG
1373                 for (entry = irq_2_pin + irq;;) {
1374                         unsigned int reg;
1375
1376                         if (entry->pin == -1)
1377                                 break;
1378                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1379                         if (reg & 0x00004000)
1380                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1381                                         " still set after unlock!\n");
1382                         if (!entry->next)
1383                                 break;
1384                         entry = irq_2_pin + entry->next;
1385                 }
1386 #endif
1387                 __unmask_and_level_IO_APIC_irq(irq);
1388                 spin_unlock(&ioapic_lock);
1389         }
1390 }
1391
1392 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1393 {
1394         unsigned long flags;
1395         unsigned int dest;
1396
1397         dest = cpu_mask_to_apicid(mask);
1398
1399         /*
1400          * Only the first 8 bits are valid.
1401          */
1402         dest = dest << 24;
1403
1404         spin_lock_irqsave(&ioapic_lock, flags);
1405         __DO_ACTION(1, = dest, )
1406         spin_unlock_irqrestore(&ioapic_lock, flags);
1407 }
1408
1409 #ifdef CONFIG_PCI_MSI
1410 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1411 {
1412         int irq = vector_to_irq(vector);
1413
1414         return startup_edge_ioapic_irq(irq);
1415 }
1416
1417 static void ack_edge_ioapic_vector(unsigned int vector)
1418 {
1419         int irq = vector_to_irq(vector);
1420
1421         ack_edge_ioapic_irq(irq);
1422 }
1423
1424 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1425 {
1426         int irq = vector_to_irq(vector);
1427
1428         return startup_level_ioapic_irq (irq);
1429 }
1430
1431 static void end_level_ioapic_vector (unsigned int vector)
1432 {
1433         int irq = vector_to_irq(vector);
1434
1435         end_level_ioapic_irq(irq);
1436 }
1437
1438 static void mask_IO_APIC_vector (unsigned int vector)
1439 {
1440         int irq = vector_to_irq(vector);
1441
1442         mask_IO_APIC_irq(irq);
1443 }
1444
1445 static void unmask_IO_APIC_vector (unsigned int vector)
1446 {
1447         int irq = vector_to_irq(vector);
1448
1449         unmask_IO_APIC_irq(irq);
1450 }
1451
1452 static void set_ioapic_affinity_vector (unsigned int vector,
1453                                         cpumask_t cpu_mask)
1454 {
1455         int irq = vector_to_irq(vector);
1456
1457         set_ioapic_affinity_irq(irq, cpu_mask);
1458 }
1459 #endif
1460
1461 /*
1462  * Level and edge triggered IO-APIC interrupts need different handling,
1463  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1464  * handled with the level-triggered descriptor, but that one has slightly
1465  * more overhead. Level-triggered interrupts cannot be handled with the
1466  * edge-triggered handler, without risking IRQ storms and other ugly
1467  * races.
1468  */
1469
1470 static struct hw_interrupt_type ioapic_edge_type = {
1471         .typename = "IO-APIC-edge",
1472         .startup        = startup_edge_ioapic,
1473         .shutdown       = shutdown_edge_ioapic,
1474         .enable         = enable_edge_ioapic,
1475         .disable        = disable_edge_ioapic,
1476         .ack            = ack_edge_ioapic,
1477         .end            = end_edge_ioapic,
1478         .set_affinity = set_ioapic_affinity,
1479 };
1480
1481 static struct hw_interrupt_type ioapic_level_type = {
1482         .typename = "IO-APIC-level",
1483         .startup        = startup_level_ioapic,
1484         .shutdown       = shutdown_level_ioapic,
1485         .enable         = enable_level_ioapic,
1486         .disable        = disable_level_ioapic,
1487         .ack            = mask_and_ack_level_ioapic,
1488         .end            = end_level_ioapic,
1489         .set_affinity = set_ioapic_affinity,
1490 };
1491
1492 static inline void init_IO_APIC_traps(void)
1493 {
1494         int irq;
1495
1496         /*
1497          * NOTE! The local APIC isn't very good at handling
1498          * multiple interrupts at the same interrupt level.
1499          * As the interrupt level is determined by taking the
1500          * vector number and shifting that right by 4, we
1501          * want to spread these out a bit so that they don't
1502          * all fall in the same interrupt level.
1503          *
1504          * Also, we've got to be careful not to trash gate
1505          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1506          */
1507         for (irq = 0; irq < NR_IRQS ; irq++) {
1508                 int tmp = irq;
1509                 if (use_pci_vector()) {
1510                         if (!platform_legacy_irq(tmp))
1511                                 if ((tmp = vector_to_irq(tmp)) == -1)
1512                                         continue;
1513                 }
1514                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1515                         /*
1516                          * Hmm.. We don't have an entry for this,
1517                          * so default to an old-fashioned 8259
1518                          * interrupt if we can..
1519                          */
1520                         if (irq < 16)
1521                                 make_8259A_irq(irq);
1522                         else
1523                                 /* Strange. Oh, well.. */
1524                                 irq_desc[irq].handler = &no_irq_type;
1525                 }
1526         }
1527 }
1528
1529 static void enable_lapic_irq (unsigned int irq)
1530 {
1531         unsigned long v;
1532
1533         v = apic_read(APIC_LVT0);
1534         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1535 }
1536
1537 static void disable_lapic_irq (unsigned int irq)
1538 {
1539         unsigned long v;
1540
1541         v = apic_read(APIC_LVT0);
1542         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1543 }
1544
1545 static void ack_lapic_irq (unsigned int irq)
1546 {
1547         ack_APIC_irq();
1548 }
1549
1550 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1551
1552 static struct hw_interrupt_type lapic_irq_type = {
1553         .typename = "local-APIC-edge",
1554         .startup = NULL, /* startup_irq() not used for IRQ0 */
1555         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1556         .enable = enable_lapic_irq,
1557         .disable = disable_lapic_irq,
1558         .ack = ack_lapic_irq,
1559         .end = end_lapic_irq,
1560 };
1561
1562 static void setup_nmi (void)
1563 {
1564         /*
1565          * Dirty trick to enable the NMI watchdog ...
1566          * We put the 8259A master into AEOI mode and
1567          * unmask on all local APICs LVT0 as NMI.
1568          *
1569          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1570          * is from Maciej W. Rozycki - so we do not have to EOI from
1571          * the NMI handler or the timer interrupt.
1572          */
1573         printk(KERN_INFO "activating NMI Watchdog ...");
1574
1575         enable_NMI_through_LVT0(NULL);
1576
1577         printk(" done.\n");
1578 }
1579
1580 /*
1581  * This looks a bit hackish but it's about the only one way of sending
1582  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1583  * not support the ExtINT mode, unfortunately.  We need to send these
1584  * cycles as some i82489DX-based boards have glue logic that keeps the
1585  * 8259A interrupt line asserted until INTA.  --macro
1586  */
1587 static inline void unlock_ExtINT_logic(void)
1588 {
1589         int pin, i;
1590         struct IO_APIC_route_entry entry0, entry1;
1591         unsigned char save_control, save_freq_select;
1592         unsigned long flags;
1593
1594         pin = find_isa_irq_pin(8, mp_INT);
1595         if (pin == -1)
1596                 return;
1597
1598         spin_lock_irqsave(&ioapic_lock, flags);
1599         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1600         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1601         spin_unlock_irqrestore(&ioapic_lock, flags);
1602         clear_IO_APIC_pin(0, pin);
1603
1604         memset(&entry1, 0, sizeof(entry1));
1605
1606         entry1.dest_mode = 0;                   /* physical delivery */
1607         entry1.mask = 0;                        /* unmask IRQ now */
1608         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1609         entry1.delivery_mode = dest_ExtINT;
1610         entry1.polarity = entry0.polarity;
1611         entry1.trigger = 0;
1612         entry1.vector = 0;
1613
1614         spin_lock_irqsave(&ioapic_lock, flags);
1615         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1616         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1617         spin_unlock_irqrestore(&ioapic_lock, flags);
1618
1619         save_control = CMOS_READ(RTC_CONTROL);
1620         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1621         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1622                    RTC_FREQ_SELECT);
1623         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1624
1625         i = 100;
1626         while (i-- > 0) {
1627                 mdelay(10);
1628                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1629                         i -= 10;
1630         }
1631
1632         CMOS_WRITE(save_control, RTC_CONTROL);
1633         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1634         clear_IO_APIC_pin(0, pin);
1635
1636         spin_lock_irqsave(&ioapic_lock, flags);
1637         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1638         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1639         spin_unlock_irqrestore(&ioapic_lock, flags);
1640 }
1641
1642 /*
1643  * This code may look a bit paranoid, but it's supposed to cooperate with
1644  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1645  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1646  * fanatically on his truly buggy board.
1647  */
1648 static inline void check_timer(void)
1649 {
1650         int pin1, pin2;
1651         int vector;
1652
1653         /*
1654          * get/set the timer IRQ vector:
1655          */
1656         disable_8259A_irq(0);
1657         vector = assign_irq_vector(0);
1658         set_intr_gate(vector, interrupt[0]);
1659
1660         /*
1661          * Subtle, code in do_timer_interrupt() expects an AEOI
1662          * mode for the 8259A whenever interrupts are routed
1663          * through I/O APICs.  Also IRQ0 has to be enabled in
1664          * the 8259A which implies the virtual wire has to be
1665          * disabled in the local APIC.
1666          */
1667         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1668         init_8259A(1);
1669         enable_8259A_irq(0);
1670
1671         pin1 = find_isa_irq_pin(0, mp_INT);
1672         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1673
1674         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1675
1676         if (pin1 != -1) {
1677                 /*
1678                  * Ok, does IRQ0 through the IOAPIC work?
1679                  */
1680                 unmask_IO_APIC_irq(0);
1681                 if (timer_irq_works()) {
1682                         nmi_watchdog_default();
1683                         if (nmi_watchdog == NMI_IO_APIC) {
1684                                 disable_8259A_irq(0);
1685                                 setup_nmi();
1686                                 enable_8259A_irq(0);
1687                                 check_nmi_watchdog();
1688                         }
1689                         return;
1690                 }
1691                 clear_IO_APIC_pin(0, pin1);
1692                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1693         }
1694
1695         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1696         if (pin2 != -1) {
1697                 printk("\n..... (found pin %d) ...", pin2);
1698                 /*
1699                  * legacy devices should be connected to IO APIC #0
1700                  */
1701                 setup_ExtINT_IRQ0_pin(pin2, vector);
1702                 if (timer_irq_works()) {
1703                         printk("works.\n");
1704                         nmi_watchdog_default();
1705                         if (nmi_watchdog == NMI_IO_APIC) {
1706                                 setup_nmi();
1707                                 check_nmi_watchdog();
1708                         }
1709                         return;
1710                 }
1711                 /*
1712                  * Cleanup, just in case ...
1713                  */
1714                 clear_IO_APIC_pin(0, pin2);
1715         }
1716         printk(" failed.\n");
1717
1718         if (nmi_watchdog) {
1719                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1720                 nmi_watchdog = 0;
1721         }
1722
1723         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1724
1725         disable_8259A_irq(0);
1726         irq_desc[0].handler = &lapic_irq_type;
1727         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1728         enable_8259A_irq(0);
1729
1730         if (timer_irq_works()) {
1731                 printk(" works.\n");
1732                 return;
1733         }
1734         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1735         printk(" failed.\n");
1736
1737         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1738
1739         init_8259A(0);
1740         make_8259A_irq(0);
1741         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1742
1743         unlock_ExtINT_logic();
1744
1745         if (timer_irq_works()) {
1746                 printk(" works.\n");
1747                 return;
1748         }
1749         printk(" failed :(.\n");
1750         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1751 }
1752
1753 /*
1754  *
1755  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1756  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1757  *   Linux doesn't really care, as it's not actually used
1758  *   for any interrupt handling anyway.
1759  */
1760 #define PIC_IRQS        (1<<2)
1761
1762 void __init setup_IO_APIC(void)
1763 {
1764         enable_IO_APIC();
1765
1766         if (acpi_ioapic)
1767                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1768         else
1769                 io_apic_irqs = ~PIC_IRQS;
1770
1771         printk("ENABLING IO-APIC IRQs\n");
1772
1773         /*
1774          * Set up the IO-APIC IRQ routing table.
1775          */
1776         if (!acpi_ioapic)
1777                 setup_ioapic_ids_from_mpc();
1778         sync_Arb_IDs();
1779         setup_IO_APIC_irqs();
1780         init_IO_APIC_traps();
1781         check_timer();
1782         if (!acpi_ioapic)
1783                 print_IO_APIC();
1784 }
1785
1786 /* --------------------------------------------------------------------------
1787                           ACPI-based IOAPIC Configuration
1788    -------------------------------------------------------------------------- */
1789
1790 #ifdef CONFIG_ACPI_BOOT
1791
1792 #define IO_APIC_MAX_ID          15
1793
1794 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1795 {
1796         union IO_APIC_reg_00 reg_00;
1797         static physid_mask_t apic_id_map;
1798         unsigned long flags;
1799         int i = 0;
1800
1801         /*
1802          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1803          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1804          * supports up to 16 on one shared APIC bus.
1805          *
1806          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1807          *      advantage of new APIC bus architecture.
1808          */
1809
1810         if (physids_empty(apic_id_map))
1811                 apic_id_map = phys_cpu_present_map;
1812
1813         spin_lock_irqsave(&ioapic_lock, flags);
1814         reg_00.raw = io_apic_read(ioapic, 0);
1815         spin_unlock_irqrestore(&ioapic_lock, flags);
1816
1817         if (apic_id >= IO_APIC_MAX_ID) {
1818                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1819                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1820                 apic_id = reg_00.bits.ID;
1821         }
1822
1823         /*
1824          * Every APIC in a system must have a unique ID or we get lots of nice
1825          * 'stuck on smp_invalidate_needed IPI wait' messages.
1826          */
1827         if (physid_isset(apic_id, apic_id_map)) {
1828
1829                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1830                         if (!physid_isset(i, apic_id_map))
1831                                 break;
1832                 }
1833
1834                 if (i == IO_APIC_MAX_ID)
1835                         panic("Max apic_id exceeded!\n");
1836
1837                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1838                         "trying %d\n", ioapic, apic_id, i);
1839
1840                 apic_id = i;
1841         }
1842
1843         physid_set(apic_id, apic_id_map);
1844
1845         if (reg_00.bits.ID != apic_id) {
1846                 reg_00.bits.ID = apic_id;
1847
1848                 spin_lock_irqsave(&ioapic_lock, flags);
1849                 io_apic_write(ioapic, 0, reg_00.raw);
1850                 reg_00.raw = io_apic_read(ioapic, 0);
1851                 spin_unlock_irqrestore(&ioapic_lock, flags);
1852
1853                 /* Sanity check */
1854                 if (reg_00.bits.ID != apic_id)
1855                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1856         }
1857
1858         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1859
1860         return apic_id;
1861 }
1862
1863
1864 int __init io_apic_get_version (int ioapic)
1865 {
1866         union IO_APIC_reg_01    reg_01;
1867         unsigned long flags;
1868
1869         spin_lock_irqsave(&ioapic_lock, flags);
1870         reg_01.raw = io_apic_read(ioapic, 1);
1871         spin_unlock_irqrestore(&ioapic_lock, flags);
1872
1873         return reg_01.bits.version;
1874 }
1875
1876
1877 int __init io_apic_get_redir_entries (int ioapic)
1878 {
1879         union IO_APIC_reg_01    reg_01;
1880         unsigned long flags;
1881
1882         spin_lock_irqsave(&ioapic_lock, flags);
1883         reg_01.raw = io_apic_read(ioapic, 1);
1884         spin_unlock_irqrestore(&ioapic_lock, flags);
1885
1886         return reg_01.bits.entries;
1887 }
1888
1889
1890 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1891 {
1892         struct IO_APIC_route_entry entry;
1893         unsigned long flags;
1894
1895         if (!IO_APIC_IRQ(irq)) {
1896                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1897                         ioapic);
1898                 return -EINVAL;
1899         }
1900
1901         /*
1902          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1903          * Note that we mask (disable) IRQs now -- these get enabled when the
1904          * corresponding device driver registers for this IRQ.
1905          */
1906
1907         memset(&entry,0,sizeof(entry));
1908
1909         entry.delivery_mode = dest_LowestPrio;
1910         entry.dest_mode = INT_DELIVERY_MODE;
1911         entry.dest.logical.logical_dest = TARGET_CPUS;
1912         entry.trigger = edge_level;
1913         entry.polarity = active_high_low;
1914         entry.mask = 1;                                  /* Disabled (masked) */
1915
1916         /*
1917          * IRQs < 16 are already in the irq_2_pin[] map
1918          */
1919         if (irq >= 16)
1920                 add_pin_to_irq(irq, ioapic, pin);
1921
1922         entry.vector = assign_irq_vector(irq);
1923
1924         printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1925                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1926                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1927                edge_level, active_high_low);
1928
1929         if (use_pci_vector() && !platform_legacy_irq(irq))
1930                 irq = IO_APIC_VECTOR(irq);
1931         if (edge_level) {
1932                 irq_desc[irq].handler = &ioapic_level_type;
1933         } else {
1934                 irq_desc[irq].handler = &ioapic_edge_type;
1935         }
1936
1937         set_intr_gate(entry.vector, interrupt[irq]);
1938
1939         if (!ioapic && (irq < 16))
1940                 disable_8259A_irq(irq);
1941
1942         spin_lock_irqsave(&ioapic_lock, flags);
1943         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1944         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1945         spin_unlock_irqrestore(&ioapic_lock, flags);
1946
1947         return 0;
1948 }
1949
1950 #endif /*CONFIG_ACPI_BOOT*/
1951
1952 #ifndef CONFIG_SMP
1953 void send_IPI_self(int vector)
1954 {
1955         unsigned int cfg;
1956
1957        /*
1958         * Wait for idle.
1959         */
1960         apic_wait_icr_idle();
1961         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1962
1963         /*
1964          * Send the IPI. The write to APIC_ICR fires this off.
1965          */
1966         apic_write_around(APIC_ICR, cfg);
1967 }
1968 #endif