arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/smp.h>
  36 #include <asm/desc.h>
  37 #include <asm/proto.h>
  38
  39 int sis_apic_bug; /* not actually supported, dummy for compile */
  40
  41 #undef APIC_LOCKUP_DEBUG
  42
  43 #define APIC_LOCKUP_DEBUG
  44
  45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  46
  47 /*
  48  * # of IRQ routing registers
  49  */
  50 int nr_ioapic_registers[MAX_IO_APICS];
  51
  52 /*
  53  * Rough estimation of how many shared IRQs there are, can
  54  * be changed anytime.
  55  */
  56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  58
  59 /*
  60  * This is performance-critical, we want to do it O(1)
  61  *
  62  * the indexing order of this array favors 1:1 mappings
  63  * between pins and IRQs.
  64  */
  65
  66 static struct irq_pin_list {
  67         short apic, pin, next;
  68 } irq_2_pin[PIN_MAP_SIZE];
  69
  70 #ifdef CONFIG_PCI_USE_VECTOR
  71 int vector_irq[NR_IRQS] = { [0 ... NR_IRQS -1] = -1};
  72 #define vector_to_irq(vector)   \
  73         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  74 #else
  75 #define vector_to_irq(vector)   (vector)
  76 #endif
  77
  78 /*
  79  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  80  * shared ISA-space IRQs, so we have to support them. We are super
  81  * fast in the common case, and fast for shared ISA-space IRQs.
  82  */
  83 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  84 {
  85         static int first_free_entry = NR_IRQS;
  86         struct irq_pin_list *entry = irq_2_pin + irq;
  87
  88         while (entry->next)
  89                 entry = irq_2_pin + entry->next;
  90
  91         if (entry->pin != -1) {
  92                 entry->next = first_free_entry;
  93                 entry = irq_2_pin + entry->next;
  94                 if (++first_free_entry >= PIN_MAP_SIZE)
  95                         panic("io_apic.c: whoops");
  96         }
  97         entry->apic = apic;
  98         entry->pin = pin;
  99 }
 100
 101 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 102                                                                         \
 103 {                                                                       \
 104         int pin;                                                        \
 105         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 106                                                                         \
 107         for (;;) {                                                      \
 108                 unsigned int reg;                                       \
 109                 pin = entry->pin;                                       \
 110                 if (pin == -1)                                          \
 111                         break;                                          \
 112                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 113                 reg ACTION;                                             \
 114                 io_apic_modify(entry->apic, reg);                       \
 115                 if (!entry->next)                                       \
 116                         break;                                          \
 117                 entry = irq_2_pin + entry->next;                        \
 118         }                                                               \
 119         FINAL;                                                          \
 120 }
 121
 122 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 123                                                                         \
 124         static void name##_IO_APIC_irq (unsigned int irq)               \
 125         __DO_ACTION(R, ACTION, FINAL)
 126
 127 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 128                                                 /* mask = 1 */
 129 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 130                                                 /* mask = 0 */
 131 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
 132                                                 /* mask = 1, trigger = 0 */
 133 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
 134                                                 /* mask = 0, trigger = 1 */
 135
 136 static void mask_IO_APIC_irq (unsigned int irq)
 137 {
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&ioapic_lock, flags);
 141         __mask_IO_APIC_irq(irq);
 142         spin_unlock_irqrestore(&ioapic_lock, flags);
 143 }
 144
 145 static void unmask_IO_APIC_irq (unsigned int irq)
 146 {
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&ioapic_lock, flags);
 150         __unmask_IO_APIC_irq(irq);
 151         spin_unlock_irqrestore(&ioapic_lock, flags);
 152 }
 153
 154 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 155 {
 156         struct IO_APIC_route_entry entry;
 157         unsigned long flags;
 158
 159         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 160         spin_lock_irqsave(&ioapic_lock, flags);
 161         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 162         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 163         spin_unlock_irqrestore(&ioapic_lock, flags);
 164         if (entry.delivery_mode == dest_SMI)
 165                 return;
 166         /*
 167          * Disable it in the IO-APIC irq-routing table:
 168          */
 169         memset(&entry, 0, sizeof(entry));
 170         entry.mask = 1;
 171         spin_lock_irqsave(&ioapic_lock, flags);
 172         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 173         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 174         spin_unlock_irqrestore(&ioapic_lock, flags);
 175 }
 176
 177 static void clear_IO_APIC (void)
 178 {
 179         int apic, pin;
 180
 181         for (apic = 0; apic < nr_ioapics; apic++)
 182                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 183                         clear_IO_APIC_pin(apic, pin);
 184 }
 185
 186 /*
 187  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 188  * specific CPU-side IRQs.
 189  */
 190
 191 #define MAX_PIRQS 8
 192 int pirq_entries [MAX_PIRQS];
 193 int pirqs_enabled;
 194 int skip_ioapic_setup;
 195 int ioapic_force;
 196
 197 /* dummy parsing: see setup.c */
 198
 199 static int __init disable_ioapic_setup(char *str)
 200 {
 201         skip_ioapic_setup = 1;
 202         return 1;
 203 }
 204
 205 static int __init enable_ioapic_setup(char *str)
 206 {
 207         ioapic_force = 1;
 208         skip_ioapic_setup = 0;
 209         return 1;
 210 }
 211
 212 __setup("noapic", disable_ioapic_setup);
 213 __setup("apic", enable_ioapic_setup);
 214
 215 #include <asm/pci-direct.h>
 216 #include <linux/pci_ids.h>
 217 #include <linux/pci.h>
 218
 219 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 220    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 221    Use pci direct infrastructure because this runs before the PCI subsystem.
 222
 223    Can be overwritten with "apic"
 224
 225    And another hack to disable the IOMMU on VIA chipsets.
 226
 227    Kludge-O-Rama. */
 228 void __init check_ioapic(void)
 229 {
 230         int num,slot,func;
 231         if (ioapic_force)
 232                 return;
 233
 234         /* Poor man's PCI discovery */
 235         for (num = 0; num < 32; num++) {
 236                 for (slot = 0; slot < 32; slot++) {
 237                         for (func = 0; func < 8; func++) {
 238                                 u32 class;
 239                                 u32 vendor;
 240                                 u8 type;
 241                                 class = read_pci_config(num,slot,func,
 242                                                         PCI_CLASS_REVISION);
 243                                 if (class == 0xffffffff)
 244                                         break;
 245
 246                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 247                                         continue;
 248
 249                                 vendor = read_pci_config(num, slot, func,
 250                                                          PCI_VENDOR_ID);
 251                                 vendor &= 0xffff;
 252                                 switch (vendor) {
 253                                 case PCI_VENDOR_ID_VIA:
 254 #ifdef CONFIG_GART_IOMMU
 255                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 256                                              force_iommu) &&
 257                                             !iommu_aperture_allowed) {
 258                                                 printk(KERN_INFO
 259     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 260                                                 iommu_aperture_disabled = 1;
 261                                         }
 262 #endif
 263                                         return;
 264                                 case PCI_VENDOR_ID_NVIDIA:
 265 #ifndef CONFIG_SMP
 266                                         printk(KERN_INFO
 267      "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
 268                                                num,slot,vendor);
 269                                         skip_ioapic_setup = 1;
 270 #endif
 271                                         return;
 272                                 }
 273
 274                                 /* No multi-function device? */
 275                                 type = read_pci_config_byte(num,slot,func,
 276                                                             PCI_HEADER_TYPE);
 277                                 if (!(type & 0x80))
 278                                         break;
 279                         }
 280                 }
 281         }
 282 }
 283
 284 static int __init ioapic_pirq_setup(char *str)
 285 {
 286         int i, max;
 287         int ints[MAX_PIRQS+1];
 288
 289         get_options(str, ARRAY_SIZE(ints), ints);
 290
 291         for (i = 0; i < MAX_PIRQS; i++)
 292                 pirq_entries[i] = -1;
 293
 294         pirqs_enabled = 1;
 295         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
 296         max = MAX_PIRQS;
 297         if (ints[0] < MAX_PIRQS)
 298                 max = ints[0];
 299
 300         for (i = 0; i < max; i++) {
 301                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 302                 /*
 303                  * PIRQs are mapped upside down, usually.
 304                  */
 305                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 306         }
 307         return 1;
 308 }
 309
 310 __setup("pirq=", ioapic_pirq_setup);
 311
 312 /*
 313  * Find the IRQ entry number of a certain pin.
 314  */
 315 static int __init find_irq_entry(int apic, int pin, int type)
 316 {
 317         int i;
 318
 319         for (i = 0; i < mp_irq_entries; i++)
 320                 if (mp_irqs[i].mpc_irqtype == type &&
 321                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 322                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 323                     mp_irqs[i].mpc_dstirq == pin)
 324                         return i;
 325
 326         return -1;
 327 }
 328
 329 /*
 330  * Find the pin to which IRQ[irq] (ISA) is connected
 331  */
 332 static int __init find_isa_irq_pin(int irq, int type)
 333 {
 334         int i;
 335
 336         for (i = 0; i < mp_irq_entries; i++) {
 337                 int lbus = mp_irqs[i].mpc_srcbus;
 338
 339                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 340                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 341                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 342                     (mp_irqs[i].mpc_irqtype == type) &&
 343                     (mp_irqs[i].mpc_srcbusirq == irq))
 344
 345                         return mp_irqs[i].mpc_dstirq;
 346         }
 347         return -1;
 348 }
 349
 350 /*
 351  * Find a specific PCI IRQ entry.
 352  * Not an __init, possibly needed by modules
 353  */
 354 static int pin_2_irq(int idx, int apic, int pin);
 355
 356 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 357 {
 358         int apic, i, best_guess = -1;
 359
 360         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 361                 bus, slot, pin);
 362         if (mp_bus_id_to_pci_bus[bus] == -1) {
 363                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 364                 return -1;
 365         }
 366         for (i = 0; i < mp_irq_entries; i++) {
 367                 int lbus = mp_irqs[i].mpc_srcbus;
 368
 369                 for (apic = 0; apic < nr_ioapics; apic++)
 370                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 371                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 372                                 break;
 373
 374                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 375                     !mp_irqs[i].mpc_irqtype &&
 376                     (bus == lbus) &&
 377                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 378                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 379
 380                         if (!(apic || IO_APIC_IRQ(irq)))
 381                                 continue;
 382
 383                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 384                                 return irq;
 385                         /*
 386                          * Use the first all-but-pin matching entry as a
 387                          * best-guess fuzzy result for broken mptables.
 388                          */
 389                         if (best_guess < 0)
 390                                 best_guess = irq;
 391                 }
 392         }
 393         return best_guess;
 394 }
 395
 396 /*
 397  * EISA Edge/Level control register, ELCR
 398  */
 399 static int __init EISA_ELCR(unsigned int irq)
 400 {
 401         if (irq < 16) {
 402                 unsigned int port = 0x4d0 + (irq >> 3);
 403                 return (inb(port) >> (irq & 7)) & 1;
 404         }
 405         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
 406         return 0;
 407 }
 408
 409 /* EISA interrupts are always polarity zero and can be edge or level
 410  * trigger depending on the ELCR value.  If an interrupt is listed as
 411  * EISA conforming in the MP table, that means its trigger type must
 412  * be read in from the ELCR */
 413
 414 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 415 #define default_EISA_polarity(idx)      (0)
 416
 417 /* ISA interrupts are always polarity zero edge triggered,
 418  * when listed as conforming in the MP table. */
 419
 420 #define default_ISA_trigger(idx)        (0)
 421 #define default_ISA_polarity(idx)       (0)
 422
 423 /* PCI interrupts are always polarity one level triggered,
 424  * when listed as conforming in the MP table. */
 425
 426 #define default_PCI_trigger(idx)        (1)
 427 #define default_PCI_polarity(idx)       (1)
 428
 429 /* MCA interrupts are always polarity zero level triggered,
 430  * when listed as conforming in the MP table. */
 431
 432 #define default_MCA_trigger(idx)        (1)
 433 #define default_MCA_polarity(idx)       (0)
 434
 435 static int __init MPBIOS_polarity(int idx)
 436 {
 437         int bus = mp_irqs[idx].mpc_srcbus;
 438         int polarity;
 439
 440         /*
 441          * Determine IRQ line polarity (high active or low active):
 442          */
 443         switch (mp_irqs[idx].mpc_irqflag & 3)
 444         {
 445                 case 0: /* conforms, ie. bus-type dependent polarity */
 446                 {
 447                         switch (mp_bus_id_to_type[bus])
 448                         {
 449                                 case MP_BUS_ISA: /* ISA pin */
 450                                 {
 451                                         polarity = default_ISA_polarity(idx);
 452                                         break;
 453                                 }
 454                                 case MP_BUS_EISA: /* EISA pin */
 455                                 {
 456                                         polarity = default_EISA_polarity(idx);
 457                                         break;
 458                                 }
 459                                 case MP_BUS_PCI: /* PCI pin */
 460                                 {
 461                                         polarity = default_PCI_polarity(idx);
 462                                         break;
 463                                 }
 464                                 case MP_BUS_MCA: /* MCA pin */
 465                                 {
 466                                         polarity = default_MCA_polarity(idx);
 467                                         break;
 468                                 }
 469                                 default:
 470                                 {
 471                                         printk(KERN_WARNING "broken BIOS!!\n");
 472                                         polarity = 1;
 473                                         break;
 474                                 }
 475                         }
 476                         break;
 477                 }
 478                 case 1: /* high active */
 479                 {
 480                         polarity = 0;
 481                         break;
 482                 }
 483                 case 2: /* reserved */
 484                 {
 485                         printk(KERN_WARNING "broken BIOS!!\n");
 486                         polarity = 1;
 487                         break;
 488                 }
 489                 case 3: /* low active */
 490                 {
 491                         polarity = 1;
 492                         break;
 493                 }
 494                 default: /* invalid */
 495                 {
 496                         printk(KERN_WARNING "broken BIOS!!\n");
 497                         polarity = 1;
 498                         break;
 499                 }
 500         }
 501         return polarity;
 502 }
 503
 504 static int __init MPBIOS_trigger(int idx)
 505 {
 506         int bus = mp_irqs[idx].mpc_srcbus;
 507         int trigger;
 508
 509         /*
 510          * Determine IRQ trigger mode (edge or level sensitive):
 511          */
 512         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 513         {
 514                 case 0: /* conforms, ie. bus-type dependent */
 515                 {
 516                         switch (mp_bus_id_to_type[bus])
 517                         {
 518                                 case MP_BUS_ISA: /* ISA pin */
 519                                 {
 520                                         trigger = default_ISA_trigger(idx);
 521                                         break;
 522                                 }
 523                                 case MP_BUS_EISA: /* EISA pin */
 524                                 {
 525                                         trigger = default_EISA_trigger(idx);
 526                                         break;
 527                                 }
 528                                 case MP_BUS_PCI: /* PCI pin */
 529                                 {
 530                                         trigger = default_PCI_trigger(idx);
 531                                         break;
 532                                 }
 533                                 case MP_BUS_MCA: /* MCA pin */
 534                                 {
 535                                         trigger = default_MCA_trigger(idx);
 536                                         break;
 537                                 }
 538                                 default:
 539                                 {
 540                                         printk(KERN_WARNING "broken BIOS!!\n");
 541                                         trigger = 1;
 542                                         break;
 543                                 }
 544                         }
 545                         break;
 546                 }
 547                 case 1: /* edge */
 548                 {
 549                         trigger = 0;
 550                         break;
 551                 }
 552                 case 2: /* reserved */
 553                 {
 554                         printk(KERN_WARNING "broken BIOS!!\n");
 555                         trigger = 1;
 556                         break;
 557                 }
 558                 case 3: /* level */
 559                 {
 560                         trigger = 1;
 561                         break;
 562                 }
 563                 default: /* invalid */
 564                 {
 565                         printk(KERN_WARNING "broken BIOS!!\n");
 566                         trigger = 0;
 567                         break;
 568                 }
 569         }
 570         return trigger;
 571 }
 572
 573 static inline int irq_polarity(int idx)
 574 {
 575         return MPBIOS_polarity(idx);
 576 }
 577
 578 static inline int irq_trigger(int idx)
 579 {
 580         return MPBIOS_trigger(idx);
 581 }
 582
 583 static int pin_2_irq(int idx, int apic, int pin)
 584 {
 585         int irq, i;
 586         int bus = mp_irqs[idx].mpc_srcbus;
 587
 588         /*
 589          * Debugging check, we are in big trouble if this message pops up!
 590          */
 591         if (mp_irqs[idx].mpc_dstirq != pin)
 592                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 593
 594         switch (mp_bus_id_to_type[bus])
 595         {
 596                 case MP_BUS_ISA: /* ISA pin */
 597                 case MP_BUS_EISA:
 598                 case MP_BUS_MCA:
 599                 {
 600                         irq = mp_irqs[idx].mpc_srcbusirq;
 601                         break;
 602                 }
 603                 case MP_BUS_PCI: /* PCI pin */
 604                 {
 605                         /*
 606                          * PCI IRQs are mapped in order
 607                          */
 608                         i = irq = 0;
 609                         while (i < apic)
 610                                 irq += nr_ioapic_registers[i++];
 611                         irq += pin;
 612                         break;
 613                 }
 614                 default:
 615                 {
 616                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 617                         irq = 0;
 618                         break;
 619                 }
 620         }
 621
 622         /*
 623          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 624          */
 625         if ((pin >= 16) && (pin <= 23)) {
 626                 if (pirq_entries[pin-16] != -1) {
 627                         if (!pirq_entries[pin-16]) {
 628                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
 629                         } else {
 630                                 irq = pirq_entries[pin-16];
 631                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
 632                                                 pin-16, irq);
 633                         }
 634                 }
 635         }
 636         return irq;
 637 }
 638
 639 static inline int IO_APIC_irq_trigger(int irq)
 640 {
 641         int apic, idx, pin;
 642
 643         for (apic = 0; apic < nr_ioapics; apic++) {
 644                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 645                         idx = find_irq_entry(apic,pin,mp_INT);
 646                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 647                                 return irq_trigger(idx);
 648                 }
 649         }
 650         /*
 651          * nonexistent IRQs are edge default
 652          */
 653         return 0;
 654 }
 655
 656 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 657 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 658
 659 #ifndef CONFIG_PCI_USE_VECTOR
 660 int __init assign_irq_vector(int irq)
 661 {
 662         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 663         BUG_ON(irq >= NR_IRQ_VECTORS);
 664         if (IO_APIC_VECTOR(irq) > 0)
 665                 return IO_APIC_VECTOR(irq);
 666 next:
 667         current_vector += 8;
 668         if (current_vector == IA32_SYSCALL_VECTOR)
 669                 goto next;
 670
 671         if (current_vector > FIRST_SYSTEM_VECTOR) {
 672                 offset++;
 673                 current_vector = FIRST_DEVICE_VECTOR + offset;
 674         }
 675
 676         if (current_vector == FIRST_SYSTEM_VECTOR)
 677                 panic("ran out of interrupt sources!");
 678
 679         IO_APIC_VECTOR(irq) = current_vector;
 680         return current_vector;
 681 }
 682 #endif
 683
 684 extern void (*interrupt[NR_IRQS])(void);
 685 static struct hw_interrupt_type ioapic_level_type;
 686 static struct hw_interrupt_type ioapic_edge_type;
 687
 688 #define IOAPIC_AUTO     -1
 689 #define IOAPIC_EDGE     0
 690 #define IOAPIC_LEVEL    1
 691
 692 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 693 {
 694         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 695                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 696                                 trigger == IOAPIC_LEVEL)
 697                         irq_desc[vector].handler = &ioapic_level_type;
 698                 else
 699                         irq_desc[vector].handler = &ioapic_edge_type;
 700                 set_intr_gate(vector, interrupt[vector]);
 701         } else  {
 702                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 703                                 trigger == IOAPIC_LEVEL)
 704                         irq_desc[irq].handler = &ioapic_level_type;
 705                 else
 706                         irq_desc[irq].handler = &ioapic_edge_type;
 707                 set_intr_gate(vector, interrupt[irq]);
 708         }
 709 }
 710
 711 void __init setup_IO_APIC_irqs(void)
 712 {
 713         struct IO_APIC_route_entry entry;
 714         int apic, pin, idx, irq, first_notcon = 1, vector;
 715         unsigned long flags;
 716
 717         printk(KERN_DEBUG "init IO_APIC IRQs\n");
 718
 719         for (apic = 0; apic < nr_ioapics; apic++) {
 720         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 721
 722                 /*
 723                  * add it to the IO-APIC irq-routing table:
 724                  */
 725                 memset(&entry,0,sizeof(entry));
 726
 727                 entry.delivery_mode = dest_LowestPrio;
 728                 entry.dest_mode = INT_DELIVERY_MODE;
 729                 entry.mask = 0;                         /* enable IRQ */
 730                 entry.dest.logical.logical_dest = TARGET_CPUS;
 731
 732                 idx = find_irq_entry(apic,pin,mp_INT);
 733                 if (idx == -1) {
 734                         if (first_notcon) {
 735                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 736                                 first_notcon = 0;
 737                         } else
 738                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 739                         continue;
 740                 }
 741
 742                 entry.trigger = irq_trigger(idx);
 743                 entry.polarity = irq_polarity(idx);
 744
 745                 if (irq_trigger(idx)) {
 746                         entry.trigger = 1;
 747                         entry.mask = 1;
 748                         entry.dest.logical.logical_dest = TARGET_CPUS;
 749                 }
 750
 751                 irq = pin_2_irq(idx, apic, pin);
 752                 add_pin_to_irq(irq, apic, pin);
 753
 754                 if (!apic && !IO_APIC_IRQ(irq))
 755                         continue;
 756
 757                 if (IO_APIC_IRQ(irq)) {
 758                         vector = assign_irq_vector(irq);
 759                         entry.vector = vector;
 760
 761                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 762                         if (!apic && (irq < 16))
 763                                 disable_8259A_irq(irq);
 764                 }
 765                 spin_lock_irqsave(&ioapic_lock, flags);
 766                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 767                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 768                 spin_unlock_irqrestore(&ioapic_lock, flags);
 769         }
 770         }
 771
 772         if (!first_notcon)
 773                 printk(" not connected.\n");
 774 }
 775
 776 /*
 777  * Set up the 8259A-master output pin as broadcast to all
 778  * CPUs.
 779  */
 780 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 781 {
 782         struct IO_APIC_route_entry entry;
 783         unsigned long flags;
 784
 785         memset(&entry,0,sizeof(entry));
 786
 787         disable_8259A_irq(0);
 788
 789         /* mask LVT0 */
 790         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 791
 792         /*
 793          * We use logical delivery to get the timer IRQ
 794          * to the first CPU.
 795          */
 796         entry.dest_mode = INT_DELIVERY_MODE;
 797         entry.mask = 0;                                 /* unmask IRQ now */
 798         entry.dest.logical.logical_dest = TARGET_CPUS;
 799         entry.delivery_mode = dest_LowestPrio;
 800         entry.polarity = 0;
 801         entry.trigger = 0;
 802         entry.vector = vector;
 803
 804         /*
 805          * The timer IRQ doesn't have to know that behind the
 806          * scene we have a 8259A-master in AEOI mode ...
 807          */
 808         irq_desc[0].handler = &ioapic_edge_type;
 809
 810         /*
 811          * Add it to the IO-APIC irq-routing table:
 812          */
 813         spin_lock_irqsave(&ioapic_lock, flags);
 814         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 815         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 816         spin_unlock_irqrestore(&ioapic_lock, flags);
 817
 818         enable_8259A_irq(0);
 819 }
 820
 821 void __init UNEXPECTED_IO_APIC(void)
 822 {
 823 #if 0
 824         printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
 825         printk(KERN_WARNING "          to linux-smp@vger.kernel.org\n");
 826 #endif
 827 }
 828
 829 void __init print_IO_APIC(void)
 830 {
 831         int apic, i;
 832         union IO_APIC_reg_00 reg_00;
 833         union IO_APIC_reg_01 reg_01;
 834         union IO_APIC_reg_02 reg_02;
 835         unsigned long flags;
 836
 837         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 838         for (i = 0; i < nr_ioapics; i++)
 839                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 840                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 841
 842         /*
 843          * We are a bit conservative about what we expect.  We have to
 844          * know about every hardware change ASAP.
 845          */
 846         printk(KERN_INFO "testing the IO APIC.......................\n");
 847
 848         for (apic = 0; apic < nr_ioapics; apic++) {
 849
 850         spin_lock_irqsave(&ioapic_lock, flags);
 851         reg_00.raw = io_apic_read(apic, 0);
 852         reg_01.raw = io_apic_read(apic, 1);
 853         if (reg_01.bits.version >= 0x10)
 854                 reg_02.raw = io_apic_read(apic, 2);
 855         spin_unlock_irqrestore(&ioapic_lock, flags);
 856
 857         printk("\n");
 858         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 859         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 860         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 861         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 862                 UNEXPECTED_IO_APIC();
 863
 864         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 865         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 866         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 867                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 868                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 869                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 870                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 871                 (reg_01.bits.entries != 0x2E) &&
 872                 (reg_01.bits.entries != 0x3F) &&
 873                 (reg_01.bits.entries != 0x03)
 874         )
 875                 UNEXPECTED_IO_APIC();
 876
 877         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 878         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 879         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 880                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 881                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 882                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 883                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 884                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 885         )
 886                 UNEXPECTED_IO_APIC();
 887         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 888                 UNEXPECTED_IO_APIC();
 889
 890         if (reg_01.bits.version >= 0x10) {
 891                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 892                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 893                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 894                         UNEXPECTED_IO_APIC();
 895         }
 896
 897         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 898
 899         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 900                           " Stat Dest Deli Vect:   \n");
 901
 902         for (i = 0; i <= reg_01.bits.entries; i++) {
 903                 struct IO_APIC_route_entry entry;
 904
 905                 spin_lock_irqsave(&ioapic_lock, flags);
 906                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 907                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 908                 spin_unlock_irqrestore(&ioapic_lock, flags);
 909
 910                 printk(KERN_DEBUG " %02x %03X %02X  ",
 911                         i,
 912                         entry.dest.logical.logical_dest,
 913                         entry.dest.physical.physical_dest
 914                 );
 915
 916                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 917                         entry.mask,
 918                         entry.trigger,
 919                         entry.irr,
 920                         entry.polarity,
 921                         entry.delivery_status,
 922                         entry.dest_mode,
 923                         entry.delivery_mode,
 924                         entry.vector
 925                 );
 926         }
 927         }
 928         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 929         for (i = 0; i < NR_IRQS; i++) {
 930                 struct irq_pin_list *entry = irq_2_pin + i;
 931                 if (entry->pin < 0)
 932                         continue;
 933                 printk(KERN_DEBUG "IRQ%d ", i);
 934                 for (;;) {
 935                         printk("-> %d:%d", entry->apic, entry->pin);
 936                         if (!entry->next)
 937                                 break;
 938                         entry = irq_2_pin + entry->next;
 939                 }
 940                 printk("\n");
 941         }
 942
 943         printk(KERN_INFO ".................................... done.\n");
 944
 945         return;
 946 }
 947
 948 static void print_APIC_bitfield (int base)
 949 {
 950         unsigned int v;
 951         int i, j;
 952
 953         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 954         for (i = 0; i < 8; i++) {
 955                 v = apic_read(base + i*0x10);
 956                 for (j = 0; j < 32; j++) {
 957                         if (v & (1<<j))
 958                                 printk("1");
 959                         else
 960                                 printk("0");
 961                 }
 962                 printk("\n");
 963         }
 964 }
 965
 966 void /*__init*/ print_local_APIC(void * dummy)
 967 {
 968         unsigned int v, ver, maxlvt;
 969
 970         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 971                 smp_processor_id(), hard_smp_processor_id());
 972         v = apic_read(APIC_ID);
 973         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 974         v = apic_read(APIC_LVR);
 975         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 976         ver = GET_APIC_VERSION(v);
 977         maxlvt = get_maxlvt();
 978
 979         v = apic_read(APIC_TASKPRI);
 980         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 981
 982         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
 983                 v = apic_read(APIC_ARBPRI);
 984                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 985                         v & APIC_ARBPRI_MASK);
 986                 v = apic_read(APIC_PROCPRI);
 987                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 988         }
 989
 990         v = apic_read(APIC_EOI);
 991         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
 992         v = apic_read(APIC_RRR);
 993         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
 994         v = apic_read(APIC_LDR);
 995         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
 996         v = apic_read(APIC_DFR);
 997         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
 998         v = apic_read(APIC_SPIV);
 999         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1000
1001         printk(KERN_DEBUG "... APIC ISR field:\n");
1002         print_APIC_bitfield(APIC_ISR);
1003         printk(KERN_DEBUG "... APIC TMR field:\n");
1004         print_APIC_bitfield(APIC_TMR);
1005         printk(KERN_DEBUG "... APIC IRR field:\n");
1006         print_APIC_bitfield(APIC_IRR);
1007
1008         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1009                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1010                         apic_write(APIC_ESR, 0);
1011                 v = apic_read(APIC_ESR);
1012                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1013         }
1014
1015         v = apic_read(APIC_ICR);
1016         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1017         v = apic_read(APIC_ICR2);
1018         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1019
1020         v = apic_read(APIC_LVTT);
1021         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1022
1023         if (maxlvt > 3) {                       /* PC is LVT#4. */
1024                 v = apic_read(APIC_LVTPC);
1025                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1026         }
1027         v = apic_read(APIC_LVT0);
1028         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1029         v = apic_read(APIC_LVT1);
1030         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1031
1032         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1033                 v = apic_read(APIC_LVTERR);
1034                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1035         }
1036
1037         v = apic_read(APIC_TMICT);
1038         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1039         v = apic_read(APIC_TMCCT);
1040         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1041         v = apic_read(APIC_TDCR);
1042         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1043         printk("\n");
1044 }
1045
1046 void print_all_local_APICs (void)
1047 {
1048         on_each_cpu(print_local_APIC, NULL, 1, 1);
1049 }
1050
1051 void /*__init*/ print_PIC(void)
1052 {
1053         extern spinlock_t i8259A_lock;
1054         unsigned int v;
1055         unsigned long flags;
1056
1057         printk(KERN_DEBUG "\nprinting PIC contents\n");
1058
1059         spin_lock_irqsave(&i8259A_lock, flags);
1060
1061         v = inb(0xa1) << 8 | inb(0x21);
1062         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1063
1064         v = inb(0xa0) << 8 | inb(0x20);
1065         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1066
1067         outb(0x0b,0xa0);
1068         outb(0x0b,0x20);
1069         v = inb(0xa0) << 8 | inb(0x20);
1070         outb(0x0a,0xa0);
1071         outb(0x0a,0x20);
1072
1073         spin_unlock_irqrestore(&i8259A_lock, flags);
1074
1075         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1076
1077         v = inb(0x4d1) << 8 | inb(0x4d0);
1078         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1079 }
1080
1081 static void __init enable_IO_APIC(void)
1082 {
1083         union IO_APIC_reg_01 reg_01;
1084         int i;
1085         unsigned long flags;
1086
1087         for (i = 0; i < PIN_MAP_SIZE; i++) {
1088                 irq_2_pin[i].pin = -1;
1089                 irq_2_pin[i].next = 0;
1090         }
1091         if (!pirqs_enabled)
1092                 for (i = 0; i < MAX_PIRQS; i++)
1093                         pirq_entries[i] = -1;
1094
1095         /*
1096          * The number of IO-APIC IRQ registers (== #pins):
1097          */
1098         for (i = 0; i < nr_ioapics; i++) {
1099                 spin_lock_irqsave(&ioapic_lock, flags);
1100                 reg_01.raw = io_apic_read(i, 1);
1101                 spin_unlock_irqrestore(&ioapic_lock, flags);
1102                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1103         }
1104
1105         /*
1106          * Do not trust the IO-APIC being empty at bootup
1107          */
1108         clear_IO_APIC();
1109 }
1110
1111 /*
1112  * Not an __init, needed by the reboot code
1113  */
1114 void disable_IO_APIC(void)
1115 {
1116         /*
1117          * Clear the IO-APIC before rebooting:
1118          */
1119         clear_IO_APIC();
1120
1121         disconnect_bsp_APIC();
1122 }
1123
1124 /*
1125  * function to set the IO-APIC physical IDs based on the
1126  * values stored in the MPC table.
1127  *
1128  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1129  */
1130
1131 static void __init setup_ioapic_ids_from_mpc (void)
1132 {
1133         union IO_APIC_reg_00 reg_00;
1134         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1135         int apic;
1136         int i;
1137         unsigned char old_id;
1138         unsigned long flags;
1139
1140         /*
1141          * Set the IOAPIC ID to the value stored in the MPC table.
1142          */
1143         for (apic = 0; apic < nr_ioapics; apic++) {
1144
1145                 /* Read the register 0 value */
1146                 spin_lock_irqsave(&ioapic_lock, flags);
1147                 reg_00.raw = io_apic_read(apic, 0);
1148                 spin_unlock_irqrestore(&ioapic_lock, flags);
1149
1150                 old_id = mp_ioapics[apic].mpc_apicid;
1151
1152                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1153                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1154                                 apic, mp_ioapics[apic].mpc_apicid);
1155                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1156                                 reg_00.bits.ID);
1157                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1158                 }
1159
1160                 /*
1161                  * Sanity check, is the ID really free? Every APIC in a
1162                  * system must have a unique ID or we get lots of nice
1163                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1164                  */
1165                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1166                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1167                                 apic, mp_ioapics[apic].mpc_apicid);
1168                         for (i = 0; i < 0xf; i++)
1169                                 if (!physid_isset(i, phys_id_present_map))
1170                                         break;
1171                         if (i >= 0xf)
1172                                 panic("Max APIC ID exceeded!\n");
1173                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1174                                 i);
1175                         physid_set(i, phys_id_present_map);
1176                         mp_ioapics[apic].mpc_apicid = i;
1177                 } else {
1178                         printk(KERN_INFO
1179                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1180                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1181                 }
1182
1183
1184                 /*
1185                  * We need to adjust the IRQ routing table
1186                  * if the ID changed.
1187                  */
1188                 if (old_id != mp_ioapics[apic].mpc_apicid)
1189                         for (i = 0; i < mp_irq_entries; i++)
1190                                 if (mp_irqs[i].mpc_dstapic == old_id)
1191                                         mp_irqs[i].mpc_dstapic
1192                                                 = mp_ioapics[apic].mpc_apicid;
1193
1194                 /*
1195                  * Read the right value from the MPC table and
1196                  * write it into the ID register.
1197                  */
1198                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1199                                 mp_ioapics[apic].mpc_apicid);
1200
1201                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1202                 spin_lock_irqsave(&ioapic_lock, flags);
1203                 io_apic_write(apic, 0, reg_00.raw);
1204                 spin_unlock_irqrestore(&ioapic_lock, flags);
1205
1206                 /*
1207                  * Sanity check
1208                  */
1209                 spin_lock_irqsave(&ioapic_lock, flags);
1210                 reg_00.raw = io_apic_read(apic, 0);
1211                 spin_unlock_irqrestore(&ioapic_lock, flags);
1212                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1213                         panic("could not set ID!\n");
1214                 else
1215                         printk(" ok.\n");
1216         }
1217 }
1218
1219 /*
1220  * There is a nasty bug in some older SMP boards, their mptable lies
1221  * about the timer IRQ. We do the following to work around the situation:
1222  *
1223  *      - timer IRQ defaults to IO-APIC IRQ
1224  *      - if this function detects that timer IRQs are defunct, then we fall
1225  *        back to ISA timer IRQs
1226  */
1227 static int __init timer_irq_works(void)
1228 {
1229         unsigned long t1 = jiffies;
1230
1231         local_irq_enable();
1232         /* Let ten ticks pass... */
1233         mdelay((10 * 1000) / HZ);
1234
1235         /*
1236          * Expect a few ticks at least, to be sure some possible
1237          * glue logic does not lock up after one or two first
1238          * ticks in a non-ExtINT mode.  Also the local APIC
1239          * might have cached one ExtINT interrupt.  Finally, at
1240          * least one tick may be lost due to delays.
1241          */
1242
1243         /* jiffies wrap? */
1244         if (jiffies - t1 > 4)
1245                 return 1;
1246         return 0;
1247 }
1248
1249 /*
1250  * In the SMP+IOAPIC case it might happen that there are an unspecified
1251  * number of pending IRQ events unhandled. These cases are very rare,
1252  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1253  * better to do it this way as thus we do not have to be aware of
1254  * 'pending' interrupts in the IRQ path, except at this point.
1255  */
1256 /*
1257  * Edge triggered needs to resend any interrupt
1258  * that was delayed but this is now handled in the device
1259  * independent code.
1260  */
1261
1262 /*
1263  * Starting up a edge-triggered IO-APIC interrupt is
1264  * nasty - we need to make sure that we get the edge.
1265  * If it is already asserted for some reason, we need
1266  * return 1 to indicate that is was pending.
1267  *
1268  * This is not complete - we should be able to fake
1269  * an edge even if it isn't on the 8259A...
1270  */
1271
1272 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1273 {
1274         int was_pending = 0;
1275         unsigned long flags;
1276
1277         spin_lock_irqsave(&ioapic_lock, flags);
1278         if (irq < 16) {
1279                 disable_8259A_irq(irq);
1280                 if (i8259A_irq_pending(irq))
1281                         was_pending = 1;
1282         }
1283         __unmask_IO_APIC_irq(irq);
1284         spin_unlock_irqrestore(&ioapic_lock, flags);
1285
1286         return was_pending;
1287 }
1288
1289 /*
1290  * Once we have recorded IRQ_PENDING already, we can mask the
1291  * interrupt for real. This prevents IRQ storms from unhandled
1292  * devices.
1293  */
1294 static void ack_edge_ioapic_irq(unsigned int irq)
1295 {
1296         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1297                                         == (IRQ_PENDING | IRQ_DISABLED))
1298                 mask_IO_APIC_irq(irq);
1299         ack_APIC_irq();
1300 }
1301
1302 /*
1303  * Level triggered interrupts can just be masked,
1304  * and shutting down and starting up the interrupt
1305  * is the same as enabling and disabling them -- except
1306  * with a startup need to return a "was pending" value.
1307  *
1308  * Level triggered interrupts are special because we
1309  * do not touch any IO-APIC register while handling
1310  * them. We ack the APIC in the end-IRQ handler, not
1311  * in the start-IRQ-handler. Protection against reentrance
1312  * from the same interrupt is still provided, both by the
1313  * generic IRQ layer and by the fact that an unacked local
1314  * APIC does not accept IRQs.
1315  */
1316 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1317 {
1318         unmask_IO_APIC_irq(irq);
1319
1320         return 0; /* don't check for pending */
1321 }
1322
1323 static void end_level_ioapic_irq (unsigned int irq)
1324 {
1325         unsigned long v;
1326         int i;
1327
1328 /*
1329  * It appears there is an erratum which affects at least version 0x11
1330  * of I/O APIC (that's the 82093AA and cores integrated into various
1331  * chipsets).  Under certain conditions a level-triggered interrupt is
1332  * erroneously delivered as edge-triggered one but the respective IRR
1333  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1334  * message but it will never arrive and further interrupts are blocked
1335  * from the source.  The exact reason is so far unknown, but the
1336  * phenomenon was observed when two consecutive interrupt requests
1337  * from a given source get delivered to the same CPU and the source is
1338  * temporarily disabled in between.
1339  *
1340  * A workaround is to simulate an EOI message manually.  We achieve it
1341  * by setting the trigger mode to edge and then to level when the edge
1342  * trigger mode gets detected in the TMR of a local APIC for a
1343  * level-triggered interrupt.  We mask the source for the time of the
1344  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1345  * The idea is from Manfred Spraul.  --macro
1346  */
1347         i = IO_APIC_VECTOR(irq);
1348         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1349
1350         ack_APIC_irq();
1351
1352         if (!(v & (1 << (i & 0x1f)))) {
1353 #ifdef APIC_LOCKUP_DEBUG
1354                 struct irq_pin_list *entry;
1355 #endif
1356
1357 #ifdef APIC_MISMATCH_DEBUG
1358                 atomic_inc(&irq_mis_count);
1359 #endif
1360                 spin_lock(&ioapic_lock);
1361                 __mask_and_edge_IO_APIC_irq(irq);
1362 #ifdef APIC_LOCKUP_DEBUG
1363                 for (entry = irq_2_pin + irq;;) {
1364                         unsigned int reg;
1365
1366                         if (entry->pin == -1)
1367                                 break;
1368                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1369                         if (reg & 0x00004000)
1370                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1371                                         " still set after unlock!\n");
1372                         if (!entry->next)
1373                                 break;
1374                         entry = irq_2_pin + entry->next;
1375                 }
1376 #endif
1377                 __unmask_and_level_IO_APIC_irq(irq);
1378                 spin_unlock(&ioapic_lock);
1379         }
1380 }
1381
1382 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1383 {
1384         unsigned long flags;
1385         unsigned int dest;
1386
1387         dest = cpu_mask_to_apicid(mk_cpumask_const(mask));
1388
1389         /*
1390          * Only the first 8 bits are valid.
1391          */
1392         dest = dest << 24;
1393
1394         spin_lock_irqsave(&ioapic_lock, flags);
1395         __DO_ACTION(1, = dest, )
1396         spin_unlock_irqrestore(&ioapic_lock, flags);
1397 }
1398
1399 #ifdef CONFIG_PCI_USE_VECTOR
1400 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1401 {
1402         int irq = vector_to_irq(vector);
1403
1404         return startup_edge_ioapic_irq(irq);
1405 }
1406
1407 static void ack_edge_ioapic_vector(unsigned int vector)
1408 {
1409         int irq = vector_to_irq(vector);
1410
1411         ack_edge_ioapic_irq(irq);
1412 }
1413
1414 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1415 {
1416         int irq = vector_to_irq(vector);
1417
1418         return startup_level_ioapic_irq (irq);
1419 }
1420
1421 static void end_level_ioapic_vector (unsigned int vector)
1422 {
1423         int irq = vector_to_irq(vector);
1424
1425         end_level_ioapic_irq(irq);
1426 }
1427
1428 static void mask_IO_APIC_vector (unsigned int vector)
1429 {
1430         int irq = vector_to_irq(vector);
1431
1432         mask_IO_APIC_irq(irq);
1433 }
1434
1435 static void unmask_IO_APIC_vector (unsigned int vector)
1436 {
1437         int irq = vector_to_irq(vector);
1438
1439         unmask_IO_APIC_irq(irq);
1440 }
1441
1442 static void set_ioapic_affinity_vector (unsigned int vector,
1443                                         cpumask_t cpu_mask)
1444 {
1445         int irq = vector_to_irq(vector);
1446
1447         set_ioapic_affinity_irq(irq, cpu_mask);
1448 }
1449 #endif
1450
1451 /*
1452  * Level and edge triggered IO-APIC interrupts need different handling,
1453  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1454  * handled with the level-triggered descriptor, but that one has slightly
1455  * more overhead. Level-triggered interrupts cannot be handled with the
1456  * edge-triggered handler, without risking IRQ storms and other ugly
1457  * races.
1458  */
1459
1460 static struct hw_interrupt_type ioapic_edge_type = {
1461         .typename = "IO-APIC-edge",
1462         .startup        = startup_edge_ioapic,
1463         .shutdown       = shutdown_edge_ioapic,
1464         .enable         = enable_edge_ioapic,
1465         .disable        = disable_edge_ioapic,
1466         .ack            = ack_edge_ioapic,
1467         .end            = end_edge_ioapic,
1468         .set_affinity = set_ioapic_affinity,
1469 };
1470
1471 static struct hw_interrupt_type ioapic_level_type = {
1472         .typename = "IO-APIC-level",
1473         .startup        = startup_level_ioapic,
1474         .shutdown       = shutdown_level_ioapic,
1475         .enable         = enable_level_ioapic,
1476         .disable        = disable_level_ioapic,
1477         .ack            = mask_and_ack_level_ioapic,
1478         .end            = end_level_ioapic,
1479         .set_affinity = set_ioapic_affinity,
1480 };
1481
1482 static inline void init_IO_APIC_traps(void)
1483 {
1484         int irq;
1485
1486         /*
1487          * NOTE! The local APIC isn't very good at handling
1488          * multiple interrupts at the same interrupt level.
1489          * As the interrupt level is determined by taking the
1490          * vector number and shifting that right by 4, we
1491          * want to spread these out a bit so that they don't
1492          * all fall in the same interrupt level.
1493          *
1494          * Also, we've got to be careful not to trash gate
1495          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1496          */
1497         for (irq = 0; irq < NR_IRQS ; irq++) {
1498                 int tmp = irq;
1499                 if (use_pci_vector()) {
1500                         if (!platform_legacy_irq(tmp))
1501                                 if ((tmp = vector_to_irq(tmp)) == -1)
1502                                         continue;
1503                 }
1504                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1505                         /*
1506                          * Hmm.. We don't have an entry for this,
1507                          * so default to an old-fashioned 8259
1508                          * interrupt if we can..
1509                          */
1510                         if (irq < 16)
1511                                 make_8259A_irq(irq);
1512                         else
1513                                 /* Strange. Oh, well.. */
1514                                 irq_desc[irq].handler = &no_irq_type;
1515                 }
1516         }
1517 }
1518
1519 static void enable_lapic_irq (unsigned int irq)
1520 {
1521         unsigned long v;
1522
1523         v = apic_read(APIC_LVT0);
1524         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1525 }
1526
1527 static void disable_lapic_irq (unsigned int irq)
1528 {
1529         unsigned long v;
1530
1531         v = apic_read(APIC_LVT0);
1532         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1533 }
1534
1535 static void ack_lapic_irq (unsigned int irq)
1536 {
1537         ack_APIC_irq();
1538 }
1539
1540 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1541
1542 static struct hw_interrupt_type lapic_irq_type = {
1543         .typename = "local-APIC-edge",
1544         .startup = NULL, /* startup_irq() not used for IRQ0 */
1545         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1546         .enable = enable_lapic_irq,
1547         .disable = disable_lapic_irq,
1548         .ack = ack_lapic_irq,
1549         .end = end_lapic_irq,
1550 };
1551
1552 static void setup_nmi (void)
1553 {
1554         /*
1555          * Dirty trick to enable the NMI watchdog ...
1556          * We put the 8259A master into AEOI mode and
1557          * unmask on all local APICs LVT0 as NMI.
1558          *
1559          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1560          * is from Maciej W. Rozycki - so we do not have to EOI from
1561          * the NMI handler or the timer interrupt.
1562          */
1563         printk(KERN_INFO "activating NMI Watchdog ...");
1564
1565         enable_NMI_through_LVT0(NULL);
1566
1567         printk(" done.\n");
1568 }
1569
1570 /*
1571  * This looks a bit hackish but it's about the only one way of sending
1572  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1573  * not support the ExtINT mode, unfortunately.  We need to send these
1574  * cycles as some i82489DX-based boards have glue logic that keeps the
1575  * 8259A interrupt line asserted until INTA.  --macro
1576  */
1577 static inline void unlock_ExtINT_logic(void)
1578 {
1579         int pin, i;
1580         struct IO_APIC_route_entry entry0, entry1;
1581         unsigned char save_control, save_freq_select;
1582         unsigned long flags;
1583
1584         pin = find_isa_irq_pin(8, mp_INT);
1585         if (pin == -1)
1586                 return;
1587
1588         spin_lock_irqsave(&ioapic_lock, flags);
1589         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1590         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1591         spin_unlock_irqrestore(&ioapic_lock, flags);
1592         clear_IO_APIC_pin(0, pin);
1593
1594         memset(&entry1, 0, sizeof(entry1));
1595
1596         entry1.dest_mode = 0;                   /* physical delivery */
1597         entry1.mask = 0;                        /* unmask IRQ now */
1598         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1599         entry1.delivery_mode = dest_ExtINT;
1600         entry1.polarity = entry0.polarity;
1601         entry1.trigger = 0;
1602         entry1.vector = 0;
1603
1604         spin_lock_irqsave(&ioapic_lock, flags);
1605         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1606         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1607         spin_unlock_irqrestore(&ioapic_lock, flags);
1608
1609         save_control = CMOS_READ(RTC_CONTROL);
1610         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1611         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1612                    RTC_FREQ_SELECT);
1613         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1614
1615         i = 100;
1616         while (i-- > 0) {
1617                 mdelay(10);
1618                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1619                         i -= 10;
1620         }
1621
1622         CMOS_WRITE(save_control, RTC_CONTROL);
1623         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1624         clear_IO_APIC_pin(0, pin);
1625
1626         spin_lock_irqsave(&ioapic_lock, flags);
1627         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1628         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1629         spin_unlock_irqrestore(&ioapic_lock, flags);
1630 }
1631
1632 /*
1633  * This code may look a bit paranoid, but it's supposed to cooperate with
1634  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1635  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1636  * fanatically on his truly buggy board.
1637  */
1638 static inline void check_timer(void)
1639 {
1640         int pin1, pin2;
1641         int vector;
1642
1643         /*
1644          * get/set the timer IRQ vector:
1645          */
1646         disable_8259A_irq(0);
1647         vector = assign_irq_vector(0);
1648         set_intr_gate(vector, interrupt[0]);
1649
1650         /*
1651          * Subtle, code in do_timer_interrupt() expects an AEOI
1652          * mode for the 8259A whenever interrupts are routed
1653          * through I/O APICs.  Also IRQ0 has to be enabled in
1654          * the 8259A which implies the virtual wire has to be
1655          * disabled in the local APIC.
1656          */
1657         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1658         init_8259A(1);
1659         enable_8259A_irq(0);
1660
1661         pin1 = find_isa_irq_pin(0, mp_INT);
1662         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1663
1664         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1665
1666         if (pin1 != -1) {
1667                 /*
1668                  * Ok, does IRQ0 through the IOAPIC work?
1669                  */
1670                 unmask_IO_APIC_irq(0);
1671                 if (timer_irq_works()) {
1672                         nmi_watchdog_default();
1673                         if (nmi_watchdog == NMI_IO_APIC) {
1674                                 disable_8259A_irq(0);
1675                                 setup_nmi();
1676                                 enable_8259A_irq(0);
1677                                 check_nmi_watchdog();
1678                         }
1679                         return;
1680                 }
1681                 clear_IO_APIC_pin(0, pin1);
1682                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1683         }
1684
1685         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1686         if (pin2 != -1) {
1687                 printk("\n..... (found pin %d) ...", pin2);
1688                 /*
1689                  * legacy devices should be connected to IO APIC #0
1690                  */
1691                 setup_ExtINT_IRQ0_pin(pin2, vector);
1692                 if (timer_irq_works()) {
1693                         printk("works.\n");
1694                         nmi_watchdog_default();
1695                         if (nmi_watchdog == NMI_IO_APIC) {
1696                                 setup_nmi();
1697                                 check_nmi_watchdog();
1698                         }
1699                         return;
1700                 }
1701                 /*
1702                  * Cleanup, just in case ...
1703                  */
1704                 clear_IO_APIC_pin(0, pin2);
1705         }
1706         printk(" failed.\n");
1707
1708         if (nmi_watchdog) {
1709                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1710                 nmi_watchdog = 0;
1711         }
1712
1713         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1714
1715         disable_8259A_irq(0);
1716         irq_desc[0].handler = &lapic_irq_type;
1717         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1718         enable_8259A_irq(0);
1719
1720         if (timer_irq_works()) {
1721                 printk(" works.\n");
1722                 return;
1723         }
1724         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1725         printk(" failed.\n");
1726
1727         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1728
1729         init_8259A(0);
1730         make_8259A_irq(0);
1731         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1732
1733         unlock_ExtINT_logic();
1734
1735         if (timer_irq_works()) {
1736                 printk(" works.\n");
1737                 return;
1738         }
1739         printk(" failed :(.\n");
1740         panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1741 }
1742
1743 /*
1744  *
1745  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1746  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1747  *   Linux doesn't really care, as it's not actually used
1748  *   for any interrupt handling anyway.
1749  */
1750 #define PIC_IRQS        (1<<2)
1751
1752 void __init setup_IO_APIC(void)
1753 {
1754         enable_IO_APIC();
1755
1756         if (acpi_ioapic)
1757                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1758         else
1759                 io_apic_irqs = ~PIC_IRQS;
1760
1761         printk("ENABLING IO-APIC IRQs\n");
1762
1763         /*
1764          * Set up the IO-APIC IRQ routing table.
1765          */
1766         if (!acpi_ioapic)
1767                 setup_ioapic_ids_from_mpc();
1768         sync_Arb_IDs();
1769         setup_IO_APIC_irqs();
1770         init_IO_APIC_traps();
1771         check_timer();
1772         if (!acpi_ioapic)
1773                 print_IO_APIC();
1774 }
1775
1776 /* --------------------------------------------------------------------------
1777                           ACPI-based IOAPIC Configuration
1778    -------------------------------------------------------------------------- */
1779
1780 #ifdef CONFIG_ACPI_BOOT
1781
1782 #define IO_APIC_MAX_ID          15
1783
1784 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1785 {
1786         union IO_APIC_reg_00 reg_00;
1787         static physid_mask_t apic_id_map;
1788         unsigned long flags;
1789         int i = 0;
1790
1791         /*
1792          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1793          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1794          * supports up to 16 on one shared APIC bus.
1795          *
1796          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1797          *      advantage of new APIC bus architecture.
1798          */
1799
1800         if (physids_empty(apic_id_map))
1801                 apic_id_map = phys_cpu_present_map;
1802
1803         spin_lock_irqsave(&ioapic_lock, flags);
1804         reg_00.raw = io_apic_read(ioapic, 0);
1805         spin_unlock_irqrestore(&ioapic_lock, flags);
1806
1807         if (apic_id >= IO_APIC_MAX_ID) {
1808                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1809                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1810                 apic_id = reg_00.bits.ID;
1811         }
1812
1813         /*
1814          * Every APIC in a system must have a unique ID or we get lots of nice
1815          * 'stuck on smp_invalidate_needed IPI wait' messages.
1816          */
1817         if (physid_isset(apic_id, apic_id_map)) {
1818
1819                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1820                         if (!physid_isset(i, apic_id_map))
1821                                 break;
1822                 }
1823
1824                 if (i == IO_APIC_MAX_ID)
1825                         panic("Max apic_id exceeded!\n");
1826
1827                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1828                         "trying %d\n", ioapic, apic_id, i);
1829
1830                 apic_id = i;
1831         }
1832
1833         physid_set(apic_id, apic_id_map);
1834
1835         if (reg_00.bits.ID != apic_id) {
1836                 reg_00.bits.ID = apic_id;
1837
1838                 spin_lock_irqsave(&ioapic_lock, flags);
1839                 io_apic_write(ioapic, 0, reg_00.raw);
1840                 reg_00.raw = io_apic_read(ioapic, 0);
1841                 spin_unlock_irqrestore(&ioapic_lock, flags);
1842
1843                 /* Sanity check */
1844                 if (reg_00.bits.ID != apic_id)
1845                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1846         }
1847
1848         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1849
1850         return apic_id;
1851 }
1852
1853
1854 int __init io_apic_get_version (int ioapic)
1855 {
1856         union IO_APIC_reg_01    reg_01;
1857         unsigned long flags;
1858
1859         spin_lock_irqsave(&ioapic_lock, flags);
1860         reg_01.raw = io_apic_read(ioapic, 1);
1861         spin_unlock_irqrestore(&ioapic_lock, flags);
1862
1863         return reg_01.bits.version;
1864 }
1865
1866
1867 int __init io_apic_get_redir_entries (int ioapic)
1868 {
1869         union IO_APIC_reg_01    reg_01;
1870         unsigned long flags;
1871
1872         spin_lock_irqsave(&ioapic_lock, flags);
1873         reg_01.raw = io_apic_read(ioapic, 1);
1874         spin_unlock_irqrestore(&ioapic_lock, flags);
1875
1876         return reg_01.bits.entries;
1877 }
1878
1879
1880 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1881 {
1882         struct IO_APIC_route_entry entry;
1883         unsigned long flags;
1884
1885         if (!IO_APIC_IRQ(irq)) {
1886                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1887                         ioapic);
1888                 return -EINVAL;
1889         }
1890
1891         /*
1892          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1893          * Note that we mask (disable) IRQs now -- these get enabled when the
1894          * corresponding device driver registers for this IRQ.
1895          */
1896
1897         memset(&entry,0,sizeof(entry));
1898
1899         entry.delivery_mode = dest_LowestPrio;
1900         entry.dest_mode = INT_DELIVERY_MODE;
1901         entry.dest.logical.logical_dest = TARGET_CPUS;
1902         entry.trigger = edge_level;
1903         entry.polarity = active_high_low;
1904         entry.mask = 1;                                  /* Disabled (masked) */
1905
1906         /*
1907          * IRQs < 16 are already in the irq_2_pin[] map
1908          */
1909         if (irq >= 16)
1910                 add_pin_to_irq(irq, ioapic, pin);
1911
1912         entry.vector = assign_irq_vector(irq);
1913
1914         printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1915                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1916                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1917                edge_level, active_high_low);
1918
1919         if (use_pci_vector() && !platform_legacy_irq(irq))
1920                 irq = IO_APIC_VECTOR(irq);
1921         if (edge_level) {
1922                 irq_desc[irq].handler = &ioapic_level_type;
1923         } else {
1924                 irq_desc[irq].handler = &ioapic_edge_type;
1925         }
1926
1927         set_intr_gate(entry.vector, interrupt[irq]);
1928
1929         if (!ioapic && (irq < 16))
1930                 disable_8259A_irq(irq);
1931
1932         spin_lock_irqsave(&ioapic_lock, flags);
1933         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1934         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1935         spin_unlock_irqrestore(&ioapic_lock, flags);
1936
1937         return 0;
1938 }
1939
1940 #endif /*CONFIG_ACPI_BOOT*/
1941
1942 #ifndef CONFIG_SMP
1943 void send_IPI_self(int vector)
1944 {
1945         unsigned int cfg;
1946
1947        /*
1948         * Wait for idle.
1949         */
1950         apic_wait_icr_idle();
1951         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1952
1953         /*
1954          * Send the IPI. The write to APIC_ICR fires this off.
1955          */
1956         apic_write_around(APIC_ICR, cfg);
1957 }
1958 #endif