arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/proto.h>
  39
  40 #define __apicdebuginit  __init
  41
  42 int sis_apic_bug; /* not actually supported, dummy for compile */
  43
  44 #undef APIC_LOCKUP_DEBUG
  45
  46 #define APIC_LOCKUP_DEBUG
  47
  48 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  49
  50 /*
  51  * # of IRQ routing registers
  52  */
  53 int nr_ioapic_registers[MAX_IO_APICS];
  54
  55 /*
  56  * Rough estimation of how many shared IRQs there are, can
  57  * be changed anytime.
  58  */
  59 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  60 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  61
  62 /*
  63  * This is performance-critical, we want to do it O(1)
  64  *
  65  * the indexing order of this array favors 1:1 mappings
  66  * between pins and IRQs.
  67  */
  68
  69 static struct irq_pin_list {
  70         short apic, pin, next;
  71 } irq_2_pin[PIN_MAP_SIZE];
  72
  73 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  74 #ifdef CONFIG_PCI_MSI
  75 #define vector_to_irq(vector)   \
  76         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  77 #else
  78 #define vector_to_irq(vector)   (vector)
  79 #endif
  80
  81 /*
  82  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  83  * shared ISA-space IRQs, so we have to support them. We are super
  84  * fast in the common case, and fast for shared ISA-space IRQs.
  85  */
  86 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  87 {
  88         static int first_free_entry = NR_IRQS;
  89         struct irq_pin_list *entry = irq_2_pin + irq;
  90
  91         while (entry->next)
  92                 entry = irq_2_pin + entry->next;
  93
  94         if (entry->pin != -1) {
  95                 entry->next = first_free_entry;
  96                 entry = irq_2_pin + entry->next;
  97                 if (++first_free_entry >= PIN_MAP_SIZE)
  98                         panic("io_apic.c: whoops");
  99         }
 100         entry->apic = apic;
 101         entry->pin = pin;
 102 }
 103
 104 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 105                                                                         \
 106 {                                                                       \
 107         int pin;                                                        \
 108         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 109                                                                         \
 110         for (;;) {                                                      \
 111                 unsigned int reg;                                       \
 112                 pin = entry->pin;                                       \
 113                 if (pin == -1)                                          \
 114                         break;                                          \
 115                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 116                 reg ACTION;                                             \
 117                 io_apic_modify(entry->apic, reg);                       \
 118                 if (!entry->next)                                       \
 119                         break;                                          \
 120                 entry = irq_2_pin + entry->next;                        \
 121         }                                                               \
 122         FINAL;                                                          \
 123 }
 124
 125 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 126                                                                         \
 127         static void name##_IO_APIC_irq (unsigned int irq)               \
 128         __DO_ACTION(R, ACTION, FINAL)
 129
 130 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 131                                                 /* mask = 1 */
 132 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 133                                                 /* mask = 0 */
 134 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
 135                                                 /* mask = 1, trigger = 0 */
 136 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
 137                                                 /* mask = 0, trigger = 1 */
 138
 139 static void mask_IO_APIC_irq (unsigned int irq)
 140 {
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&ioapic_lock, flags);
 144         __mask_IO_APIC_irq(irq);
 145         spin_unlock_irqrestore(&ioapic_lock, flags);
 146 }
 147
 148 static void unmask_IO_APIC_irq (unsigned int irq)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&ioapic_lock, flags);
 153         __unmask_IO_APIC_irq(irq);
 154         spin_unlock_irqrestore(&ioapic_lock, flags);
 155 }
 156
 157 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 158 {
 159         struct IO_APIC_route_entry entry;
 160         unsigned long flags;
 161
 162         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 163         spin_lock_irqsave(&ioapic_lock, flags);
 164         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 165         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 166         spin_unlock_irqrestore(&ioapic_lock, flags);
 167         if (entry.delivery_mode == dest_SMI)
 168                 return;
 169         /*
 170          * Disable it in the IO-APIC irq-routing table:
 171          */
 172         memset(&entry, 0, sizeof(entry));
 173         entry.mask = 1;
 174         spin_lock_irqsave(&ioapic_lock, flags);
 175         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 176         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 177         spin_unlock_irqrestore(&ioapic_lock, flags);
 178 }
 179
 180 static void clear_IO_APIC (void)
 181 {
 182         int apic, pin;
 183
 184         for (apic = 0; apic < nr_ioapics; apic++)
 185                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 186                         clear_IO_APIC_pin(apic, pin);
 187 }
 188
 189 /*
 190  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 191  * specific CPU-side IRQs.
 192  */
 193
 194 #define MAX_PIRQS 8
 195 int pirq_entries [MAX_PIRQS];
 196 int pirqs_enabled;
 197 int skip_ioapic_setup;
 198 int ioapic_force;
 199
 200 /* dummy parsing: see setup.c */
 201
 202 static int __init disable_ioapic_setup(char *str)
 203 {
 204         skip_ioapic_setup = 1;
 205         return 1;
 206 }
 207
 208 static int __init enable_ioapic_setup(char *str)
 209 {
 210         ioapic_force = 1;
 211         skip_ioapic_setup = 0;
 212         return 1;
 213 }
 214
 215 __setup("noapic", disable_ioapic_setup);
 216 __setup("apic", enable_ioapic_setup);
 217
 218 #include <asm/pci-direct.h>
 219 #include <linux/pci_ids.h>
 220 #include <linux/pci.h>
 221
 222 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 223    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 224    Use pci direct infrastructure because this runs before the PCI subsystem.
 225
 226    Can be overwritten with "apic"
 227
 228    And another hack to disable the IOMMU on VIA chipsets.
 229
 230    Kludge-O-Rama. */
 231 void __init check_ioapic(void)
 232 {
 233         int num,slot,func;
 234         if (ioapic_force)
 235                 return;
 236
 237         /* Poor man's PCI discovery */
 238         for (num = 0; num < 32; num++) {
 239                 for (slot = 0; slot < 32; slot++) {
 240                         for (func = 0; func < 8; func++) {
 241                                 u32 class;
 242                                 u32 vendor;
 243                                 u8 type;
 244                                 class = read_pci_config(num,slot,func,
 245                                                         PCI_CLASS_REVISION);
 246                                 if (class == 0xffffffff)
 247                                         break;
 248
 249                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 250                                         continue;
 251
 252                                 vendor = read_pci_config(num, slot, func,
 253                                                          PCI_VENDOR_ID);
 254                                 vendor &= 0xffff;
 255                                 switch (vendor) {
 256                                 case PCI_VENDOR_ID_VIA:
 257 #ifdef CONFIG_GART_IOMMU
 258                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 259                                              force_iommu) &&
 260                                             !iommu_aperture_allowed) {
 261                                                 printk(KERN_INFO
 262     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 263                                                 iommu_aperture_disabled = 1;
 264                                         }
 265 #endif
 266                                         return;
 267                                 case PCI_VENDOR_ID_NVIDIA:
 268 #ifdef CONFIG_ACPI
 269                                         /* All timer overrides on Nvidia
 270                                            seem to be wrong. Skip them. */
 271                                         acpi_skip_timer_override = 1;
 272                                         printk(KERN_INFO
 273              "Nvidia board detected. Ignoring ACPI timer override.\n");
 274 #endif
 275                                         /* RED-PEN skip them on mptables too? */
 276                                         return;
 277                                 }
 278
 279                                 /* No multi-function device? */
 280                                 type = read_pci_config_byte(num,slot,func,
 281                                                             PCI_HEADER_TYPE);
 282                                 if (!(type & 0x80))
 283                                         break;
 284                         }
 285                 }
 286         }
 287 }
 288
 289 static int __init ioapic_pirq_setup(char *str)
 290 {
 291         int i, max;
 292         int ints[MAX_PIRQS+1];
 293
 294         get_options(str, ARRAY_SIZE(ints), ints);
 295
 296         for (i = 0; i < MAX_PIRQS; i++)
 297                 pirq_entries[i] = -1;
 298
 299         pirqs_enabled = 1;
 300         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 301         max = MAX_PIRQS;
 302         if (ints[0] < MAX_PIRQS)
 303                 max = ints[0];
 304
 305         for (i = 0; i < max; i++) {
 306                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 307                 /*
 308                  * PIRQs are mapped upside down, usually.
 309                  */
 310                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 311         }
 312         return 1;
 313 }
 314
 315 __setup("pirq=", ioapic_pirq_setup);
 316
 317 /*
 318  * Find the IRQ entry number of a certain pin.
 319  */
 320 static int __init find_irq_entry(int apic, int pin, int type)
 321 {
 322         int i;
 323
 324         for (i = 0; i < mp_irq_entries; i++)
 325                 if (mp_irqs[i].mpc_irqtype == type &&
 326                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 327                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 328                     mp_irqs[i].mpc_dstirq == pin)
 329                         return i;
 330
 331         return -1;
 332 }
 333
 334 /*
 335  * Find the pin to which IRQ[irq] (ISA) is connected
 336  */
 337 static int find_isa_irq_pin(int irq, int type)
 338 {
 339         int i;
 340
 341         for (i = 0; i < mp_irq_entries; i++) {
 342                 int lbus = mp_irqs[i].mpc_srcbus;
 343
 344                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 345                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 346                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 347                     (mp_irqs[i].mpc_irqtype == type) &&
 348                     (mp_irqs[i].mpc_srcbusirq == irq))
 349
 350                         return mp_irqs[i].mpc_dstirq;
 351         }
 352         return -1;
 353 }
 354
 355 /*
 356  * Find a specific PCI IRQ entry.
 357  * Not an __init, possibly needed by modules
 358  */
 359 static int pin_2_irq(int idx, int apic, int pin);
 360
 361 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 362 {
 363         int apic, i, best_guess = -1;
 364
 365         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 366                 bus, slot, pin);
 367         if (mp_bus_id_to_pci_bus[bus] == -1) {
 368                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 369                 return -1;
 370         }
 371         for (i = 0; i < mp_irq_entries; i++) {
 372                 int lbus = mp_irqs[i].mpc_srcbus;
 373
 374                 for (apic = 0; apic < nr_ioapics; apic++)
 375                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 376                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 377                                 break;
 378
 379                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 380                     !mp_irqs[i].mpc_irqtype &&
 381                     (bus == lbus) &&
 382                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 383                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 384
 385                         if (!(apic || IO_APIC_IRQ(irq)))
 386                                 continue;
 387
 388                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 389                                 return irq;
 390                         /*
 391                          * Use the first all-but-pin matching entry as a
 392                          * best-guess fuzzy result for broken mptables.
 393                          */
 394                         if (best_guess < 0)
 395                                 best_guess = irq;
 396                 }
 397         }
 398         return best_guess;
 399 }
 400
 401 /*
 402  * EISA Edge/Level control register, ELCR
 403  */
 404 static int __init EISA_ELCR(unsigned int irq)
 405 {
 406         if (irq < 16) {
 407                 unsigned int port = 0x4d0 + (irq >> 3);
 408                 return (inb(port) >> (irq & 7)) & 1;
 409         }
 410         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 411         return 0;
 412 }
 413
 414 /* EISA interrupts are always polarity zero and can be edge or level
 415  * trigger depending on the ELCR value.  If an interrupt is listed as
 416  * EISA conforming in the MP table, that means its trigger type must
 417  * be read in from the ELCR */
 418
 419 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 420 #define default_EISA_polarity(idx)      (0)
 421
 422 /* ISA interrupts are always polarity zero edge triggered,
 423  * when listed as conforming in the MP table. */
 424
 425 #define default_ISA_trigger(idx)        (0)
 426 #define default_ISA_polarity(idx)       (0)
 427
 428 /* PCI interrupts are always polarity one level triggered,
 429  * when listed as conforming in the MP table. */
 430
 431 #define default_PCI_trigger(idx)        (1)
 432 #define default_PCI_polarity(idx)       (1)
 433
 434 /* MCA interrupts are always polarity zero level triggered,
 435  * when listed as conforming in the MP table. */
 436
 437 #define default_MCA_trigger(idx)        (1)
 438 #define default_MCA_polarity(idx)       (0)
 439
 440 static int __init MPBIOS_polarity(int idx)
 441 {
 442         int bus = mp_irqs[idx].mpc_srcbus;
 443         int polarity;
 444
 445         /*
 446          * Determine IRQ line polarity (high active or low active):
 447          */
 448         switch (mp_irqs[idx].mpc_irqflag & 3)
 449         {
 450                 case 0: /* conforms, ie. bus-type dependent polarity */
 451                 {
 452                         switch (mp_bus_id_to_type[bus])
 453                         {
 454                                 case MP_BUS_ISA: /* ISA pin */
 455                                 {
 456                                         polarity = default_ISA_polarity(idx);
 457                                         break;
 458                                 }
 459                                 case MP_BUS_EISA: /* EISA pin */
 460                                 {
 461                                         polarity = default_EISA_polarity(idx);
 462                                         break;
 463                                 }
 464                                 case MP_BUS_PCI: /* PCI pin */
 465                                 {
 466                                         polarity = default_PCI_polarity(idx);
 467                                         break;
 468                                 }
 469                                 case MP_BUS_MCA: /* MCA pin */
 470                                 {
 471                                         polarity = default_MCA_polarity(idx);
 472                                         break;
 473                                 }
 474                                 default:
 475                                 {
 476                                         printk(KERN_WARNING "broken BIOS!!\n");
 477                                         polarity = 1;
 478                                         break;
 479                                 }
 480                         }
 481                         break;
 482                 }
 483                 case 1: /* high active */
 484                 {
 485                         polarity = 0;
 486                         break;
 487                 }
 488                 case 2: /* reserved */
 489                 {
 490                         printk(KERN_WARNING "broken BIOS!!\n");
 491                         polarity = 1;
 492                         break;
 493                 }
 494                 case 3: /* low active */
 495                 {
 496                         polarity = 1;
 497                         break;
 498                 }
 499                 default: /* invalid */
 500                 {
 501                         printk(KERN_WARNING "broken BIOS!!\n");
 502                         polarity = 1;
 503                         break;
 504                 }
 505         }
 506         return polarity;
 507 }
 508
 509 static int __init MPBIOS_trigger(int idx)
 510 {
 511         int bus = mp_irqs[idx].mpc_srcbus;
 512         int trigger;
 513
 514         /*
 515          * Determine IRQ trigger mode (edge or level sensitive):
 516          */
 517         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 518         {
 519                 case 0: /* conforms, ie. bus-type dependent */
 520                 {
 521                         switch (mp_bus_id_to_type[bus])
 522                         {
 523                                 case MP_BUS_ISA: /* ISA pin */
 524                                 {
 525                                         trigger = default_ISA_trigger(idx);
 526                                         break;
 527                                 }
 528                                 case MP_BUS_EISA: /* EISA pin */
 529                                 {
 530                                         trigger = default_EISA_trigger(idx);
 531                                         break;
 532                                 }
 533                                 case MP_BUS_PCI: /* PCI pin */
 534                                 {
 535                                         trigger = default_PCI_trigger(idx);
 536                                         break;
 537                                 }
 538                                 case MP_BUS_MCA: /* MCA pin */
 539                                 {
 540                                         trigger = default_MCA_trigger(idx);
 541                                         break;
 542                                 }
 543                                 default:
 544                                 {
 545                                         printk(KERN_WARNING "broken BIOS!!\n");
 546                                         trigger = 1;
 547                                         break;
 548                                 }
 549                         }
 550                         break;
 551                 }
 552                 case 1: /* edge */
 553                 {
 554                         trigger = 0;
 555                         break;
 556                 }
 557                 case 2: /* reserved */
 558                 {
 559                         printk(KERN_WARNING "broken BIOS!!\n");
 560                         trigger = 1;
 561                         break;
 562                 }
 563                 case 3: /* level */
 564                 {
 565                         trigger = 1;
 566                         break;
 567                 }
 568                 default: /* invalid */
 569                 {
 570                         printk(KERN_WARNING "broken BIOS!!\n");
 571                         trigger = 0;
 572                         break;
 573                 }
 574         }
 575         return trigger;
 576 }
 577
 578 static inline int irq_polarity(int idx)
 579 {
 580         return MPBIOS_polarity(idx);
 581 }
 582
 583 static inline int irq_trigger(int idx)
 584 {
 585         return MPBIOS_trigger(idx);
 586 }
 587
 588 static int pin_2_irq(int idx, int apic, int pin)
 589 {
 590         int irq, i;
 591         int bus = mp_irqs[idx].mpc_srcbus;
 592
 593         /*
 594          * Debugging check, we are in big trouble if this message pops up!
 595          */
 596         if (mp_irqs[idx].mpc_dstirq != pin)
 597                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 598
 599         switch (mp_bus_id_to_type[bus])
 600         {
 601                 case MP_BUS_ISA: /* ISA pin */
 602                 case MP_BUS_EISA:
 603                 case MP_BUS_MCA:
 604                 {
 605                         irq = mp_irqs[idx].mpc_srcbusirq;
 606                         break;
 607                 }
 608                 case MP_BUS_PCI: /* PCI pin */
 609                 {
 610                         /*
 611                          * PCI IRQs are mapped in order
 612                          */
 613                         i = irq = 0;
 614                         while (i < apic)
 615                                 irq += nr_ioapic_registers[i++];
 616                         irq += pin;
 617                         break;
 618                 }
 619                 default:
 620                 {
 621                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 622                         irq = 0;
 623                         break;
 624                 }
 625         }
 626
 627         /*
 628          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 629          */
 630         if ((pin >= 16) && (pin <= 23)) {
 631                 if (pirq_entries[pin-16] != -1) {
 632                         if (!pirq_entries[pin-16]) {
 633                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 634                         } else {
 635                                 irq = pirq_entries[pin-16];
 636                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 637                                                 pin-16, irq);
 638                         }
 639                 }
 640         }
 641         return irq;
 642 }
 643
 644 static inline int IO_APIC_irq_trigger(int irq)
 645 {
 646         int apic, idx, pin;
 647
 648         for (apic = 0; apic < nr_ioapics; apic++) {
 649                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 650                         idx = find_irq_entry(apic,pin,mp_INT);
 651                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 652                                 return irq_trigger(idx);
 653                 }
 654         }
 655         /*
 656          * nonexistent IRQs are edge default
 657          */
 658         return 0;
 659 }
 660
 661 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 662 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 663
 664 #ifdef CONFIG_PCI_MSI
 665 int assign_irq_vector(int irq)
 666 #else
 667 int __init assign_irq_vector(int irq)
 668 #endif
 669 {
 670         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 671
 672         BUG_ON(irq >= NR_IRQ_VECTORS);
 673         if (IO_APIC_VECTOR(irq) > 0)
 674                 return IO_APIC_VECTOR(irq);
 675 next:
 676         current_vector += 8;
 677         if (current_vector == IA32_SYSCALL_VECTOR)
 678                 goto next;
 679
 680         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 681                 offset++;
 682                 if (!(offset%8))
 683                         return -ENOSPC;
 684                 current_vector = FIRST_DEVICE_VECTOR + offset;
 685         }
 686
 687         vector_irq[current_vector] = irq;
 688         if (irq != AUTO_ASSIGN)
 689                 IO_APIC_VECTOR(irq) = current_vector;
 690
 691         return current_vector;
 692 }
 693
 694 extern void (*interrupt[NR_IRQS])(void);
 695 static struct hw_interrupt_type ioapic_level_type;
 696 static struct hw_interrupt_type ioapic_edge_type;
 697
 698 #define IOAPIC_AUTO     -1
 699 #define IOAPIC_EDGE     0
 700 #define IOAPIC_LEVEL    1
 701
 702 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 703 {
 704         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 705                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 706                                 trigger == IOAPIC_LEVEL)
 707                         irq_desc[vector].handler = &ioapic_level_type;
 708                 else
 709                         irq_desc[vector].handler = &ioapic_edge_type;
 710                 set_intr_gate(vector, interrupt[vector]);
 711         } else  {
 712                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 713                                 trigger == IOAPIC_LEVEL)
 714                         irq_desc[irq].handler = &ioapic_level_type;
 715                 else
 716                         irq_desc[irq].handler = &ioapic_edge_type;
 717                 set_intr_gate(vector, interrupt[irq]);
 718         }
 719 }
 720
 721 void __init setup_IO_APIC_irqs(void)
 722 {
 723         struct IO_APIC_route_entry entry;
 724         int apic, pin, idx, irq, first_notcon = 1, vector;
 725         unsigned long flags;
 726
 727         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 728
 729         for (apic = 0; apic < nr_ioapics; apic++) {
 730         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 731
 732                 /*
 733                  * add it to the IO-APIC irq-routing table:
 734                  */
 735                 memset(&entry,0,sizeof(entry));
 736
 737                 entry.delivery_mode = dest_LowestPrio;
 738                 entry.dest_mode = INT_DELIVERY_MODE;
 739                 entry.mask = 0;                         /* enable IRQ */
 740                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 741
 742                 idx = find_irq_entry(apic,pin,mp_INT);
 743                 if (idx == -1) {
 744                         if (first_notcon) {
 745                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 746                                 first_notcon = 0;
 747                         } else
 748                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 749                         continue;
 750                 }
 751
 752                 entry.trigger = irq_trigger(idx);
 753                 entry.polarity = irq_polarity(idx);
 754
 755                 if (irq_trigger(idx)) {
 756                         entry.trigger = 1;
 757                         entry.mask = 1;
 758                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 759                 }
 760
 761                 irq = pin_2_irq(idx, apic, pin);
 762                 add_pin_to_irq(irq, apic, pin);
 763
 764                 if (!apic && !IO_APIC_IRQ(irq))
 765                         continue;
 766
 767                 if (IO_APIC_IRQ(irq)) {
 768                         vector = assign_irq_vector(irq);
 769                         entry.vector = vector;
 770
 771                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 772                         if (!apic && (irq < 16))
 773                                 disable_8259A_irq(irq);
 774                 }
 775                 spin_lock_irqsave(&ioapic_lock, flags);
 776                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 777                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 778                 spin_unlock_irqrestore(&ioapic_lock, flags);
 779         }
 780         }
 781
 782         if (!first_notcon)
 783                 apic_printk(APIC_VERBOSE," not connected.\n");
 784 }
 785
 786 /*
 787  * Set up the 8259A-master output pin as broadcast to all
 788  * CPUs.
 789  */
 790 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 791 {
 792         struct IO_APIC_route_entry entry;
 793         unsigned long flags;
 794
 795         memset(&entry,0,sizeof(entry));
 796
 797         disable_8259A_irq(0);
 798
 799         /* mask LVT0 */
 800         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 801
 802         /*
 803          * We use logical delivery to get the timer IRQ
 804          * to the first CPU.
 805          */
 806         entry.dest_mode = INT_DELIVERY_MODE;
 807         entry.mask = 0;                                 /* unmask IRQ now */
 808         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 809         entry.delivery_mode = dest_LowestPrio;
 810         entry.polarity = 0;
 811         entry.trigger = 0;
 812         entry.vector = vector;
 813
 814         /*
 815          * The timer IRQ doesn't have to know that behind the
 816          * scene we have a 8259A-master in AEOI mode ...
 817          */
 818         irq_desc[0].handler = &ioapic_edge_type;
 819
 820         /*
 821          * Add it to the IO-APIC irq-routing table:
 822          */
 823         spin_lock_irqsave(&ioapic_lock, flags);
 824         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 825         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 826         spin_unlock_irqrestore(&ioapic_lock, flags);
 827
 828         enable_8259A_irq(0);
 829 }
 830
 831 void __init UNEXPECTED_IO_APIC(void)
 832 {
 833 }
 834
 835 void __apicdebuginit print_IO_APIC(void)
 836 {
 837         int apic, i;
 838         union IO_APIC_reg_00 reg_00;
 839         union IO_APIC_reg_01 reg_01;
 840         union IO_APIC_reg_02 reg_02;
 841         unsigned long flags;
 842
 843         if (apic_verbosity == APIC_QUIET)
 844                 return;
 845
 846         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 847         for (i = 0; i < nr_ioapics; i++)
 848                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 849                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 850
 851         /*
 852          * We are a bit conservative about what we expect.  We have to
 853          * know about every hardware change ASAP.
 854          */
 855         printk(KERN_INFO "testing the IO APIC.......................\n");
 856
 857         for (apic = 0; apic < nr_ioapics; apic++) {
 858
 859         spin_lock_irqsave(&ioapic_lock, flags);
 860         reg_00.raw = io_apic_read(apic, 0);
 861         reg_01.raw = io_apic_read(apic, 1);
 862         if (reg_01.bits.version >= 0x10)
 863                 reg_02.raw = io_apic_read(apic, 2);
 864         spin_unlock_irqrestore(&ioapic_lock, flags);
 865
 866         printk("\n");
 867         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 868         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 869         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 870         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 871                 UNEXPECTED_IO_APIC();
 872
 873         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 874         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 875         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 876                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 877                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 878                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 879                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 880                 (reg_01.bits.entries != 0x2E) &&
 881                 (reg_01.bits.entries != 0x3F) &&
 882                 (reg_01.bits.entries != 0x03)
 883         )
 884                 UNEXPECTED_IO_APIC();
 885
 886         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 887         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 888         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 889                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 890                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 891                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 892                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 893                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 894         )
 895                 UNEXPECTED_IO_APIC();
 896         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 897                 UNEXPECTED_IO_APIC();
 898
 899         if (reg_01.bits.version >= 0x10) {
 900                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 901                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 902                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 903                         UNEXPECTED_IO_APIC();
 904         }
 905
 906         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 907
 908         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 909                           " Stat Dest Deli Vect:   \n");
 910
 911         for (i = 0; i <= reg_01.bits.entries; i++) {
 912                 struct IO_APIC_route_entry entry;
 913
 914                 spin_lock_irqsave(&ioapic_lock, flags);
 915                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 916                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 917                 spin_unlock_irqrestore(&ioapic_lock, flags);
 918
 919                 printk(KERN_DEBUG " %02x %03X %02X  ",
 920                         i,
 921                         entry.dest.logical.logical_dest,
 922                         entry.dest.physical.physical_dest
 923                 );
 924
 925                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 926                         entry.mask,
 927                         entry.trigger,
 928                         entry.irr,
 929                         entry.polarity,
 930                         entry.delivery_status,
 931                         entry.dest_mode,
 932                         entry.delivery_mode,
 933                         entry.vector
 934                 );
 935         }
 936         }
 937         if (use_pci_vector())
 938                 printk(KERN_INFO "Using vector-based indexing\n");
 939         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 940         for (i = 0; i < NR_IRQS; i++) {
 941                 struct irq_pin_list *entry = irq_2_pin + i;
 942                 if (entry->pin < 0)
 943                         continue;
 944                 if (use_pci_vector() && !platform_legacy_irq(i))
 945                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 946                 else
 947                         printk(KERN_DEBUG "IRQ%d ", i);
 948                 for (;;) {
 949                         printk("-> %d:%d", entry->apic, entry->pin);
 950                         if (!entry->next)
 951                                 break;
 952                         entry = irq_2_pin + entry->next;
 953                 }
 954                 printk("\n");
 955         }
 956
 957         printk(KERN_INFO ".................................... done.\n");
 958
 959         return;
 960 }
 961
 962 static __apicdebuginit void print_APIC_bitfield (int base)
 963 {
 964         unsigned int v;
 965         int i, j;
 966
 967         if (apic_verbosity == APIC_QUIET)
 968                 return;
 969
 970         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 971         for (i = 0; i < 8; i++) {
 972                 v = apic_read(base + i*0x10);
 973                 for (j = 0; j < 32; j++) {
 974                         if (v & (1<<j))
 975                                 printk("1");
 976                         else
 977                                 printk("0");
 978                 }
 979                 printk("\n");
 980         }
 981 }
 982
 983 void __apicdebuginit print_local_APIC(void * dummy)
 984 {
 985         unsigned int v, ver, maxlvt;
 986
 987         if (apic_verbosity == APIC_QUIET)
 988                 return;
 989
 990         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 991                 smp_processor_id(), hard_smp_processor_id());
 992         v = apic_read(APIC_ID);
 993         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 994         v = apic_read(APIC_LVR);
 995         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 996         ver = GET_APIC_VERSION(v);
 997         maxlvt = get_maxlvt();
 998
 999         v = apic_read(APIC_TASKPRI);
1000         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1001
1002         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1003                 v = apic_read(APIC_ARBPRI);
1004                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1005                         v & APIC_ARBPRI_MASK);
1006                 v = apic_read(APIC_PROCPRI);
1007                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1008         }
1009
1010         v = apic_read(APIC_EOI);
1011         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1012         v = apic_read(APIC_RRR);
1013         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1014         v = apic_read(APIC_LDR);
1015         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1016         v = apic_read(APIC_DFR);
1017         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1018         v = apic_read(APIC_SPIV);
1019         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1020
1021         printk(KERN_DEBUG "... APIC ISR field:\n");
1022         print_APIC_bitfield(APIC_ISR);
1023         printk(KERN_DEBUG "... APIC TMR field:\n");
1024         print_APIC_bitfield(APIC_TMR);
1025         printk(KERN_DEBUG "... APIC IRR field:\n");
1026         print_APIC_bitfield(APIC_IRR);
1027
1028         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1029                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1030                         apic_write(APIC_ESR, 0);
1031                 v = apic_read(APIC_ESR);
1032                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1033         }
1034
1035         v = apic_read(APIC_ICR);
1036         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1037         v = apic_read(APIC_ICR2);
1038         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1039
1040         v = apic_read(APIC_LVTT);
1041         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1042
1043         if (maxlvt > 3) {                       /* PC is LVT#4. */
1044                 v = apic_read(APIC_LVTPC);
1045                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1046         }
1047         v = apic_read(APIC_LVT0);
1048         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1049         v = apic_read(APIC_LVT1);
1050         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1051
1052         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1053                 v = apic_read(APIC_LVTERR);
1054                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1055         }
1056
1057         v = apic_read(APIC_TMICT);
1058         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1059         v = apic_read(APIC_TMCCT);
1060         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1061         v = apic_read(APIC_TDCR);
1062         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1063         printk("\n");
1064 }
1065
1066 void print_all_local_APICs (void)
1067 {
1068         on_each_cpu(print_local_APIC, NULL, 1, 1);
1069 }
1070
1071 void __apicdebuginit print_PIC(void)
1072 {
1073         extern spinlock_t i8259A_lock;
1074         unsigned int v;
1075         unsigned long flags;
1076
1077         if (apic_verbosity == APIC_QUIET)
1078                 return;
1079
1080         printk(KERN_DEBUG "\nprinting PIC contents\n");
1081
1082         spin_lock_irqsave(&i8259A_lock, flags);
1083
1084         v = inb(0xa1) << 8 | inb(0x21);
1085         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1086
1087         v = inb(0xa0) << 8 | inb(0x20);
1088         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1089
1090         outb(0x0b,0xa0);
1091         outb(0x0b,0x20);
1092         v = inb(0xa0) << 8 | inb(0x20);
1093         outb(0x0a,0xa0);
1094         outb(0x0a,0x20);
1095
1096         spin_unlock_irqrestore(&i8259A_lock, flags);
1097
1098         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1099
1100         v = inb(0x4d1) << 8 | inb(0x4d0);
1101         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1102 }
1103
1104 static void __init enable_IO_APIC(void)
1105 {
1106         union IO_APIC_reg_01 reg_01;
1107         int i;
1108         unsigned long flags;
1109
1110         for (i = 0; i < PIN_MAP_SIZE; i++) {
1111                 irq_2_pin[i].pin = -1;
1112                 irq_2_pin[i].next = 0;
1113         }
1114         if (!pirqs_enabled)
1115                 for (i = 0; i < MAX_PIRQS; i++)
1116                         pirq_entries[i] = -1;
1117
1118         /*
1119          * The number of IO-APIC IRQ registers (== #pins):
1120          */
1121         for (i = 0; i < nr_ioapics; i++) {
1122                 spin_lock_irqsave(&ioapic_lock, flags);
1123                 reg_01.raw = io_apic_read(i, 1);
1124                 spin_unlock_irqrestore(&ioapic_lock, flags);
1125                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1126         }
1127
1128         /*
1129          * Do not trust the IO-APIC being empty at bootup
1130          */
1131         clear_IO_APIC();
1132 }
1133
1134 /*
1135  * Not an __init, needed by the reboot code
1136  */
1137 void disable_IO_APIC(void)
1138 {
1139         int pin;
1140         /*
1141          * Clear the IO-APIC before rebooting:
1142          */
1143         clear_IO_APIC();
1144
1145         /*
1146          * If the i82559 is routed through an IOAPIC
1147          * Put that IOAPIC in virtual wire mode
1148          * so legacy interrups can be delivered.
1149          */
1150         pin = find_isa_irq_pin(0, mp_ExtINT);
1151         if (pin != -1) {
1152                 struct IO_APIC_route_entry entry;
1153                 unsigned long flags;
1154
1155                 memset(&entry, 0, sizeof(entry));
1156                 entry.mask            = 0; /* Enabled */
1157                 entry.trigger         = 0; /* Edge */
1158                 entry.irr             = 0;
1159                 entry.polarity        = 0; /* High */
1160                 entry.delivery_status = 0;
1161                 entry.dest_mode       = 0; /* Physical */
1162                 entry.delivery_mode   = 7; /* ExtInt */
1163                 entry.vector          = 0;
1164                 entry.dest.physical.physical_dest = 0;
1165
1166
1167                 /*
1168                  * Add it to the IO-APIC irq-routing table:
1169                  */
1170                 spin_lock_irqsave(&ioapic_lock, flags);
1171                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1172                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1173                 spin_unlock_irqrestore(&ioapic_lock, flags);
1174         }
1175
1176         disconnect_bsp_APIC();
1177 }
1178
1179 /*
1180  * function to set the IO-APIC physical IDs based on the
1181  * values stored in the MPC table.
1182  *
1183  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1184  */
1185
1186 static void __init setup_ioapic_ids_from_mpc (void)
1187 {
1188         union IO_APIC_reg_00 reg_00;
1189         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1190         int apic;
1191         int i;
1192         unsigned char old_id;
1193         unsigned long flags;
1194
1195         /*
1196          * Set the IOAPIC ID to the value stored in the MPC table.
1197          */
1198         for (apic = 0; apic < nr_ioapics; apic++) {
1199
1200                 /* Read the register 0 value */
1201                 spin_lock_irqsave(&ioapic_lock, flags);
1202                 reg_00.raw = io_apic_read(apic, 0);
1203                 spin_unlock_irqrestore(&ioapic_lock, flags);
1204
1205                 old_id = mp_ioapics[apic].mpc_apicid;
1206
1207                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1208                         apic_printk(APIC_QUIET,KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1209                                 apic, mp_ioapics[apic].mpc_apicid);
1210                         apic_printk(APIC_QUIET,KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1211                                 reg_00.bits.ID);
1212                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1213                 }
1214
1215                 /*
1216                  * Sanity check, is the ID really free? Every APIC in a
1217                  * system must have a unique ID or we get lots of nice
1218                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1219                  */
1220                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1221                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1222                                 apic, mp_ioapics[apic].mpc_apicid);
1223                         for (i = 0; i < 0xf; i++)
1224                                 if (!physid_isset(i, phys_id_present_map))
1225                                         break;
1226                         if (i >= 0xf)
1227                                 panic("Max APIC ID exceeded!\n");
1228                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1229                                 i);
1230                         physid_set(i, phys_id_present_map);
1231                         mp_ioapics[apic].mpc_apicid = i;
1232                 } else {
1233                         printk(KERN_INFO
1234                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1235                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1236                 }
1237
1238
1239                 /*
1240                  * We need to adjust the IRQ routing table
1241                  * if the ID changed.
1242                  */
1243                 if (old_id != mp_ioapics[apic].mpc_apicid)
1244                         for (i = 0; i < mp_irq_entries; i++)
1245                                 if (mp_irqs[i].mpc_dstapic == old_id)
1246                                         mp_irqs[i].mpc_dstapic
1247                                                 = mp_ioapics[apic].mpc_apicid;
1248
1249                 /*
1250                  * Read the right value from the MPC table and
1251                  * write it into the ID register.
1252                  */
1253                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1254                                 mp_ioapics[apic].mpc_apicid);
1255
1256                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1257                 spin_lock_irqsave(&ioapic_lock, flags);
1258                 io_apic_write(apic, 0, reg_00.raw);
1259                 spin_unlock_irqrestore(&ioapic_lock, flags);
1260
1261                 /*
1262                  * Sanity check
1263                  */
1264                 spin_lock_irqsave(&ioapic_lock, flags);
1265                 reg_00.raw = io_apic_read(apic, 0);
1266                 spin_unlock_irqrestore(&ioapic_lock, flags);
1267                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1268                         printk("could not set ID!\n");
1269                 else
1270                         apic_printk(APIC_VERBOSE," ok.\n");
1271         }
1272 }
1273
1274 /*
1275  * There is a nasty bug in some older SMP boards, their mptable lies
1276  * about the timer IRQ. We do the following to work around the situation:
1277  *
1278  *      - timer IRQ defaults to IO-APIC IRQ
1279  *      - if this function detects that timer IRQs are defunct, then we fall
1280  *        back to ISA timer IRQs
1281  */
1282 static int __init timer_irq_works(void)
1283 {
1284         unsigned long t1 = jiffies;
1285
1286         local_irq_enable();
1287         /* Let ten ticks pass... */
1288         mdelay((10 * 1000) / HZ);
1289
1290         /*
1291          * Expect a few ticks at least, to be sure some possible
1292          * glue logic does not lock up after one or two first
1293          * ticks in a non-ExtINT mode.  Also the local APIC
1294          * might have cached one ExtINT interrupt.  Finally, at
1295          * least one tick may be lost due to delays.
1296          */
1297
1298         /* jiffies wrap? */
1299         if (jiffies - t1 > 4)
1300                 return 1;
1301         return 0;
1302 }
1303
1304 /*
1305  * In the SMP+IOAPIC case it might happen that there are an unspecified
1306  * number of pending IRQ events unhandled. These cases are very rare,
1307  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1308  * better to do it this way as thus we do not have to be aware of
1309  * 'pending' interrupts in the IRQ path, except at this point.
1310  */
1311 /*
1312  * Edge triggered needs to resend any interrupt
1313  * that was delayed but this is now handled in the device
1314  * independent code.
1315  */
1316
1317 /*
1318  * Starting up a edge-triggered IO-APIC interrupt is
1319  * nasty - we need to make sure that we get the edge.
1320  * If it is already asserted for some reason, we need
1321  * return 1 to indicate that is was pending.
1322  *
1323  * This is not complete - we should be able to fake
1324  * an edge even if it isn't on the 8259A...
1325  */
1326
1327 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1328 {
1329         int was_pending = 0;
1330         unsigned long flags;
1331
1332         spin_lock_irqsave(&ioapic_lock, flags);
1333         if (irq < 16) {
1334                 disable_8259A_irq(irq);
1335                 if (i8259A_irq_pending(irq))
1336                         was_pending = 1;
1337         }
1338         __unmask_IO_APIC_irq(irq);
1339         spin_unlock_irqrestore(&ioapic_lock, flags);
1340
1341         return was_pending;
1342 }
1343
1344 /*
1345  * Once we have recorded IRQ_PENDING already, we can mask the
1346  * interrupt for real. This prevents IRQ storms from unhandled
1347  * devices.
1348  */
1349 static void ack_edge_ioapic_irq(unsigned int irq)
1350 {
1351         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1352                                         == (IRQ_PENDING | IRQ_DISABLED))
1353                 mask_IO_APIC_irq(irq);
1354         ack_APIC_irq();
1355 }
1356
1357 /*
1358  * Level triggered interrupts can just be masked,
1359  * and shutting down and starting up the interrupt
1360  * is the same as enabling and disabling them -- except
1361  * with a startup need to return a "was pending" value.
1362  *
1363  * Level triggered interrupts are special because we
1364  * do not touch any IO-APIC register while handling
1365  * them. We ack the APIC in the end-IRQ handler, not
1366  * in the start-IRQ-handler. Protection against reentrance
1367  * from the same interrupt is still provided, both by the
1368  * generic IRQ layer and by the fact that an unacked local
1369  * APIC does not accept IRQs.
1370  */
1371 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1372 {
1373         unmask_IO_APIC_irq(irq);
1374
1375         return 0; /* don't check for pending */
1376 }
1377
1378 static void end_level_ioapic_irq (unsigned int irq)
1379 {
1380         unsigned long v;
1381         int i;
1382
1383 /*
1384  * It appears there is an erratum which affects at least version 0x11
1385  * of I/O APIC (that's the 82093AA and cores integrated into various
1386  * chipsets).  Under certain conditions a level-triggered interrupt is
1387  * erroneously delivered as edge-triggered one but the respective IRR
1388  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1389  * message but it will never arrive and further interrupts are blocked
1390  * from the source.  The exact reason is so far unknown, but the
1391  * phenomenon was observed when two consecutive interrupt requests
1392  * from a given source get delivered to the same CPU and the source is
1393  * temporarily disabled in between.
1394  *
1395  * A workaround is to simulate an EOI message manually.  We achieve it
1396  * by setting the trigger mode to edge and then to level when the edge
1397  * trigger mode gets detected in the TMR of a local APIC for a
1398  * level-triggered interrupt.  We mask the source for the time of the
1399  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1400  * The idea is from Manfred Spraul.  --macro
1401  */
1402         i = IO_APIC_VECTOR(irq);
1403         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1404
1405         ack_APIC_irq();
1406
1407         if (!(v & (1 << (i & 0x1f)))) {
1408 #ifdef APIC_LOCKUP_DEBUG
1409                 struct irq_pin_list *entry;
1410 #endif
1411
1412 #ifdef APIC_MISMATCH_DEBUG
1413                 atomic_inc(&irq_mis_count);
1414 #endif
1415                 spin_lock(&ioapic_lock);
1416                 __mask_and_edge_IO_APIC_irq(irq);
1417 #ifdef APIC_LOCKUP_DEBUG
1418                 for (entry = irq_2_pin + irq;;) {
1419                         unsigned int reg;
1420
1421                         if (entry->pin == -1)
1422                                 break;
1423                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1424                         if (reg & 0x00004000)
1425                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1426                                         " still set after unlock!\n");
1427                         if (!entry->next)
1428                                 break;
1429                         entry = irq_2_pin + entry->next;
1430                 }
1431 #endif
1432                 __unmask_and_level_IO_APIC_irq(irq);
1433                 spin_unlock(&ioapic_lock);
1434         }
1435 }
1436
1437 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1438 {
1439         unsigned long flags;
1440         unsigned int dest;
1441
1442         dest = cpu_mask_to_apicid(mask);
1443
1444         /*
1445          * Only the first 8 bits are valid.
1446          */
1447         dest = dest << 24;
1448
1449         spin_lock_irqsave(&ioapic_lock, flags);
1450         __DO_ACTION(1, = dest, )
1451         spin_unlock_irqrestore(&ioapic_lock, flags);
1452 }
1453
1454 #ifdef CONFIG_PCI_MSI
1455 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1456 {
1457         int irq = vector_to_irq(vector);
1458
1459         return startup_edge_ioapic_irq(irq);
1460 }
1461
1462 static void ack_edge_ioapic_vector(unsigned int vector)
1463 {
1464         int irq = vector_to_irq(vector);
1465
1466         ack_edge_ioapic_irq(irq);
1467 }
1468
1469 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1470 {
1471         int irq = vector_to_irq(vector);
1472
1473         return startup_level_ioapic_irq (irq);
1474 }
1475
1476 static void end_level_ioapic_vector (unsigned int vector)
1477 {
1478         int irq = vector_to_irq(vector);
1479
1480         end_level_ioapic_irq(irq);
1481 }
1482
1483 static void mask_IO_APIC_vector (unsigned int vector)
1484 {
1485         int irq = vector_to_irq(vector);
1486
1487         mask_IO_APIC_irq(irq);
1488 }
1489
1490 static void unmask_IO_APIC_vector (unsigned int vector)
1491 {
1492         int irq = vector_to_irq(vector);
1493
1494         unmask_IO_APIC_irq(irq);
1495 }
1496
1497 static void set_ioapic_affinity_vector (unsigned int vector,
1498                                         cpumask_t cpu_mask)
1499 {
1500         int irq = vector_to_irq(vector);
1501
1502         set_ioapic_affinity_irq(irq, cpu_mask);
1503 }
1504 #endif
1505
1506 /*
1507  * Level and edge triggered IO-APIC interrupts need different handling,
1508  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1509  * handled with the level-triggered descriptor, but that one has slightly
1510  * more overhead. Level-triggered interrupts cannot be handled with the
1511  * edge-triggered handler, without risking IRQ storms and other ugly
1512  * races.
1513  */
1514
1515 static struct hw_interrupt_type ioapic_edge_type = {
1516         .typename = "IO-APIC-edge",
1517         .startup        = startup_edge_ioapic,
1518         .shutdown       = shutdown_edge_ioapic,
1519         .enable         = enable_edge_ioapic,
1520         .disable        = disable_edge_ioapic,
1521         .ack            = ack_edge_ioapic,
1522         .end            = end_edge_ioapic,
1523         .set_affinity = set_ioapic_affinity,
1524 };
1525
1526 static struct hw_interrupt_type ioapic_level_type = {
1527         .typename = "IO-APIC-level",
1528         .startup        = startup_level_ioapic,
1529         .shutdown       = shutdown_level_ioapic,
1530         .enable         = enable_level_ioapic,
1531         .disable        = disable_level_ioapic,
1532         .ack            = mask_and_ack_level_ioapic,
1533         .end            = end_level_ioapic,
1534         .set_affinity = set_ioapic_affinity,
1535 };
1536
1537 static inline void init_IO_APIC_traps(void)
1538 {
1539         int irq;
1540
1541         /*
1542          * NOTE! The local APIC isn't very good at handling
1543          * multiple interrupts at the same interrupt level.
1544          * As the interrupt level is determined by taking the
1545          * vector number and shifting that right by 4, we
1546          * want to spread these out a bit so that they don't
1547          * all fall in the same interrupt level.
1548          *
1549          * Also, we've got to be careful not to trash gate
1550          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1551          */
1552         for (irq = 0; irq < NR_IRQS ; irq++) {
1553                 int tmp = irq;
1554                 if (use_pci_vector()) {
1555                         if (!platform_legacy_irq(tmp))
1556                                 if ((tmp = vector_to_irq(tmp)) == -1)
1557                                         continue;
1558                 }
1559                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1560                         /*
1561                          * Hmm.. We don't have an entry for this,
1562                          * so default to an old-fashioned 8259
1563                          * interrupt if we can..
1564                          */
1565                         if (irq < 16)
1566                                 make_8259A_irq(irq);
1567                         else
1568                                 /* Strange. Oh, well.. */
1569                                 irq_desc[irq].handler = &no_irq_type;
1570                 }
1571         }
1572 }
1573
1574 static void enable_lapic_irq (unsigned int irq)
1575 {
1576         unsigned long v;
1577
1578         v = apic_read(APIC_LVT0);
1579         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1580 }
1581
1582 static void disable_lapic_irq (unsigned int irq)
1583 {
1584         unsigned long v;
1585
1586         v = apic_read(APIC_LVT0);
1587         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1588 }
1589
1590 static void ack_lapic_irq (unsigned int irq)
1591 {
1592         ack_APIC_irq();
1593 }
1594
1595 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1596
1597 static struct hw_interrupt_type lapic_irq_type = {
1598         .typename = "local-APIC-edge",
1599         .startup = NULL, /* startup_irq() not used for IRQ0 */
1600         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1601         .enable = enable_lapic_irq,
1602         .disable = disable_lapic_irq,
1603         .ack = ack_lapic_irq,
1604         .end = end_lapic_irq,
1605 };
1606
1607 static void setup_nmi (void)
1608 {
1609         /*
1610          * Dirty trick to enable the NMI watchdog ...
1611          * We put the 8259A master into AEOI mode and
1612          * unmask on all local APICs LVT0 as NMI.
1613          *
1614          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1615          * is from Maciej W. Rozycki - so we do not have to EOI from
1616          * the NMI handler or the timer interrupt.
1617          */
1618         printk(KERN_INFO "activating NMI Watchdog ...");
1619
1620         enable_NMI_through_LVT0(NULL);
1621
1622         printk(" done.\n");
1623 }
1624
1625 /*
1626  * This looks a bit hackish but it's about the only one way of sending
1627  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1628  * not support the ExtINT mode, unfortunately.  We need to send these
1629  * cycles as some i82489DX-based boards have glue logic that keeps the
1630  * 8259A interrupt line asserted until INTA.  --macro
1631  */
1632 static inline void unlock_ExtINT_logic(void)
1633 {
1634         int pin, i;
1635         struct IO_APIC_route_entry entry0, entry1;
1636         unsigned char save_control, save_freq_select;
1637         unsigned long flags;
1638
1639         pin = find_isa_irq_pin(8, mp_INT);
1640         if (pin == -1)
1641                 return;
1642
1643         spin_lock_irqsave(&ioapic_lock, flags);
1644         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1645         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1646         spin_unlock_irqrestore(&ioapic_lock, flags);
1647         clear_IO_APIC_pin(0, pin);
1648
1649         memset(&entry1, 0, sizeof(entry1));
1650
1651         entry1.dest_mode = 0;                   /* physical delivery */
1652         entry1.mask = 0;                        /* unmask IRQ now */
1653         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1654         entry1.delivery_mode = dest_ExtINT;
1655         entry1.polarity = entry0.polarity;
1656         entry1.trigger = 0;
1657         entry1.vector = 0;
1658
1659         spin_lock_irqsave(&ioapic_lock, flags);
1660         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1661         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1662         spin_unlock_irqrestore(&ioapic_lock, flags);
1663
1664         save_control = CMOS_READ(RTC_CONTROL);
1665         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1666         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1667                    RTC_FREQ_SELECT);
1668         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1669
1670         i = 100;
1671         while (i-- > 0) {
1672                 mdelay(10);
1673                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1674                         i -= 10;
1675         }
1676
1677         CMOS_WRITE(save_control, RTC_CONTROL);
1678         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1679         clear_IO_APIC_pin(0, pin);
1680
1681         spin_lock_irqsave(&ioapic_lock, flags);
1682         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1683         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1684         spin_unlock_irqrestore(&ioapic_lock, flags);
1685 }
1686
1687 /*
1688  * This code may look a bit paranoid, but it's supposed to cooperate with
1689  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1690  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1691  * fanatically on his truly buggy board.
1692  */
1693 static inline void check_timer(void)
1694 {
1695         int pin1, pin2;
1696         int vector;
1697
1698         /*
1699          * get/set the timer IRQ vector:
1700          */
1701         disable_8259A_irq(0);
1702         vector = assign_irq_vector(0);
1703         set_intr_gate(vector, interrupt[0]);
1704
1705         /*
1706          * Subtle, code in do_timer_interrupt() expects an AEOI
1707          * mode for the 8259A whenever interrupts are routed
1708          * through I/O APICs.  Also IRQ0 has to be enabled in
1709          * the 8259A which implies the virtual wire has to be
1710          * disabled in the local APIC.
1711          */
1712         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1713         init_8259A(1);
1714         enable_8259A_irq(0);
1715
1716         pin1 = find_isa_irq_pin(0, mp_INT);
1717         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1718
1719         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1720
1721         if (pin1 != -1) {
1722                 /*
1723                  * Ok, does IRQ0 through the IOAPIC work?
1724                  */
1725                 unmask_IO_APIC_irq(0);
1726                 if (timer_irq_works()) {
1727                         nmi_watchdog_default();
1728                         if (nmi_watchdog == NMI_IO_APIC) {
1729                                 disable_8259A_irq(0);
1730                                 setup_nmi();
1731                                 enable_8259A_irq(0);
1732                                 check_nmi_watchdog();
1733                         }
1734                         return;
1735                 }
1736                 clear_IO_APIC_pin(0, pin1);
1737                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1738         }
1739
1740         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1741         if (pin2 != -1) {
1742                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1743                 /*
1744                  * legacy devices should be connected to IO APIC #0
1745                  */
1746                 setup_ExtINT_IRQ0_pin(pin2, vector);
1747                 if (timer_irq_works()) {
1748                         printk("works.\n");
1749                         nmi_watchdog_default();
1750                         if (nmi_watchdog == NMI_IO_APIC) {
1751                                 setup_nmi();
1752                                 check_nmi_watchdog();
1753                         }
1754                         return;
1755                 }
1756                 /*
1757                  * Cleanup, just in case ...
1758                  */
1759                 clear_IO_APIC_pin(0, pin2);
1760         }
1761         printk(" failed.\n");
1762
1763         if (nmi_watchdog) {
1764                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1765                 nmi_watchdog = 0;
1766         }
1767
1768         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1769
1770         disable_8259A_irq(0);
1771         irq_desc[0].handler = &lapic_irq_type;
1772         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1773         enable_8259A_irq(0);
1774
1775         if (timer_irq_works()) {
1776                 apic_printk(APIC_QUIET, " works.\n");
1777                 return;
1778         }
1779         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1780         apic_printk(APIC_VERBOSE," failed.\n");
1781
1782         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1783
1784         init_8259A(0);
1785         make_8259A_irq(0);
1786         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1787
1788         unlock_ExtINT_logic();
1789
1790         if (timer_irq_works()) {
1791                 apic_printk(APIC_VERBOSE," works.\n");
1792                 return;
1793         }
1794         apic_printk(APIC_VERBOSE," failed :(.\n");
1795         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1796 }
1797
1798 /*
1799  *
1800  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1801  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1802  *   Linux doesn't really care, as it's not actually used
1803  *   for any interrupt handling anyway.
1804  */
1805 #define PIC_IRQS        (1<<2)
1806
1807 void __init setup_IO_APIC(void)
1808 {
1809         enable_IO_APIC();
1810
1811         if (acpi_ioapic)
1812                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1813         else
1814                 io_apic_irqs = ~PIC_IRQS;
1815
1816         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1817
1818         /*
1819          * Set up the IO-APIC IRQ routing table.
1820          */
1821         if (!acpi_ioapic)
1822                 setup_ioapic_ids_from_mpc();
1823         sync_Arb_IDs();
1824         setup_IO_APIC_irqs();
1825         init_IO_APIC_traps();
1826         check_timer();
1827         if (!acpi_ioapic)
1828                 print_IO_APIC();
1829 }
1830
1831 struct sysfs_ioapic_data {
1832         struct sys_device dev;
1833         struct IO_APIC_route_entry entry[0];
1834 };
1835 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1836
1837 static int ioapic_suspend(struct sys_device *dev, u32 state)
1838 {
1839         struct IO_APIC_route_entry *entry;
1840         struct sysfs_ioapic_data *data;
1841         unsigned long flags;
1842         int i;
1843
1844         data = container_of(dev, struct sysfs_ioapic_data, dev);
1845         entry = data->entry;
1846         spin_lock_irqsave(&ioapic_lock, flags);
1847         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1848                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1849                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1850         }
1851         spin_unlock_irqrestore(&ioapic_lock, flags);
1852
1853         return 0;
1854 }
1855
1856 static int ioapic_resume(struct sys_device *dev)
1857 {
1858         struct IO_APIC_route_entry *entry;
1859         struct sysfs_ioapic_data *data;
1860         unsigned long flags;
1861         union IO_APIC_reg_00 reg_00;
1862         int i;
1863
1864         data = container_of(dev, struct sysfs_ioapic_data, dev);
1865         entry = data->entry;
1866
1867         spin_lock_irqsave(&ioapic_lock, flags);
1868         reg_00.raw = io_apic_read(dev->id, 0);
1869         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1870                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1871                 io_apic_write(dev->id, 0, reg_00.raw);
1872         }
1873         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1874                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1875                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1876         }
1877         spin_unlock_irqrestore(&ioapic_lock, flags);
1878
1879         return 0;
1880 }
1881
1882 static struct sysdev_class ioapic_sysdev_class = {
1883         set_kset_name("ioapic"),
1884         .suspend = ioapic_suspend,
1885         .resume = ioapic_resume,
1886 };
1887
1888 static int __init ioapic_init_sysfs(void)
1889 {
1890         struct sys_device * dev;
1891         int i, size, error = 0;
1892
1893         error = sysdev_class_register(&ioapic_sysdev_class);
1894         if (error)
1895                 return error;
1896
1897         for (i = 0; i < nr_ioapics; i++ ) {
1898                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1899                         * sizeof(struct IO_APIC_route_entry);
1900                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1901                 if (!mp_ioapic_data[i]) {
1902                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1903                         continue;
1904                 }
1905                 memset(mp_ioapic_data[i], 0, size);
1906                 dev = &mp_ioapic_data[i]->dev;
1907                 dev->id = i;
1908                 dev->cls = &ioapic_sysdev_class;
1909                 error = sysdev_register(dev);
1910                 if (error) {
1911                         kfree(mp_ioapic_data[i]);
1912                         mp_ioapic_data[i] = NULL;
1913                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1914                         continue;
1915                 }
1916         }
1917
1918         return 0;
1919 }
1920
1921 device_initcall(ioapic_init_sysfs);
1922
1923 /* --------------------------------------------------------------------------
1924                           ACPI-based IOAPIC Configuration
1925    -------------------------------------------------------------------------- */
1926
1927 #ifdef CONFIG_ACPI_BOOT
1928
1929 #define IO_APIC_MAX_ID          15
1930
1931 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1932 {
1933         union IO_APIC_reg_00 reg_00;
1934         static physid_mask_t apic_id_map;
1935         unsigned long flags;
1936         int i = 0;
1937
1938         /*
1939          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1940          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1941          * supports up to 16 on one shared APIC bus.
1942          *
1943          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1944          *      advantage of new APIC bus architecture.
1945          */
1946
1947         if (physids_empty(apic_id_map))
1948                 apic_id_map = phys_cpu_present_map;
1949
1950         spin_lock_irqsave(&ioapic_lock, flags);
1951         reg_00.raw = io_apic_read(ioapic, 0);
1952         spin_unlock_irqrestore(&ioapic_lock, flags);
1953
1954         if (apic_id >= IO_APIC_MAX_ID) {
1955                 apic_printk(APIC_QUIET, KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1956                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1957                 apic_id = reg_00.bits.ID;
1958         }
1959
1960         /*
1961          * Every APIC in a system must have a unique ID or we get lots of nice
1962          * 'stuck on smp_invalidate_needed IPI wait' messages.
1963          */
1964         if (physid_isset(apic_id, apic_id_map)) {
1965
1966                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1967                         if (!physid_isset(i, apic_id_map))
1968                                 break;
1969                 }
1970
1971                 if (i == IO_APIC_MAX_ID)
1972                         panic("Max apic_id exceeded!\n");
1973
1974                 apic_printk(APIC_VERBOSE, KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1975                         "trying %d\n", ioapic, apic_id, i);
1976
1977                 apic_id = i;
1978         }
1979
1980         physid_set(apic_id, apic_id_map);
1981
1982         if (reg_00.bits.ID != apic_id) {
1983                 reg_00.bits.ID = apic_id;
1984
1985                 spin_lock_irqsave(&ioapic_lock, flags);
1986                 io_apic_write(ioapic, 0, reg_00.raw);
1987                 reg_00.raw = io_apic_read(ioapic, 0);
1988                 spin_unlock_irqrestore(&ioapic_lock, flags);
1989
1990                 /* Sanity check */
1991                 if (reg_00.bits.ID != apic_id)
1992                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1993         }
1994
1995         apic_printk(APIC_VERBOSE,KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1996
1997         return apic_id;
1998 }
1999
2000
2001 int __init io_apic_get_version (int ioapic)
2002 {
2003         union IO_APIC_reg_01    reg_01;
2004         unsigned long flags;
2005
2006         spin_lock_irqsave(&ioapic_lock, flags);
2007         reg_01.raw = io_apic_read(ioapic, 1);
2008         spin_unlock_irqrestore(&ioapic_lock, flags);
2009
2010         return reg_01.bits.version;
2011 }
2012
2013
2014 int __init io_apic_get_redir_entries (int ioapic)
2015 {
2016         union IO_APIC_reg_01    reg_01;
2017         unsigned long flags;
2018
2019         spin_lock_irqsave(&ioapic_lock, flags);
2020         reg_01.raw = io_apic_read(ioapic, 1);
2021         spin_unlock_irqrestore(&ioapic_lock, flags);
2022
2023         return reg_01.bits.entries;
2024 }
2025
2026
2027 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2028 {
2029         struct IO_APIC_route_entry entry;
2030         unsigned long flags;
2031
2032         if (!IO_APIC_IRQ(irq)) {
2033                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2034                         ioapic);
2035                 return -EINVAL;
2036         }
2037
2038         /*
2039          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2040          * Note that we mask (disable) IRQs now -- these get enabled when the
2041          * corresponding device driver registers for this IRQ.
2042          */
2043
2044         memset(&entry,0,sizeof(entry));
2045
2046         entry.delivery_mode = dest_LowestPrio;
2047         entry.dest_mode = INT_DELIVERY_MODE;
2048         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2049         entry.trigger = edge_level;
2050         entry.polarity = active_high_low;
2051         entry.mask = 1;                                  /* Disabled (masked) */
2052
2053         /*
2054          * IRQs < 16 are already in the irq_2_pin[] map
2055          */
2056         if (irq >= 16)
2057                 add_pin_to_irq(irq, ioapic, pin);
2058
2059         entry.vector = assign_irq_vector(irq);
2060
2061         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2062                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2063                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2064                edge_level, active_high_low);
2065
2066         ioapic_register_intr(irq, entry.vector, edge_level);
2067
2068         if (!ioapic && (irq < 16))
2069                 disable_8259A_irq(irq);
2070
2071         spin_lock_irqsave(&ioapic_lock, flags);
2072         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2073         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2074         spin_unlock_irqrestore(&ioapic_lock, flags);
2075
2076         return 0;
2077 }
2078
2079 #endif /*CONFIG_ACPI_BOOT*/
2080
2081 #ifndef CONFIG_SMP
2082 void send_IPI_self(int vector)
2083 {
2084         unsigned int cfg;
2085
2086        /*
2087         * Wait for idle.
2088         */
2089         apic_wait_icr_idle();
2090         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
2091
2092         /*
2093          * Send the IPI. The write to APIC_ICR fires this off.
2094          */
2095         apic_write_around(APIC_ICR, cfg);
2096 }
2097 #endif
2098
2099
2100 /*
2101  * This function currently is only a helper for the i386 smp boot process where
2102  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2103  * so mask in all cases should simply be TARGET_CPUS
2104  */
2105 void __init setup_ioapic_dest(void)
2106 {
2107         int pin, ioapic, irq, irq_entry;
2108
2109         if (skip_ioapic_setup == 1)
2110                 return;
2111
2112         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2113                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2114                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2115                         if (irq_entry == -1)
2116                                 continue;
2117                         irq = pin_2_irq(irq_entry, ioapic, pin);
2118                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2119                 }
2120
2121         }
2122 }