arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/proto.h>
  39
  40 #define __apicdebuginit  __init
  41
  42 int sis_apic_bug; /* not actually supported, dummy for compile */
  43
  44 #undef APIC_LOCKUP_DEBUG
  45
  46 #define APIC_LOCKUP_DEBUG
  47
  48 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  49
  50 /*
  51  * # of IRQ routing registers
  52  */
  53 int nr_ioapic_registers[MAX_IO_APICS];
  54
  55 /*
  56  * Rough estimation of how many shared IRQs there are, can
  57  * be changed anytime.
  58  */
  59 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  60 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  61
  62 /*
  63  * This is performance-critical, we want to do it O(1)
  64  *
  65  * the indexing order of this array favors 1:1 mappings
  66  * between pins and IRQs.
  67  */
  68
  69 static struct irq_pin_list {
  70         short apic, pin, next;
  71 } irq_2_pin[PIN_MAP_SIZE];
  72
  73 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  74 #ifdef CONFIG_PCI_MSI
  75 #define vector_to_irq(vector)   \
  76         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  77 #else
  78 #define vector_to_irq(vector)   (vector)
  79 #endif
  80
  81 /*
  82  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  83  * shared ISA-space IRQs, so we have to support them. We are super
  84  * fast in the common case, and fast for shared ISA-space IRQs.
  85  */
  86 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  87 {
  88         static int first_free_entry = NR_IRQS;
  89         struct irq_pin_list *entry = irq_2_pin + irq;
  90
  91         while (entry->next)
  92                 entry = irq_2_pin + entry->next;
  93
  94         if (entry->pin != -1) {
  95                 entry->next = first_free_entry;
  96                 entry = irq_2_pin + entry->next;
  97                 if (++first_free_entry >= PIN_MAP_SIZE)
  98                         panic("io_apic.c: whoops");
  99         }
 100         entry->apic = apic;
 101         entry->pin = pin;
 102 }
 103
 104 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 105                                                                         \
 106 {                                                                       \
 107         int pin;                                                        \
 108         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 109                                                                         \
 110         for (;;) {                                                      \
 111                 unsigned int reg;                                       \
 112                 pin = entry->pin;                                       \
 113                 if (pin == -1)                                          \
 114                         break;                                          \
 115                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 116                 reg ACTION;                                             \
 117                 io_apic_modify(entry->apic, reg);                       \
 118                 if (!entry->next)                                       \
 119                         break;                                          \
 120                 entry = irq_2_pin + entry->next;                        \
 121         }                                                               \
 122         FINAL;                                                          \
 123 }
 124
 125 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 126                                                                         \
 127         static void name##_IO_APIC_irq (unsigned int irq)               \
 128         __DO_ACTION(R, ACTION, FINAL)
 129
 130 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 131                                                 /* mask = 1 */
 132 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 133                                                 /* mask = 0 */
 134 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
 135                                                 /* mask = 1, trigger = 0 */
 136 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
 137                                                 /* mask = 0, trigger = 1 */
 138
 139 static void mask_IO_APIC_irq (unsigned int irq)
 140 {
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&ioapic_lock, flags);
 144         __mask_IO_APIC_irq(irq);
 145         spin_unlock_irqrestore(&ioapic_lock, flags);
 146 }
 147
 148 static void unmask_IO_APIC_irq (unsigned int irq)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&ioapic_lock, flags);
 153         __unmask_IO_APIC_irq(irq);
 154         spin_unlock_irqrestore(&ioapic_lock, flags);
 155 }
 156
 157 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 158 {
 159         struct IO_APIC_route_entry entry;
 160         unsigned long flags;
 161
 162         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 163         spin_lock_irqsave(&ioapic_lock, flags);
 164         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 165         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 166         spin_unlock_irqrestore(&ioapic_lock, flags);
 167         if (entry.delivery_mode == dest_SMI)
 168                 return;
 169         /*
 170          * Disable it in the IO-APIC irq-routing table:
 171          */
 172         memset(&entry, 0, sizeof(entry));
 173         entry.mask = 1;
 174         spin_lock_irqsave(&ioapic_lock, flags);
 175         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 176         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 177         spin_unlock_irqrestore(&ioapic_lock, flags);
 178 }
 179
 180 static void clear_IO_APIC (void)
 181 {
 182         int apic, pin;
 183
 184         for (apic = 0; apic < nr_ioapics; apic++)
 185                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 186                         clear_IO_APIC_pin(apic, pin);
 187 }
 188
 189 /*
 190  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 191  * specific CPU-side IRQs.
 192  */
 193
 194 #define MAX_PIRQS 8
 195 int pirq_entries [MAX_PIRQS];
 196 int pirqs_enabled;
 197 int skip_ioapic_setup;
 198 int ioapic_force;
 199
 200 /* dummy parsing: see setup.c */
 201
 202 static int __init disable_ioapic_setup(char *str)
 203 {
 204         skip_ioapic_setup = 1;
 205         return 1;
 206 }
 207
 208 static int __init enable_ioapic_setup(char *str)
 209 {
 210         ioapic_force = 1;
 211         skip_ioapic_setup = 0;
 212         return 1;
 213 }
 214
 215 __setup("noapic", disable_ioapic_setup);
 216 __setup("apic", enable_ioapic_setup);
 217
 218 #include <asm/pci-direct.h>
 219 #include <linux/pci_ids.h>
 220 #include <linux/pci.h>
 221
 222 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 223    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 224    Use pci direct infrastructure because this runs before the PCI subsystem.
 225
 226    Can be overwritten with "apic"
 227
 228    And another hack to disable the IOMMU on VIA chipsets.
 229
 230    Kludge-O-Rama. */
 231 void __init check_ioapic(void)
 232 {
 233         int num,slot,func;
 234         if (ioapic_force)
 235                 return;
 236
 237         /* Poor man's PCI discovery */
 238         for (num = 0; num < 32; num++) {
 239                 for (slot = 0; slot < 32; slot++) {
 240                         for (func = 0; func < 8; func++) {
 241                                 u32 class;
 242                                 u32 vendor;
 243                                 u8 type;
 244                                 class = read_pci_config(num,slot,func,
 245                                                         PCI_CLASS_REVISION);
 246                                 if (class == 0xffffffff)
 247                                         break;
 248
 249                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 250                                         continue;
 251
 252                                 vendor = read_pci_config(num, slot, func,
 253                                                          PCI_VENDOR_ID);
 254                                 vendor &= 0xffff;
 255                                 switch (vendor) {
 256                                 case PCI_VENDOR_ID_VIA:
 257 #ifdef CONFIG_GART_IOMMU
 258                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 259                                              force_iommu) &&
 260                                             !iommu_aperture_allowed) {
 261                                                 printk(KERN_INFO
 262     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 263                                                 iommu_aperture_disabled = 1;
 264                                         }
 265 #endif
 266                                         return;
 267                                 case PCI_VENDOR_ID_NVIDIA:
 268 #ifndef CONFIG_SMP
 269                                         printk(KERN_INFO
 270      "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
 271                                                num,slot,vendor);
 272                                         skip_ioapic_setup = 1;
 273 #endif
 274                                         return;
 275                                 }
 276
 277                                 /* No multi-function device? */
 278                                 type = read_pci_config_byte(num,slot,func,
 279                                                             PCI_HEADER_TYPE);
 280                                 if (!(type & 0x80))
 281                                         break;
 282                         }
 283                 }
 284         }
 285 }
 286
 287 static int __init ioapic_pirq_setup(char *str)
 288 {
 289         int i, max;
 290         int ints[MAX_PIRQS+1];
 291
 292         get_options(str, ARRAY_SIZE(ints), ints);
 293
 294         for (i = 0; i < MAX_PIRQS; i++)
 295                 pirq_entries[i] = -1;
 296
 297         pirqs_enabled = 1;
 298         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 299         max = MAX_PIRQS;
 300         if (ints[0] < MAX_PIRQS)
 301                 max = ints[0];
 302
 303         for (i = 0; i < max; i++) {
 304                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 305                 /*
 306                  * PIRQs are mapped upside down, usually.
 307                  */
 308                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 309         }
 310         return 1;
 311 }
 312
 313 __setup("pirq=", ioapic_pirq_setup);
 314
 315 /*
 316  * Find the IRQ entry number of a certain pin.
 317  */
 318 static int __init find_irq_entry(int apic, int pin, int type)
 319 {
 320         int i;
 321
 322         for (i = 0; i < mp_irq_entries; i++)
 323                 if (mp_irqs[i].mpc_irqtype == type &&
 324                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 325                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 326                     mp_irqs[i].mpc_dstirq == pin)
 327                         return i;
 328
 329         return -1;
 330 }
 331
 332 /*
 333  * Find the pin to which IRQ[irq] (ISA) is connected
 334  */
 335 static int __init find_isa_irq_pin(int irq, int type)
 336 {
 337         int i;
 338
 339         for (i = 0; i < mp_irq_entries; i++) {
 340                 int lbus = mp_irqs[i].mpc_srcbus;
 341
 342                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 343                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 344                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 345                     (mp_irqs[i].mpc_irqtype == type) &&
 346                     (mp_irqs[i].mpc_srcbusirq == irq))
 347
 348                         return mp_irqs[i].mpc_dstirq;
 349         }
 350         return -1;
 351 }
 352
 353 /*
 354  * Find a specific PCI IRQ entry.
 355  * Not an __init, possibly needed by modules
 356  */
 357 static int pin_2_irq(int idx, int apic, int pin);
 358
 359 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 360 {
 361         int apic, i, best_guess = -1;
 362
 363         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 364                 bus, slot, pin);
 365         if (mp_bus_id_to_pci_bus[bus] == -1) {
 366                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 367                 return -1;
 368         }
 369         for (i = 0; i < mp_irq_entries; i++) {
 370                 int lbus = mp_irqs[i].mpc_srcbus;
 371
 372                 for (apic = 0; apic < nr_ioapics; apic++)
 373                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 374                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 375                                 break;
 376
 377                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 378                     !mp_irqs[i].mpc_irqtype &&
 379                     (bus == lbus) &&
 380                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 381                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 382
 383                         if (!(apic || IO_APIC_IRQ(irq)))
 384                                 continue;
 385
 386                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 387                                 return irq;
 388                         /*
 389                          * Use the first all-but-pin matching entry as a
 390                          * best-guess fuzzy result for broken mptables.
 391                          */
 392                         if (best_guess < 0)
 393                                 best_guess = irq;
 394                 }
 395         }
 396         return best_guess;
 397 }
 398
 399 /*
 400  * EISA Edge/Level control register, ELCR
 401  */
 402 static int __init EISA_ELCR(unsigned int irq)
 403 {
 404         if (irq < 16) {
 405                 unsigned int port = 0x4d0 + (irq >> 3);
 406                 return (inb(port) >> (irq & 7)) & 1;
 407         }
 408         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 409         return 0;
 410 }
 411
 412 /* EISA interrupts are always polarity zero and can be edge or level
 413  * trigger depending on the ELCR value.  If an interrupt is listed as
 414  * EISA conforming in the MP table, that means its trigger type must
 415  * be read in from the ELCR */
 416
 417 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 418 #define default_EISA_polarity(idx)      (0)
 419
 420 /* ISA interrupts are always polarity zero edge triggered,
 421  * when listed as conforming in the MP table. */
 422
 423 #define default_ISA_trigger(idx)        (0)
 424 #define default_ISA_polarity(idx)       (0)
 425
 426 /* PCI interrupts are always polarity one level triggered,
 427  * when listed as conforming in the MP table. */
 428
 429 #define default_PCI_trigger(idx)        (1)
 430 #define default_PCI_polarity(idx)       (1)
 431
 432 /* MCA interrupts are always polarity zero level triggered,
 433  * when listed as conforming in the MP table. */
 434
 435 #define default_MCA_trigger(idx)        (1)
 436 #define default_MCA_polarity(idx)       (0)
 437
 438 static int __init MPBIOS_polarity(int idx)
 439 {
 440         int bus = mp_irqs[idx].mpc_srcbus;
 441         int polarity;
 442
 443         /*
 444          * Determine IRQ line polarity (high active or low active):
 445          */
 446         switch (mp_irqs[idx].mpc_irqflag & 3)
 447         {
 448                 case 0: /* conforms, ie. bus-type dependent polarity */
 449                 {
 450                         switch (mp_bus_id_to_type[bus])
 451                         {
 452                                 case MP_BUS_ISA: /* ISA pin */
 453                                 {
 454                                         polarity = default_ISA_polarity(idx);
 455                                         break;
 456                                 }
 457                                 case MP_BUS_EISA: /* EISA pin */
 458                                 {
 459                                         polarity = default_EISA_polarity(idx);
 460                                         break;
 461                                 }
 462                                 case MP_BUS_PCI: /* PCI pin */
 463                                 {
 464                                         polarity = default_PCI_polarity(idx);
 465                                         break;
 466                                 }
 467                                 case MP_BUS_MCA: /* MCA pin */
 468                                 {
 469                                         polarity = default_MCA_polarity(idx);
 470                                         break;
 471                                 }
 472                                 default:
 473                                 {
 474                                         printk(KERN_WARNING "broken BIOS!!\n");
 475                                         polarity = 1;
 476                                         break;
 477                                 }
 478                         }
 479                         break;
 480                 }
 481                 case 1: /* high active */
 482                 {
 483                         polarity = 0;
 484                         break;
 485                 }
 486                 case 2: /* reserved */
 487                 {
 488                         printk(KERN_WARNING "broken BIOS!!\n");
 489                         polarity = 1;
 490                         break;
 491                 }
 492                 case 3: /* low active */
 493                 {
 494                         polarity = 1;
 495                         break;
 496                 }
 497                 default: /* invalid */
 498                 {
 499                         printk(KERN_WARNING "broken BIOS!!\n");
 500                         polarity = 1;
 501                         break;
 502                 }
 503         }
 504         return polarity;
 505 }
 506
 507 static int __init MPBIOS_trigger(int idx)
 508 {
 509         int bus = mp_irqs[idx].mpc_srcbus;
 510         int trigger;
 511
 512         /*
 513          * Determine IRQ trigger mode (edge or level sensitive):
 514          */
 515         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 516         {
 517                 case 0: /* conforms, ie. bus-type dependent */
 518                 {
 519                         switch (mp_bus_id_to_type[bus])
 520                         {
 521                                 case MP_BUS_ISA: /* ISA pin */
 522                                 {
 523                                         trigger = default_ISA_trigger(idx);
 524                                         break;
 525                                 }
 526                                 case MP_BUS_EISA: /* EISA pin */
 527                                 {
 528                                         trigger = default_EISA_trigger(idx);
 529                                         break;
 530                                 }
 531                                 case MP_BUS_PCI: /* PCI pin */
 532                                 {
 533                                         trigger = default_PCI_trigger(idx);
 534                                         break;
 535                                 }
 536                                 case MP_BUS_MCA: /* MCA pin */
 537                                 {
 538                                         trigger = default_MCA_trigger(idx);
 539                                         break;
 540                                 }
 541                                 default:
 542                                 {
 543                                         printk(KERN_WARNING "broken BIOS!!\n");
 544                                         trigger = 1;
 545                                         break;
 546                                 }
 547                         }
 548                         break;
 549                 }
 550                 case 1: /* edge */
 551                 {
 552                         trigger = 0;
 553                         break;
 554                 }
 555                 case 2: /* reserved */
 556                 {
 557                         printk(KERN_WARNING "broken BIOS!!\n");
 558                         trigger = 1;
 559                         break;
 560                 }
 561                 case 3: /* level */
 562                 {
 563                         trigger = 1;
 564                         break;
 565                 }
 566                 default: /* invalid */
 567                 {
 568                         printk(KERN_WARNING "broken BIOS!!\n");
 569                         trigger = 0;
 570                         break;
 571                 }
 572         }
 573         return trigger;
 574 }
 575
 576 static inline int irq_polarity(int idx)
 577 {
 578         return MPBIOS_polarity(idx);
 579 }
 580
 581 static inline int irq_trigger(int idx)
 582 {
 583         return MPBIOS_trigger(idx);
 584 }
 585
 586 static int pin_2_irq(int idx, int apic, int pin)
 587 {
 588         int irq, i;
 589         int bus = mp_irqs[idx].mpc_srcbus;
 590
 591         /*
 592          * Debugging check, we are in big trouble if this message pops up!
 593          */
 594         if (mp_irqs[idx].mpc_dstirq != pin)
 595                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 596
 597         switch (mp_bus_id_to_type[bus])
 598         {
 599                 case MP_BUS_ISA: /* ISA pin */
 600                 case MP_BUS_EISA:
 601                 case MP_BUS_MCA:
 602                 {
 603                         irq = mp_irqs[idx].mpc_srcbusirq;
 604                         break;
 605                 }
 606                 case MP_BUS_PCI: /* PCI pin */
 607                 {
 608                         /*
 609                          * PCI IRQs are mapped in order
 610                          */
 611                         i = irq = 0;
 612                         while (i < apic)
 613                                 irq += nr_ioapic_registers[i++];
 614                         irq += pin;
 615                         break;
 616                 }
 617                 default:
 618                 {
 619                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 620                         irq = 0;
 621                         break;
 622                 }
 623         }
 624
 625         /*
 626          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 627          */
 628         if ((pin >= 16) && (pin <= 23)) {
 629                 if (pirq_entries[pin-16] != -1) {
 630                         if (!pirq_entries[pin-16]) {
 631                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 632                         } else {
 633                                 irq = pirq_entries[pin-16];
 634                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 635                                                 pin-16, irq);
 636                         }
 637                 }
 638         }
 639         return irq;
 640 }
 641
 642 static inline int IO_APIC_irq_trigger(int irq)
 643 {
 644         int apic, idx, pin;
 645
 646         for (apic = 0; apic < nr_ioapics; apic++) {
 647                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 648                         idx = find_irq_entry(apic,pin,mp_INT);
 649                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 650                                 return irq_trigger(idx);
 651                 }
 652         }
 653         /*
 654          * nonexistent IRQs are edge default
 655          */
 656         return 0;
 657 }
 658
 659 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 660 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 661
 662 #ifdef CONFIG_PCI_MSI
 663 int assign_irq_vector(int irq)
 664 #else
 665 int __init assign_irq_vector(int irq)
 666 #endif
 667 {
 668         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 669
 670         BUG_ON(irq >= NR_IRQ_VECTORS);
 671         if (IO_APIC_VECTOR(irq) > 0)
 672                 return IO_APIC_VECTOR(irq);
 673 next:
 674         current_vector += 8;
 675         if (current_vector == IA32_SYSCALL_VECTOR)
 676                 goto next;
 677
 678         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 679                 offset++;
 680                 if (!(offset%8))
 681                         return -ENOSPC;
 682                 current_vector = FIRST_DEVICE_VECTOR + offset;
 683         }
 684
 685         vector_irq[current_vector] = irq;
 686         if (irq != AUTO_ASSIGN)
 687                 IO_APIC_VECTOR(irq) = current_vector;
 688
 689         return current_vector;
 690 }
 691
 692 extern void (*interrupt[NR_IRQS])(void);
 693 static struct hw_interrupt_type ioapic_level_type;
 694 static struct hw_interrupt_type ioapic_edge_type;
 695
 696 #define IOAPIC_AUTO     -1
 697 #define IOAPIC_EDGE     0
 698 #define IOAPIC_LEVEL    1
 699
 700 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 701 {
 702         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 703                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 704                                 trigger == IOAPIC_LEVEL)
 705                         irq_desc[vector].handler = &ioapic_level_type;
 706                 else
 707                         irq_desc[vector].handler = &ioapic_edge_type;
 708                 set_intr_gate(vector, interrupt[vector]);
 709         } else  {
 710                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 711                                 trigger == IOAPIC_LEVEL)
 712                         irq_desc[irq].handler = &ioapic_level_type;
 713                 else
 714                         irq_desc[irq].handler = &ioapic_edge_type;
 715                 set_intr_gate(vector, interrupt[irq]);
 716         }
 717 }
 718
 719 void __init setup_IO_APIC_irqs(void)
 720 {
 721         struct IO_APIC_route_entry entry;
 722         int apic, pin, idx, irq, first_notcon = 1, vector;
 723         unsigned long flags;
 724
 725         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 726
 727         for (apic = 0; apic < nr_ioapics; apic++) {
 728         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 729
 730                 /*
 731                  * add it to the IO-APIC irq-routing table:
 732                  */
 733                 memset(&entry,0,sizeof(entry));
 734
 735                 entry.delivery_mode = dest_LowestPrio;
 736                 entry.dest_mode = INT_DELIVERY_MODE;
 737                 entry.mask = 0;                         /* enable IRQ */
 738                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 739
 740                 idx = find_irq_entry(apic,pin,mp_INT);
 741                 if (idx == -1) {
 742                         if (first_notcon) {
 743                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 744                                 first_notcon = 0;
 745                         } else
 746                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 747                         continue;
 748                 }
 749
 750                 entry.trigger = irq_trigger(idx);
 751                 entry.polarity = irq_polarity(idx);
 752
 753                 if (irq_trigger(idx)) {
 754                         entry.trigger = 1;
 755                         entry.mask = 1;
 756                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 757                 }
 758
 759                 irq = pin_2_irq(idx, apic, pin);
 760                 add_pin_to_irq(irq, apic, pin);
 761
 762                 if (!apic && !IO_APIC_IRQ(irq))
 763                         continue;
 764
 765                 if (IO_APIC_IRQ(irq)) {
 766                         vector = assign_irq_vector(irq);
 767                         entry.vector = vector;
 768
 769                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 770                         if (!apic && (irq < 16))
 771                                 disable_8259A_irq(irq);
 772                 }
 773                 spin_lock_irqsave(&ioapic_lock, flags);
 774                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 775                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 776                 spin_unlock_irqrestore(&ioapic_lock, flags);
 777         }
 778         }
 779
 780         if (!first_notcon)
 781                 apic_printk(APIC_VERBOSE," not connected.\n");
 782 }
 783
 784 /*
 785  * Set up the 8259A-master output pin as broadcast to all
 786  * CPUs.
 787  */
 788 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 789 {
 790         struct IO_APIC_route_entry entry;
 791         unsigned long flags;
 792
 793         memset(&entry,0,sizeof(entry));
 794
 795         disable_8259A_irq(0);
 796
 797         /* mask LVT0 */
 798         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 799
 800         /*
 801          * We use logical delivery to get the timer IRQ
 802          * to the first CPU.
 803          */
 804         entry.dest_mode = INT_DELIVERY_MODE;
 805         entry.mask = 0;                                 /* unmask IRQ now */
 806         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 807         entry.delivery_mode = dest_LowestPrio;
 808         entry.polarity = 0;
 809         entry.trigger = 0;
 810         entry.vector = vector;
 811
 812         /*
 813          * The timer IRQ doesn't have to know that behind the
 814          * scene we have a 8259A-master in AEOI mode ...
 815          */
 816         irq_desc[0].handler = &ioapic_edge_type;
 817
 818         /*
 819          * Add it to the IO-APIC irq-routing table:
 820          */
 821         spin_lock_irqsave(&ioapic_lock, flags);
 822         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 823         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 824         spin_unlock_irqrestore(&ioapic_lock, flags);
 825
 826         enable_8259A_irq(0);
 827 }
 828
 829 void __init UNEXPECTED_IO_APIC(void)
 830 {
 831 }
 832
 833 void __apicdebuginit print_IO_APIC(void)
 834 {
 835         int apic, i;
 836         union IO_APIC_reg_00 reg_00;
 837         union IO_APIC_reg_01 reg_01;
 838         union IO_APIC_reg_02 reg_02;
 839         unsigned long flags;
 840
 841         if (apic_verbosity == APIC_QUIET)
 842                 return;
 843
 844         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 845         for (i = 0; i < nr_ioapics; i++)
 846                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 847                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 848
 849         /*
 850          * We are a bit conservative about what we expect.  We have to
 851          * know about every hardware change ASAP.
 852          */
 853         printk(KERN_INFO "testing the IO APIC.......................\n");
 854
 855         for (apic = 0; apic < nr_ioapics; apic++) {
 856
 857         spin_lock_irqsave(&ioapic_lock, flags);
 858         reg_00.raw = io_apic_read(apic, 0);
 859         reg_01.raw = io_apic_read(apic, 1);
 860         if (reg_01.bits.version >= 0x10)
 861                 reg_02.raw = io_apic_read(apic, 2);
 862         spin_unlock_irqrestore(&ioapic_lock, flags);
 863
 864         printk("\n");
 865         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 866         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 867         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 868         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 869                 UNEXPECTED_IO_APIC();
 870
 871         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 872         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 873         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 874                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 875                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 876                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 877                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 878                 (reg_01.bits.entries != 0x2E) &&
 879                 (reg_01.bits.entries != 0x3F) &&
 880                 (reg_01.bits.entries != 0x03)
 881         )
 882                 UNEXPECTED_IO_APIC();
 883
 884         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 885         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 886         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 887                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 888                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 889                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 890                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 891                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 892         )
 893                 UNEXPECTED_IO_APIC();
 894         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 895                 UNEXPECTED_IO_APIC();
 896
 897         if (reg_01.bits.version >= 0x10) {
 898                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 899                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 900                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 901                         UNEXPECTED_IO_APIC();
 902         }
 903
 904         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 905
 906         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 907                           " Stat Dest Deli Vect:   \n");
 908
 909         for (i = 0; i <= reg_01.bits.entries; i++) {
 910                 struct IO_APIC_route_entry entry;
 911
 912                 spin_lock_irqsave(&ioapic_lock, flags);
 913                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 914                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 915                 spin_unlock_irqrestore(&ioapic_lock, flags);
 916
 917                 printk(KERN_DEBUG " %02x %03X %02X  ",
 918                         i,
 919                         entry.dest.logical.logical_dest,
 920                         entry.dest.physical.physical_dest
 921                 );
 922
 923                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 924                         entry.mask,
 925                         entry.trigger,
 926                         entry.irr,
 927                         entry.polarity,
 928                         entry.delivery_status,
 929                         entry.dest_mode,
 930                         entry.delivery_mode,
 931                         entry.vector
 932                 );
 933         }
 934         }
 935         if (use_pci_vector())
 936                 printk(KERN_INFO "Using vector-based indexing\n");
 937         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 938         for (i = 0; i < NR_IRQS; i++) {
 939                 struct irq_pin_list *entry = irq_2_pin + i;
 940                 if (entry->pin < 0)
 941                         continue;
 942                 if (use_pci_vector() && !platform_legacy_irq(i))
 943                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 944                 else
 945                         printk(KERN_DEBUG "IRQ%d ", i);
 946                 for (;;) {
 947                         printk("-> %d:%d", entry->apic, entry->pin);
 948                         if (!entry->next)
 949                                 break;
 950                         entry = irq_2_pin + entry->next;
 951                 }
 952                 printk("\n");
 953         }
 954
 955         printk(KERN_INFO ".................................... done.\n");
 956
 957         return;
 958 }
 959
 960 static __apicdebuginit void print_APIC_bitfield (int base)
 961 {
 962         unsigned int v;
 963         int i, j;
 964
 965         if (apic_verbosity == APIC_QUIET)
 966                 return;
 967
 968         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 969         for (i = 0; i < 8; i++) {
 970                 v = apic_read(base + i*0x10);
 971                 for (j = 0; j < 32; j++) {
 972                         if (v & (1<<j))
 973                                 printk("1");
 974                         else
 975                                 printk("0");
 976                 }
 977                 printk("\n");
 978         }
 979 }
 980
 981 void __apicdebuginit print_local_APIC(void * dummy)
 982 {
 983         unsigned int v, ver, maxlvt;
 984
 985         if (apic_verbosity == APIC_QUIET)
 986                 return;
 987
 988         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 989                 smp_processor_id(), hard_smp_processor_id());
 990         v = apic_read(APIC_ID);
 991         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 992         v = apic_read(APIC_LVR);
 993         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 994         ver = GET_APIC_VERSION(v);
 995         maxlvt = get_maxlvt();
 996
 997         v = apic_read(APIC_TASKPRI);
 998         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 999
1000         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1001                 v = apic_read(APIC_ARBPRI);
1002                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1003                         v & APIC_ARBPRI_MASK);
1004                 v = apic_read(APIC_PROCPRI);
1005                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1006         }
1007
1008         v = apic_read(APIC_EOI);
1009         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1010         v = apic_read(APIC_RRR);
1011         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1012         v = apic_read(APIC_LDR);
1013         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1014         v = apic_read(APIC_DFR);
1015         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1016         v = apic_read(APIC_SPIV);
1017         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1018
1019         printk(KERN_DEBUG "... APIC ISR field:\n");
1020         print_APIC_bitfield(APIC_ISR);
1021         printk(KERN_DEBUG "... APIC TMR field:\n");
1022         print_APIC_bitfield(APIC_TMR);
1023         printk(KERN_DEBUG "... APIC IRR field:\n");
1024         print_APIC_bitfield(APIC_IRR);
1025
1026         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1027                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1028                         apic_write(APIC_ESR, 0);
1029                 v = apic_read(APIC_ESR);
1030                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1031         }
1032
1033         v = apic_read(APIC_ICR);
1034         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1035         v = apic_read(APIC_ICR2);
1036         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1037
1038         v = apic_read(APIC_LVTT);
1039         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1040
1041         if (maxlvt > 3) {                       /* PC is LVT#4. */
1042                 v = apic_read(APIC_LVTPC);
1043                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1044         }
1045         v = apic_read(APIC_LVT0);
1046         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1047         v = apic_read(APIC_LVT1);
1048         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1049
1050         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1051                 v = apic_read(APIC_LVTERR);
1052                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1053         }
1054
1055         v = apic_read(APIC_TMICT);
1056         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1057         v = apic_read(APIC_TMCCT);
1058         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1059         v = apic_read(APIC_TDCR);
1060         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1061         printk("\n");
1062 }
1063
1064 void print_all_local_APICs (void)
1065 {
1066         on_each_cpu(print_local_APIC, NULL, 1, 1);
1067 }
1068
1069 void __apicdebuginit print_PIC(void)
1070 {
1071         extern spinlock_t i8259A_lock;
1072         unsigned int v;
1073         unsigned long flags;
1074
1075         if (apic_verbosity == APIC_QUIET)
1076                 return;
1077
1078         printk(KERN_DEBUG "\nprinting PIC contents\n");
1079
1080         spin_lock_irqsave(&i8259A_lock, flags);
1081
1082         v = inb(0xa1) << 8 | inb(0x21);
1083         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1084
1085         v = inb(0xa0) << 8 | inb(0x20);
1086         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1087
1088         outb(0x0b,0xa0);
1089         outb(0x0b,0x20);
1090         v = inb(0xa0) << 8 | inb(0x20);
1091         outb(0x0a,0xa0);
1092         outb(0x0a,0x20);
1093
1094         spin_unlock_irqrestore(&i8259A_lock, flags);
1095
1096         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1097
1098         v = inb(0x4d1) << 8 | inb(0x4d0);
1099         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1100 }
1101
1102 static void __init enable_IO_APIC(void)
1103 {
1104         union IO_APIC_reg_01 reg_01;
1105         int i;
1106         unsigned long flags;
1107
1108         for (i = 0; i < PIN_MAP_SIZE; i++) {
1109                 irq_2_pin[i].pin = -1;
1110                 irq_2_pin[i].next = 0;
1111         }
1112         if (!pirqs_enabled)
1113                 for (i = 0; i < MAX_PIRQS; i++)
1114                         pirq_entries[i] = -1;
1115
1116         /*
1117          * The number of IO-APIC IRQ registers (== #pins):
1118          */
1119         for (i = 0; i < nr_ioapics; i++) {
1120                 spin_lock_irqsave(&ioapic_lock, flags);
1121                 reg_01.raw = io_apic_read(i, 1);
1122                 spin_unlock_irqrestore(&ioapic_lock, flags);
1123                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1124         }
1125
1126         /*
1127          * Do not trust the IO-APIC being empty at bootup
1128          */
1129         clear_IO_APIC();
1130 }
1131
1132 /*
1133  * Not an __init, needed by the reboot code
1134  */
1135 void disable_IO_APIC(void)
1136 {
1137         /*
1138          * Clear the IO-APIC before rebooting:
1139          */
1140         clear_IO_APIC();
1141
1142         disconnect_bsp_APIC();
1143 }
1144
1145 /*
1146  * function to set the IO-APIC physical IDs based on the
1147  * values stored in the MPC table.
1148  *
1149  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1150  */
1151
1152 static void __init setup_ioapic_ids_from_mpc (void)
1153 {
1154         union IO_APIC_reg_00 reg_00;
1155         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1156         int apic;
1157         int i;
1158         unsigned char old_id;
1159         unsigned long flags;
1160
1161         /*
1162          * Set the IOAPIC ID to the value stored in the MPC table.
1163          */
1164         for (apic = 0; apic < nr_ioapics; apic++) {
1165
1166                 /* Read the register 0 value */
1167                 spin_lock_irqsave(&ioapic_lock, flags);
1168                 reg_00.raw = io_apic_read(apic, 0);
1169                 spin_unlock_irqrestore(&ioapic_lock, flags);
1170
1171                 old_id = mp_ioapics[apic].mpc_apicid;
1172
1173                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1174                         apic_printk(APIC_QUIET,KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1175                                 apic, mp_ioapics[apic].mpc_apicid);
1176                         apic_printk(APIC_QUIET,KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1177                                 reg_00.bits.ID);
1178                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1179                 }
1180
1181                 /*
1182                  * Sanity check, is the ID really free? Every APIC in a
1183                  * system must have a unique ID or we get lots of nice
1184                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1185                  */
1186                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1187                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1188                                 apic, mp_ioapics[apic].mpc_apicid);
1189                         for (i = 0; i < 0xf; i++)
1190                                 if (!physid_isset(i, phys_id_present_map))
1191                                         break;
1192                         if (i >= 0xf)
1193                                 panic("Max APIC ID exceeded!\n");
1194                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1195                                 i);
1196                         physid_set(i, phys_id_present_map);
1197                         mp_ioapics[apic].mpc_apicid = i;
1198                 } else {
1199                         printk(KERN_INFO
1200                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1201                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1202                 }
1203
1204
1205                 /*
1206                  * We need to adjust the IRQ routing table
1207                  * if the ID changed.
1208                  */
1209                 if (old_id != mp_ioapics[apic].mpc_apicid)
1210                         for (i = 0; i < mp_irq_entries; i++)
1211                                 if (mp_irqs[i].mpc_dstapic == old_id)
1212                                         mp_irqs[i].mpc_dstapic
1213                                                 = mp_ioapics[apic].mpc_apicid;
1214
1215                 /*
1216                  * Read the right value from the MPC table and
1217                  * write it into the ID register.
1218                  */
1219                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1220                                 mp_ioapics[apic].mpc_apicid);
1221
1222                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1223                 spin_lock_irqsave(&ioapic_lock, flags);
1224                 io_apic_write(apic, 0, reg_00.raw);
1225                 spin_unlock_irqrestore(&ioapic_lock, flags);
1226
1227                 /*
1228                  * Sanity check
1229                  */
1230                 spin_lock_irqsave(&ioapic_lock, flags);
1231                 reg_00.raw = io_apic_read(apic, 0);
1232                 spin_unlock_irqrestore(&ioapic_lock, flags);
1233                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1234                         printk("could not set ID!\n");
1235                 else
1236                         apic_printk(APIC_VERBOSE," ok.\n");
1237         }
1238 }
1239
1240 /*
1241  * There is a nasty bug in some older SMP boards, their mptable lies
1242  * about the timer IRQ. We do the following to work around the situation:
1243  *
1244  *      - timer IRQ defaults to IO-APIC IRQ
1245  *      - if this function detects that timer IRQs are defunct, then we fall
1246  *        back to ISA timer IRQs
1247  */
1248 static int __init timer_irq_works(void)
1249 {
1250         unsigned long t1 = jiffies;
1251
1252         local_irq_enable();
1253         /* Let ten ticks pass... */
1254         mdelay((10 * 1000) / HZ);
1255
1256         /*
1257          * Expect a few ticks at least, to be sure some possible
1258          * glue logic does not lock up after one or two first
1259          * ticks in a non-ExtINT mode.  Also the local APIC
1260          * might have cached one ExtINT interrupt.  Finally, at
1261          * least one tick may be lost due to delays.
1262          */
1263
1264         /* jiffies wrap? */
1265         if (jiffies - t1 > 4)
1266                 return 1;
1267         return 0;
1268 }
1269
1270 /*
1271  * In the SMP+IOAPIC case it might happen that there are an unspecified
1272  * number of pending IRQ events unhandled. These cases are very rare,
1273  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1274  * better to do it this way as thus we do not have to be aware of
1275  * 'pending' interrupts in the IRQ path, except at this point.
1276  */
1277 /*
1278  * Edge triggered needs to resend any interrupt
1279  * that was delayed but this is now handled in the device
1280  * independent code.
1281  */
1282
1283 /*
1284  * Starting up a edge-triggered IO-APIC interrupt is
1285  * nasty - we need to make sure that we get the edge.
1286  * If it is already asserted for some reason, we need
1287  * return 1 to indicate that is was pending.
1288  *
1289  * This is not complete - we should be able to fake
1290  * an edge even if it isn't on the 8259A...
1291  */
1292
1293 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1294 {
1295         int was_pending = 0;
1296         unsigned long flags;
1297
1298         spin_lock_irqsave(&ioapic_lock, flags);
1299         if (irq < 16) {
1300                 disable_8259A_irq(irq);
1301                 if (i8259A_irq_pending(irq))
1302                         was_pending = 1;
1303         }
1304         __unmask_IO_APIC_irq(irq);
1305         spin_unlock_irqrestore(&ioapic_lock, flags);
1306
1307         return was_pending;
1308 }
1309
1310 /*
1311  * Once we have recorded IRQ_PENDING already, we can mask the
1312  * interrupt for real. This prevents IRQ storms from unhandled
1313  * devices.
1314  */
1315 static void ack_edge_ioapic_irq(unsigned int irq)
1316 {
1317         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1318                                         == (IRQ_PENDING | IRQ_DISABLED))
1319                 mask_IO_APIC_irq(irq);
1320         ack_APIC_irq();
1321 }
1322
1323 /*
1324  * Level triggered interrupts can just be masked,
1325  * and shutting down and starting up the interrupt
1326  * is the same as enabling and disabling them -- except
1327  * with a startup need to return a "was pending" value.
1328  *
1329  * Level triggered interrupts are special because we
1330  * do not touch any IO-APIC register while handling
1331  * them. We ack the APIC in the end-IRQ handler, not
1332  * in the start-IRQ-handler. Protection against reentrance
1333  * from the same interrupt is still provided, both by the
1334  * generic IRQ layer and by the fact that an unacked local
1335  * APIC does not accept IRQs.
1336  */
1337 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1338 {
1339         unmask_IO_APIC_irq(irq);
1340
1341         return 0; /* don't check for pending */
1342 }
1343
1344 static void end_level_ioapic_irq (unsigned int irq)
1345 {
1346         unsigned long v;
1347         int i;
1348
1349 /*
1350  * It appears there is an erratum which affects at least version 0x11
1351  * of I/O APIC (that's the 82093AA and cores integrated into various
1352  * chipsets).  Under certain conditions a level-triggered interrupt is
1353  * erroneously delivered as edge-triggered one but the respective IRR
1354  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1355  * message but it will never arrive and further interrupts are blocked
1356  * from the source.  The exact reason is so far unknown, but the
1357  * phenomenon was observed when two consecutive interrupt requests
1358  * from a given source get delivered to the same CPU and the source is
1359  * temporarily disabled in between.
1360  *
1361  * A workaround is to simulate an EOI message manually.  We achieve it
1362  * by setting the trigger mode to edge and then to level when the edge
1363  * trigger mode gets detected in the TMR of a local APIC for a
1364  * level-triggered interrupt.  We mask the source for the time of the
1365  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1366  * The idea is from Manfred Spraul.  --macro
1367  */
1368         i = IO_APIC_VECTOR(irq);
1369         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1370
1371         ack_APIC_irq();
1372
1373         if (!(v & (1 << (i & 0x1f)))) {
1374 #ifdef APIC_LOCKUP_DEBUG
1375                 struct irq_pin_list *entry;
1376 #endif
1377
1378 #ifdef APIC_MISMATCH_DEBUG
1379                 atomic_inc(&irq_mis_count);
1380 #endif
1381                 spin_lock(&ioapic_lock);
1382                 __mask_and_edge_IO_APIC_irq(irq);
1383 #ifdef APIC_LOCKUP_DEBUG
1384                 for (entry = irq_2_pin + irq;;) {
1385                         unsigned int reg;
1386
1387                         if (entry->pin == -1)
1388                                 break;
1389                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1390                         if (reg & 0x00004000)
1391                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1392                                         " still set after unlock!\n");
1393                         if (!entry->next)
1394                                 break;
1395                         entry = irq_2_pin + entry->next;
1396                 }
1397 #endif
1398                 __unmask_and_level_IO_APIC_irq(irq);
1399                 spin_unlock(&ioapic_lock);
1400         }
1401 }
1402
1403 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1404 {
1405         unsigned long flags;
1406         unsigned int dest;
1407
1408         dest = cpu_mask_to_apicid(mask);
1409
1410         /*
1411          * Only the first 8 bits are valid.
1412          */
1413         dest = dest << 24;
1414
1415         spin_lock_irqsave(&ioapic_lock, flags);
1416         __DO_ACTION(1, = dest, )
1417         spin_unlock_irqrestore(&ioapic_lock, flags);
1418 }
1419
1420 #ifdef CONFIG_PCI_MSI
1421 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1422 {
1423         int irq = vector_to_irq(vector);
1424
1425         return startup_edge_ioapic_irq(irq);
1426 }
1427
1428 static void ack_edge_ioapic_vector(unsigned int vector)
1429 {
1430         int irq = vector_to_irq(vector);
1431
1432         ack_edge_ioapic_irq(irq);
1433 }
1434
1435 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1436 {
1437         int irq = vector_to_irq(vector);
1438
1439         return startup_level_ioapic_irq (irq);
1440 }
1441
1442 static void end_level_ioapic_vector (unsigned int vector)
1443 {
1444         int irq = vector_to_irq(vector);
1445
1446         end_level_ioapic_irq(irq);
1447 }
1448
1449 static void mask_IO_APIC_vector (unsigned int vector)
1450 {
1451         int irq = vector_to_irq(vector);
1452
1453         mask_IO_APIC_irq(irq);
1454 }
1455
1456 static void unmask_IO_APIC_vector (unsigned int vector)
1457 {
1458         int irq = vector_to_irq(vector);
1459
1460         unmask_IO_APIC_irq(irq);
1461 }
1462
1463 static void set_ioapic_affinity_vector (unsigned int vector,
1464                                         cpumask_t cpu_mask)
1465 {
1466         int irq = vector_to_irq(vector);
1467
1468         set_ioapic_affinity_irq(irq, cpu_mask);
1469 }
1470 #endif
1471
1472 /*
1473  * Level and edge triggered IO-APIC interrupts need different handling,
1474  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1475  * handled with the level-triggered descriptor, but that one has slightly
1476  * more overhead. Level-triggered interrupts cannot be handled with the
1477  * edge-triggered handler, without risking IRQ storms and other ugly
1478  * races.
1479  */
1480
1481 static struct hw_interrupt_type ioapic_edge_type = {
1482         .typename = "IO-APIC-edge",
1483         .startup        = startup_edge_ioapic,
1484         .shutdown       = shutdown_edge_ioapic,
1485         .enable         = enable_edge_ioapic,
1486         .disable        = disable_edge_ioapic,
1487         .ack            = ack_edge_ioapic,
1488         .end            = end_edge_ioapic,
1489         .set_affinity = set_ioapic_affinity,
1490 };
1491
1492 static struct hw_interrupt_type ioapic_level_type = {
1493         .typename = "IO-APIC-level",
1494         .startup        = startup_level_ioapic,
1495         .shutdown       = shutdown_level_ioapic,
1496         .enable         = enable_level_ioapic,
1497         .disable        = disable_level_ioapic,
1498         .ack            = mask_and_ack_level_ioapic,
1499         .end            = end_level_ioapic,
1500         .set_affinity = set_ioapic_affinity,
1501 };
1502
1503 static inline void init_IO_APIC_traps(void)
1504 {
1505         int irq;
1506
1507         /*
1508          * NOTE! The local APIC isn't very good at handling
1509          * multiple interrupts at the same interrupt level.
1510          * As the interrupt level is determined by taking the
1511          * vector number and shifting that right by 4, we
1512          * want to spread these out a bit so that they don't
1513          * all fall in the same interrupt level.
1514          *
1515          * Also, we've got to be careful not to trash gate
1516          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1517          */
1518         for (irq = 0; irq < NR_IRQS ; irq++) {
1519                 int tmp = irq;
1520                 if (use_pci_vector()) {
1521                         if (!platform_legacy_irq(tmp))
1522                                 if ((tmp = vector_to_irq(tmp)) == -1)
1523                                         continue;
1524                 }
1525                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1526                         /*
1527                          * Hmm.. We don't have an entry for this,
1528                          * so default to an old-fashioned 8259
1529                          * interrupt if we can..
1530                          */
1531                         if (irq < 16)
1532                                 make_8259A_irq(irq);
1533                         else
1534                                 /* Strange. Oh, well.. */
1535                                 irq_desc[irq].handler = &no_irq_type;
1536                 }
1537         }
1538 }
1539
1540 static void enable_lapic_irq (unsigned int irq)
1541 {
1542         unsigned long v;
1543
1544         v = apic_read(APIC_LVT0);
1545         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1546 }
1547
1548 static void disable_lapic_irq (unsigned int irq)
1549 {
1550         unsigned long v;
1551
1552         v = apic_read(APIC_LVT0);
1553         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1554 }
1555
1556 static void ack_lapic_irq (unsigned int irq)
1557 {
1558         ack_APIC_irq();
1559 }
1560
1561 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1562
1563 static struct hw_interrupt_type lapic_irq_type = {
1564         .typename = "local-APIC-edge",
1565         .startup = NULL, /* startup_irq() not used for IRQ0 */
1566         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1567         .enable = enable_lapic_irq,
1568         .disable = disable_lapic_irq,
1569         .ack = ack_lapic_irq,
1570         .end = end_lapic_irq,
1571 };
1572
1573 static void setup_nmi (void)
1574 {
1575         /*
1576          * Dirty trick to enable the NMI watchdog ...
1577          * We put the 8259A master into AEOI mode and
1578          * unmask on all local APICs LVT0 as NMI.
1579          *
1580          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1581          * is from Maciej W. Rozycki - so we do not have to EOI from
1582          * the NMI handler or the timer interrupt.
1583          */
1584         printk(KERN_INFO "activating NMI Watchdog ...");
1585
1586         enable_NMI_through_LVT0(NULL);
1587
1588         printk(" done.\n");
1589 }
1590
1591 /*
1592  * This looks a bit hackish but it's about the only one way of sending
1593  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1594  * not support the ExtINT mode, unfortunately.  We need to send these
1595  * cycles as some i82489DX-based boards have glue logic that keeps the
1596  * 8259A interrupt line asserted until INTA.  --macro
1597  */
1598 static inline void unlock_ExtINT_logic(void)
1599 {
1600         int pin, i;
1601         struct IO_APIC_route_entry entry0, entry1;
1602         unsigned char save_control, save_freq_select;
1603         unsigned long flags;
1604
1605         pin = find_isa_irq_pin(8, mp_INT);
1606         if (pin == -1)
1607                 return;
1608
1609         spin_lock_irqsave(&ioapic_lock, flags);
1610         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1611         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1612         spin_unlock_irqrestore(&ioapic_lock, flags);
1613         clear_IO_APIC_pin(0, pin);
1614
1615         memset(&entry1, 0, sizeof(entry1));
1616
1617         entry1.dest_mode = 0;                   /* physical delivery */
1618         entry1.mask = 0;                        /* unmask IRQ now */
1619         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1620         entry1.delivery_mode = dest_ExtINT;
1621         entry1.polarity = entry0.polarity;
1622         entry1.trigger = 0;
1623         entry1.vector = 0;
1624
1625         spin_lock_irqsave(&ioapic_lock, flags);
1626         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1627         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1628         spin_unlock_irqrestore(&ioapic_lock, flags);
1629
1630         save_control = CMOS_READ(RTC_CONTROL);
1631         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1632         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1633                    RTC_FREQ_SELECT);
1634         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1635
1636         i = 100;
1637         while (i-- > 0) {
1638                 mdelay(10);
1639                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1640                         i -= 10;
1641         }
1642
1643         CMOS_WRITE(save_control, RTC_CONTROL);
1644         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1645         clear_IO_APIC_pin(0, pin);
1646
1647         spin_lock_irqsave(&ioapic_lock, flags);
1648         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1649         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1650         spin_unlock_irqrestore(&ioapic_lock, flags);
1651 }
1652
1653 /*
1654  * This code may look a bit paranoid, but it's supposed to cooperate with
1655  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1656  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1657  * fanatically on his truly buggy board.
1658  */
1659 static inline void check_timer(void)
1660 {
1661         int pin1, pin2;
1662         int vector;
1663
1664         /*
1665          * get/set the timer IRQ vector:
1666          */
1667         disable_8259A_irq(0);
1668         vector = assign_irq_vector(0);
1669         set_intr_gate(vector, interrupt[0]);
1670
1671         /*
1672          * Subtle, code in do_timer_interrupt() expects an AEOI
1673          * mode for the 8259A whenever interrupts are routed
1674          * through I/O APICs.  Also IRQ0 has to be enabled in
1675          * the 8259A which implies the virtual wire has to be
1676          * disabled in the local APIC.
1677          */
1678         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1679         init_8259A(1);
1680         enable_8259A_irq(0);
1681
1682         pin1 = find_isa_irq_pin(0, mp_INT);
1683         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1684
1685         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1686
1687         if (pin1 != -1) {
1688                 /*
1689                  * Ok, does IRQ0 through the IOAPIC work?
1690                  */
1691                 unmask_IO_APIC_irq(0);
1692                 if (timer_irq_works()) {
1693                         nmi_watchdog_default();
1694                         if (nmi_watchdog == NMI_IO_APIC) {
1695                                 disable_8259A_irq(0);
1696                                 setup_nmi();
1697                                 enable_8259A_irq(0);
1698                                 check_nmi_watchdog();
1699                         }
1700                         return;
1701                 }
1702                 clear_IO_APIC_pin(0, pin1);
1703                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1704         }
1705
1706         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1707         if (pin2 != -1) {
1708                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1709                 /*
1710                  * legacy devices should be connected to IO APIC #0
1711                  */
1712                 setup_ExtINT_IRQ0_pin(pin2, vector);
1713                 if (timer_irq_works()) {
1714                         printk("works.\n");
1715                         nmi_watchdog_default();
1716                         if (nmi_watchdog == NMI_IO_APIC) {
1717                                 setup_nmi();
1718                                 check_nmi_watchdog();
1719                         }
1720                         return;
1721                 }
1722                 /*
1723                  * Cleanup, just in case ...
1724                  */
1725                 clear_IO_APIC_pin(0, pin2);
1726         }
1727         printk(" failed.\n");
1728
1729         if (nmi_watchdog) {
1730                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1731                 nmi_watchdog = 0;
1732         }
1733
1734         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1735
1736         disable_8259A_irq(0);
1737         irq_desc[0].handler = &lapic_irq_type;
1738         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1739         enable_8259A_irq(0);
1740
1741         if (timer_irq_works()) {
1742                 apic_printk(APIC_QUIET, " works.\n");
1743                 return;
1744         }
1745         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1746         apic_printk(APIC_VERBOSE," failed.\n");
1747
1748         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1749
1750         init_8259A(0);
1751         make_8259A_irq(0);
1752         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1753
1754         unlock_ExtINT_logic();
1755
1756         if (timer_irq_works()) {
1757                 apic_printk(APIC_VERBOSE," works.\n");
1758                 return;
1759         }
1760         apic_printk(APIC_VERBOSE," failed :(.\n");
1761         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1762 }
1763
1764 /*
1765  *
1766  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1767  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1768  *   Linux doesn't really care, as it's not actually used
1769  *   for any interrupt handling anyway.
1770  */
1771 #define PIC_IRQS        (1<<2)
1772
1773 void __init setup_IO_APIC(void)
1774 {
1775         enable_IO_APIC();
1776
1777         if (acpi_ioapic)
1778                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1779         else
1780                 io_apic_irqs = ~PIC_IRQS;
1781
1782         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1783
1784         /*
1785          * Set up the IO-APIC IRQ routing table.
1786          */
1787         if (!acpi_ioapic)
1788                 setup_ioapic_ids_from_mpc();
1789         sync_Arb_IDs();
1790         setup_IO_APIC_irqs();
1791         init_IO_APIC_traps();
1792         check_timer();
1793         if (!acpi_ioapic)
1794                 print_IO_APIC();
1795 }
1796
1797 struct sysfs_ioapic_data {
1798         struct sys_device dev;
1799         struct IO_APIC_route_entry entry[0];
1800 };
1801 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1802
1803 static int ioapic_suspend(struct sys_device *dev, u32 state)
1804 {
1805         struct IO_APIC_route_entry *entry;
1806         struct sysfs_ioapic_data *data;
1807         unsigned long flags;
1808         int i;
1809
1810         data = container_of(dev, struct sysfs_ioapic_data, dev);
1811         entry = data->entry;
1812         spin_lock_irqsave(&ioapic_lock, flags);
1813         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1814                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1815                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1816         }
1817         spin_unlock_irqrestore(&ioapic_lock, flags);
1818
1819         return 0;
1820 }
1821
1822 static int ioapic_resume(struct sys_device *dev)
1823 {
1824         struct IO_APIC_route_entry *entry;
1825         struct sysfs_ioapic_data *data;
1826         unsigned long flags;
1827         union IO_APIC_reg_00 reg_00;
1828         int i;
1829
1830         data = container_of(dev, struct sysfs_ioapic_data, dev);
1831         entry = data->entry;
1832
1833         spin_lock_irqsave(&ioapic_lock, flags);
1834         reg_00.raw = io_apic_read(dev->id, 0);
1835         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1836                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1837                 io_apic_write(dev->id, 0, reg_00.raw);
1838         }
1839         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1840                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1841                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1842         }
1843         spin_unlock_irqrestore(&ioapic_lock, flags);
1844
1845         return 0;
1846 }
1847
1848 static struct sysdev_class ioapic_sysdev_class = {
1849         set_kset_name("ioapic"),
1850         .suspend = ioapic_suspend,
1851         .resume = ioapic_resume,
1852 };
1853
1854 static int __init ioapic_init_sysfs(void)
1855 {
1856         struct sys_device * dev;
1857         int i, size, error = 0;
1858
1859         error = sysdev_class_register(&ioapic_sysdev_class);
1860         if (error)
1861                 return error;
1862
1863         for (i = 0; i < nr_ioapics; i++ ) {
1864                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1865                         * sizeof(struct IO_APIC_route_entry);
1866                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1867                 if (!mp_ioapic_data[i]) {
1868                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1869                         continue;
1870                 }
1871                 memset(mp_ioapic_data[i], 0, size);
1872                 dev = &mp_ioapic_data[i]->dev;
1873                 dev->id = i;
1874                 dev->cls = &ioapic_sysdev_class;
1875                 error = sysdev_register(dev);
1876                 if (error) {
1877                         kfree(mp_ioapic_data[i]);
1878                         mp_ioapic_data[i] = NULL;
1879                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1880                         continue;
1881                 }
1882         }
1883
1884         return 0;
1885 }
1886
1887 device_initcall(ioapic_init_sysfs);
1888
1889 /* --------------------------------------------------------------------------
1890                           ACPI-based IOAPIC Configuration
1891    -------------------------------------------------------------------------- */
1892
1893 #ifdef CONFIG_ACPI_BOOT
1894
1895 #define IO_APIC_MAX_ID          15
1896
1897 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1898 {
1899         union IO_APIC_reg_00 reg_00;
1900         static physid_mask_t apic_id_map;
1901         unsigned long flags;
1902         int i = 0;
1903
1904         /*
1905          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1906          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1907          * supports up to 16 on one shared APIC bus.
1908          *
1909          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1910          *      advantage of new APIC bus architecture.
1911          */
1912
1913         if (physids_empty(apic_id_map))
1914                 apic_id_map = phys_cpu_present_map;
1915
1916         spin_lock_irqsave(&ioapic_lock, flags);
1917         reg_00.raw = io_apic_read(ioapic, 0);
1918         spin_unlock_irqrestore(&ioapic_lock, flags);
1919
1920         if (apic_id >= IO_APIC_MAX_ID) {
1921                 apic_printk(APIC_QUIET, KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1922                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1923                 apic_id = reg_00.bits.ID;
1924         }
1925
1926         /*
1927          * Every APIC in a system must have a unique ID or we get lots of nice
1928          * 'stuck on smp_invalidate_needed IPI wait' messages.
1929          */
1930         if (physid_isset(apic_id, apic_id_map)) {
1931
1932                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1933                         if (!physid_isset(i, apic_id_map))
1934                                 break;
1935                 }
1936
1937                 if (i == IO_APIC_MAX_ID)
1938                         panic("Max apic_id exceeded!\n");
1939
1940                 apic_printk(APIC_VERBOSE, KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1941                         "trying %d\n", ioapic, apic_id, i);
1942
1943                 apic_id = i;
1944         }
1945
1946         physid_set(apic_id, apic_id_map);
1947
1948         if (reg_00.bits.ID != apic_id) {
1949                 reg_00.bits.ID = apic_id;
1950
1951                 spin_lock_irqsave(&ioapic_lock, flags);
1952                 io_apic_write(ioapic, 0, reg_00.raw);
1953                 reg_00.raw = io_apic_read(ioapic, 0);
1954                 spin_unlock_irqrestore(&ioapic_lock, flags);
1955
1956                 /* Sanity check */
1957                 if (reg_00.bits.ID != apic_id)
1958                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1959         }
1960
1961         apic_printk(APIC_VERBOSE,KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1962
1963         return apic_id;
1964 }
1965
1966
1967 int __init io_apic_get_version (int ioapic)
1968 {
1969         union IO_APIC_reg_01    reg_01;
1970         unsigned long flags;
1971
1972         spin_lock_irqsave(&ioapic_lock, flags);
1973         reg_01.raw = io_apic_read(ioapic, 1);
1974         spin_unlock_irqrestore(&ioapic_lock, flags);
1975
1976         return reg_01.bits.version;
1977 }
1978
1979
1980 int __init io_apic_get_redir_entries (int ioapic)
1981 {
1982         union IO_APIC_reg_01    reg_01;
1983         unsigned long flags;
1984
1985         spin_lock_irqsave(&ioapic_lock, flags);
1986         reg_01.raw = io_apic_read(ioapic, 1);
1987         spin_unlock_irqrestore(&ioapic_lock, flags);
1988
1989         return reg_01.bits.entries;
1990 }
1991
1992
1993 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1994 {
1995         struct IO_APIC_route_entry entry;
1996         unsigned long flags;
1997
1998         if (!IO_APIC_IRQ(irq)) {
1999                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2000                         ioapic);
2001                 return -EINVAL;
2002         }
2003
2004         /*
2005          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2006          * Note that we mask (disable) IRQs now -- these get enabled when the
2007          * corresponding device driver registers for this IRQ.
2008          */
2009
2010         memset(&entry,0,sizeof(entry));
2011
2012         entry.delivery_mode = dest_LowestPrio;
2013         entry.dest_mode = INT_DELIVERY_MODE;
2014         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2015         entry.trigger = edge_level;
2016         entry.polarity = active_high_low;
2017         entry.mask = 1;                                  /* Disabled (masked) */
2018
2019         /*
2020          * IRQs < 16 are already in the irq_2_pin[] map
2021          */
2022         if (irq >= 16)
2023                 add_pin_to_irq(irq, ioapic, pin);
2024
2025         entry.vector = assign_irq_vector(irq);
2026
2027         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2028                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2029                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2030                edge_level, active_high_low);
2031
2032         ioapic_register_intr(irq, entry.vector, edge_level);
2033
2034         if (!ioapic && (irq < 16))
2035                 disable_8259A_irq(irq);
2036
2037         spin_lock_irqsave(&ioapic_lock, flags);
2038         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2039         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2040         spin_unlock_irqrestore(&ioapic_lock, flags);
2041
2042         return 0;
2043 }
2044
2045 #endif /*CONFIG_ACPI_BOOT*/
2046
2047 #ifndef CONFIG_SMP
2048 void send_IPI_self(int vector)
2049 {
2050         unsigned int cfg;
2051
2052        /*
2053         * Wait for idle.
2054         */
2055         apic_wait_icr_idle();
2056         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
2057
2058         /*
2059          * Send the IPI. The write to APIC_ICR fires this off.
2060          */
2061         apic_write_around(APIC_ICR, cfg);
2062 }
2063 #endif
2064
2065
2066 /*
2067  * This function currently is only a helper for the i386 smp boot process where
2068  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2069  * so mask in all cases should simply be TARGET_CPUS
2070  */
2071 void __init setup_ioapic_dest(void)
2072 {
2073         int pin, ioapic, irq, irq_entry;
2074
2075         if (skip_ioapic_setup == 1)
2076                 return;
2077
2078         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2079                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2080                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2081                         if (irq_entry == -1)
2082                                 continue;
2083                         irq = pin_2_irq(irq_entry, ioapic, pin);
2084                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2085                 }
2086
2087         }
2088 }