arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/smp.h>
  36 #include <asm/desc.h>
  37 #include <asm/proto.h>
  38
  39 int sis_apic_bug; /* not actually supported, dummy for compile */
  40
  41 #undef APIC_LOCKUP_DEBUG
  42
  43 #define APIC_LOCKUP_DEBUG
  44
  45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  46
  47 /*
  48  * # of IRQ routing registers
  49  */
  50 int nr_ioapic_registers[MAX_IO_APICS];
  51
  52 /*
  53  * Rough estimation of how many shared IRQs there are, can
  54  * be changed anytime.
  55  */
  56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  58
  59 /*
  60  * This is performance-critical, we want to do it O(1)
  61  *
  62  * the indexing order of this array favors 1:1 mappings
  63  * between pins and IRQs.
  64  */
  65
  66 static struct irq_pin_list {
  67         short apic, pin, next;
  68 } irq_2_pin[PIN_MAP_SIZE];
  69
  70 #ifdef CONFIG_PCI_USE_VECTOR
  71 int vector_irq[NR_IRQS] = { [0 ... NR_IRQS -1] = -1};
  72 #define vector_to_irq(vector)   \
  73         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  74 #else
  75 #define vector_to_irq(vector)   (vector)
  76 #endif
  77
  78 /*
  79  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  80  * shared ISA-space IRQs, so we have to support them. We are super
  81  * fast in the common case, and fast for shared ISA-space IRQs.
  82  */
  83 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  84 {
  85         static int first_free_entry = NR_IRQS;
  86         struct irq_pin_list *entry = irq_2_pin + irq;
  87
  88         while (entry->next)
  89                 entry = irq_2_pin + entry->next;
  90
  91         if (entry->pin != -1) {
  92                 entry->next = first_free_entry;
  93                 entry = irq_2_pin + entry->next;
  94                 if (++first_free_entry >= PIN_MAP_SIZE)
  95                         panic("io_apic.c: whoops");
  96         }
  97         entry->apic = apic;
  98         entry->pin = pin;
  99 }
 100
 101 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 102                                                                         \
 103 {                                                                       \
 104         int pin;                                                        \
 105         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 106                                                                         \
 107         for (;;) {                                                      \
 108                 unsigned int reg;                                       \
 109                 pin = entry->pin;                                       \
 110                 if (pin == -1)                                          \
 111                         break;                                          \
 112                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 113                 reg ACTION;                                             \
 114                 io_apic_modify(entry->apic, reg);                       \
 115                 if (!entry->next)                                       \
 116                         break;                                          \
 117                 entry = irq_2_pin + entry->next;                        \
 118         }                                                               \
 119         FINAL;                                                          \
 120 }
 121
 122 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 123                                                                         \
 124         static void name##_IO_APIC_irq (unsigned int irq)               \
 125         __DO_ACTION(R, ACTION, FINAL)
 126
 127 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 128                                                 /* mask = 1 */
 129 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 130                                                 /* mask = 0 */
 131 DO_ACTION( __mask_and_edge,    0, = (reg & 0xffff7fff) | 0x00010000, )
 132                                                 /* mask = 1, trigger = 0 */
 133 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
 134                                                 /* mask = 0, trigger = 1 */
 135
 136 static void mask_IO_APIC_irq (unsigned int irq)
 137 {
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&ioapic_lock, flags);
 141         __mask_IO_APIC_irq(irq);
 142         spin_unlock_irqrestore(&ioapic_lock, flags);
 143 }
 144
 145 static void unmask_IO_APIC_irq (unsigned int irq)
 146 {
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&ioapic_lock, flags);
 150         __unmask_IO_APIC_irq(irq);
 151         spin_unlock_irqrestore(&ioapic_lock, flags);
 152 }
 153
 154 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 155 {
 156         struct IO_APIC_route_entry entry;
 157         unsigned long flags;
 158
 159         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 160         spin_lock_irqsave(&ioapic_lock, flags);
 161         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 162         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 163         spin_unlock_irqrestore(&ioapic_lock, flags);
 164         if (entry.delivery_mode == dest_SMI)
 165                 return;
 166         /*
 167          * Disable it in the IO-APIC irq-routing table:
 168          */
 169         memset(&entry, 0, sizeof(entry));
 170         entry.mask = 1;
 171         spin_lock_irqsave(&ioapic_lock, flags);
 172         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 173         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 174         spin_unlock_irqrestore(&ioapic_lock, flags);
 175 }
 176
 177 static void clear_IO_APIC (void)
 178 {
 179         int apic, pin;
 180
 181         for (apic = 0; apic < nr_ioapics; apic++)
 182                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 183                         clear_IO_APIC_pin(apic, pin);
 184 }
 185
 186 /*
 187  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 188  * specific CPU-side IRQs.
 189  */
 190
 191 #define MAX_PIRQS 8
 192 int pirq_entries [MAX_PIRQS];
 193 int pirqs_enabled;
 194 int skip_ioapic_setup;
 195 int ioapic_force;
 196
 197 /* dummy parsing: see setup.c */
 198
 199 static int __init disable_ioapic_setup(char *str)
 200 {
 201         skip_ioapic_setup = 1;
 202         return 1;
 203 }
 204
 205 static int __init enable_ioapic_setup(char *str)
 206 {
 207         ioapic_force = 1;
 208         skip_ioapic_setup = 0;
 209         return 1;
 210 }
 211
 212 __setup("noapic", disable_ioapic_setup);
 213 __setup("apic", enable_ioapic_setup);
 214
 215 #include <asm/pci-direct.h>
 216 #include <linux/pci_ids.h>
 217 #include <linux/pci.h>
 218
 219 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 220    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 221    Use pci direct infrastructure because this runs before the PCI subsystem.
 222
 223    Can be overwritten with "apic"
 224
 225    And another hack to disable the IOMMU on VIA chipsets.
 226
 227    Kludge-O-Rama. */
 228 void __init check_ioapic(void)
 229 {
 230         int num,slot,func;
 231         if (ioapic_force)
 232                 return;
 233
 234         /* Poor man's PCI discovery */
 235         for (num = 0; num < 32; num++) {
 236                 for (slot = 0; slot < 32; slot++) {
 237                         for (func = 0; func < 8; func++) {
 238                                 u32 class;
 239                                 u32 vendor;
 240                                 u8 type;
 241                                 class = read_pci_config(num,slot,func,
 242                                                         PCI_CLASS_REVISION);
 243                                 if (class == 0xffffffff)
 244                                         break;
 245
 246                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 247                                         continue;
 248
 249                                 vendor = read_pci_config(num, slot, func,
 250                                                          PCI_VENDOR_ID);
 251                                 vendor &= 0xffff;
 252                                 switch (vendor) {
 253                                 case PCI_VENDOR_ID_VIA:
 254 #ifdef CONFIG_GART_IOMMU
 255                                         if (end_pfn >= (0xffffffff>>PAGE_SHIFT) &&
 256                                             !iommu_aperture_allowed) {
 257                                                 printk(KERN_INFO
 258     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 259                                                 iommu_aperture_disabled = 1;
 260                                         }
 261 #endif
 262                                         return;
 263                                 case PCI_VENDOR_ID_NVIDIA:
 264 #ifndef CONFIG_SMP
 265                                         printk(KERN_INFO
 266      "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
 267                                                num,slot,vendor);
 268                                         skip_ioapic_setup = 1;
 269 #endif
 270                                         return;
 271                                 }
 272
 273                                 /* No multi-function device? */
 274                                 type = read_pci_config_byte(num,slot,func,
 275                                                             PCI_HEADER_TYPE);
 276                                 if (!(type & 0x80))
 277                                         break;
 278                         }
 279                 }
 280         }
 281 }
 282
 283 static int __init ioapic_pirq_setup(char *str)
 284 {
 285         int i, max;
 286         int ints[MAX_PIRQS+1];
 287
 288         get_options(str, ARRAY_SIZE(ints), ints);
 289
 290         for (i = 0; i < MAX_PIRQS; i++)
 291                 pirq_entries[i] = -1;
 292
 293         pirqs_enabled = 1;
 294         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
 295         max = MAX_PIRQS;
 296         if (ints[0] < MAX_PIRQS)
 297                 max = ints[0];
 298
 299         for (i = 0; i < max; i++) {
 300                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 301                 /*
 302                  * PIRQs are mapped upside down, usually.
 303                  */
 304                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 305         }
 306         return 1;
 307 }
 308
 309 __setup("pirq=", ioapic_pirq_setup);
 310
 311 /*
 312  * Find the IRQ entry number of a certain pin.
 313  */
 314 static int __init find_irq_entry(int apic, int pin, int type)
 315 {
 316         int i;
 317
 318         for (i = 0; i < mp_irq_entries; i++)
 319                 if (mp_irqs[i].mpc_irqtype == type &&
 320                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 321                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 322                     mp_irqs[i].mpc_dstirq == pin)
 323                         return i;
 324
 325         return -1;
 326 }
 327
 328 /*
 329  * Find the pin to which IRQ[irq] (ISA) is connected
 330  */
 331 static int __init find_isa_irq_pin(int irq, int type)
 332 {
 333         int i;
 334
 335         for (i = 0; i < mp_irq_entries; i++) {
 336                 int lbus = mp_irqs[i].mpc_srcbus;
 337
 338                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 339                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 340                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 341                     (mp_irqs[i].mpc_irqtype == type) &&
 342                     (mp_irqs[i].mpc_srcbusirq == irq))
 343
 344                         return mp_irqs[i].mpc_dstirq;
 345         }
 346         return -1;
 347 }
 348
 349 /*
 350  * Find a specific PCI IRQ entry.
 351  * Not an __init, possibly needed by modules
 352  */
 353 static int pin_2_irq(int idx, int apic, int pin);
 354
 355 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 356 {
 357         int apic, i, best_guess = -1;
 358
 359         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 360                 bus, slot, pin);
 361         if (mp_bus_id_to_pci_bus[bus] == -1) {
 362                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 363                 return -1;
 364         }
 365         for (i = 0; i < mp_irq_entries; i++) {
 366                 int lbus = mp_irqs[i].mpc_srcbus;
 367
 368                 for (apic = 0; apic < nr_ioapics; apic++)
 369                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 370                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 371                                 break;
 372
 373                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 374                     !mp_irqs[i].mpc_irqtype &&
 375                     (bus == lbus) &&
 376                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 377                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 378
 379                         if (!(apic || IO_APIC_IRQ(irq)))
 380                                 continue;
 381
 382                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 383                                 return irq;
 384                         /*
 385                          * Use the first all-but-pin matching entry as a
 386                          * best-guess fuzzy result for broken mptables.
 387                          */
 388                         if (best_guess < 0)
 389                                 best_guess = irq;
 390                 }
 391         }
 392         return best_guess;
 393 }
 394
 395 /*
 396  * EISA Edge/Level control register, ELCR
 397  */
 398 static int __init EISA_ELCR(unsigned int irq)
 399 {
 400         if (irq < 16) {
 401                 unsigned int port = 0x4d0 + (irq >> 3);
 402                 return (inb(port) >> (irq & 7)) & 1;
 403         }
 404         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
 405         return 0;
 406 }
 407
 408 /* EISA interrupts are always polarity zero and can be edge or level
 409  * trigger depending on the ELCR value.  If an interrupt is listed as
 410  * EISA conforming in the MP table, that means its trigger type must
 411  * be read in from the ELCR */
 412
 413 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 414 #define default_EISA_polarity(idx)      (0)
 415
 416 /* ISA interrupts are always polarity zero edge triggered,
 417  * when listed as conforming in the MP table. */
 418
 419 #define default_ISA_trigger(idx)        (0)
 420 #define default_ISA_polarity(idx)       (0)
 421
 422 /* PCI interrupts are always polarity one level triggered,
 423  * when listed as conforming in the MP table. */
 424
 425 #define default_PCI_trigger(idx)        (1)
 426 #define default_PCI_polarity(idx)       (1)
 427
 428 /* MCA interrupts are always polarity zero level triggered,
 429  * when listed as conforming in the MP table. */
 430
 431 #define default_MCA_trigger(idx)        (1)
 432 #define default_MCA_polarity(idx)       (0)
 433
 434 static int __init MPBIOS_polarity(int idx)
 435 {
 436         int bus = mp_irqs[idx].mpc_srcbus;
 437         int polarity;
 438
 439         /*
 440          * Determine IRQ line polarity (high active or low active):
 441          */
 442         switch (mp_irqs[idx].mpc_irqflag & 3)
 443         {
 444                 case 0: /* conforms, ie. bus-type dependent polarity */
 445                 {
 446                         switch (mp_bus_id_to_type[bus])
 447                         {
 448                                 case MP_BUS_ISA: /* ISA pin */
 449                                 {
 450                                         polarity = default_ISA_polarity(idx);
 451                                         break;
 452                                 }
 453                                 case MP_BUS_EISA: /* EISA pin */
 454                                 {
 455                                         polarity = default_EISA_polarity(idx);
 456                                         break;
 457                                 }
 458                                 case MP_BUS_PCI: /* PCI pin */
 459                                 {
 460                                         polarity = default_PCI_polarity(idx);
 461                                         break;
 462                                 }
 463                                 case MP_BUS_MCA: /* MCA pin */
 464                                 {
 465                                         polarity = default_MCA_polarity(idx);
 466                                         break;
 467                                 }
 468                                 default:
 469                                 {
 470                                         printk(KERN_WARNING "broken BIOS!!\n");
 471                                         polarity = 1;
 472                                         break;
 473                                 }
 474                         }
 475                         break;
 476                 }
 477                 case 1: /* high active */
 478                 {
 479                         polarity = 0;
 480                         break;
 481                 }
 482                 case 2: /* reserved */
 483                 {
 484                         printk(KERN_WARNING "broken BIOS!!\n");
 485                         polarity = 1;
 486                         break;
 487                 }
 488                 case 3: /* low active */
 489                 {
 490                         polarity = 1;
 491                         break;
 492                 }
 493                 default: /* invalid */
 494                 {
 495                         printk(KERN_WARNING "broken BIOS!!\n");
 496                         polarity = 1;
 497                         break;
 498                 }
 499         }
 500         return polarity;
 501 }
 502
 503 static int __init MPBIOS_trigger(int idx)
 504 {
 505         int bus = mp_irqs[idx].mpc_srcbus;
 506         int trigger;
 507
 508         /*
 509          * Determine IRQ trigger mode (edge or level sensitive):
 510          */
 511         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 512         {
 513                 case 0: /* conforms, ie. bus-type dependent */
 514                 {
 515                         switch (mp_bus_id_to_type[bus])
 516                         {
 517                                 case MP_BUS_ISA: /* ISA pin */
 518                                 {
 519                                         trigger = default_ISA_trigger(idx);
 520                                         break;
 521                                 }
 522                                 case MP_BUS_EISA: /* EISA pin */
 523                                 {
 524                                         trigger = default_EISA_trigger(idx);
 525                                         break;
 526                                 }
 527                                 case MP_BUS_PCI: /* PCI pin */
 528                                 {
 529                                         trigger = default_PCI_trigger(idx);
 530                                         break;
 531                                 }
 532                                 case MP_BUS_MCA: /* MCA pin */
 533                                 {
 534                                         trigger = default_MCA_trigger(idx);
 535                                         break;
 536                                 }
 537                                 default:
 538                                 {
 539                                         printk(KERN_WARNING "broken BIOS!!\n");
 540                                         trigger = 1;
 541                                         break;
 542                                 }
 543                         }
 544                         break;
 545                 }
 546                 case 1: /* edge */
 547                 {
 548                         trigger = 0;
 549                         break;
 550                 }
 551                 case 2: /* reserved */
 552                 {
 553                         printk(KERN_WARNING "broken BIOS!!\n");
 554                         trigger = 1;
 555                         break;
 556                 }
 557                 case 3: /* level */
 558                 {
 559                         trigger = 1;
 560                         break;
 561                 }
 562                 default: /* invalid */
 563                 {
 564                         printk(KERN_WARNING "broken BIOS!!\n");
 565                         trigger = 0;
 566                         break;
 567                 }
 568         }
 569         return trigger;
 570 }
 571
 572 static inline int irq_polarity(int idx)
 573 {
 574         return MPBIOS_polarity(idx);
 575 }
 576
 577 static inline int irq_trigger(int idx)
 578 {
 579         return MPBIOS_trigger(idx);
 580 }
 581
 582 static int pin_2_irq(int idx, int apic, int pin)
 583 {
 584         int irq, i;
 585         int bus = mp_irqs[idx].mpc_srcbus;
 586
 587         /*
 588          * Debugging check, we are in big trouble if this message pops up!
 589          */
 590         if (mp_irqs[idx].mpc_dstirq != pin)
 591                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 592
 593         switch (mp_bus_id_to_type[bus])
 594         {
 595                 case MP_BUS_ISA: /* ISA pin */
 596                 case MP_BUS_EISA:
 597                 case MP_BUS_MCA:
 598                 {
 599                         irq = mp_irqs[idx].mpc_srcbusirq;
 600                         break;
 601                 }
 602                 case MP_BUS_PCI: /* PCI pin */
 603                 {
 604                         /*
 605                          * PCI IRQs are mapped in order
 606                          */
 607                         i = irq = 0;
 608                         while (i < apic)
 609                                 irq += nr_ioapic_registers[i++];
 610                         irq += pin;
 611                         break;
 612                 }
 613                 default:
 614                 {
 615                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 616                         irq = 0;
 617                         break;
 618                 }
 619         }
 620
 621         /*
 622          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 623          */
 624         if ((pin >= 16) && (pin <= 23)) {
 625                 if (pirq_entries[pin-16] != -1) {
 626                         if (!pirq_entries[pin-16]) {
 627                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
 628                         } else {
 629                                 irq = pirq_entries[pin-16];
 630                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
 631                                                 pin-16, irq);
 632                         }
 633                 }
 634         }
 635         return irq;
 636 }
 637
 638 static inline int IO_APIC_irq_trigger(int irq)
 639 {
 640         int apic, idx, pin;
 641
 642         for (apic = 0; apic < nr_ioapics; apic++) {
 643                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 644                         idx = find_irq_entry(apic,pin,mp_INT);
 645                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 646                                 return irq_trigger(idx);
 647                 }
 648         }
 649         /*
 650          * nonexistent IRQs are edge default
 651          */
 652         return 0;
 653 }
 654
 655 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 656 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 657
 658 #ifndef CONFIG_PCI_USE_VECTOR
 659 int __init assign_irq_vector(int irq)
 660 {
 661         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 662         BUG_ON(irq >= NR_IRQ_VECTORS);
 663         if (IO_APIC_VECTOR(irq) > 0)
 664                 return IO_APIC_VECTOR(irq);
 665 next:
 666         current_vector += 8;
 667         if (current_vector == IA32_SYSCALL_VECTOR)
 668                 goto next;
 669
 670         if (current_vector > FIRST_SYSTEM_VECTOR) {
 671                 offset++;
 672                 current_vector = FIRST_DEVICE_VECTOR + offset;
 673         }
 674
 675         if (current_vector == FIRST_SYSTEM_VECTOR)
 676                 panic("ran out of interrupt sources!");
 677
 678         IO_APIC_VECTOR(irq) = current_vector;
 679         return current_vector;
 680 }
 681 #endif
 682
 683 extern void (*interrupt[NR_IRQS])(void);
 684 static struct hw_interrupt_type ioapic_level_type;
 685 static struct hw_interrupt_type ioapic_edge_type;
 686
 687 #define IOAPIC_AUTO     -1
 688 #define IOAPIC_EDGE     0
 689 #define IOAPIC_LEVEL    1
 690
 691 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 692 {
 693         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 694                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 695                                 trigger == IOAPIC_LEVEL)
 696                         irq_desc[vector].handler = &ioapic_level_type;
 697                 else
 698                         irq_desc[vector].handler = &ioapic_edge_type;
 699                 set_intr_gate(vector, interrupt[vector]);
 700         } else  {
 701                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 702                                 trigger == IOAPIC_LEVEL)
 703                         irq_desc[irq].handler = &ioapic_level_type;
 704                 else
 705                         irq_desc[irq].handler = &ioapic_edge_type;
 706                 set_intr_gate(vector, interrupt[irq]);
 707         }
 708 }
 709
 710 void __init setup_IO_APIC_irqs(void)
 711 {
 712         struct IO_APIC_route_entry entry;
 713         int apic, pin, idx, irq, first_notcon = 1, vector;
 714         unsigned long flags;
 715
 716         printk(KERN_DEBUG "init IO_APIC IRQs\n");
 717
 718         for (apic = 0; apic < nr_ioapics; apic++) {
 719         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 720
 721                 /*
 722                  * add it to the IO-APIC irq-routing table:
 723                  */
 724                 memset(&entry,0,sizeof(entry));
 725
 726                 entry.delivery_mode = dest_LowestPrio;
 727                 entry.dest_mode = INT_DELIVERY_MODE;
 728                 entry.mask = 0;                         /* enable IRQ */
 729                 entry.dest.logical.logical_dest = TARGET_CPUS;
 730
 731                 idx = find_irq_entry(apic,pin,mp_INT);
 732                 if (idx == -1) {
 733                         if (first_notcon) {
 734                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 735                                 first_notcon = 0;
 736                         } else
 737                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 738                         continue;
 739                 }
 740
 741                 entry.trigger = irq_trigger(idx);
 742                 entry.polarity = irq_polarity(idx);
 743
 744                 if (irq_trigger(idx)) {
 745                         entry.trigger = 1;
 746                         entry.mask = 1;
 747                         entry.dest.logical.logical_dest = TARGET_CPUS;
 748                 }
 749
 750                 irq = pin_2_irq(idx, apic, pin);
 751                 add_pin_to_irq(irq, apic, pin);
 752
 753                 if (!apic && !IO_APIC_IRQ(irq))
 754                         continue;
 755
 756                 if (IO_APIC_IRQ(irq)) {
 757                         vector = assign_irq_vector(irq);
 758                         entry.vector = vector;
 759
 760                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 761                         if (!apic && (irq < 16))
 762                                 disable_8259A_irq(irq);
 763                 }
 764                 spin_lock_irqsave(&ioapic_lock, flags);
 765                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 766                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 767                 spin_unlock_irqrestore(&ioapic_lock, flags);
 768         }
 769         }
 770
 771         if (!first_notcon)
 772                 printk(" not connected.\n");
 773 }
 774
 775 /*
 776  * Set up the 8259A-master output pin as broadcast to all
 777  * CPUs.
 778  */
 779 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 780 {
 781         struct IO_APIC_route_entry entry;
 782         unsigned long flags;
 783
 784         memset(&entry,0,sizeof(entry));
 785
 786         disable_8259A_irq(0);
 787
 788         /* mask LVT0 */
 789         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 790
 791         /*
 792          * We use logical delivery to get the timer IRQ
 793          * to the first CPU.
 794          */
 795         entry.dest_mode = INT_DELIVERY_MODE;
 796         entry.mask = 0;                                 /* unmask IRQ now */
 797         entry.dest.logical.logical_dest = TARGET_CPUS;
 798         entry.delivery_mode = dest_LowestPrio;
 799         entry.polarity = 0;
 800         entry.trigger = 0;
 801         entry.vector = vector;
 802
 803         /*
 804          * The timer IRQ doesn't have to know that behind the
 805          * scene we have a 8259A-master in AEOI mode ...
 806          */
 807         irq_desc[0].handler = &ioapic_edge_type;
 808
 809         /*
 810          * Add it to the IO-APIC irq-routing table:
 811          */
 812         spin_lock_irqsave(&ioapic_lock, flags);
 813         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 814         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 815         spin_unlock_irqrestore(&ioapic_lock, flags);
 816
 817         enable_8259A_irq(0);
 818 }
 819
 820 void __init UNEXPECTED_IO_APIC(void)
 821 {
 822 #if 0
 823         printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
 824         printk(KERN_WARNING "          to linux-smp@vger.kernel.org\n");
 825 #endif
 826 }
 827
 828 void __init print_IO_APIC(void)
 829 {
 830         int apic, i;
 831         union IO_APIC_reg_00 reg_00;
 832         union IO_APIC_reg_01 reg_01;
 833         union IO_APIC_reg_02 reg_02;
 834         unsigned long flags;
 835
 836         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 837         for (i = 0; i < nr_ioapics; i++)
 838                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 839                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 840
 841         /*
 842          * We are a bit conservative about what we expect.  We have to
 843          * know about every hardware change ASAP.
 844          */
 845         printk(KERN_INFO "testing the IO APIC.......................\n");
 846
 847         for (apic = 0; apic < nr_ioapics; apic++) {
 848
 849         spin_lock_irqsave(&ioapic_lock, flags);
 850         reg_00.raw = io_apic_read(apic, 0);
 851         reg_01.raw = io_apic_read(apic, 1);
 852         if (reg_01.bits.version >= 0x10)
 853                 reg_02.raw = io_apic_read(apic, 2);
 854         spin_unlock_irqrestore(&ioapic_lock, flags);
 855
 856         printk("\n");
 857         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 858         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 859         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 860         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 861                 UNEXPECTED_IO_APIC();
 862
 863         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 864         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 865         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 866                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 867                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 868                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 869                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 870                 (reg_01.bits.entries != 0x2E) &&
 871                 (reg_01.bits.entries != 0x3F) &&
 872                 (reg_01.bits.entries != 0x03)
 873         )
 874                 UNEXPECTED_IO_APIC();
 875
 876         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 877         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 878         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 879                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 880                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 881                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 882                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 883                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 884         )
 885                 UNEXPECTED_IO_APIC();
 886         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 887                 UNEXPECTED_IO_APIC();
 888
 889         if (reg_01.bits.version >= 0x10) {
 890                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 891                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 892                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 893                         UNEXPECTED_IO_APIC();
 894         }
 895
 896         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 897
 898         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 899                           " Stat Dest Deli Vect:   \n");
 900
 901         for (i = 0; i <= reg_01.bits.entries; i++) {
 902                 struct IO_APIC_route_entry entry;
 903
 904                 spin_lock_irqsave(&ioapic_lock, flags);
 905                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 906                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 907                 spin_unlock_irqrestore(&ioapic_lock, flags);
 908
 909                 printk(KERN_DEBUG " %02x %03X %02X  ",
 910                         i,
 911                         entry.dest.logical.logical_dest,
 912                         entry.dest.physical.physical_dest
 913                 );
 914
 915                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 916                         entry.mask,
 917                         entry.trigger,
 918                         entry.irr,
 919                         entry.polarity,
 920                         entry.delivery_status,
 921                         entry.dest_mode,
 922                         entry.delivery_mode,
 923                         entry.vector
 924                 );
 925         }
 926         }
 927         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 928         for (i = 0; i < NR_IRQS; i++) {
 929                 struct irq_pin_list *entry = irq_2_pin + i;
 930                 if (entry->pin < 0)
 931                         continue;
 932                 printk(KERN_DEBUG "IRQ%d ", i);
 933                 for (;;) {
 934                         printk("-> %d:%d", entry->apic, entry->pin);
 935                         if (!entry->next)
 936                                 break;
 937                         entry = irq_2_pin + entry->next;
 938                 }
 939                 printk("\n");
 940         }
 941
 942         printk(KERN_INFO ".................................... done.\n");
 943
 944         return;
 945 }
 946
 947 static void print_APIC_bitfield (int base)
 948 {
 949         unsigned int v;
 950         int i, j;
 951
 952         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 953         for (i = 0; i < 8; i++) {
 954                 v = apic_read(base + i*0x10);
 955                 for (j = 0; j < 32; j++) {
 956                         if (v & (1<<j))
 957                                 printk("1");
 958                         else
 959                                 printk("0");
 960                 }
 961                 printk("\n");
 962         }
 963 }
 964
 965 void /*__init*/ print_local_APIC(void * dummy)
 966 {
 967         unsigned int v, ver, maxlvt;
 968
 969         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 970                 smp_processor_id(), hard_smp_processor_id());
 971         v = apic_read(APIC_ID);
 972         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 973         v = apic_read(APIC_LVR);
 974         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 975         ver = GET_APIC_VERSION(v);
 976         maxlvt = get_maxlvt();
 977
 978         v = apic_read(APIC_TASKPRI);
 979         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 980
 981         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
 982                 v = apic_read(APIC_ARBPRI);
 983                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 984                         v & APIC_ARBPRI_MASK);
 985                 v = apic_read(APIC_PROCPRI);
 986                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 987         }
 988
 989         v = apic_read(APIC_EOI);
 990         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
 991         v = apic_read(APIC_RRR);
 992         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
 993         v = apic_read(APIC_LDR);
 994         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
 995         v = apic_read(APIC_DFR);
 996         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
 997         v = apic_read(APIC_SPIV);
 998         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
 999
1000         printk(KERN_DEBUG "... APIC ISR field:\n");
1001         print_APIC_bitfield(APIC_ISR);
1002         printk(KERN_DEBUG "... APIC TMR field:\n");
1003         print_APIC_bitfield(APIC_TMR);
1004         printk(KERN_DEBUG "... APIC IRR field:\n");
1005         print_APIC_bitfield(APIC_IRR);
1006
1007         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1008                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1009                         apic_write(APIC_ESR, 0);
1010                 v = apic_read(APIC_ESR);
1011                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1012         }
1013
1014         v = apic_read(APIC_ICR);
1015         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1016         v = apic_read(APIC_ICR2);
1017         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1018
1019         v = apic_read(APIC_LVTT);
1020         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1021
1022         if (maxlvt > 3) {                       /* PC is LVT#4. */
1023                 v = apic_read(APIC_LVTPC);
1024                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1025         }
1026         v = apic_read(APIC_LVT0);
1027         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1028         v = apic_read(APIC_LVT1);
1029         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1030
1031         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1032                 v = apic_read(APIC_LVTERR);
1033                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1034         }
1035
1036         v = apic_read(APIC_TMICT);
1037         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1038         v = apic_read(APIC_TMCCT);
1039         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1040         v = apic_read(APIC_TDCR);
1041         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1042         printk("\n");
1043 }
1044
1045 void print_all_local_APICs (void)
1046 {
1047         on_each_cpu(print_local_APIC, NULL, 1, 1);
1048 }
1049
1050 void /*__init*/ print_PIC(void)
1051 {
1052         extern spinlock_t i8259A_lock;
1053         unsigned int v;
1054         unsigned long flags;
1055
1056         printk(KERN_DEBUG "\nprinting PIC contents\n");
1057
1058         spin_lock_irqsave(&i8259A_lock, flags);
1059
1060         v = inb(0xa1) << 8 | inb(0x21);
1061         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1062
1063         v = inb(0xa0) << 8 | inb(0x20);
1064         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1065
1066         outb(0x0b,0xa0);
1067         outb(0x0b,0x20);
1068         v = inb(0xa0) << 8 | inb(0x20);
1069         outb(0x0a,0xa0);
1070         outb(0x0a,0x20);
1071
1072         spin_unlock_irqrestore(&i8259A_lock, flags);
1073
1074         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1075
1076         v = inb(0x4d1) << 8 | inb(0x4d0);
1077         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1078 }
1079
1080 static void __init enable_IO_APIC(void)
1081 {
1082         union IO_APIC_reg_01 reg_01;
1083         int i;
1084         unsigned long flags;
1085
1086         for (i = 0; i < PIN_MAP_SIZE; i++) {
1087                 irq_2_pin[i].pin = -1;
1088                 irq_2_pin[i].next = 0;
1089         }
1090         if (!pirqs_enabled)
1091                 for (i = 0; i < MAX_PIRQS; i++)
1092                         pirq_entries[i] = -1;
1093
1094         /*
1095          * The number of IO-APIC IRQ registers (== #pins):
1096          */
1097         for (i = 0; i < nr_ioapics; i++) {
1098                 spin_lock_irqsave(&ioapic_lock, flags);
1099                 reg_01.raw = io_apic_read(i, 1);
1100                 spin_unlock_irqrestore(&ioapic_lock, flags);
1101                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1102         }
1103
1104         /*
1105          * Do not trust the IO-APIC being empty at bootup
1106          */
1107         clear_IO_APIC();
1108 }
1109
1110 /*
1111  * Not an __init, needed by the reboot code
1112  */
1113 void disable_IO_APIC(void)
1114 {
1115         /*
1116          * Clear the IO-APIC before rebooting:
1117          */
1118         clear_IO_APIC();
1119
1120         disconnect_bsp_APIC();
1121 }
1122
1123 /*
1124  * function to set the IO-APIC physical IDs based on the
1125  * values stored in the MPC table.
1126  *
1127  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1128  */
1129
1130 static void __init setup_ioapic_ids_from_mpc (void)
1131 {
1132         union IO_APIC_reg_00 reg_00;
1133         physid_mask_t phys_id_present_map = phys_cpu_present_map;
1134         int apic;
1135         int i;
1136         unsigned char old_id;
1137         unsigned long flags;
1138
1139         /*
1140          * Set the IOAPIC ID to the value stored in the MPC table.
1141          */
1142         for (apic = 0; apic < nr_ioapics; apic++) {
1143
1144                 /* Read the register 0 value */
1145                 spin_lock_irqsave(&ioapic_lock, flags);
1146                 reg_00.raw = io_apic_read(apic, 0);
1147                 spin_unlock_irqrestore(&ioapic_lock, flags);
1148
1149                 old_id = mp_ioapics[apic].mpc_apicid;
1150
1151                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1152                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1153                                 apic, mp_ioapics[apic].mpc_apicid);
1154                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1155                                 reg_00.bits.ID);
1156                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1157                 }
1158
1159                 /*
1160                  * Sanity check, is the ID really free? Every APIC in a
1161                  * system must have a unique ID or we get lots of nice
1162                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1163                  */
1164                 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1165                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1166                                 apic, mp_ioapics[apic].mpc_apicid);
1167                         for (i = 0; i < 0xf; i++)
1168                                 if (!physid_isset(i, phys_id_present_map))
1169                                         break;
1170                         if (i >= 0xf)
1171                                 panic("Max APIC ID exceeded!\n");
1172                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1173                                 i);
1174                         physid_set(i, phys_id_present_map);
1175                         mp_ioapics[apic].mpc_apicid = i;
1176                 } else {
1177                         printk(KERN_INFO
1178                                "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1179                         physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1180                 }
1181
1182
1183                 /*
1184                  * We need to adjust the IRQ routing table
1185                  * if the ID changed.
1186                  */
1187                 if (old_id != mp_ioapics[apic].mpc_apicid)
1188                         for (i = 0; i < mp_irq_entries; i++)
1189                                 if (mp_irqs[i].mpc_dstapic == old_id)
1190                                         mp_irqs[i].mpc_dstapic
1191                                                 = mp_ioapics[apic].mpc_apicid;
1192
1193                 /*
1194                  * Read the right value from the MPC table and
1195                  * write it into the ID register.
1196                  */
1197                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1198                                 mp_ioapics[apic].mpc_apicid);
1199
1200                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1201                 spin_lock_irqsave(&ioapic_lock, flags);
1202                 io_apic_write(apic, 0, reg_00.raw);
1203                 spin_unlock_irqrestore(&ioapic_lock, flags);
1204
1205                 /*
1206                  * Sanity check
1207                  */
1208                 spin_lock_irqsave(&ioapic_lock, flags);
1209                 reg_00.raw = io_apic_read(apic, 0);
1210                 spin_unlock_irqrestore(&ioapic_lock, flags);
1211                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1212                         panic("could not set ID!\n");
1213                 else
1214                         printk(" ok.\n");
1215         }
1216 }
1217
1218 /*
1219  * There is a nasty bug in some older SMP boards, their mptable lies
1220  * about the timer IRQ. We do the following to work around the situation:
1221  *
1222  *      - timer IRQ defaults to IO-APIC IRQ
1223  *      - if this function detects that timer IRQs are defunct, then we fall
1224  *        back to ISA timer IRQs
1225  */
1226 static int __init timer_irq_works(void)
1227 {
1228         unsigned long t1 = jiffies;
1229
1230         local_irq_enable();
1231         /* Let ten ticks pass... */
1232         mdelay((10 * 1000) / HZ);
1233
1234         /*
1235          * Expect a few ticks at least, to be sure some possible
1236          * glue logic does not lock up after one or two first
1237          * ticks in a non-ExtINT mode.  Also the local APIC
1238          * might have cached one ExtINT interrupt.  Finally, at
1239          * least one tick may be lost due to delays.
1240          */
1241
1242         /* jiffies wrap? */
1243         if (jiffies - t1 > 4)
1244                 return 1;
1245         return 0;
1246 }
1247
1248 /*
1249  * In the SMP+IOAPIC case it might happen that there are an unspecified
1250  * number of pending IRQ events unhandled. These cases are very rare,
1251  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1252  * better to do it this way as thus we do not have to be aware of
1253  * 'pending' interrupts in the IRQ path, except at this point.
1254  */
1255 /*
1256  * Edge triggered needs to resend any interrupt
1257  * that was delayed but this is now handled in the device
1258  * independent code.
1259  */
1260
1261 /*
1262  * Starting up a edge-triggered IO-APIC interrupt is
1263  * nasty - we need to make sure that we get the edge.
1264  * If it is already asserted for some reason, we need
1265  * return 1 to indicate that is was pending.
1266  *
1267  * This is not complete - we should be able to fake
1268  * an edge even if it isn't on the 8259A...
1269  */
1270
1271 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1272 {
1273         int was_pending = 0;
1274         unsigned long flags;
1275
1276         spin_lock_irqsave(&ioapic_lock, flags);
1277         if (irq < 16) {
1278                 disable_8259A_irq(irq);
1279                 if (i8259A_irq_pending(irq))
1280                         was_pending = 1;
1281         }
1282         __unmask_IO_APIC_irq(irq);
1283         spin_unlock_irqrestore(&ioapic_lock, flags);
1284
1285         return was_pending;
1286 }
1287
1288 /*
1289  * Once we have recorded IRQ_PENDING already, we can mask the
1290  * interrupt for real. This prevents IRQ storms from unhandled
1291  * devices.
1292  */
1293 static void ack_edge_ioapic_irq(unsigned int irq)
1294 {
1295         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1296                                         == (IRQ_PENDING | IRQ_DISABLED))
1297                 mask_IO_APIC_irq(irq);
1298         ack_APIC_irq();
1299 }
1300
1301 /*
1302  * Level triggered interrupts can just be masked,
1303  * and shutting down and starting up the interrupt
1304  * is the same as enabling and disabling them -- except
1305  * with a startup need to return a "was pending" value.
1306  *
1307  * Level triggered interrupts are special because we
1308  * do not touch any IO-APIC register while handling
1309  * them. We ack the APIC in the end-IRQ handler, not
1310  * in the start-IRQ-handler. Protection against reentrance
1311  * from the same interrupt is still provided, both by the
1312  * generic IRQ layer and by the fact that an unacked local
1313  * APIC does not accept IRQs.
1314  */
1315 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1316 {
1317         unmask_IO_APIC_irq(irq);
1318
1319         return 0; /* don't check for pending */
1320 }
1321
1322 static void end_level_ioapic_irq (unsigned int irq)
1323 {
1324         unsigned long v;
1325         int i;
1326
1327 /*
1328  * It appears there is an erratum which affects at least version 0x11
1329  * of I/O APIC (that's the 82093AA and cores integrated into various
1330  * chipsets).  Under certain conditions a level-triggered interrupt is
1331  * erroneously delivered as edge-triggered one but the respective IRR
1332  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1333  * message but it will never arrive and further interrupts are blocked
1334  * from the source.  The exact reason is so far unknown, but the
1335  * phenomenon was observed when two consecutive interrupt requests
1336  * from a given source get delivered to the same CPU and the source is
1337  * temporarily disabled in between.
1338  *
1339  * A workaround is to simulate an EOI message manually.  We achieve it
1340  * by setting the trigger mode to edge and then to level when the edge
1341  * trigger mode gets detected in the TMR of a local APIC for a
1342  * level-triggered interrupt.  We mask the source for the time of the
1343  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1344  * The idea is from Manfred Spraul.  --macro
1345  */
1346         i = IO_APIC_VECTOR(irq);
1347         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1348
1349         ack_APIC_irq();
1350
1351         if (!(v & (1 << (i & 0x1f)))) {
1352 #ifdef APIC_LOCKUP_DEBUG
1353                 struct irq_pin_list *entry;
1354 #endif
1355
1356 #ifdef APIC_MISMATCH_DEBUG
1357                 atomic_inc(&irq_mis_count);
1358 #endif
1359                 spin_lock(&ioapic_lock);
1360                 __mask_and_edge_IO_APIC_irq(irq);
1361 #ifdef APIC_LOCKUP_DEBUG
1362                 for (entry = irq_2_pin + irq;;) {
1363                         unsigned int reg;
1364
1365                         if (entry->pin == -1)
1366                                 break;
1367                         reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1368                         if (reg & 0x00004000)
1369                                 printk(KERN_CRIT "Aieee!!!  Remote IRR"
1370                                         " still set after unlock!\n");
1371                         if (!entry->next)
1372                                 break;
1373                         entry = irq_2_pin + entry->next;
1374                 }
1375 #endif
1376                 __unmask_and_level_IO_APIC_irq(irq);
1377                 spin_unlock(&ioapic_lock);
1378         }
1379 }
1380
1381 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1382 {
1383         unsigned long flags;
1384         unsigned int dest;
1385
1386         dest = cpu_mask_to_apicid(mk_cpumask_const(mask));
1387
1388         /*
1389          * Only the first 8 bits are valid.
1390          */
1391         dest = dest << 24;
1392
1393         spin_lock_irqsave(&ioapic_lock, flags);
1394         __DO_ACTION(1, = dest, )
1395         spin_unlock_irqrestore(&ioapic_lock, flags);
1396 }
1397
1398 #ifdef CONFIG_PCI_USE_VECTOR
1399 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1400 {
1401         int irq = vector_to_irq(vector);
1402
1403         return startup_edge_ioapic_irq(irq);
1404 }
1405
1406 static void ack_edge_ioapic_vector(unsigned int vector)
1407 {
1408         int irq = vector_to_irq(vector);
1409
1410         ack_edge_ioapic_irq(irq);
1411 }
1412
1413 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1414 {
1415         int irq = vector_to_irq(vector);
1416
1417         return startup_level_ioapic_irq (irq);
1418 }
1419
1420 static void end_level_ioapic_vector (unsigned int vector)
1421 {
1422         int irq = vector_to_irq(vector);
1423
1424         end_level_ioapic_irq(irq);
1425 }
1426
1427 static void mask_IO_APIC_vector (unsigned int vector)
1428 {
1429         int irq = vector_to_irq(vector);
1430
1431         mask_IO_APIC_irq(irq);
1432 }
1433
1434 static void unmask_IO_APIC_vector (unsigned int vector)
1435 {
1436         int irq = vector_to_irq(vector);
1437
1438         unmask_IO_APIC_irq(irq);
1439 }
1440
1441 static void set_ioapic_affinity_vector (unsigned int vector,
1442                                         cpumask_t cpu_mask)
1443 {
1444         int irq = vector_to_irq(vector);
1445
1446         set_ioapic_affinity_irq(irq, cpu_mask);
1447 }
1448 #endif
1449
1450 /*
1451  * Level and edge triggered IO-APIC interrupts need different handling,
1452  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1453  * handled with the level-triggered descriptor, but that one has slightly
1454  * more overhead. Level-triggered interrupts cannot be handled with the
1455  * edge-triggered handler, without risking IRQ storms and other ugly
1456  * races.
1457  */
1458
1459 static struct hw_interrupt_type ioapic_edge_type = {
1460         .typename = "IO-APIC-edge",
1461         .startup        = startup_edge_ioapic,
1462         .shutdown       = shutdown_edge_ioapic,
1463         .enable         = enable_edge_ioapic,
1464         .disable        = disable_edge_ioapic,
1465         .ack            = ack_edge_ioapic,
1466         .end            = end_edge_ioapic,
1467         .set_affinity = set_ioapic_affinity,
1468 };
1469
1470 static struct hw_interrupt_type ioapic_level_type = {
1471         .typename = "IO-APIC-level",
1472         .startup        = startup_level_ioapic,
1473         .shutdown       = shutdown_level_ioapic,
1474         .enable         = enable_level_ioapic,
1475         .disable        = disable_level_ioapic,
1476         .ack            = mask_and_ack_level_ioapic,
1477         .end            = end_level_ioapic,
1478         .set_affinity = set_ioapic_affinity,
1479 };
1480
1481 static inline void init_IO_APIC_traps(void)
1482 {
1483         int irq;
1484
1485         /*
1486          * NOTE! The local APIC isn't very good at handling
1487          * multiple interrupts at the same interrupt level.
1488          * As the interrupt level is determined by taking the
1489          * vector number and shifting that right by 4, we
1490          * want to spread these out a bit so that they don't
1491          * all fall in the same interrupt level.
1492          *
1493          * Also, we've got to be careful not to trash gate
1494          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1495          */
1496         for (irq = 0; irq < NR_IRQS ; irq++) {
1497                 int tmp = irq;
1498                 if (use_pci_vector()) {
1499                         if (!platform_legacy_irq(tmp))
1500                                 if ((tmp = vector_to_irq(tmp)) == -1)
1501                                         continue;
1502                 }
1503                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1504                         /*
1505                          * Hmm.. We don't have an entry for this,
1506                          * so default to an old-fashioned 8259
1507                          * interrupt if we can..
1508                          */
1509                         if (irq < 16)
1510                                 make_8259A_irq(irq);
1511                         else
1512                                 /* Strange. Oh, well.. */
1513                                 irq_desc[irq].handler = &no_irq_type;
1514                 }
1515         }
1516 }
1517
1518 static void enable_lapic_irq (unsigned int irq)
1519 {
1520         unsigned long v;
1521
1522         v = apic_read(APIC_LVT0);
1523         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1524 }
1525
1526 static void disable_lapic_irq (unsigned int irq)
1527 {
1528         unsigned long v;
1529
1530         v = apic_read(APIC_LVT0);
1531         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1532 }
1533
1534 static void ack_lapic_irq (unsigned int irq)
1535 {
1536         ack_APIC_irq();
1537 }
1538
1539 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1540
1541 static struct hw_interrupt_type lapic_irq_type = {
1542         .typename = "local-APIC-edge",
1543         .startup = NULL, /* startup_irq() not used for IRQ0 */
1544         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1545         .enable = enable_lapic_irq,
1546         .disable = disable_lapic_irq,
1547         .ack = ack_lapic_irq,
1548         .end = end_lapic_irq,
1549 };
1550
1551 static void setup_nmi (void)
1552 {
1553         /*
1554          * Dirty trick to enable the NMI watchdog ...
1555          * We put the 8259A master into AEOI mode and
1556          * unmask on all local APICs LVT0 as NMI.
1557          *
1558          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1559          * is from Maciej W. Rozycki - so we do not have to EOI from
1560          * the NMI handler or the timer interrupt.
1561          */
1562         printk(KERN_INFO "activating NMI Watchdog ...");
1563
1564         enable_NMI_through_LVT0(NULL);
1565
1566         printk(" done.\n");
1567 }
1568
1569 /*
1570  * This looks a bit hackish but it's about the only one way of sending
1571  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1572  * not support the ExtINT mode, unfortunately.  We need to send these
1573  * cycles as some i82489DX-based boards have glue logic that keeps the
1574  * 8259A interrupt line asserted until INTA.  --macro
1575  */
1576 static inline void unlock_ExtINT_logic(void)
1577 {
1578         int pin, i;
1579         struct IO_APIC_route_entry entry0, entry1;
1580         unsigned char save_control, save_freq_select;
1581         unsigned long flags;
1582
1583         pin = find_isa_irq_pin(8, mp_INT);
1584         if (pin == -1)
1585                 return;
1586
1587         spin_lock_irqsave(&ioapic_lock, flags);
1588         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1589         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1590         spin_unlock_irqrestore(&ioapic_lock, flags);
1591         clear_IO_APIC_pin(0, pin);
1592
1593         memset(&entry1, 0, sizeof(entry1));
1594
1595         entry1.dest_mode = 0;                   /* physical delivery */
1596         entry1.mask = 0;                        /* unmask IRQ now */
1597         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1598         entry1.delivery_mode = dest_ExtINT;
1599         entry1.polarity = entry0.polarity;
1600         entry1.trigger = 0;
1601         entry1.vector = 0;
1602
1603         spin_lock_irqsave(&ioapic_lock, flags);
1604         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1605         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1606         spin_unlock_irqrestore(&ioapic_lock, flags);
1607
1608         save_control = CMOS_READ(RTC_CONTROL);
1609         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1610         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1611                    RTC_FREQ_SELECT);
1612         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1613
1614         i = 100;
1615         while (i-- > 0) {
1616                 mdelay(10);
1617                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1618                         i -= 10;
1619         }
1620
1621         CMOS_WRITE(save_control, RTC_CONTROL);
1622         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1623         clear_IO_APIC_pin(0, pin);
1624
1625         spin_lock_irqsave(&ioapic_lock, flags);
1626         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1627         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1628         spin_unlock_irqrestore(&ioapic_lock, flags);
1629 }
1630
1631 /*
1632  * This code may look a bit paranoid, but it's supposed to cooperate with
1633  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1634  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1635  * fanatically on his truly buggy board.
1636  */
1637 static inline void check_timer(void)
1638 {
1639         int pin1, pin2;
1640         int vector;
1641
1642         /*
1643          * get/set the timer IRQ vector:
1644          */
1645         disable_8259A_irq(0);
1646         vector = assign_irq_vector(0);
1647         set_intr_gate(vector, interrupt[0]);
1648
1649         /*
1650          * Subtle, code in do_timer_interrupt() expects an AEOI
1651          * mode for the 8259A whenever interrupts are routed
1652          * through I/O APICs.  Also IRQ0 has to be enabled in
1653          * the 8259A which implies the virtual wire has to be
1654          * disabled in the local APIC.
1655          */
1656         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1657         init_8259A(1);
1658         enable_8259A_irq(0);
1659
1660         pin1 = find_isa_irq_pin(0, mp_INT);
1661         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1662
1663         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1664
1665         if (pin1 != -1) {
1666                 /*
1667                  * Ok, does IRQ0 through the IOAPIC work?
1668                  */
1669                 unmask_IO_APIC_irq(0);
1670                 if (timer_irq_works()) {
1671                         nmi_watchdog_default();
1672                         if (nmi_watchdog == NMI_IO_APIC) {
1673                                 disable_8259A_irq(0);
1674                                 setup_nmi();
1675                                 enable_8259A_irq(0);
1676                                 check_nmi_watchdog();
1677                         }
1678                         return;
1679                 }
1680                 clear_IO_APIC_pin(0, pin1);
1681                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1682         }
1683
1684         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1685         if (pin2 != -1) {
1686                 printk("\n..... (found pin %d) ...", pin2);
1687                 /*
1688                  * legacy devices should be connected to IO APIC #0
1689                  */
1690                 setup_ExtINT_IRQ0_pin(pin2, vector);
1691                 if (timer_irq_works()) {
1692                         printk("works.\n");
1693                         nmi_watchdog_default();
1694                         if (nmi_watchdog == NMI_IO_APIC) {
1695                                 setup_nmi();
1696                                 check_nmi_watchdog();
1697                         }
1698                         return;
1699                 }
1700                 /*
1701                  * Cleanup, just in case ...
1702                  */
1703                 clear_IO_APIC_pin(0, pin2);
1704         }
1705         printk(" failed.\n");
1706
1707         if (nmi_watchdog) {
1708                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1709                 nmi_watchdog = 0;
1710         }
1711
1712         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1713
1714         disable_8259A_irq(0);
1715         irq_desc[0].handler = &lapic_irq_type;
1716         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1717         enable_8259A_irq(0);
1718
1719         if (timer_irq_works()) {
1720                 printk(" works.\n");
1721                 return;
1722         }
1723         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1724         printk(" failed.\n");
1725
1726         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1727
1728         init_8259A(0);
1729         make_8259A_irq(0);
1730         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1731
1732         unlock_ExtINT_logic();
1733
1734         if (timer_irq_works()) {
1735                 printk(" works.\n");
1736                 return;
1737         }
1738         printk(" failed :(.\n");
1739         panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1740 }
1741
1742 /*
1743  *
1744  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1745  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1746  *   Linux doesn't really care, as it's not actually used
1747  *   for any interrupt handling anyway.
1748  */
1749 #define PIC_IRQS        (1<<2)
1750
1751 void __init setup_IO_APIC(void)
1752 {
1753         enable_IO_APIC();
1754
1755         if (acpi_ioapic)
1756                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1757         else
1758                 io_apic_irqs = ~PIC_IRQS;
1759
1760         printk("ENABLING IO-APIC IRQs\n");
1761
1762         /*
1763          * Set up the IO-APIC IRQ routing table.
1764          */
1765         if (!acpi_ioapic)
1766                 setup_ioapic_ids_from_mpc();
1767         sync_Arb_IDs();
1768         setup_IO_APIC_irqs();
1769         init_IO_APIC_traps();
1770         check_timer();
1771         if (!acpi_ioapic)
1772                 print_IO_APIC();
1773 }
1774
1775 /* --------------------------------------------------------------------------
1776                           ACPI-based IOAPIC Configuration
1777    -------------------------------------------------------------------------- */
1778
1779 #ifdef CONFIG_ACPI_BOOT
1780
1781 #define IO_APIC_MAX_ID          15
1782
1783 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1784 {
1785         union IO_APIC_reg_00 reg_00;
1786         static physid_mask_t apic_id_map;
1787         unsigned long flags;
1788         int i = 0;
1789
1790         /*
1791          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1792          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1793          * supports up to 16 on one shared APIC bus.
1794          *
1795          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1796          *      advantage of new APIC bus architecture.
1797          */
1798
1799         if (physids_empty(apic_id_map))
1800                 apic_id_map = phys_cpu_present_map;
1801
1802         spin_lock_irqsave(&ioapic_lock, flags);
1803         reg_00.raw = io_apic_read(ioapic, 0);
1804         spin_unlock_irqrestore(&ioapic_lock, flags);
1805
1806         if (apic_id >= IO_APIC_MAX_ID) {
1807                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1808                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1809                 apic_id = reg_00.bits.ID;
1810         }
1811
1812         /*
1813          * Every APIC in a system must have a unique ID or we get lots of nice
1814          * 'stuck on smp_invalidate_needed IPI wait' messages.
1815          */
1816         if (physid_isset(apic_id, apic_id_map)) {
1817
1818                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1819                         if (!physid_isset(i, apic_id_map))
1820                                 break;
1821                 }
1822
1823                 if (i == IO_APIC_MAX_ID)
1824                         panic("Max apic_id exceeded!\n");
1825
1826                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1827                         "trying %d\n", ioapic, apic_id, i);
1828
1829                 apic_id = i;
1830         }
1831
1832         physid_set(apic_id, apic_id_map);
1833
1834         if (reg_00.bits.ID != apic_id) {
1835                 reg_00.bits.ID = apic_id;
1836
1837                 spin_lock_irqsave(&ioapic_lock, flags);
1838                 io_apic_write(ioapic, 0, reg_00.raw);
1839                 reg_00.raw = io_apic_read(ioapic, 0);
1840                 spin_unlock_irqrestore(&ioapic_lock, flags);
1841
1842                 /* Sanity check */
1843                 if (reg_00.bits.ID != apic_id)
1844                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1845         }
1846
1847         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1848
1849         return apic_id;
1850 }
1851
1852
1853 int __init io_apic_get_version (int ioapic)
1854 {
1855         union IO_APIC_reg_01    reg_01;
1856         unsigned long flags;
1857
1858         spin_lock_irqsave(&ioapic_lock, flags);
1859         reg_01.raw = io_apic_read(ioapic, 1);
1860         spin_unlock_irqrestore(&ioapic_lock, flags);
1861
1862         return reg_01.bits.version;
1863 }
1864
1865
1866 int __init io_apic_get_redir_entries (int ioapic)
1867 {
1868         union IO_APIC_reg_01    reg_01;
1869         unsigned long flags;
1870
1871         spin_lock_irqsave(&ioapic_lock, flags);
1872         reg_01.raw = io_apic_read(ioapic, 1);
1873         spin_unlock_irqrestore(&ioapic_lock, flags);
1874
1875         return reg_01.bits.entries;
1876 }
1877
1878
1879 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1880 {
1881         struct IO_APIC_route_entry entry;
1882         unsigned long flags;
1883
1884         if (!IO_APIC_IRQ(irq)) {
1885                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1886                         ioapic);
1887                 return -EINVAL;
1888         }
1889
1890         /*
1891          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1892          * Note that we mask (disable) IRQs now -- these get enabled when the
1893          * corresponding device driver registers for this IRQ.
1894          */
1895
1896         memset(&entry,0,sizeof(entry));
1897
1898         entry.delivery_mode = dest_LowestPrio;
1899         entry.dest_mode = INT_DELIVERY_MODE;
1900         entry.dest.logical.logical_dest = TARGET_CPUS;
1901         entry.trigger = edge_level;
1902         entry.polarity = active_high_low;
1903         entry.mask = 1;                                  /* Disabled (masked) */
1904
1905         /*
1906          * IRQs < 16 are already in the irq_2_pin[] map
1907          */
1908         if (irq >= 16)
1909                 add_pin_to_irq(irq, ioapic, pin);
1910
1911         entry.vector = assign_irq_vector(irq);
1912
1913         printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1914                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1915                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1916                edge_level, active_high_low);
1917
1918         if (use_pci_vector() && !platform_legacy_irq(irq))
1919                 irq = IO_APIC_VECTOR(irq);
1920         if (edge_level) {
1921                 irq_desc[irq].handler = &ioapic_level_type;
1922         } else {
1923                 irq_desc[irq].handler = &ioapic_edge_type;
1924         }
1925
1926         set_intr_gate(entry.vector, interrupt[irq]);
1927
1928         if (!ioapic && (irq < 16))
1929                 disable_8259A_irq(irq);
1930
1931         spin_lock_irqsave(&ioapic_lock, flags);
1932         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1933         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1934         spin_unlock_irqrestore(&ioapic_lock, flags);
1935
1936         return 0;
1937 }
1938
1939 #endif /*CONFIG_ACPI_BOOT*/
1940
1941 #ifndef CONFIG_SMP
1942 void send_IPI_self(int vector)
1943 {
1944         unsigned int cfg;
1945
1946        /*
1947         * Wait for idle.
1948         */
1949         apic_wait_icr_idle();
1950         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1951
1952         /*
1953          * Send the IPI. The write to APIC_ICR fires this off.
1954          */
1955         apic_write_around(APIC_ICR, cfg);
1956 }
1957 #endif