arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  *
   6  * Author: Jon Mason <jdmason@us.ibm.com>
   7  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/mm.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/string.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/pci_ids.h>
  35 #include <linux/pci.h>
  36 #include <linux/delay.h>
  37 #include <asm/proto.h>
  38 #include <asm/calgary.h>
  39 #include <asm/tce.h>
  40 #include <asm/pci-direct.h>
  41 #include <asm/system.h>
  42 #include <asm/dma.h>
  43
  44 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  45 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  46         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  47
  48 /* we need these for register space address calculation */
  49 #define START_ADDRESS           0xfe000000
  50 #define CHASSIS_BASE            0
  51 #define ONE_BASED_CHASSIS_NUM   1
  52
  53 /* register offsets inside the host bridge space */
  54 #define PHB_CSR_OFFSET          0x0110
  55 #define PHB_PLSSR_OFFSET        0x0120
  56 #define PHB_CONFIG_RW_OFFSET    0x0160
  57 #define PHB_IOBASE_BAR_LOW      0x0170
  58 #define PHB_IOBASE_BAR_HIGH     0x0180
  59 #define PHB_MEM_1_LOW           0x0190
  60 #define PHB_MEM_1_HIGH          0x01A0
  61 #define PHB_IO_ADDR_SIZE        0x01B0
  62 #define PHB_MEM_1_SIZE          0x01C0
  63 #define PHB_MEM_ST_OFFSET       0x01D0
  64 #define PHB_AER_OFFSET          0x0200
  65 #define PHB_CONFIG_0_HIGH       0x0220
  66 #define PHB_CONFIG_0_LOW        0x0230
  67 #define PHB_CONFIG_0_END        0x0240
  68 #define PHB_MEM_2_LOW           0x02B0
  69 #define PHB_MEM_2_HIGH          0x02C0
  70 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  71 #define PHB_MEM_2_SIZE_LOW      0x02E0
  72 #define PHB_DOSHOLE_OFFSET      0x08E0
  73
  74 /* PHB_CONFIG_RW */
  75 #define PHB_TCE_ENABLE          0x20000000
  76 #define PHB_SLOT_DISABLE        0x1C000000
  77 #define PHB_DAC_DISABLE         0x01000000
  78 #define PHB_MEM2_ENABLE         0x00400000
  79 #define PHB_MCSR_ENABLE         0x00100000
  80 /* TAR (Table Address Register) */
  81 #define TAR_SW_BITS             0x0000ffffffff800fUL
  82 #define TAR_VALID               0x0000000000000008UL
  83 /* CSR (Channel/DMA Status Register) */
  84 #define CSR_AGENT_MASK          0xffe0ffff
  85
  86 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  87 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  88 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) /* max dev->bus->number */
  89 #define PHBS_PER_CALGARY        4
  90
  91 /* register offsets in Calgary's internal register space */
  92 static const unsigned long tar_offsets[] = {
  93         0x0580 /* TAR0 */,
  94         0x0588 /* TAR1 */,
  95         0x0590 /* TAR2 */,
  96         0x0598 /* TAR3 */
  97 };
  98
  99 static const unsigned long split_queue_offsets[] = {
 100         0x4870 /* SPLIT QUEUE 0 */,
 101         0x5870 /* SPLIT QUEUE 1 */,
 102         0x6870 /* SPLIT QUEUE 2 */,
 103         0x7870 /* SPLIT QUEUE 3 */
 104 };
 105
 106 static const unsigned long phb_offsets[] = {
 107         0x8000 /* PHB0 */,
 108         0x9000 /* PHB1 */,
 109         0xA000 /* PHB2 */,
 110         0xB000 /* PHB3 */
 111 };
 112
 113 static char bus_to_phb[MAX_PHB_BUS_NUM];
 114 void* tce_table_kva[MAX_PHB_BUS_NUM];
 115 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 116 static int translate_empty_slots __read_mostly = 0;
 117 static int calgary_detected __read_mostly = 0;
 118
 119 /*
 120  * the bitmap of PHBs the user requested that we disable
 121  * translation on.
 122  */
 123 static DECLARE_BITMAP(translation_disabled, MAX_PHB_BUS_NUM);
 124
 125 static void tce_cache_blast(struct iommu_table *tbl);
 126
 127 /* enable this to stress test the chip's TCE cache */
 128 #ifdef CONFIG_IOMMU_DEBUG
 129 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 130 {
 131         tce_cache_blast(tbl);
 132 }
 133 #else
 134 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 135 {
 136 }
 137 #endif /* BLAST_TCE_CACHE_ON_UNMAP */
 138
 139 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 140 {
 141         unsigned int npages;
 142
 143         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 144         npages >>= PAGE_SHIFT;
 145
 146         return npages;
 147 }
 148
 149 static inline int translate_phb(struct pci_dev* dev)
 150 {
 151         int disabled = test_bit(dev->bus->number, translation_disabled);
 152         return !disabled;
 153 }
 154
 155 static void iommu_range_reserve(struct iommu_table *tbl,
 156         unsigned long start_addr, unsigned int npages)
 157 {
 158         unsigned long index;
 159         unsigned long end;
 160
 161         index = start_addr >> PAGE_SHIFT;
 162
 163         /* bail out if we're asked to reserve a region we don't cover */
 164         if (index >= tbl->it_size)
 165                 return;
 166
 167         end = index + npages;
 168         if (end > tbl->it_size) /* don't go off the table */
 169                 end = tbl->it_size;
 170
 171         while (index < end) {
 172                 if (test_bit(index, tbl->it_map))
 173                         printk(KERN_ERR "Calgary: entry already allocated at "
 174                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 175                                index, tbl, start_addr, npages);
 176                 ++index;
 177         }
 178         set_bit_string(tbl->it_map, start_addr >> PAGE_SHIFT, npages);
 179 }
 180
 181 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 182         unsigned int npages)
 183 {
 184         unsigned long offset;
 185
 186         BUG_ON(npages == 0);
 187
 188         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 189                                        tbl->it_size, npages);
 190         if (offset == ~0UL) {
 191                 tce_cache_blast(tbl);
 192                 offset = find_next_zero_string(tbl->it_map, 0,
 193                                                tbl->it_size, npages);
 194                 if (offset == ~0UL) {
 195                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 196                         if (panic_on_overflow)
 197                                 panic("Calgary: fix the allocator.\n");
 198                         else
 199                                 return bad_dma_address;
 200                 }
 201         }
 202
 203         set_bit_string(tbl->it_map, offset, npages);
 204         tbl->it_hint = offset + npages;
 205         BUG_ON(tbl->it_hint > tbl->it_size);
 206
 207         return offset;
 208 }
 209
 210 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 211         unsigned int npages, int direction)
 212 {
 213         unsigned long entry, flags;
 214         dma_addr_t ret = bad_dma_address;
 215
 216         spin_lock_irqsave(&tbl->it_lock, flags);
 217
 218         entry = iommu_range_alloc(tbl, npages);
 219
 220         if (unlikely(entry == bad_dma_address))
 221                 goto error;
 222
 223         /* set the return dma address */
 224         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 225
 226         /* put the TCEs in the HW table */
 227         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 228                   direction);
 229
 230         spin_unlock_irqrestore(&tbl->it_lock, flags);
 231
 232         return ret;
 233
 234 error:
 235         spin_unlock_irqrestore(&tbl->it_lock, flags);
 236         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 237                "iommu %p\n", npages, tbl);
 238         return bad_dma_address;
 239 }
 240
 241 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 242         unsigned int npages)
 243 {
 244         unsigned long entry;
 245         unsigned long i;
 246
 247         entry = dma_addr >> PAGE_SHIFT;
 248
 249         BUG_ON(entry + npages > tbl->it_size);
 250
 251         tce_free(tbl, entry, npages);
 252
 253         for (i = 0; i < npages; ++i) {
 254                 if (!test_bit(entry + i, tbl->it_map))
 255                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 256                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 257                                entry + i, tbl, dma_addr, entry, npages);
 258         }
 259
 260         __clear_bit_string(tbl->it_map, entry, npages);
 261
 262         tce_cache_blast_stress(tbl);
 263 }
 264
 265 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 266         unsigned int npages)
 267 {
 268         unsigned long flags;
 269
 270         spin_lock_irqsave(&tbl->it_lock, flags);
 271
 272         __iommu_free(tbl, dma_addr, npages);
 273
 274         spin_unlock_irqrestore(&tbl->it_lock, flags);
 275 }
 276
 277 static void __calgary_unmap_sg(struct iommu_table *tbl,
 278         struct scatterlist *sglist, int nelems, int direction)
 279 {
 280         while (nelems--) {
 281                 unsigned int npages;
 282                 dma_addr_t dma = sglist->dma_address;
 283                 unsigned int dmalen = sglist->dma_length;
 284
 285                 if (dmalen == 0)
 286                         break;
 287
 288                 npages = num_dma_pages(dma, dmalen);
 289                 __iommu_free(tbl, dma, npages);
 290                 sglist++;
 291         }
 292 }
 293
 294 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 295                       int nelems, int direction)
 296 {
 297         unsigned long flags;
 298         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 299
 300         if (!translate_phb(to_pci_dev(dev)))
 301                 return;
 302
 303         spin_lock_irqsave(&tbl->it_lock, flags);
 304
 305         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 306
 307         spin_unlock_irqrestore(&tbl->it_lock, flags);
 308 }
 309
 310 static int calgary_nontranslate_map_sg(struct device* dev,
 311         struct scatterlist *sg, int nelems, int direction)
 312 {
 313         int i;
 314
 315         for (i = 0; i < nelems; i++ ) {
 316                 struct scatterlist *s = &sg[i];
 317                 BUG_ON(!s->page);
 318                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 319                 s->dma_length = s->length;
 320         }
 321         return nelems;
 322 }
 323
 324 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 325         int nelems, int direction)
 326 {
 327         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 328         unsigned long flags;
 329         unsigned long vaddr;
 330         unsigned int npages;
 331         unsigned long entry;
 332         int i;
 333
 334         if (!translate_phb(to_pci_dev(dev)))
 335                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 336
 337         spin_lock_irqsave(&tbl->it_lock, flags);
 338
 339         for (i = 0; i < nelems; i++ ) {
 340                 struct scatterlist *s = &sg[i];
 341                 BUG_ON(!s->page);
 342
 343                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 344                 npages = num_dma_pages(vaddr, s->length);
 345
 346                 entry = iommu_range_alloc(tbl, npages);
 347                 if (entry == bad_dma_address) {
 348                         /* makes sure unmap knows to stop */
 349                         s->dma_length = 0;
 350                         goto error;
 351                 }
 352
 353                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 354
 355                 /* insert into HW table */
 356                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 357                           direction);
 358
 359                 s->dma_length = s->length;
 360         }
 361
 362         spin_unlock_irqrestore(&tbl->it_lock, flags);
 363
 364         return nelems;
 365 error:
 366         __calgary_unmap_sg(tbl, sg, nelems, direction);
 367         for (i = 0; i < nelems; i++) {
 368                 sg[i].dma_address = bad_dma_address;
 369                 sg[i].dma_length = 0;
 370         }
 371         spin_unlock_irqrestore(&tbl->it_lock, flags);
 372         return 0;
 373 }
 374
 375 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 376         size_t size, int direction)
 377 {
 378         dma_addr_t dma_handle = bad_dma_address;
 379         unsigned long uaddr;
 380         unsigned int npages;
 381         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 382
 383         uaddr = (unsigned long)vaddr;
 384         npages = num_dma_pages(uaddr, size);
 385
 386         if (translate_phb(to_pci_dev(dev)))
 387                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 388         else
 389                 dma_handle = virt_to_bus(vaddr);
 390
 391         return dma_handle;
 392 }
 393
 394 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 395         size_t size, int direction)
 396 {
 397         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 398         unsigned int npages;
 399
 400         if (!translate_phb(to_pci_dev(dev)))
 401                 return;
 402
 403         npages = num_dma_pages(dma_handle, size);
 404         iommu_free(tbl, dma_handle, npages);
 405 }
 406
 407 void* calgary_alloc_coherent(struct device *dev, size_t size,
 408         dma_addr_t *dma_handle, gfp_t flag)
 409 {
 410         void *ret = NULL;
 411         dma_addr_t mapping;
 412         unsigned int npages, order;
 413         struct iommu_table *tbl;
 414
 415         tbl = to_pci_dev(dev)->bus->self->sysdata;
 416
 417         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 418         npages = size >> PAGE_SHIFT;
 419         order = get_order(size);
 420
 421         /* alloc enough pages (and possibly more) */
 422         ret = (void *)__get_free_pages(flag, order);
 423         if (!ret)
 424                 goto error;
 425         memset(ret, 0, size);
 426
 427         if (translate_phb(to_pci_dev(dev))) {
 428                 /* set up tces to cover the allocated range */
 429                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 430                 if (mapping == bad_dma_address)
 431                         goto free;
 432
 433                 *dma_handle = mapping;
 434         } else /* non translated slot */
 435                 *dma_handle = virt_to_bus(ret);
 436
 437         return ret;
 438
 439 free:
 440         free_pages((unsigned long)ret, get_order(size));
 441         ret = NULL;
 442 error:
 443         return ret;
 444 }
 445
 446 static struct dma_mapping_ops calgary_dma_ops = {
 447         .alloc_coherent = calgary_alloc_coherent,
 448         .map_single = calgary_map_single,
 449         .unmap_single = calgary_unmap_single,
 450         .map_sg = calgary_map_sg,
 451         .unmap_sg = calgary_unmap_sg,
 452 };
 453
 454 static inline int busno_to_phbid(unsigned char num)
 455 {
 456         return bus_to_phb[num];
 457 }
 458
 459 static inline unsigned long split_queue_offset(unsigned char num)
 460 {
 461         size_t idx = busno_to_phbid(num);
 462
 463         return split_queue_offsets[idx];
 464 }
 465
 466 static inline unsigned long tar_offset(unsigned char num)
 467 {
 468         size_t idx = busno_to_phbid(num);
 469
 470         return tar_offsets[idx];
 471 }
 472
 473 static inline unsigned long phb_offset(unsigned char num)
 474 {
 475         size_t idx = busno_to_phbid(num);
 476
 477         return phb_offsets[idx];
 478 }
 479
 480 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 481 {
 482         unsigned long target = ((unsigned long)bar) | offset;
 483         return (void __iomem*)target;
 484 }
 485
 486 static void tce_cache_blast(struct iommu_table *tbl)
 487 {
 488         u64 val;
 489         u32 aer;
 490         int i = 0;
 491         void __iomem *bbar = tbl->bbar;
 492         void __iomem *target;
 493
 494         /* disable arbitration on the bus */
 495         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 496         aer = readl(target);
 497         writel(0, target);
 498
 499         /* read plssr to ensure it got there */
 500         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 501         val = readl(target);
 502
 503         /* poll split queues until all DMA activity is done */
 504         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 505         do {
 506                 val = readq(target);
 507                 i++;
 508         } while ((val & 0xff) != 0xff && i < 100);
 509         if (i == 100)
 510                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 511                        "continuing anyway\n");
 512
 513         /* invalidate TCE cache */
 514         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 515         writeq(tbl->tar_val, target);
 516
 517         /* enable arbitration */
 518         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 519         writel(aer, target);
 520         (void)readl(target); /* flush */
 521 }
 522
 523 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 524         u64 limit)
 525 {
 526         unsigned int numpages;
 527
 528         limit = limit | 0xfffff;
 529         limit++;
 530
 531         numpages = ((limit - start) >> PAGE_SHIFT);
 532         iommu_range_reserve(dev->sysdata, start, numpages);
 533 }
 534
 535 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 536 {
 537         void __iomem *target;
 538         u64 low, high, sizelow;
 539         u64 start, limit;
 540         struct iommu_table *tbl = dev->sysdata;
 541         unsigned char busnum = dev->bus->number;
 542         void __iomem *bbar = tbl->bbar;
 543
 544         /* peripheral MEM_1 region */
 545         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 546         low = be32_to_cpu(readl(target));
 547         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 548         high = be32_to_cpu(readl(target));
 549         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 550         sizelow = be32_to_cpu(readl(target));
 551
 552         start = (high << 32) | low;
 553         limit = sizelow;
 554
 555         calgary_reserve_mem_region(dev, start, limit);
 556 }
 557
 558 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 559 {
 560         void __iomem *target;
 561         u32 val32;
 562         u64 low, high, sizelow, sizehigh;
 563         u64 start, limit;
 564         struct iommu_table *tbl = dev->sysdata;
 565         unsigned char busnum = dev->bus->number;
 566         void __iomem *bbar = tbl->bbar;
 567
 568         /* is it enabled? */
 569         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 570         val32 = be32_to_cpu(readl(target));
 571         if (!(val32 & PHB_MEM2_ENABLE))
 572                 return;
 573
 574         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 575         low = be32_to_cpu(readl(target));
 576         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 577         high = be32_to_cpu(readl(target));
 578         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 579         sizelow = be32_to_cpu(readl(target));
 580         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 581         sizehigh = be32_to_cpu(readl(target));
 582
 583         start = (high << 32) | low;
 584         limit = (sizehigh << 32) | sizelow;
 585
 586         calgary_reserve_mem_region(dev, start, limit);
 587 }
 588
 589 /*
 590  * some regions of the IO address space do not get translated, so we
 591  * must not give devices IO addresses in those regions. The regions
 592  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 593  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 594  * later.
 595  */
 596 static void __init calgary_reserve_regions(struct pci_dev *dev)
 597 {
 598         unsigned int npages;
 599         void __iomem *bbar;
 600         unsigned char busnum;
 601         u64 start;
 602         struct iommu_table *tbl = dev->sysdata;
 603
 604         bbar = tbl->bbar;
 605         busnum = dev->bus->number;
 606
 607         /* reserve bad_dma_address in case it's a legal address */
 608         iommu_range_reserve(tbl, bad_dma_address, 1);
 609
 610         /* avoid the BIOS/VGA first 640KB-1MB region */
 611         start = (640 * 1024);
 612         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 613         iommu_range_reserve(tbl, start, npages);
 614
 615         /* reserve the two PCI peripheral memory regions in IO space */
 616         calgary_reserve_peripheral_mem_1(dev);
 617         calgary_reserve_peripheral_mem_2(dev);
 618 }
 619
 620 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 621 {
 622         u64 val64;
 623         u64 table_phys;
 624         void __iomem *target;
 625         int ret;
 626         struct iommu_table *tbl;
 627
 628         /* build TCE tables for each PHB */
 629         ret = build_tce_table(dev, bbar);
 630         if (ret)
 631                 return ret;
 632
 633         calgary_reserve_regions(dev);
 634
 635         /* set TARs for each PHB */
 636         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 637         val64 = be64_to_cpu(readq(target));
 638
 639         /* zero out all TAR bits under sw control */
 640         val64 &= ~TAR_SW_BITS;
 641
 642         tbl = dev->sysdata;
 643         table_phys = (u64)__pa(tbl->it_base);
 644         val64 |= table_phys;
 645
 646         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 647         val64 |= (u64) specified_table_size;
 648
 649         tbl->tar_val = cpu_to_be64(val64);
 650         writeq(tbl->tar_val, target);
 651         readq(target); /* flush */
 652
 653         return 0;
 654 }
 655
 656 static void __init calgary_free_tar(struct pci_dev *dev)
 657 {
 658         u64 val64;
 659         struct iommu_table *tbl = dev->sysdata;
 660         void __iomem *target;
 661
 662         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 663         val64 = be64_to_cpu(readq(target));
 664         val64 &= ~TAR_SW_BITS;
 665         writeq(cpu_to_be64(val64), target);
 666         readq(target); /* flush */
 667
 668         kfree(tbl);
 669         dev->sysdata = NULL;
 670 }
 671
 672 static void calgary_watchdog(unsigned long data)
 673 {
 674         struct pci_dev *dev = (struct pci_dev *)data;
 675         struct iommu_table *tbl = dev->sysdata;
 676         void __iomem *bbar = tbl->bbar;
 677         u32 val32;
 678         void __iomem *target;
 679
 680         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 681         val32 = be32_to_cpu(readl(target));
 682
 683         /* If no error, the agent ID in the CSR is not valid */
 684         if (val32 & CSR_AGENT_MASK) {
 685                 printk(KERN_EMERG "calgary_watchdog: DMA error on bus %d, "
 686                                   "CSR = %#x\n", dev->bus->number, val32);
 687                 writel(0, target);
 688
 689                 /* Disable bus that caused the error */
 690                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 691                                            PHB_CONFIG_RW_OFFSET);
 692                 val32 = be32_to_cpu(readl(target));
 693                 val32 |= PHB_SLOT_DISABLE;
 694                 writel(cpu_to_be32(val32), target);
 695                 readl(target); /* flush */
 696         } else {
 697                 /* Reset the timer */
 698                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 699         }
 700 }
 701
 702 static void __init calgary_enable_translation(struct pci_dev *dev)
 703 {
 704         u32 val32;
 705         unsigned char busnum;
 706         void __iomem *target;
 707         void __iomem *bbar;
 708         struct iommu_table *tbl;
 709
 710         busnum = dev->bus->number;
 711         tbl = dev->sysdata;
 712         bbar = tbl->bbar;
 713
 714         /* enable TCE in PHB Config Register */
 715         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 716         val32 = be32_to_cpu(readl(target));
 717         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 718
 719         printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
 720         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 721                "bus.\n");
 722
 723         writel(cpu_to_be32(val32), target);
 724         readl(target); /* flush */
 725
 726         init_timer(&tbl->watchdog_timer);
 727         tbl->watchdog_timer.function = &calgary_watchdog;
 728         tbl->watchdog_timer.data = (unsigned long)dev;
 729         mod_timer(&tbl->watchdog_timer, jiffies);
 730 }
 731
 732 static void __init calgary_disable_translation(struct pci_dev *dev)
 733 {
 734         u32 val32;
 735         unsigned char busnum;
 736         void __iomem *target;
 737         void __iomem *bbar;
 738         struct iommu_table *tbl;
 739
 740         busnum = dev->bus->number;
 741         tbl = dev->sysdata;
 742         bbar = tbl->bbar;
 743
 744         /* disable TCE in PHB Config Register */
 745         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 746         val32 = be32_to_cpu(readl(target));
 747         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 748
 749         printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
 750         writel(cpu_to_be32(val32), target);
 751         readl(target); /* flush */
 752
 753         del_timer_sync(&tbl->watchdog_timer);
 754 }
 755
 756 static inline unsigned int __init locate_register_space(struct pci_dev *dev)
 757 {
 758         int rionodeid;
 759         u32 address;
 760
 761         /*
 762          * Each Calgary has four busses. The first four busses (first Calgary)
 763          * have RIO node ID 2, then the next four (second Calgary) have RIO
 764          * node ID 3, the next four (third Calgary) have node ID 2 again, etc.
 765          * We use a gross hack - relying on the dev->bus->number ordering,
 766          * modulo 14 - to decide which Calgary a given bus is on. Busses 0, 1,
 767          * 2 and 4 are on the first Calgary (id 2), 6, 8, a and c are on the
 768          * second (id 3), and then it repeats modulo 14.
 769          */
 770         rionodeid = (dev->bus->number % 14 > 4) ? 3 : 2;
 771         /*
 772          * register space address calculation as follows:
 773          * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
 774          * ChassisBase is always zero for x366/x260/x460
 775          * RioNodeId is 2 for first Calgary, 3 for second Calgary
 776          */
 777         address = START_ADDRESS -
 778                 (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 14)) +
 779                 (0x100000) * (rionodeid - CHASSIS_BASE);
 780         return address;
 781 }
 782
 783 static int __init calgary_init_one_nontraslated(struct pci_dev *dev)
 784 {
 785         dev->sysdata = NULL;
 786         dev->bus->self = dev;
 787
 788         return 0;
 789 }
 790
 791 static int __init calgary_init_one(struct pci_dev *dev)
 792 {
 793         u32 address;
 794         void __iomem *bbar;
 795         int ret;
 796
 797         address = locate_register_space(dev);
 798         /* map entire 1MB of Calgary config space */
 799         bbar = ioremap_nocache(address, 1024 * 1024);
 800         if (!bbar) {
 801                 ret = -ENODATA;
 802                 goto done;
 803         }
 804
 805         ret = calgary_setup_tar(dev, bbar);
 806         if (ret)
 807                 goto iounmap;
 808
 809         dev->bus->self = dev;
 810         calgary_enable_translation(dev);
 811
 812         return 0;
 813
 814 iounmap:
 815         iounmap(bbar);
 816 done:
 817         return ret;
 818 }
 819
 820 static int __init calgary_init(void)
 821 {
 822         int i, ret = -ENODEV;
 823         struct pci_dev *dev = NULL;
 824
 825         for (i = 0; i < MAX_PHB_BUS_NUM; i++) {
 826                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 827                                      PCI_DEVICE_ID_IBM_CALGARY,
 828                                      dev);
 829                 if (!dev)
 830                         break;
 831                 if (!translate_phb(dev)) {
 832                         calgary_init_one_nontraslated(dev);
 833                         continue;
 834                 }
 835                 if (!tce_table_kva[dev->bus->number] && !translate_empty_slots) {
 836                         pci_dev_put(dev);
 837                         continue;
 838                 }
 839                 ret = calgary_init_one(dev);
 840                 if (ret)
 841                         goto error;
 842         }
 843
 844         return ret;
 845
 846 error:
 847         for (i--; i >= 0; i--) {
 848                 dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
 849                                               PCI_DEVICE_ID_IBM_CALGARY,
 850                                               dev);
 851                 if (!translate_phb(dev)) {
 852                         pci_dev_put(dev);
 853                         continue;
 854                 }
 855                 if (!tce_table_kva[dev->bus->number] && !translate_empty_slots)
 856                         continue;
 857                 calgary_disable_translation(dev);
 858                 calgary_free_tar(dev);
 859                 pci_dev_put(dev);
 860         }
 861
 862         return ret;
 863 }
 864
 865 static inline int __init determine_tce_table_size(u64 ram)
 866 {
 867         int ret;
 868
 869         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 870                 return specified_table_size;
 871
 872         /*
 873          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
 874          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
 875          * larger table size has twice as many entries, so shift the
 876          * max ram address by 13 to divide by 8K and then look at the
 877          * order of the result to choose between 0-7.
 878          */
 879         ret = get_order(ram >> 13);
 880         if (ret > TCE_TABLE_SIZE_8M)
 881                 ret = TCE_TABLE_SIZE_8M;
 882
 883         return ret;
 884 }
 885
 886 void __init detect_calgary(void)
 887 {
 888         u32 val;
 889         int bus;
 890         void *tbl;
 891         int calgary_found = 0;
 892         int phb = -1;
 893
 894         /*
 895          * if the user specified iommu=off or iommu=soft or we found
 896          * another HW IOMMU already, bail out.
 897          */
 898         if (swiotlb || no_iommu || iommu_detected)
 899                 return;
 900
 901         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
 902
 903         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
 904                 int dev;
 905
 906                 tce_table_kva[bus] = NULL;
 907                 bus_to_phb[bus] = -1;
 908
 909                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
 910                         continue;
 911
 912                 /*
 913                  * There are 4 PHBs per Calgary chip.  Set phb to which phb (0-3)
 914                  * it is connected to releative to the clagary chip.
 915                  */
 916                 phb = (phb + 1) % PHBS_PER_CALGARY;
 917
 918                 if (test_bit(bus, translation_disabled)) {
 919                         printk(KERN_INFO "Calgary: translation is disabled for "
 920                                "PHB 0x%x\n", bus);
 921                         /* skip this phb, don't allocate a tbl for it */
 922                         continue;
 923                 }
 924                 /*
 925                  * Scan the slots of the PCI bus to see if there is a device present.
 926                  * The parent bus will be the zero-ith device, so start at 1.
 927                  */
 928                 for (dev = 1; dev < 8; dev++) {
 929                         val = read_pci_config(bus, dev, 0, 0);
 930                         if (val != 0xffffffff || translate_empty_slots) {
 931                                 tbl = alloc_tce_table();
 932                                 if (!tbl)
 933                                         goto cleanup;
 934                                 tce_table_kva[bus] = tbl;
 935                                 bus_to_phb[bus] = phb;
 936                                 calgary_found = 1;
 937                                 break;
 938                         }
 939                 }
 940         }
 941
 942         if (calgary_found) {
 943                 iommu_detected = 1;
 944                 calgary_detected = 1;
 945                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. "
 946                        "TCE table spec is %d.\n", specified_table_size);
 947         }
 948         return;
 949
 950 cleanup:
 951         for (--bus; bus >= 0; --bus)
 952                 if (tce_table_kva[bus])
 953                         free_tce_table(tce_table_kva[bus]);
 954 }
 955
 956 int __init calgary_iommu_init(void)
 957 {
 958         int ret;
 959
 960         if (no_iommu || swiotlb)
 961                 return -ENODEV;
 962
 963         if (!calgary_detected)
 964                 return -ENODEV;
 965
 966         /* ok, we're trying to use Calgary - let's roll */
 967         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
 968
 969         ret = calgary_init();
 970         if (ret) {
 971                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
 972                        "falling back to no_iommu\n", ret);
 973                 if (end_pfn > MAX_DMA32_PFN)
 974                         printk(KERN_ERR "WARNING more than 4GB of memory, "
 975                                         "32bit PCI may malfunction.\n");
 976                 return ret;
 977         }
 978
 979         force_iommu = 1;
 980         dma_ops = &calgary_dma_ops;
 981
 982         return 0;
 983 }
 984
 985 static int __init calgary_parse_options(char *p)
 986 {
 987         unsigned int bridge;
 988         size_t len;
 989         char* endp;
 990
 991         while (*p) {
 992                 if (!strncmp(p, "64k", 3))
 993                         specified_table_size = TCE_TABLE_SIZE_64K;
 994                 else if (!strncmp(p, "128k", 4))
 995                         specified_table_size = TCE_TABLE_SIZE_128K;
 996                 else if (!strncmp(p, "256k", 4))
 997                         specified_table_size = TCE_TABLE_SIZE_256K;
 998                 else if (!strncmp(p, "512k", 4))
 999                         specified_table_size = TCE_TABLE_SIZE_512K;
1000                 else if (!strncmp(p, "1M", 2))
1001                         specified_table_size = TCE_TABLE_SIZE_1M;
1002                 else if (!strncmp(p, "2M", 2))
1003                         specified_table_size = TCE_TABLE_SIZE_2M;
1004                 else if (!strncmp(p, "4M", 2))
1005                         specified_table_size = TCE_TABLE_SIZE_4M;
1006                 else if (!strncmp(p, "8M", 2))
1007                         specified_table_size = TCE_TABLE_SIZE_8M;
1008
1009                 len = strlen("translate_empty_slots");
1010                 if (!strncmp(p, "translate_empty_slots", len))
1011                         translate_empty_slots = 1;
1012
1013                 len = strlen("disable");
1014                 if (!strncmp(p, "disable", len)) {
1015                         p += len;
1016                         if (*p == '=')
1017                                 ++p;
1018                         if (*p == '\0')
1019                                 break;
1020                         bridge = simple_strtol(p, &endp, 0);
1021                         if (p == endp)
1022                                 break;
1023
1024                         if (bridge < MAX_PHB_BUS_NUM) {
1025                                 printk(KERN_INFO "Calgary: disabling "
1026                                        "translation for PHB 0x%x\n", bridge);
1027                                 set_bit(bridge, translation_disabled);
1028                         }
1029                 }
1030
1031                 p = strpbrk(p, ",");
1032                 if (!p)
1033                         break;
1034
1035                 p++; /* skip ',' */
1036         }
1037         return 1;
1038 }
1039 __setup("calgary=", calgary_parse_options);