drivers/char/agp/amd-k7-agp.c

   1 /*
   2  * AMD K7 AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/gfp.h>
  10 #include <linux/page-flags.h>
  11 #include <linux/mm.h>
  12 #include "agp.h"
  13
  14 #define AMD_MMBASE      0x14
  15 #define AMD_APSIZE      0xac
  16 #define AMD_MODECNTL    0xb0
  17 #define AMD_MODECNTL2   0xb2
  18 #define AMD_GARTENABLE  0x02    /* In mmio region (16-bit register) */
  19 #define AMD_ATTBASE     0x04    /* In mmio region (32-bit register) */
  20 #define AMD_TLBFLUSH    0x0c    /* In mmio region (32-bit register) */
  21 #define AMD_CACHEENTRY  0x10    /* In mmio region (32-bit register) */
  22
  23 static struct pci_device_id agp_amdk7_pci_table[];
  24
  25 struct amd_page_map {
  26         unsigned long *real;
  27         unsigned long __iomem *remapped;
  28 };
  29
  30 static struct _amd_irongate_private {
  31         volatile u8 __iomem *registers;
  32         struct amd_page_map **gatt_pages;
  33         int num_tables;
  34 } amd_irongate_private;
  35
  36 static int amd_create_page_map(struct amd_page_map *page_map)
  37 {
  38         int i;
  39
  40         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  41         if (page_map->real == NULL)
  42                 return -ENOMEM;
  43
  44         SetPageReserved(virt_to_page(page_map->real));
  45         global_cache_flush();
  46         page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
  47                                             PAGE_SIZE);
  48         if (page_map->remapped == NULL) {
  49                 ClearPageReserved(virt_to_page(page_map->real));
  50                 free_page((unsigned long) page_map->real);
  51                 page_map->real = NULL;
  52                 return -ENOMEM;
  53         }
  54         global_cache_flush();
  55
  56         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
  57                 writel(agp_bridge->scratch_page, page_map->remapped+i);
  58                 readl(page_map->remapped+i);    /* PCI Posting. */
  59         }
  60
  61         return 0;
  62 }
  63
  64 static void amd_free_page_map(struct amd_page_map *page_map)
  65 {
  66         iounmap(page_map->remapped);
  67         ClearPageReserved(virt_to_page(page_map->real));
  68         free_page((unsigned long) page_map->real);
  69 }
  70
  71 static void amd_free_gatt_pages(void)
  72 {
  73         int i;
  74         struct amd_page_map **tables;
  75         struct amd_page_map *entry;
  76
  77         tables = amd_irongate_private.gatt_pages;
  78         for (i = 0; i < amd_irongate_private.num_tables; i++) {
  79                 entry = tables[i];
  80                 if (entry != NULL) {
  81                         if (entry->real != NULL)
  82                                 amd_free_page_map(entry);
  83                         kfree(entry);
  84                 }
  85         }
  86         kfree(tables);
  87         amd_irongate_private.gatt_pages = NULL;
  88 }
  89
  90 static int amd_create_gatt_pages(int nr_tables)
  91 {
  92         struct amd_page_map **tables;
  93         struct amd_page_map *entry;
  94         int retval = 0;
  95         int i;
  96
  97         tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *),
  98                          GFP_KERNEL);
  99         if (tables == NULL)
 100                 return -ENOMEM;
 101
 102         memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1));
 103         for (i = 0; i < nr_tables; i++) {
 104                 entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL);
 105                 if (entry == NULL) {
 106                         retval = -ENOMEM;
 107                         break;
 108                 }
 109                 memset (entry, 0, sizeof(struct amd_page_map));
 110                 tables[i] = entry;
 111                 retval = amd_create_page_map(entry);
 112                 if (retval != 0)
 113                         break;
 114         }
 115         amd_irongate_private.num_tables = nr_tables;
 116         amd_irongate_private.gatt_pages = tables;
 117
 118         if (retval != 0)
 119                 amd_free_gatt_pages();
 120
 121         return retval;
 122 }
 123
 124 /* Since we don't need contigious memory we just try
 125  * to get the gatt table once
 126  */
 127
 128 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 129 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 130         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 131 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 132 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
 133         GET_PAGE_DIR_IDX(addr)]->remapped)
 134
 135 static int amd_create_gatt_table(void)
 136 {
 137         struct aper_size_info_lvl2 *value;
 138         struct amd_page_map page_dir;
 139         unsigned long addr;
 140         int retval;
 141         u32 temp;
 142         int i;
 143
 144         value = A_SIZE_LVL2(agp_bridge->current_size);
 145         retval = amd_create_page_map(&page_dir);
 146         if (retval != 0)
 147                 return retval;
 148
 149         retval = amd_create_gatt_pages(value->num_entries / 1024);
 150         if (retval != 0) {
 151                 amd_free_page_map(&page_dir);
 152                 return retval;
 153         }
 154
 155         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 156         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
 157         agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
 158
 159         /* Get the address for the gart region.
 160          * This is a bus address even on the alpha, b/c its
 161          * used to program the agp master not the cpu
 162          */
 163
 164         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
 165         addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 166         agp_bridge->gart_bus_addr = addr;
 167
 168         /* Calculate the agp offset */
 169         for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
 170                 writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
 171                         page_dir.remapped+GET_PAGE_DIR_OFF(addr));
 172                 readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));        /* PCI Posting. */
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int amd_free_gatt_table(void)
 179 {
 180         struct amd_page_map page_dir;
 181
 182         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 183         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
 184
 185         amd_free_gatt_pages();
 186         amd_free_page_map(&page_dir);
 187         return 0;
 188 }
 189
 190 static int amd_irongate_fetch_size(void)
 191 {
 192         int i;
 193         u32 temp;
 194         struct aper_size_info_lvl2 *values;
 195
 196         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 197         temp = (temp & 0x0000000e);
 198         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 199         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 200                 if (temp == values[i].size_value) {
 201                         agp_bridge->previous_size =
 202                             agp_bridge->current_size = (void *) (values + i);
 203
 204                         agp_bridge->aperture_size_idx = i;
 205                         return values[i].size;
 206                 }
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int amd_irongate_configure(void)
 213 {
 214         struct aper_size_info_lvl2 *current_size;
 215         u32 temp;
 216         u16 enable_reg;
 217
 218         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 219
 220         /* Get the memory mapped registers */
 221         pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
 222         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 223         amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 224
 225         /* Write out the address of the gatt table */
 226         writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
 227         readl(amd_irongate_private.registers+AMD_ATTBASE);      /* PCI Posting. */
 228
 229         /* Write the Sync register */
 230         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
 231
 232         /* Set indexing mode */
 233         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
 234
 235         /* Write the enable register */
 236         enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
 237         enable_reg = (enable_reg | 0x0004);
 238         writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
 239         readw(amd_irongate_private.registers+AMD_GARTENABLE);   /* PCI Posting. */
 240
 241         /* Write out the size register */
 242         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 243         temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
 244         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 245
 246         /* Flush the tlb */
 247         writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
 248         readl(amd_irongate_private.registers+AMD_TLBFLUSH);     /* PCI Posting.*/
 249         return 0;
 250 }
 251
 252 static void amd_irongate_cleanup(void)
 253 {
 254         struct aper_size_info_lvl2 *previous_size;
 255         u32 temp;
 256         u16 enable_reg;
 257
 258         previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
 259
 260         enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
 261         enable_reg = (enable_reg & ~(0x0004));
 262         writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
 263         readw(amd_irongate_private.registers+AMD_GARTENABLE);   /* PCI Posting. */
 264
 265         /* Write back the previous size and disable gart translation */
 266         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 267         temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
 268         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 269         iounmap((void __iomem *) amd_irongate_private.registers);
 270 }
 271
 272 /*
 273  * This routine could be implemented by taking the addresses
 274  * written to the GATT, and flushing them individually.  However
 275  * currently it just flushes the whole table.  Which is probably
 276  * more efficent, since agp_memory blocks can be a large number of
 277  * entries.
 278  */
 279
 280 static void amd_irongate_tlbflush(struct agp_memory *temp)
 281 {
 282         writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
 283         readl(amd_irongate_private.registers+AMD_TLBFLUSH);     /* PCI Posting. */
 284 }
 285
 286 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 287 {
 288         int i, j, num_entries;
 289         unsigned long __iomem *cur_gatt;
 290         unsigned long addr;
 291
 292         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 293
 294         if (type != 0 || mem->type != 0)
 295                 return -EINVAL;
 296
 297         if ((pg_start + mem->page_count) > num_entries)
 298                 return -EINVAL;
 299
 300         j = pg_start;
 301         while (j < (pg_start + mem->page_count)) {
 302                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 303                 cur_gatt = GET_GATT(addr);
 304                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
 305                         return -EBUSY;
 306                 j++;
 307         }
 308
 309         if (mem->is_flushed == FALSE) {
 310                 global_cache_flush();
 311                 mem->is_flushed = TRUE;
 312         }
 313
 314         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 315                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 316                 cur_gatt = GET_GATT(addr);
 317                 writel(agp_generic_mask_memory(mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
 318                 readl(cur_gatt+GET_GATT_OFF(addr));     /* PCI Posting. */
 319         }
 320         amd_irongate_tlbflush(mem);
 321         return 0;
 322 }
 323
 324 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 325 {
 326         int i;
 327         unsigned long __iomem *cur_gatt;
 328         unsigned long addr;
 329
 330         if (type != 0 || mem->type != 0)
 331                 return -EINVAL;
 332
 333         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 334                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 335                 cur_gatt = GET_GATT(addr);
 336                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
 337                 readl(cur_gatt+GET_GATT_OFF(addr));     /* PCI Posting. */
 338         }
 339
 340         amd_irongate_tlbflush(mem);
 341         return 0;
 342 }
 343
 344 static struct aper_size_info_lvl2 amd_irongate_sizes[7] =
 345 {
 346         {2048, 524288, 0x0000000c},
 347         {1024, 262144, 0x0000000a},
 348         {512, 131072, 0x00000008},
 349         {256, 65536, 0x00000006},
 350         {128, 32768, 0x00000004},
 351         {64, 16384, 0x00000002},
 352         {32, 8192, 0x00000000}
 353 };
 354
 355 static struct gatt_mask amd_irongate_masks[] =
 356 {
 357         {.mask = 1, .type = 0}
 358 };
 359
 360 struct agp_bridge_driver amd_irongate_driver = {
 361         .owner                  = THIS_MODULE,
 362         .aperture_sizes         = amd_irongate_sizes,
 363         .size_type              = LVL2_APER_SIZE,
 364         .num_aperture_sizes     = 7,
 365         .configure              = amd_irongate_configure,
 366         .fetch_size             = amd_irongate_fetch_size,
 367         .cleanup                = amd_irongate_cleanup,
 368         .tlb_flush              = amd_irongate_tlbflush,
 369         .mask_memory            = agp_generic_mask_memory,
 370         .masks                  = amd_irongate_masks,
 371         .agp_enable             = agp_generic_enable,
 372         .cache_flush            = global_cache_flush,
 373         .create_gatt_table      = amd_create_gatt_table,
 374         .free_gatt_table        = amd_free_gatt_table,
 375         .insert_memory          = amd_insert_memory,
 376         .remove_memory          = amd_remove_memory,
 377         .alloc_by_type          = agp_generic_alloc_by_type,
 378         .free_by_type           = agp_generic_free_by_type,
 379         .agp_alloc_page         = agp_generic_alloc_page,
 380         .agp_destroy_page       = agp_generic_destroy_page,
 381 };
 382
 383 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
 384 {
 385         {
 386                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_7006,
 387                 .chipset_name   = "Irongate",
 388         },
 389         {
 390                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700E,
 391                 .chipset_name   = "761",
 392         },
 393         {
 394                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700C,
 395                 .chipset_name   = "760MP",
 396         },
 397         { }, /* dummy final entry, always present */
 398 };
 399
 400 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
 401                                      const struct pci_device_id *ent)
 402 {
 403         struct agp_bridge_data *bridge;
 404         u8 cap_ptr;
 405         int j;
 406
 407         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 408         if (!cap_ptr)
 409                 return -ENODEV;
 410
 411         j = ent - agp_amdk7_pci_table;
 412         printk(KERN_INFO PFX "Detected AMD %s chipset\n",
 413                amd_agp_device_ids[j].chipset_name);
 414
 415         bridge = agp_alloc_bridge();
 416         if (!bridge)
 417                 return -ENOMEM;
 418
 419         bridge->driver = &amd_irongate_driver;
 420         bridge->dev_private_data = &amd_irongate_private,
 421         bridge->dev = pdev;
 422         bridge->capndx = cap_ptr;
 423
 424         /* Fill in the mode register */
 425         pci_read_config_dword(pdev,
 426                         bridge->capndx+PCI_AGP_STATUS,
 427                         &bridge->mode);
 428
 429         pci_set_drvdata(pdev, bridge);
 430         return agp_add_bridge(bridge);
 431 }
 432
 433 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
 434 {
 435         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 436
 437         agp_remove_bridge(bridge);
 438         agp_put_bridge(bridge);
 439 }
 440
 441 /* must be the same order as name table above */
 442 static struct pci_device_id agp_amdk7_pci_table[] = {
 443         {
 444         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 445         .class_mask     = ~0,
 446         .vendor         = PCI_VENDOR_ID_AMD,
 447         .device         = PCI_DEVICE_ID_AMD_FE_GATE_7006,
 448         .subvendor      = PCI_ANY_ID,
 449         .subdevice      = PCI_ANY_ID,
 450         },
 451         {
 452         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 453         .class_mask     = ~0,
 454         .vendor         = PCI_VENDOR_ID_AMD,
 455         .device         = PCI_DEVICE_ID_AMD_FE_GATE_700E,
 456         .subvendor      = PCI_ANY_ID,
 457         .subdevice      = PCI_ANY_ID,
 458         },
 459         {
 460         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 461         .class_mask     = ~0,
 462         .vendor         = PCI_VENDOR_ID_AMD,
 463         .device         = PCI_DEVICE_ID_AMD_FE_GATE_700C,
 464         .subvendor      = PCI_ANY_ID,
 465         .subdevice      = PCI_ANY_ID,
 466         },
 467         { }
 468 };
 469
 470 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
 471
 472 static struct pci_driver agp_amdk7_pci_driver = {
 473         .name           = "agpgart-amdk7",
 474         .id_table       = agp_amdk7_pci_table,
 475         .probe          = agp_amdk7_probe,
 476         .remove         = agp_amdk7_remove,
 477 };
 478
 479 static int __init agp_amdk7_init(void)
 480 {
 481         if (agp_off)
 482                 return -EINVAL;
 483         return pci_module_init(&agp_amdk7_pci_driver);
 484 }
 485
 486 static void __exit agp_amdk7_cleanup(void)
 487 {
 488         pci_unregister_driver(&agp_amdk7_pci_driver);
 489 }
 490
 491 module_init(agp_amdk7_init);
 492 module_exit(agp_amdk7_cleanup);
 493
 494 MODULE_LICENSE("GPL and additional rights");