drivers/char/agp/amd-k7-agp.c

   1 /*
   2  * AMD K7 AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/gfp.h>
  10 #include <linux/page-flags.h>
  11 #include <linux/mm.h>
  12 #include "agp.h"
  13
  14 #define AMD_MMBASE      0x14
  15 #define AMD_APSIZE      0xac
  16 #define AMD_MODECNTL    0xb0
  17 #define AMD_MODECNTL2   0xb2
  18 #define AMD_GARTENABLE  0x02    /* In mmio region (16-bit register) */
  19 #define AMD_ATTBASE     0x04    /* In mmio region (32-bit register) */
  20 #define AMD_TLBFLUSH    0x0c    /* In mmio region (32-bit register) */
  21 #define AMD_CACHEENTRY  0x10    /* In mmio region (32-bit register) */
  22
  23 struct amd_page_map {
  24         unsigned long *real;
  25         unsigned long *remapped;
  26 };
  27
  28 static struct _amd_irongate_private {
  29         volatile u8 *registers;
  30         struct amd_page_map **gatt_pages;
  31         int num_tables;
  32 } amd_irongate_private;
  33
  34 static int amd_create_page_map(struct amd_page_map *page_map)
  35 {
  36         int i;
  37
  38         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  39         if (page_map->real == NULL)
  40                 return -ENOMEM;
  41
  42         SetPageReserved(virt_to_page(page_map->real));
  43         global_cache_flush();
  44         page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
  45                                             PAGE_SIZE);
  46         if (page_map->remapped == NULL) {
  47                 ClearPageReserved(virt_to_page(page_map->real));
  48                 free_page((unsigned long) page_map->real);
  49                 page_map->real = NULL;
  50                 return -ENOMEM;
  51         }
  52         global_cache_flush();
  53
  54         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
  55                 page_map->remapped[i] = agp_bridge->scratch_page;
  56
  57         return 0;
  58 }
  59
  60 static void amd_free_page_map(struct amd_page_map *page_map)
  61 {
  62         iounmap(page_map->remapped);
  63         ClearPageReserved(virt_to_page(page_map->real));
  64         free_page((unsigned long) page_map->real);
  65 }
  66
  67 static void amd_free_gatt_pages(void)
  68 {
  69         int i;
  70         struct amd_page_map **tables;
  71         struct amd_page_map *entry;
  72
  73         tables = amd_irongate_private.gatt_pages;
  74         for (i = 0; i < amd_irongate_private.num_tables; i++) {
  75                 entry = tables[i];
  76                 if (entry != NULL) {
  77                         if (entry->real != NULL)
  78                                 amd_free_page_map(entry);
  79                         kfree(entry);
  80                 }
  81         }
  82         kfree(tables);
  83         amd_irongate_private.gatt_pages = NULL;
  84 }
  85
  86 static int amd_create_gatt_pages(int nr_tables)
  87 {
  88         struct amd_page_map **tables;
  89         struct amd_page_map *entry;
  90         int retval = 0;
  91         int i;
  92
  93         tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *),
  94                          GFP_KERNEL);
  95         if (tables == NULL)
  96                 return -ENOMEM;
  97
  98         memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1));
  99         for (i = 0; i < nr_tables; i++) {
 100                 entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL);
 101                 if (entry == NULL) {
 102                         retval = -ENOMEM;
 103                         break;
 104                 }
 105                 memset (entry, 0, sizeof(struct amd_page_map));
 106                 tables[i] = entry;
 107                 retval = amd_create_page_map(entry);
 108                 if (retval != 0)
 109                         break;
 110         }
 111         amd_irongate_private.num_tables = nr_tables;
 112         amd_irongate_private.gatt_pages = tables;
 113
 114         if (retval != 0)
 115                 amd_free_gatt_pages();
 116
 117         return retval;
 118 }
 119
 120 /* Since we don't need contigious memory we just try
 121  * to get the gatt table once
 122  */
 123
 124 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 125 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 126         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 127 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 128 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
 129         GET_PAGE_DIR_IDX(addr)]->remapped)
 130
 131 static int amd_create_gatt_table(void)
 132 {
 133         struct aper_size_info_lvl2 *value;
 134         struct amd_page_map page_dir;
 135         unsigned long addr;
 136         int retval;
 137         u32 temp;
 138         int i;
 139
 140         value = A_SIZE_LVL2(agp_bridge->current_size);
 141         retval = amd_create_page_map(&page_dir);
 142         if (retval != 0)
 143                 return retval;
 144
 145         retval = amd_create_gatt_pages(value->num_entries / 1024);
 146         if (retval != 0) {
 147                 amd_free_page_map(&page_dir);
 148                 return retval;
 149         }
 150
 151         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 152         agp_bridge->gatt_table = (u32 *)page_dir.remapped;
 153         agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
 154
 155         /* Get the address for the gart region.
 156          * This is a bus address even on the alpha, b/c its
 157          * used to program the agp master not the cpu
 158          */
 159
 160         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
 161         addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 162         agp_bridge->gart_bus_addr = addr;
 163
 164         /* Calculate the agp offset */
 165         for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
 166                 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] =
 167                         virt_to_phys(amd_irongate_private.gatt_pages[i]->real);
 168                 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] |= 0x00000001;
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int amd_free_gatt_table(void)
 175 {
 176         struct amd_page_map page_dir;
 177
 178         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 179         page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
 180
 181         amd_free_gatt_pages();
 182         amd_free_page_map(&page_dir);
 183         return 0;
 184 }
 185
 186 static int amd_irongate_fetch_size(void)
 187 {
 188         int i;
 189         u32 temp;
 190         struct aper_size_info_lvl2 *values;
 191
 192         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 193         temp = (temp & 0x0000000e);
 194         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 195         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 196                 if (temp == values[i].size_value) {
 197                         agp_bridge->previous_size =
 198                             agp_bridge->current_size = (void *) (values + i);
 199
 200                         agp_bridge->aperture_size_idx = i;
 201                         return values[i].size;
 202                 }
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int amd_irongate_configure(void)
 209 {
 210         struct aper_size_info_lvl2 *current_size;
 211         u32 temp;
 212         u16 enable_reg;
 213
 214         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 215
 216         /* Get the memory mapped registers */
 217         pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
 218         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 219         amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
 220
 221         /* Write out the address of the gatt table */
 222         OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
 223                  agp_bridge->gatt_bus_addr);
 224
 225         /* Write the Sync register */
 226         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
 227
 228         /* Set indexing mode */
 229         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
 230
 231         /* Write the enable register */
 232         enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
 233         enable_reg = (enable_reg | 0x0004);
 234         OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
 235
 236         /* Write out the size register */
 237         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 238         temp = (((temp & ~(0x0000000e)) | current_size->size_value)
 239                 | 0x00000001);
 240         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 241
 242         /* Flush the tlb */
 243         OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
 244
 245         return 0;
 246 }
 247
 248 static void amd_irongate_cleanup(void)
 249 {
 250         struct aper_size_info_lvl2 *previous_size;
 251         u32 temp;
 252         u16 enable_reg;
 253
 254         previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
 255
 256         enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
 257         enable_reg = (enable_reg & ~(0x0004));
 258         OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
 259
 260         /* Write back the previous size and disable gart translation */
 261         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 262         temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
 263         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 264         iounmap((void *) amd_irongate_private.registers);
 265 }
 266
 267 /*
 268  * This routine could be implemented by taking the addresses
 269  * written to the GATT, and flushing them individually.  However
 270  * currently it just flushes the whole table.  Which is probably
 271  * more efficent, since agp_memory blocks can be a large number of
 272  * entries.
 273  */
 274
 275 static void amd_irongate_tlbflush(struct agp_memory *temp)
 276 {
 277         OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
 278 }
 279
 280 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 281 {
 282         int i, j, num_entries;
 283         unsigned long *cur_gatt;
 284         unsigned long addr;
 285
 286         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 287
 288         if (type != 0 || mem->type != 0)
 289                 return -EINVAL;
 290
 291         if ((pg_start + mem->page_count) > num_entries)
 292                 return -EINVAL;
 293
 294         j = pg_start;
 295         while (j < (pg_start + mem->page_count)) {
 296                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 297                 cur_gatt = GET_GATT(addr);
 298                 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)]))
 299                         return -EBUSY;
 300                 j++;
 301         }
 302
 303         if (mem->is_flushed == FALSE) {
 304                 global_cache_flush();
 305                 mem->is_flushed = TRUE;
 306         }
 307
 308         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 309                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 310                 cur_gatt = GET_GATT(addr);
 311                 cur_gatt[GET_GATT_OFF(addr)] =
 312                         agp_generic_mask_memory(mem->memory[i], mem->type);
 313         }
 314         amd_irongate_tlbflush(mem);
 315         return 0;
 316 }
 317
 318 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 319 {
 320         int i;
 321         unsigned long *cur_gatt;
 322         unsigned long addr;
 323
 324         if (type != 0 || mem->type != 0)
 325                 return -EINVAL;
 326
 327         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 328                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 329                 cur_gatt = GET_GATT(addr);
 330                 cur_gatt[GET_GATT_OFF(addr)] =
 331                         (unsigned long) agp_bridge->scratch_page;
 332         }
 333
 334         amd_irongate_tlbflush(mem);
 335         return 0;
 336 }
 337
 338 static struct aper_size_info_lvl2 amd_irongate_sizes[7] =
 339 {
 340         {2048, 524288, 0x0000000c},
 341         {1024, 262144, 0x0000000a},
 342         {512, 131072, 0x00000008},
 343         {256, 65536, 0x00000006},
 344         {128, 32768, 0x00000004},
 345         {64, 16384, 0x00000002},
 346         {32, 8192, 0x00000000}
 347 };
 348
 349 static struct gatt_mask amd_irongate_masks[] =
 350 {
 351         {.mask = 1, .type = 0}
 352 };
 353
 354 struct agp_bridge_driver amd_irongate_driver = {
 355         .owner                  = THIS_MODULE,
 356         .aperture_sizes         = amd_irongate_sizes,
 357         .size_type              = LVL2_APER_SIZE,
 358         .num_aperture_sizes     = 7,
 359         .configure              = amd_irongate_configure,
 360         .fetch_size             = amd_irongate_fetch_size,
 361         .cleanup                = amd_irongate_cleanup,
 362         .tlb_flush              = amd_irongate_tlbflush,
 363         .mask_memory            = agp_generic_mask_memory,
 364         .masks                  = amd_irongate_masks,
 365         .agp_enable             = agp_generic_enable,
 366         .cache_flush            = global_cache_flush,
 367         .create_gatt_table      = amd_create_gatt_table,
 368         .free_gatt_table        = amd_free_gatt_table,
 369         .insert_memory          = amd_insert_memory,
 370         .remove_memory          = amd_remove_memory,
 371         .alloc_by_type          = agp_generic_alloc_by_type,
 372         .free_by_type           = agp_generic_free_by_type,
 373         .agp_alloc_page         = agp_generic_alloc_page,
 374         .agp_destroy_page       = agp_generic_destroy_page,
 375 };
 376
 377 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
 378 {
 379         {
 380                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_7006,
 381                 .chipset_name   = "Irongate",
 382         },
 383         {
 384                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700E,
 385                 .chipset_name   = "761",
 386         },
 387         {
 388                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700C,
 389                 .chipset_name   = "760MP",
 390         },
 391         { }, /* dummy final entry, always present */
 392 };
 393
 394 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
 395                                      const struct pci_device_id *ent)
 396 {
 397         struct agp_device_ids *devs = amd_agp_device_ids;
 398         struct agp_bridge_data *bridge;
 399         u8 cap_ptr;
 400         int j;
 401
 402         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 403         if (!cap_ptr)
 404                 return -ENODEV;
 405
 406         for (j = 0; devs[j].chipset_name; j++) {
 407                 if (pdev->device == devs[j].device_id) {
 408                         printk (KERN_INFO PFX "Detected AMD %s chipset\n",
 409                                         devs[j].chipset_name);
 410                         goto found;
 411                 }
 412         }
 413
 414         printk(KERN_ERR PFX "Unsupported AMD chipset (device id: %04x)\n",
 415                     pdev->device);
 416         return -ENODEV;
 417
 418 found:
 419         bridge = agp_alloc_bridge();
 420         if (!bridge)
 421                 return -ENOMEM;
 422
 423         bridge->driver = &amd_irongate_driver;
 424         bridge->dev_private_data = &amd_irongate_private,
 425         bridge->dev = pdev;
 426         bridge->capndx = cap_ptr;
 427
 428         /* Fill in the mode register */
 429         pci_read_config_dword(pdev,
 430                         bridge->capndx+PCI_AGP_STATUS,
 431                         &bridge->mode);
 432
 433         pci_set_drvdata(pdev, bridge);
 434         return agp_add_bridge(bridge);
 435 }
 436
 437 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
 438 {
 439         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 440
 441         agp_remove_bridge(bridge);
 442         agp_put_bridge(bridge);
 443 }
 444
 445 static struct pci_device_id agp_amdk7_pci_table[] = {
 446         {
 447         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 448         .class_mask     = ~0,
 449         .vendor         = PCI_VENDOR_ID_AMD,
 450         .device         = PCI_ANY_ID,
 451         .subvendor      = PCI_ANY_ID,
 452         .subdevice      = PCI_ANY_ID,
 453         },
 454         { }
 455 };
 456
 457 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
 458
 459 static struct pci_driver agp_amdk7_pci_driver = {
 460         .name           = "agpgart-amdk7",
 461         .id_table       = agp_amdk7_pci_table,
 462         .probe          = agp_amdk7_probe,
 463         .remove         = agp_amdk7_remove,
 464 };
 465
 466 static int __init agp_amdk7_init(void)
 467 {
 468         return pci_module_init(&agp_amdk7_pci_driver);
 469 }
 470
 471 static void __exit agp_amdk7_cleanup(void)
 472 {
 473         pci_unregister_driver(&agp_amdk7_pci_driver);
 474 }
 475
 476 module_init(agp_amdk7_init);
 477 module_exit(agp_amdk7_cleanup);
 478
 479 MODULE_LICENSE("GPL and additional rights");