2 * AMD K7 AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
10 #include <linux/page-flags.h>
14 #define AMD_MMBASE 0x14
15 #define AMD_APSIZE 0xac
16 #define AMD_MODECNTL 0xb0
17 #define AMD_MODECNTL2 0xb2
18 #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
19 #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
20 #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
21 #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
23 static struct pci_device_id agp_amdk7_pci_table[];
27 unsigned long *remapped;
30 static struct _amd_irongate_private {
31 volatile u8 *registers;
32 struct amd_page_map **gatt_pages;
34 } amd_irongate_private;
36 static int amd_create_page_map(struct amd_page_map *page_map)
40 page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
41 if (page_map->real == NULL)
44 SetPageReserved(virt_to_page(page_map->real));
46 page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
48 if (page_map->remapped == NULL) {
49 ClearPageReserved(virt_to_page(page_map->real));
50 free_page((unsigned long) page_map->real);
51 page_map->real = NULL;
56 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
57 page_map->remapped[i] = agp_bridge->scratch_page;
62 static void amd_free_page_map(struct amd_page_map *page_map)
64 iounmap(page_map->remapped);
65 ClearPageReserved(virt_to_page(page_map->real));
66 free_page((unsigned long) page_map->real);
69 static void amd_free_gatt_pages(void)
72 struct amd_page_map **tables;
73 struct amd_page_map *entry;
75 tables = amd_irongate_private.gatt_pages;
76 for (i = 0; i < amd_irongate_private.num_tables; i++) {
79 if (entry->real != NULL)
80 amd_free_page_map(entry);
85 amd_irongate_private.gatt_pages = NULL;
88 static int amd_create_gatt_pages(int nr_tables)
90 struct amd_page_map **tables;
91 struct amd_page_map *entry;
95 tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *),
100 memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1));
101 for (i = 0; i < nr_tables; i++) {
102 entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL);
107 memset (entry, 0, sizeof(struct amd_page_map));
109 retval = amd_create_page_map(entry);
113 amd_irongate_private.num_tables = nr_tables;
114 amd_irongate_private.gatt_pages = tables;
117 amd_free_gatt_pages();
122 /* Since we don't need contigious memory we just try
123 * to get the gatt table once
126 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
127 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
128 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
129 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
130 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
131 GET_PAGE_DIR_IDX(addr)]->remapped)
133 static int amd_create_gatt_table(void)
135 struct aper_size_info_lvl2 *value;
136 struct amd_page_map page_dir;
142 value = A_SIZE_LVL2(agp_bridge->current_size);
143 retval = amd_create_page_map(&page_dir);
147 retval = amd_create_gatt_pages(value->num_entries / 1024);
149 amd_free_page_map(&page_dir);
153 agp_bridge->gatt_table_real = (u32 *)page_dir.real;
154 agp_bridge->gatt_table = (u32 *)page_dir.remapped;
155 agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
157 /* Get the address for the gart region.
158 * This is a bus address even on the alpha, b/c its
159 * used to program the agp master not the cpu
162 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
163 addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
164 agp_bridge->gart_bus_addr = addr;
166 /* Calculate the agp offset */
167 for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
168 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] =
169 virt_to_phys(amd_irongate_private.gatt_pages[i]->real);
170 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] |= 0x00000001;
176 static int amd_free_gatt_table(void)
178 struct amd_page_map page_dir;
180 page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
181 page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
183 amd_free_gatt_pages();
184 amd_free_page_map(&page_dir);
188 static int amd_irongate_fetch_size(void)
192 struct aper_size_info_lvl2 *values;
194 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
195 temp = (temp & 0x0000000e);
196 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
197 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
198 if (temp == values[i].size_value) {
199 agp_bridge->previous_size =
200 agp_bridge->current_size = (void *) (values + i);
202 agp_bridge->aperture_size_idx = i;
203 return values[i].size;
210 static int amd_irongate_configure(void)
212 struct aper_size_info_lvl2 *current_size;
216 current_size = A_SIZE_LVL2(agp_bridge->current_size);
218 /* Get the memory mapped registers */
219 pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
220 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
221 amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
223 /* Write out the address of the gatt table */
224 OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
225 agp_bridge->gatt_bus_addr);
227 /* Write the Sync register */
228 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
230 /* Set indexing mode */
231 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
233 /* Write the enable register */
234 enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
235 enable_reg = (enable_reg | 0x0004);
236 OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
238 /* Write out the size register */
239 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
240 temp = (((temp & ~(0x0000000e)) | current_size->size_value)
242 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
245 OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
250 static void amd_irongate_cleanup(void)
252 struct aper_size_info_lvl2 *previous_size;
256 previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
258 enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
259 enable_reg = (enable_reg & ~(0x0004));
260 OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
262 /* Write back the previous size and disable gart translation */
263 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
264 temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
265 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
266 iounmap((void *) amd_irongate_private.registers);
270 * This routine could be implemented by taking the addresses
271 * written to the GATT, and flushing them individually. However
272 * currently it just flushes the whole table. Which is probably
273 * more efficent, since agp_memory blocks can be a large number of
277 static void amd_irongate_tlbflush(struct agp_memory *temp)
279 OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
282 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
284 int i, j, num_entries;
285 unsigned long *cur_gatt;
288 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
290 if (type != 0 || mem->type != 0)
293 if ((pg_start + mem->page_count) > num_entries)
297 while (j < (pg_start + mem->page_count)) {
298 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
299 cur_gatt = GET_GATT(addr);
300 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)]))
305 if (mem->is_flushed == FALSE) {
306 global_cache_flush();
307 mem->is_flushed = TRUE;
310 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
311 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
312 cur_gatt = GET_GATT(addr);
313 cur_gatt[GET_GATT_OFF(addr)] =
314 agp_generic_mask_memory(mem->memory[i], mem->type);
316 amd_irongate_tlbflush(mem);
320 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
323 unsigned long *cur_gatt;
326 if (type != 0 || mem->type != 0)
329 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
330 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
331 cur_gatt = GET_GATT(addr);
332 cur_gatt[GET_GATT_OFF(addr)] =
333 (unsigned long) agp_bridge->scratch_page;
336 amd_irongate_tlbflush(mem);
340 static struct aper_size_info_lvl2 amd_irongate_sizes[7] =
342 {2048, 524288, 0x0000000c},
343 {1024, 262144, 0x0000000a},
344 {512, 131072, 0x00000008},
345 {256, 65536, 0x00000006},
346 {128, 32768, 0x00000004},
347 {64, 16384, 0x00000002},
348 {32, 8192, 0x00000000}
351 static struct gatt_mask amd_irongate_masks[] =
353 {.mask = 1, .type = 0}
356 struct agp_bridge_driver amd_irongate_driver = {
357 .owner = THIS_MODULE,
358 .aperture_sizes = amd_irongate_sizes,
359 .size_type = LVL2_APER_SIZE,
360 .num_aperture_sizes = 7,
361 .configure = amd_irongate_configure,
362 .fetch_size = amd_irongate_fetch_size,
363 .cleanup = amd_irongate_cleanup,
364 .tlb_flush = amd_irongate_tlbflush,
365 .mask_memory = agp_generic_mask_memory,
366 .masks = amd_irongate_masks,
367 .agp_enable = agp_generic_enable,
368 .cache_flush = global_cache_flush,
369 .create_gatt_table = amd_create_gatt_table,
370 .free_gatt_table = amd_free_gatt_table,
371 .insert_memory = amd_insert_memory,
372 .remove_memory = amd_remove_memory,
373 .alloc_by_type = agp_generic_alloc_by_type,
374 .free_by_type = agp_generic_free_by_type,
375 .agp_alloc_page = agp_generic_alloc_page,
376 .agp_destroy_page = agp_generic_destroy_page,
379 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
382 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
383 .chipset_name = "Irongate",
386 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
387 .chipset_name = "761",
390 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
391 .chipset_name = "760MP",
393 { }, /* dummy final entry, always present */
396 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
397 const struct pci_device_id *ent)
399 struct agp_bridge_data *bridge;
403 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
407 j = ent - agp_amdk7_pci_table;
408 printk(KERN_INFO PFX "Detected AMD %s chipset\n",
409 amd_agp_device_ids[j].chipset_name);
411 bridge = agp_alloc_bridge();
415 bridge->driver = &amd_irongate_driver;
416 bridge->dev_private_data = &amd_irongate_private,
418 bridge->capndx = cap_ptr;
420 /* Fill in the mode register */
421 pci_read_config_dword(pdev,
422 bridge->capndx+PCI_AGP_STATUS,
425 pci_set_drvdata(pdev, bridge);
426 return agp_add_bridge(bridge);
429 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
431 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
433 agp_remove_bridge(bridge);
434 agp_put_bridge(bridge);
437 /* must be the same order as name table above */
438 static struct pci_device_id agp_amdk7_pci_table[] = {
440 .class = (PCI_CLASS_BRIDGE_HOST << 8),
442 .vendor = PCI_VENDOR_ID_AMD,
443 .device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
444 .subvendor = PCI_ANY_ID,
445 .subdevice = PCI_ANY_ID,
448 .class = (PCI_CLASS_BRIDGE_HOST << 8),
450 .vendor = PCI_VENDOR_ID_AMD,
451 .device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
452 .subvendor = PCI_ANY_ID,
453 .subdevice = PCI_ANY_ID,
456 .class = (PCI_CLASS_BRIDGE_HOST << 8),
458 .vendor = PCI_VENDOR_ID_AMD,
459 .device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
460 .subvendor = PCI_ANY_ID,
461 .subdevice = PCI_ANY_ID,
466 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
468 static struct pci_driver agp_amdk7_pci_driver = {
469 .name = "agpgart-amdk7",
470 .id_table = agp_amdk7_pci_table,
471 .probe = agp_amdk7_probe,
472 .remove = agp_amdk7_remove,
475 static int __init agp_amdk7_init(void)
477 return pci_module_init(&agp_amdk7_pci_driver);
480 static void __exit agp_amdk7_cleanup(void)
482 pci_unregister_driver(&agp_amdk7_pci_driver);
485 module_init(agp_amdk7_init);
486 module_exit(agp_amdk7_cleanup);
488 MODULE_LICENSE("GPL and additional rights");