drivers/char/agp/i460-agp.c

   1 /*
   2  * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
   3  * the "Intel 460GTX Chipset Software Developer's Manual":
   4  * http://developer.intel.com/design/itanium/downloads/24870401s.htm
   5  */
   6 /*
   7  * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
   8  * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
   9  */
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/agp_backend.h>
  14
  15 #include "agp.h"
  16
  17 #define INTEL_I460_BAPBASE              0x98
  18 #define INTEL_I460_GXBCTL               0xa0
  19 #define INTEL_I460_AGPSIZ               0xa2
  20 #define INTEL_I460_ATTBASE              0xfe200000
  21 #define INTEL_I460_GATT_VALID           (1UL << 24)
  22 #define INTEL_I460_GATT_COHERENT        (1UL << 25)
  23
  24 /*
  25  * The i460 can operate with large (4MB) pages, but there is no sane way to support this
  26  * within the current kernel/DRM environment, so we disable the relevant code for now.
  27  * See also comments in ia64_alloc_page()...
  28  */
  29 #define I460_LARGE_IO_PAGES             0
  30
  31 #if I460_LARGE_IO_PAGES
  32 # define I460_IO_PAGE_SHIFT             i460.io_page_shift
  33 #else
  34 # define I460_IO_PAGE_SHIFT             12
  35 #endif
  36
  37 #define I460_IOPAGES_PER_KPAGE          (PAGE_SIZE >> I460_IO_PAGE_SHIFT)
  38 #define I460_KPAGES_PER_IOPAGE          (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
  39 #define I460_SRAM_IO_DISABLE            (1 << 4)
  40 #define I460_BAPBASE_ENABLE             (1 << 3)
  41 #define I460_AGPSIZ_MASK                0x7
  42 #define I460_4M_PS                      (1 << 1)
  43
  44 /* Control bits for Out-Of-GART coherency and Burst Write Combining */
  45 #define I460_GXBCTL_OOG         (1UL << 0)
  46 #define I460_GXBCTL_BWC         (1UL << 2)
  47
  48 /*
  49  * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
  50  * gatt_table and gatt_table_real pointers a "void *"...
  51  */
  52 #define RD_GATT(index)          readl((u32 *) i460.gatt + (index))
  53 #define WR_GATT(index, val)     writel((val), (u32 *) i460.gatt + (index))
  54 /*
  55  * The 460 spec says we have to read the last location written to make sure that all
  56  * writes have taken effect
  57  */
  58 #define WR_FLUSH_GATT(index)    RD_GATT(index)
  59
  60 #define log2(x)                 ffz(~(x))
  61
  62 static struct {
  63         void *gatt;                             /* ioremap'd GATT area */
  64
  65         /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
  66         u8 io_page_shift;
  67
  68         /* BIOS configures chipset to one of 2 possible apbase values: */
  69         u8 dynamic_apbase;
  70
  71         /* structure for tracking partial use of 4MB GART pages: */
  72         struct lp_desc {
  73                 unsigned long *alloced_map;     /* bitmap of kernel-pages in use */
  74                 int refcount;                   /* number of kernel pages using the large page */
  75                 u64 paddr;                      /* physical address of large page */
  76         } *lp_desc;
  77 } i460;
  78
  79 static struct aper_size_info_8 i460_sizes[3] =
  80 {
  81         /*
  82          * The 32GB aperture is only available with a 4M GART page size.  Due to the
  83          * dynamic GART page size, we can't figure out page_order or num_entries until
  84          * runtime.
  85          */
  86         {32768, 0, 0, 4},
  87         {1024, 0, 0, 2},
  88         {256, 0, 0, 1}
  89 };
  90
  91 static struct gatt_mask i460_masks[] =
  92 {
  93         {
  94           .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT,
  95           .type = 0
  96         }
  97 };
  98
  99 static int i460_fetch_size (void)
 100 {
 101         int i;
 102         u8 temp;
 103         struct aper_size_info_8 *values;
 104
 105         /* Determine the GART page size */
 106         pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
 107         i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
 108         pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
 109
 110         if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
 111                 printk(KERN_ERR PFX
 112                        "I/O (GART) page-size %ZuKB doesn't match expected size %ZuKB\n",
 113                        1UL << (i460.io_page_shift - 10), 1UL << (I460_IO_PAGE_SHIFT));
 114                 return 0;
 115         }
 116
 117         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 118
 119         pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
 120
 121         /* Exit now if the IO drivers for the GART SRAMS are turned off */
 122         if (temp & I460_SRAM_IO_DISABLE) {
 123                 printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
 124                 printk(KERN_ERR PFX "AGPGART operation not possible\n");
 125                 return 0;
 126         }
 127
 128         /* Make sure we don't try to create an 2 ^ 23 entry GATT */
 129         if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
 130                 printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
 131                 return 0;
 132         }
 133
 134         /* Determine the proper APBASE register */
 135         if (temp & I460_BAPBASE_ENABLE)
 136                 i460.dynamic_apbase = INTEL_I460_BAPBASE;
 137         else
 138                 i460.dynamic_apbase = AGP_APBASE;
 139
 140         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 141                 /*
 142                  * Dynamically calculate the proper num_entries and page_order values for
 143                  * the define aperture sizes. Take care not to shift off the end of
 144                  * values[i].size.
 145                  */
 146                 values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
 147                 values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
 148         }
 149
 150         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 151                 /* Neglect control bits when matching up size_value */
 152                 if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
 153                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
 154                         agp_bridge->aperture_size_idx = i;
 155                         return values[i].size;
 156                 }
 157         }
 158
 159         return 0;
 160 }
 161
 162 /* There isn't anything to do here since 460 has no GART TLB. */
 163 static void i460_tlb_flush (struct agp_memory *mem)
 164 {
 165         return;
 166 }
 167
 168 /*
 169  * This utility function is needed to prevent corruption of the control bits
 170  * which are stored along with the aperture size in 460's AGPSIZ register
 171  */
 172 static void i460_write_agpsiz (u8 size_value)
 173 {
 174         u8 temp;
 175
 176         pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
 177         pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
 178                               ((temp & ~I460_AGPSIZ_MASK) | size_value));
 179 }
 180
 181 static void i460_cleanup (void)
 182 {
 183         struct aper_size_info_8 *previous_size;
 184
 185         previous_size = A_SIZE_8(agp_bridge->previous_size);
 186         i460_write_agpsiz(previous_size->size_value);
 187
 188         if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
 189                 kfree(i460.lp_desc);
 190 }
 191
 192 static int i460_configure (void)
 193 {
 194         union {
 195                 u32 small[2];
 196                 u64 large;
 197         } temp;
 198         size_t size;
 199         u8 scratch;
 200         struct aper_size_info_8 *current_size;
 201
 202         temp.large = 0;
 203
 204         current_size = A_SIZE_8(agp_bridge->current_size);
 205         i460_write_agpsiz(current_size->size_value);
 206
 207         /*
 208          * Do the necessary rigmarole to read all eight bytes of APBASE.
 209          * This has to be done since the AGP aperture can be above 4GB on
 210          * 460 based systems.
 211          */
 212         pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
 213         pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
 214
 215         /* Clear BAR control bits */
 216         agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
 217
 218         pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
 219         pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
 220                               (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
 221
 222         /*
 223          * Initialize partial allocation trackers if a GART page is bigger than a kernel
 224          * page.
 225          */
 226         if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
 227                 size = current_size->num_entries * sizeof(i460.lp_desc[0]);
 228                 i460.lp_desc = kmalloc(size, GFP_KERNEL);
 229                 if (!i460.lp_desc)
 230                         return -ENOMEM;
 231                 memset(i460.lp_desc, 0, size);
 232         }
 233         return 0;
 234 }
 235
 236 static int i460_create_gatt_table (void)
 237 {
 238         int page_order, num_entries, i;
 239         void *temp;
 240
 241         /*
 242          * Load up the fixed address of the GART SRAMS which hold our GATT table.
 243          */
 244         temp = agp_bridge->current_size;
 245         page_order = A_SIZE_8(temp)->page_order;
 246         num_entries = A_SIZE_8(temp)->num_entries;
 247
 248         i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
 249
 250         /* These are no good, the should be removed from the agp_bridge strucure... */
 251         agp_bridge->gatt_table_real = NULL;
 252         agp_bridge->gatt_table = NULL;
 253         agp_bridge->gatt_bus_addr = 0;
 254
 255         for (i = 0; i < num_entries; ++i)
 256                 WR_GATT(i, 0);
 257         WR_FLUSH_GATT(i - 1);
 258         return 0;
 259 }
 260
 261 static int i460_free_gatt_table (void)
 262 {
 263         int num_entries, i;
 264         void *temp;
 265
 266         temp = agp_bridge->current_size;
 267
 268         num_entries = A_SIZE_8(temp)->num_entries;
 269
 270         for (i = 0; i < num_entries; ++i)
 271                 WR_GATT(i, 0);
 272         WR_FLUSH_GATT(num_entries - 1);
 273
 274         iounmap(i460.gatt);
 275         return 0;
 276 }
 277
 278 /*
 279  * The following functions are called when the I/O (GART) page size is smaller than
 280  * PAGE_SIZE.
 281  */
 282
 283 static int i460_insert_memory_small_io_page (struct agp_memory *mem,
 284                                 off_t pg_start, int type)
 285 {
 286         unsigned long paddr, io_pg_start, io_page_size;
 287         int i, j, k, num_entries;
 288         void *temp;
 289
 290         pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
 291                  mem, pg_start, type, mem->memory[0]);
 292
 293         io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
 294
 295         temp = agp_bridge->current_size;
 296         num_entries = A_SIZE_8(temp)->num_entries;
 297
 298         if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
 299                 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
 300                 return -EINVAL;
 301         }
 302
 303         j = io_pg_start;
 304         while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
 305                 if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
 306                         pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
 307                                  j, RD_GATT(j));
 308                         return -EBUSY;
 309                 }
 310                 j++;
 311         }
 312
 313         io_page_size = 1UL << I460_IO_PAGE_SHIFT;
 314         for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
 315                 paddr = mem->memory[i];
 316                 for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
 317                         WR_GATT(j, agp_bridge->driver->mask_memory(paddr, mem->type));
 318         }
 319         WR_FLUSH_GATT(j - 1);
 320         return 0;
 321 }
 322
 323 static int i460_remove_memory_small_io_page(struct agp_memory *mem,
 324                                 off_t pg_start, int type)
 325 {
 326         int i;
 327
 328         pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
 329                  mem, pg_start, type);
 330
 331         pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
 332
 333         for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
 334                 WR_GATT(i, 0);
 335         WR_FLUSH_GATT(i - 1);
 336         return 0;
 337 }
 338
 339 #if I460_LARGE_IO_PAGES
 340
 341 /*
 342  * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
 343  *
 344  * This situation is interesting since AGP memory allocations that are smaller than a
 345  * single GART page are possible.  The i460.lp_desc array tracks partial allocation of the
 346  * large GART pages to work around this issue.
 347  *
 348  * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
 349  * pg_num.  i460.lp_desc[pg_num].paddr is the physical address of the large page and
 350  * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
 351  */
 352
 353 static int i460_alloc_large_page (struct lp_desc *lp)
 354 {
 355         unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
 356         size_t map_size;
 357         void *lpage;
 358
 359         lpage = (void *) __get_free_pages(GFP_KERNEL, order);
 360         if (!lpage) {
 361                 printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
 362                 return -ENOMEM;
 363         }
 364
 365         map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
 366         lp->alloced_map = kmalloc(map_size, GFP_KERNEL);
 367         if (!lp->alloced_map) {
 368                 free_pages((unsigned long) lpage, order);
 369                 printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
 370                 return -ENOMEM;
 371         }
 372         memset(lp->alloced_map, 0, map_size);
 373
 374         lp->paddr = virt_to_phys(lpage);
 375         lp->refcount = 0;
 376         atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
 377         return 0;
 378 }
 379
 380 static void i460_free_large_page (struct lp_desc *lp)
 381 {
 382         kfree(lp->alloced_map);
 383         lp->alloced_map = NULL;
 384
 385         free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
 386         atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
 387 }
 388
 389 static int i460_insert_memory_large_io_page (struct agp_memory *mem,
 390                                 off_t pg_start, int type)
 391 {
 392         int i, start_offset, end_offset, idx, pg, num_entries;
 393         struct lp_desc *start, *end, *lp;
 394         void *temp;
 395
 396         temp = agp_bridge->current_size;
 397         num_entries = A_SIZE_8(temp)->num_entries;
 398
 399         /* Figure out what pg_start means in terms of our large GART pages */
 400         start           = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
 401         end             = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
 402         start_offset    = pg_start % I460_KPAGES_PER_IOPAGE;
 403         end_offset      = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 404
 405         if (end > i460.lp_desc + num_entries) {
 406                 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
 407                 return -EINVAL;
 408         }
 409
 410         /* Check if the requested region of the aperture is free */
 411         for (lp = start; lp <= end; ++lp) {
 412                 if (!lp->alloced_map)
 413                         continue;       /* OK, the entire large page is available... */
 414
 415                 for (idx = ((lp == start) ? start_offset : 0);
 416                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 417                      idx++)
 418                 {
 419                         if (test_bit(idx, lp->alloced_map))
 420                                 return -EBUSY;
 421                 }
 422         }
 423
 424         for (lp = start, i = 0; lp <= end; ++lp) {
 425                 if (!lp->alloced_map) {
 426                         /* Allocate new GART pages... */
 427                         if (i460_alloc_large_page(lp) < 0)
 428                                 return -ENOMEM;
 429                         pg = lp - i460.lp_desc;
 430                         WR_GATT(pg, agp_bridge->driver->mask_memory(lp->paddr, 0));
 431                         WR_FLUSH_GATT(pg);
 432                 }
 433
 434                 for (idx = ((lp == start) ? start_offset : 0);
 435                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 436                      idx++, i++)
 437                 {
 438                         mem->memory[i] = lp->paddr + idx*PAGE_SIZE;
 439                         __set_bit(idx, lp->alloced_map);
 440                         ++lp->refcount;
 441                 }
 442         }
 443         return 0;
 444 }
 445
 446 static int i460_remove_memory_large_io_page (struct agp_memory *mem,
 447                                 off_t pg_start, int type)
 448 {
 449         int i, pg, start_offset, end_offset, idx, num_entries;
 450         struct lp_desc *start, *end, *lp;
 451         void *temp;
 452
 453         temp = agp_bridge->driver->current_size;
 454         num_entries = A_SIZE_8(temp)->num_entries;
 455
 456         /* Figure out what pg_start means in terms of our large GART pages */
 457         start           = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
 458         end             = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
 459         start_offset    = pg_start % I460_KPAGES_PER_IOPAGE;
 460         end_offset      = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 461
 462         for (i = 0, lp = start; lp <= end; ++lp) {
 463                 for (idx = ((lp == start) ? start_offset : 0);
 464                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 465                      idx++, i++)
 466                 {
 467                         mem->memory[i] = 0;
 468                         __clear_bit(idx, lp->alloced_map);
 469                         --lp->refcount;
 470                 }
 471
 472                 /* Free GART pages if they are unused */
 473                 if (lp->refcount == 0) {
 474                         pg = lp - i460.lp_desc;
 475                         WR_GATT(pg, 0);
 476                         WR_FLUSH_GATT(pg);
 477                         i460_free_large_page(lp);
 478                 }
 479         }
 480         return 0;
 481 }
 482
 483 /* Wrapper routines to call the approriate {small_io_page,large_io_page} function */
 484
 485 static int i460_insert_memory (struct agp_memory *mem,
 486                                 off_t pg_start, int type)
 487 {
 488         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 489                 return i460_insert_memory_small_io_page(mem, pg_start, type);
 490         else
 491                 return i460_insert_memory_large_io_page(mem, pg_start, type);
 492 }
 493
 494 static int i460_remove_memory (struct agp_memory *mem,
 495                                 off_t pg_start, int type)
 496 {
 497         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 498                 return i460_remove_memory_small_io_page(mem, pg_start, type);
 499         else
 500                 return i460_remove_memory_large_io_page(mem, pg_start, type);
 501 }
 502
 503 /*
 504  * If the I/O (GART) page size is bigger than the kernel page size, we don't want to
 505  * allocate memory until we know where it is to be bound in the aperture (a
 506  * multi-kernel-page alloc might fit inside of an already allocated GART page).
 507  *
 508  * Let's just hope nobody counts on the allocated AGP memory being there before bind time
 509  * (I don't think current drivers do)...
 510  */
 511 static void *i460_alloc_page (void)
 512 {
 513         void *page;
 514
 515         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 516                 page = agp_generic_alloc_page();
 517         else
 518                 /* Returning NULL would cause problems */
 519                 /* AK: really dubious code. */
 520                 page = (void *)~0UL;
 521         return page;
 522 }
 523
 524 static void i460_destroy_page (void *page)
 525 {
 526         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 527                 agp_generic_destroy_page(page);
 528 }
 529
 530 #endif /* I460_LARGE_IO_PAGES */
 531
 532 static unsigned long i460_mask_memory (unsigned long addr, int type)
 533 {
 534         /* Make sure the returned address is a valid GATT entry */
 535         return (agp_bridge->driver->masks[0].mask
 536                 | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
 537 }
 538
 539 struct agp_bridge_driver intel_i460_driver = {
 540         .owner                  = THIS_MODULE,
 541         .aperture_sizes         = i460_sizes,
 542         .size_type              = U8_APER_SIZE,
 543         .num_aperture_sizes     = 3,
 544         .configure              = i460_configure,
 545         .fetch_size             = i460_fetch_size,
 546         .cleanup                = i460_cleanup,
 547         .tlb_flush              = i460_tlb_flush,
 548         .mask_memory            = i460_mask_memory,
 549         .masks                  = i460_masks,
 550         .agp_enable             = agp_generic_enable,
 551         .cache_flush            = global_cache_flush,
 552         .create_gatt_table      = i460_create_gatt_table,
 553         .free_gatt_table        = i460_free_gatt_table,
 554 #if I460_LARGE_IO_PAGES
 555         .insert_memory          = i460_insert_memory,
 556         .remove_memory          = i460_remove_memory,
 557         .agp_alloc_page         = i460_alloc_page,
 558         .agp_destroy_page       = i460_destroy_page,
 559 #else
 560         .insert_memory          = i460_insert_memory_small_io_page,
 561         .remove_memory          = i460_remove_memory_small_io_page,
 562         .agp_alloc_page         = agp_generic_alloc_page,
 563         .agp_destroy_page       = agp_generic_destroy_page,
 564 #endif
 565         .alloc_by_type          = agp_generic_alloc_by_type,
 566         .free_by_type           = agp_generic_free_by_type,
 567         .cant_use_aperture      = 1,
 568 };
 569
 570 static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
 571                                           const struct pci_device_id *ent)
 572 {
 573         struct agp_bridge_data *bridge;
 574         u8 cap_ptr;
 575
 576         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 577         if (!cap_ptr)
 578                 return -ENODEV;
 579
 580         bridge = agp_alloc_bridge();
 581         if (!bridge)
 582                 return -ENOMEM;
 583
 584         bridge->driver = &intel_i460_driver;
 585         bridge->dev = pdev;
 586         bridge->capndx = cap_ptr;
 587
 588         pci_set_drvdata(pdev, bridge);
 589         return agp_add_bridge(bridge);
 590 }
 591
 592 static void __devexit agp_intel_i460_remove(struct pci_dev *pdev)
 593 {
 594         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 595
 596         agp_remove_bridge(bridge);
 597         agp_put_bridge(bridge);
 598 }
 599
 600 static struct pci_device_id agp_intel_i460_pci_table[] = {
 601         {
 602         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 603         .class_mask     = ~0,
 604         .vendor         = PCI_VENDOR_ID_INTEL,
 605         .device         = PCI_DEVICE_ID_INTEL_84460GX,
 606         .subvendor      = PCI_ANY_ID,
 607         .subdevice      = PCI_ANY_ID,
 608         },
 609         { }
 610 };
 611
 612 MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
 613
 614 static struct pci_driver agp_intel_i460_pci_driver = {
 615         .name           = "agpgart-intel-i460",
 616         .id_table       = agp_intel_i460_pci_table,
 617         .probe          = agp_intel_i460_probe,
 618         .remove         = __devexit_p(agp_intel_i460_remove),
 619 };
 620
 621 static int __init agp_intel_i460_init(void)
 622 {
 623         return pci_module_init(&agp_intel_i460_pci_driver);
 624 }
 625
 626 static void __exit agp_intel_i460_cleanup(void)
 627 {
 628         pci_unregister_driver(&agp_intel_i460_pci_driver);
 629 }
 630
 631 module_init(agp_intel_i460_init);
 632 module_exit(agp_intel_i460_cleanup);
 633
 634 MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
 635 MODULE_LICENSE("GPL and additional rights");