drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/pagemap.h>
   9 #include <linux/agp_backend.h>
  10 #include "agp.h"
  11
  12 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  13 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  14 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  15 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  16 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  17 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  18 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  19 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  20
  21 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  22                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  23                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  24                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB)
  25
  26
  27 /* Intel 815 register */
  28 #define INTEL_815_APCONT        0x51
  29 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  30
  31 /* Intel i820 registers */
  32 #define INTEL_I820_RDCR         0x51
  33 #define INTEL_I820_ERRSTS       0xc8
  34
  35 /* Intel i840 registers */
  36 #define INTEL_I840_MCHCFG       0x50
  37 #define INTEL_I840_ERRSTS       0xc8
  38
  39 /* Intel i850 registers */
  40 #define INTEL_I850_MCHCFG       0x50
  41 #define INTEL_I850_ERRSTS       0xc8
  42
  43 /* intel 915G registers */
  44 #define I915_GMADDR     0x18
  45 #define I915_MMADDR     0x10
  46 #define I915_PTEADDR    0x1C
  47 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  48 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  49
  50 /* Intel 965G registers */
  51 #define I965_MSAC 0x62
  52
  53 /* Intel 7505 registers */
  54 #define INTEL_I7505_APSIZE      0x74
  55 #define INTEL_I7505_NCAPID      0x60
  56 #define INTEL_I7505_NISTAT      0x6c
  57 #define INTEL_I7505_ATTBASE     0x78
  58 #define INTEL_I7505_ERRSTS      0x42
  59 #define INTEL_I7505_AGPCTRL     0x70
  60 #define INTEL_I7505_MCHCFG      0x50
  61
  62 static struct aper_size_info_fixed intel_i810_sizes[] =
  63 {
  64         {64, 16384, 4},
  65         /* The 32M mode still requires a 64k gatt */
  66         {32, 8192, 4}
  67 };
  68
  69 #define AGP_DCACHE_MEMORY       1
  70 #define AGP_PHYS_MEMORY         2
  71
  72 static struct gatt_mask intel_i810_masks[] =
  73 {
  74         {.mask = I810_PTE_VALID, .type = 0},
  75         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  76         {.mask = I810_PTE_VALID, .type = 0}
  77 };
  78
  79 static struct _intel_i810_private {
  80         struct pci_dev *i810_dev;       /* device one */
  81         volatile u8 __iomem *registers;
  82         int num_dcache_entries;
  83 } intel_i810_private;
  84
  85 static int intel_i810_fetch_size(void)
  86 {
  87         u32 smram_miscc;
  88         struct aper_size_info_fixed *values;
  89
  90         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
  91         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
  92
  93         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
  94                 printk(KERN_WARNING PFX "i810 is disabled\n");
  95                 return 0;
  96         }
  97         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
  98                 agp_bridge->previous_size =
  99                         agp_bridge->current_size = (void *) (values + 1);
 100                 agp_bridge->aperture_size_idx = 1;
 101                 return values[1].size;
 102         } else {
 103                 agp_bridge->previous_size =
 104                         agp_bridge->current_size = (void *) (values);
 105                 agp_bridge->aperture_size_idx = 0;
 106                 return values[0].size;
 107         }
 108
 109         return 0;
 110 }
 111
 112 static int intel_i810_configure(void)
 113 {
 114         struct aper_size_info_fixed *current_size;
 115         u32 temp;
 116         int i;
 117
 118         current_size = A_SIZE_FIX(agp_bridge->current_size);
 119
 120         if (!intel_i810_private.registers) {
 121                 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
 122                 temp &= 0xfff80000;
 123
 124                 intel_i810_private.registers = ioremap(temp, 128 * 4096);
 125                 if (!intel_i810_private.registers) {
 126                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 127                         return -ENOMEM;
 128                 }
 129         }
 130
 131         if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
 132                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 133                 /* This will need to be dynamically assigned */
 134                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 135                 intel_i810_private.num_dcache_entries = 1024;
 136         }
 137         pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
 138         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 139         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
 140         readl(intel_i810_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 141
 142         if (agp_bridge->driver->needs_scratch_page) {
 143                 for (i = 0; i < current_size->num_entries; i++) {
 144                         writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 145                         readl(intel_i810_private.registers+I810_PTE_BASE+(i*4));        /* PCI posting. */
 146                 }
 147         }
 148         global_cache_flush();
 149         return 0;
 150 }
 151
 152 static void intel_i810_cleanup(void)
 153 {
 154         writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
 155         readl(intel_i810_private.registers);    /* PCI Posting. */
 156         iounmap(intel_i810_private.registers);
 157 }
 158
 159 static void intel_i810_tlbflush(struct agp_memory *mem)
 160 {
 161         return;
 162 }
 163
 164 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 165 {
 166         return;
 167 }
 168
 169 /* Exists to support ARGB cursors */
 170 static void *i8xx_alloc_pages(void)
 171 {
 172         struct page * page;
 173
 174         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 175         if (page == NULL)
 176                 return NULL;
 177
 178         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
 179                 global_flush_tlb();
 180                 __free_page(page);
 181                 return NULL;
 182         }
 183         global_flush_tlb();
 184         get_page(page);
 185         SetPageLocked(page);
 186         atomic_inc(&agp_bridge->current_memory_agp);
 187         return page_address(page);
 188 }
 189
 190 static void i8xx_destroy_pages(void *addr)
 191 {
 192         struct page *page;
 193
 194         if (addr == NULL)
 195                 return;
 196
 197         page = virt_to_page(addr);
 198         change_page_attr(page, 4, PAGE_KERNEL);
 199         global_flush_tlb();
 200         put_page(page);
 201         unlock_page(page);
 202         free_pages((unsigned long)addr, 2);
 203         atomic_dec(&agp_bridge->current_memory_agp);
 204 }
 205
 206 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 207                                 int type)
 208 {
 209         int i, j, num_entries;
 210         void *temp;
 211
 212         if (mem->page_count == 0)
 213                 return 0;
 214
 215         temp = agp_bridge->current_size;
 216         num_entries = A_SIZE_FIX(temp)->num_entries;
 217
 218         if ((pg_start + mem->page_count) > num_entries)
 219                 return -EINVAL;
 220
 221         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 222                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
 223                         return -EBUSY;
 224         }
 225
 226         if (type != 0 || mem->type != 0) {
 227                 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) {
 228                         /* special insert */
 229                         if (!mem->is_flushed) {
 230                                 global_cache_flush();
 231                                 mem->is_flushed = TRUE;
 232                         }
 233
 234                         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 235                                 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 236                         }
 237                         readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));    /* PCI Posting. */
 238
 239                         agp_bridge->driver->tlb_flush(mem);
 240                         return 0;
 241                 }
 242                 if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
 243                         goto insert;
 244                 return -EINVAL;
 245         }
 246
 247 insert:
 248         if (!mem->is_flushed) {
 249                 global_cache_flush();
 250                 mem->is_flushed = TRUE;
 251         }
 252
 253         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 254                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 255                         mem->memory[i], mem->type),
 256                         intel_i810_private.registers+I810_PTE_BASE+(j*4));
 257         }
 258         readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4));    /* PCI Posting. */
 259
 260         agp_bridge->driver->tlb_flush(mem);
 261         return 0;
 262 }
 263
 264 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 265                                 int type)
 266 {
 267         int i;
 268
 269         if (mem->page_count == 0)
 270                 return 0;
 271
 272         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 273                 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 274         }
 275         readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));
 276
 277         agp_bridge->driver->tlb_flush(mem);
 278         return 0;
 279 }
 280
 281 /*
 282  * The i810/i830 requires a physical address to program its mouse
 283  * pointer into hardware.
 284  * However the Xserver still writes to it through the agp aperture.
 285  */
 286 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 287 {
 288         struct agp_memory *new;
 289         void *addr;
 290
 291         if (pg_count != 1 && pg_count != 4)
 292                 return NULL;
 293
 294         switch (pg_count) {
 295         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 296                 global_flush_tlb();
 297                 break;
 298         case 4:
 299                 /* kludge to get 4 physical pages for ARGB cursor */
 300                 addr = i8xx_alloc_pages();
 301                 break;
 302         default:
 303                 return NULL;
 304         }
 305
 306         if (addr == NULL)
 307                 return NULL;
 308
 309         new = agp_create_memory(pg_count);
 310         if (new == NULL)
 311                 return NULL;
 312
 313         new->memory[0] = virt_to_gart(addr);
 314         if (pg_count == 4) {
 315                 /* kludge to get 4 physical pages for ARGB cursor */
 316                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 317                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 318                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 319         }
 320         new->page_count = pg_count;
 321         new->num_scratch_pages = pg_count;
 322         new->type = AGP_PHYS_MEMORY;
 323         new->physical = new->memory[0];
 324         return new;
 325 }
 326
 327 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 328 {
 329         struct agp_memory *new;
 330
 331         if (type == AGP_DCACHE_MEMORY) {
 332                 if (pg_count != intel_i810_private.num_dcache_entries)
 333                         return NULL;
 334
 335                 new = agp_create_memory(1);
 336                 if (new == NULL)
 337                         return NULL;
 338
 339                 new->type = AGP_DCACHE_MEMORY;
 340                 new->page_count = pg_count;
 341                 new->num_scratch_pages = 0;
 342                 vfree(new->memory);
 343                 return new;
 344         }
 345         if (type == AGP_PHYS_MEMORY)
 346                 return alloc_agpphysmem_i8xx(pg_count, type);
 347
 348         return NULL;
 349 }
 350
 351 static void intel_i810_free_by_type(struct agp_memory *curr)
 352 {
 353         agp_free_key(curr->key);
 354         if (curr->type == AGP_PHYS_MEMORY) {
 355                 if (curr->page_count == 4)
 356                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 357                 else {
 358                         agp_bridge->driver->agp_destroy_page(
 359                                  gart_to_virt(curr->memory[0]));
 360                         global_flush_tlb();
 361                 }
 362                 vfree(curr->memory);
 363         }
 364         kfree(curr);
 365 }
 366
 367 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 368         unsigned long addr, int type)
 369 {
 370         /* Type checking must be done elsewhere */
 371         return addr | bridge->driver->masks[type].mask;
 372 }
 373
 374 static struct aper_size_info_fixed intel_i830_sizes[] =
 375 {
 376         {128, 32768, 5},
 377         /* The 64M mode still requires a 128k gatt */
 378         {64, 16384, 5},
 379         {256, 65536, 6},
 380         {512, 131072, 7},
 381 };
 382
 383 static struct _intel_i830_private {
 384         struct pci_dev *i830_dev;               /* device one */
 385         volatile u8 __iomem *registers;
 386         volatile u32 __iomem *gtt;              /* I915G */
 387         /* gtt_entries is the number of gtt entries that are already mapped
 388          * to stolen memory.  Stolen memory is larger than the memory mapped
 389          * through gtt_entries, as it includes some reserved space for the BIOS
 390          * popup and for the GTT.
 391          */
 392         int gtt_entries;
 393 } intel_i830_private;
 394
 395 static void intel_i830_init_gtt_entries(void)
 396 {
 397         u16 gmch_ctrl;
 398         int gtt_entries;
 399         u8 rdct;
 400         int local = 0;
 401         static const int ddt[4] = { 0, 16, 32, 64 };
 402         int size; /* reserved space (in kb) at the top of stolen memory */
 403
 404         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 405
 406         if (IS_I965) {
 407                 u32 pgetbl_ctl;
 408                 pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL);
 409
 410                 /* The 965 has a field telling us the size of the GTT,
 411                  * which may be larger than what is necessary to map the
 412                  * aperture.
 413                  */
 414                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 415                 case I965_PGETBL_SIZE_128KB:
 416                         size = 128;
 417                         break;
 418                 case I965_PGETBL_SIZE_256KB:
 419                         size = 256;
 420                         break;
 421                 case I965_PGETBL_SIZE_512KB:
 422                         size = 512;
 423                         break;
 424                 default:
 425                         printk(KERN_INFO PFX "Unknown page table size, "
 426                                "assuming 512KB\n");
 427                         size = 512;
 428                 }
 429                 size += 4; /* add in BIOS popup space */
 430         } else {
 431                 /* On previous hardware, the GTT size was just what was
 432                  * required to map the aperture.
 433                  */
 434                 size = agp_bridge->driver->fetch_size() + 4;
 435         }
 436
 437         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 438             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 439                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 440                 case I830_GMCH_GMS_STOLEN_512:
 441                         gtt_entries = KB(512) - KB(size);
 442                         break;
 443                 case I830_GMCH_GMS_STOLEN_1024:
 444                         gtt_entries = MB(1) - KB(size);
 445                         break;
 446                 case I830_GMCH_GMS_STOLEN_8192:
 447                         gtt_entries = MB(8) - KB(size);
 448                         break;
 449                 case I830_GMCH_GMS_LOCAL:
 450                         rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
 451                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 452                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 453                         local = 1;
 454                         break;
 455                 default:
 456                         gtt_entries = 0;
 457                         break;
 458                 }
 459         } else {
 460                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 461                 case I855_GMCH_GMS_STOLEN_1M:
 462                         gtt_entries = MB(1) - KB(size);
 463                         break;
 464                 case I855_GMCH_GMS_STOLEN_4M:
 465                         gtt_entries = MB(4) - KB(size);
 466                         break;
 467                 case I855_GMCH_GMS_STOLEN_8M:
 468                         gtt_entries = MB(8) - KB(size);
 469                         break;
 470                 case I855_GMCH_GMS_STOLEN_16M:
 471                         gtt_entries = MB(16) - KB(size);
 472                         break;
 473                 case I855_GMCH_GMS_STOLEN_32M:
 474                         gtt_entries = MB(32) - KB(size);
 475                         break;
 476                 case I915_GMCH_GMS_STOLEN_48M:
 477                         /* Check it's really I915G */
 478                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 479                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 480                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 481                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
 482                                 gtt_entries = MB(48) - KB(size);
 483                         else
 484                                 gtt_entries = 0;
 485                         break;
 486                 case I915_GMCH_GMS_STOLEN_64M:
 487                         /* Check it's really I915G */
 488                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 489                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 490                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 491                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
 492                                 gtt_entries = MB(64) - KB(size);
 493                         else
 494                                 gtt_entries = 0;
 495                 default:
 496                         gtt_entries = 0;
 497                         break;
 498                 }
 499         }
 500         if (gtt_entries > 0)
 501                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 502                        gtt_entries / KB(1), local ? "local" : "stolen");
 503         else
 504                 printk(KERN_INFO PFX
 505                        "No pre-allocated video memory detected.\n");
 506         gtt_entries /= KB(4);
 507
 508         intel_i830_private.gtt_entries = gtt_entries;
 509 }
 510
 511 /* The intel i830 automatically initializes the agp aperture during POST.
 512  * Use the memory already set aside for in the GTT.
 513  */
 514 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 515 {
 516         int page_order;
 517         struct aper_size_info_fixed *size;
 518         int num_entries;
 519         u32 temp;
 520
 521         size = agp_bridge->current_size;
 522         page_order = size->page_order;
 523         num_entries = size->num_entries;
 524         agp_bridge->gatt_table_real = NULL;
 525
 526         pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
 527         temp &= 0xfff80000;
 528
 529         intel_i830_private.registers = ioremap(temp,128 * 4096);
 530         if (!intel_i830_private.registers)
 531                 return -ENOMEM;
 532
 533         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 534         global_cache_flush();   /* FIXME: ?? */
 535
 536         /* we have to call this as early as possible after the MMIO base address is known */
 537         intel_i830_init_gtt_entries();
 538
 539         agp_bridge->gatt_table = NULL;
 540
 541         agp_bridge->gatt_bus_addr = temp;
 542
 543         return 0;
 544 }
 545
 546 /* Return the gatt table to a sane state. Use the top of stolen
 547  * memory for the GTT.
 548  */
 549 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 550 {
 551         return 0;
 552 }
 553
 554 static int intel_i830_fetch_size(void)
 555 {
 556         u16 gmch_ctrl;
 557         struct aper_size_info_fixed *values;
 558
 559         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 560
 561         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 562             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 563                 /* 855GM/852GM/865G has 128MB aperture size */
 564                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 565                 agp_bridge->aperture_size_idx = 0;
 566                 return values[0].size;
 567         }
 568
 569         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 570
 571         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 572                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 573                 agp_bridge->aperture_size_idx = 0;
 574                 return values[0].size;
 575         } else {
 576                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 577                 agp_bridge->aperture_size_idx = 1;
 578                 return values[1].size;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int intel_i830_configure(void)
 585 {
 586         struct aper_size_info_fixed *current_size;
 587         u32 temp;
 588         u16 gmch_ctrl;
 589         int i;
 590
 591         current_size = A_SIZE_FIX(agp_bridge->current_size);
 592
 593         pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
 594         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 595
 596         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 597         gmch_ctrl |= I830_GMCH_ENABLED;
 598         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 599
 600         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
 601         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 602
 603         if (agp_bridge->driver->needs_scratch_page) {
 604                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
 605                         writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
 606                         readl(intel_i830_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
 607                 }
 608         }
 609
 610         global_cache_flush();
 611         return 0;
 612 }
 613
 614 static void intel_i830_cleanup(void)
 615 {
 616         iounmap(intel_i830_private.registers);
 617 }
 618
 619 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 620 {
 621         int i,j,num_entries;
 622         void *temp;
 623
 624         if (mem->page_count == 0)
 625                 return 0;
 626
 627         temp = agp_bridge->current_size;
 628         num_entries = A_SIZE_FIX(temp)->num_entries;
 629
 630         if (pg_start < intel_i830_private.gtt_entries) {
 631                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
 632                                 pg_start,intel_i830_private.gtt_entries);
 633
 634                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 635                 return -EINVAL;
 636         }
 637
 638         if ((pg_start + mem->page_count) > num_entries)
 639                 return -EINVAL;
 640
 641         /* The i830 can't check the GTT for entries since its read only,
 642          * depend on the caller to make the correct offset decisions.
 643          */
 644
 645         if ((type != 0 && type != AGP_PHYS_MEMORY) ||
 646                 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
 647                 return -EINVAL;
 648
 649         if (!mem->is_flushed) {
 650                 global_cache_flush();
 651                 mem->is_flushed = TRUE;
 652         }
 653
 654         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 655                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 656                         mem->memory[i], mem->type),
 657                         intel_i830_private.registers+I810_PTE_BASE+(j*4));
 658         }
 659         readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4));
 660
 661         agp_bridge->driver->tlb_flush(mem);
 662         return 0;
 663 }
 664
 665 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 666                                 int type)
 667 {
 668         int i;
 669
 670         if (mem->page_count == 0)
 671                 return 0;
 672
 673         if (pg_start < intel_i830_private.gtt_entries) {
 674                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 675                 return -EINVAL;
 676         }
 677
 678         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 679                 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
 680         }
 681         readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4));
 682
 683         agp_bridge->driver->tlb_flush(mem);
 684         return 0;
 685 }
 686
 687 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 688 {
 689         if (type == AGP_PHYS_MEMORY)
 690                 return alloc_agpphysmem_i8xx(pg_count, type);
 691
 692         /* always return NULL for other allocation types for now */
 693         return NULL;
 694 }
 695
 696 static int intel_i915_configure(void)
 697 {
 698         struct aper_size_info_fixed *current_size;
 699         u32 temp;
 700         u16 gmch_ctrl;
 701         int i;
 702
 703         current_size = A_SIZE_FIX(agp_bridge->current_size);
 704
 705         pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
 706
 707         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 708
 709         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 710         gmch_ctrl |= I830_GMCH_ENABLED;
 711         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 712
 713         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
 714         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 715
 716         if (agp_bridge->driver->needs_scratch_page) {
 717                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
 718                         writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
 719                         readl(intel_i830_private.gtt+i);        /* PCI Posting. */
 720                 }
 721         }
 722
 723         global_cache_flush();
 724         return 0;
 725 }
 726
 727 static void intel_i915_cleanup(void)
 728 {
 729         iounmap(intel_i830_private.gtt);
 730         iounmap(intel_i830_private.registers);
 731 }
 732
 733 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 734                                 int type)
 735 {
 736         int i,j,num_entries;
 737         void *temp;
 738
 739         if (mem->page_count == 0)
 740                 return 0;
 741
 742         temp = agp_bridge->current_size;
 743         num_entries = A_SIZE_FIX(temp)->num_entries;
 744
 745         if (pg_start < intel_i830_private.gtt_entries) {
 746                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
 747                                 pg_start,intel_i830_private.gtt_entries);
 748
 749                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 750                 return -EINVAL;
 751         }
 752
 753         if ((pg_start + mem->page_count) > num_entries)
 754                 return -EINVAL;
 755
 756         /* The i830 can't check the GTT for entries since its read only,
 757          * depend on the caller to make the correct offset decisions.
 758          */
 759
 760         if ((type != 0 && type != AGP_PHYS_MEMORY) ||
 761                 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
 762                 return -EINVAL;
 763
 764         if (!mem->is_flushed) {
 765                 global_cache_flush();
 766                 mem->is_flushed = TRUE;
 767         }
 768
 769         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 770                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 771                         mem->memory[i], mem->type), intel_i830_private.gtt+j);
 772         }
 773         readl(intel_i830_private.gtt+j-1);
 774
 775         agp_bridge->driver->tlb_flush(mem);
 776         return 0;
 777 }
 778
 779 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
 780                                 int type)
 781 {
 782         int i;
 783
 784         if (mem->page_count == 0)
 785                 return 0;
 786
 787         if (pg_start < intel_i830_private.gtt_entries) {
 788                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 789                 return -EINVAL;
 790         }
 791
 792         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 793                 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
 794         }
 795         readl(intel_i830_private.gtt+i-1);
 796
 797         agp_bridge->driver->tlb_flush(mem);
 798         return 0;
 799 }
 800
 801 /* Return the aperture size by just checking the resource length.  The effect
 802  * described in the spec of the MSAC registers is just changing of the
 803  * resource size.
 804  */
 805 static int intel_i9xx_fetch_size(void)
 806 {
 807         int num_sizes = sizeof(intel_i830_sizes) / sizeof(*intel_i830_sizes);
 808         int aper_size; /* size in megabytes */
 809         int i;
 810
 811         aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1);
 812
 813         for (i = 0; i < num_sizes; i++) {
 814                 if (aper_size == intel_i830_sizes[i].size) {
 815                         agp_bridge->current_size = intel_i830_sizes + i;
 816                         agp_bridge->previous_size = agp_bridge->current_size;
 817                         return aper_size;
 818                 }
 819         }
 820
 821         return 0;
 822 }
 823
 824 /* The intel i915 automatically initializes the agp aperture during POST.
 825  * Use the memory already set aside for in the GTT.
 826  */
 827 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 828 {
 829         int page_order;
 830         struct aper_size_info_fixed *size;
 831         int num_entries;
 832         u32 temp, temp2;
 833
 834         size = agp_bridge->current_size;
 835         page_order = size->page_order;
 836         num_entries = size->num_entries;
 837         agp_bridge->gatt_table_real = NULL;
 838
 839         pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
 840         pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
 841
 842         intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
 843         if (!intel_i830_private.gtt)
 844                 return -ENOMEM;
 845
 846         temp &= 0xfff80000;
 847
 848         intel_i830_private.registers = ioremap(temp,128 * 4096);
 849         if (!intel_i830_private.registers)
 850                 return -ENOMEM;
 851
 852         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 853         global_cache_flush();   /* FIXME: ? */
 854
 855         /* we have to call this as early as possible after the MMIO base address is known */
 856         intel_i830_init_gtt_entries();
 857
 858         agp_bridge->gatt_table = NULL;
 859
 860         agp_bridge->gatt_bus_addr = temp;
 861
 862         return 0;
 863 }
 864
 865 /*
 866  * The i965 supports 36-bit physical addresses, but to keep
 867  * the format of the GTT the same, the bits that don't fit
 868  * in a 32-bit word are shifted down to bits 4..7.
 869  *
 870  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
 871  * is always zero on 32-bit architectures, so no need to make
 872  * this conditional.
 873  */
 874 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
 875         unsigned long addr, int type)
 876 {
 877         /* Shift high bits down */
 878         addr |= (addr >> 28) & 0xf0;
 879
 880         /* Type checking must be done elsewhere */
 881         return addr | bridge->driver->masks[type].mask;
 882 }
 883
 884 /* The intel i965 automatically initializes the agp aperture during POST.
 885  * Use the memory already set aside for in the GTT.
 886  */
 887 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 888 {
 889        int page_order;
 890        struct aper_size_info_fixed *size;
 891        int num_entries;
 892        u32 temp;
 893
 894        size = agp_bridge->current_size;
 895        page_order = size->page_order;
 896        num_entries = size->num_entries;
 897        agp_bridge->gatt_table_real = NULL;
 898
 899        pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
 900
 901        temp &= 0xfff00000;
 902        intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
 903
 904        if (!intel_i830_private.gtt)
 905                return -ENOMEM;
 906
 907
 908        intel_i830_private.registers = ioremap(temp,128 * 4096);
 909        if (!intel_i830_private.registers)
 910                return -ENOMEM;
 911
 912        temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 913        global_cache_flush();   /* FIXME: ? */
 914
 915        /* we have to call this as early as possible after the MMIO base address is known */
 916        intel_i830_init_gtt_entries();
 917
 918        agp_bridge->gatt_table = NULL;
 919
 920        agp_bridge->gatt_bus_addr = temp;
 921
 922        return 0;
 923 }
 924
 925
 926 static int intel_fetch_size(void)
 927 {
 928         int i;
 929         u16 temp;
 930         struct aper_size_info_16 *values;
 931
 932         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
 933         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
 934
 935         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 936                 if (temp == values[i].size_value) {
 937                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
 938                         agp_bridge->aperture_size_idx = i;
 939                         return values[i].size;
 940                 }
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int __intel_8xx_fetch_size(u8 temp)
 947 {
 948         int i;
 949         struct aper_size_info_8 *values;
 950
 951         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 952
 953         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 954                 if (temp == values[i].size_value) {
 955                         agp_bridge->previous_size =
 956                                 agp_bridge->current_size = (void *) (values + i);
 957                         agp_bridge->aperture_size_idx = i;
 958                         return values[i].size;
 959                 }
 960         }
 961         return 0;
 962 }
 963
 964 static int intel_8xx_fetch_size(void)
 965 {
 966         u8 temp;
 967
 968         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
 969         return __intel_8xx_fetch_size(temp);
 970 }
 971
 972 static int intel_815_fetch_size(void)
 973 {
 974         u8 temp;
 975
 976         /* Intel 815 chipsets have a _weird_ APSIZE register with only
 977          * one non-reserved bit, so mask the others out ... */
 978         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
 979         temp &= (1 << 3);
 980
 981         return __intel_8xx_fetch_size(temp);
 982 }
 983
 984 static void intel_tlbflush(struct agp_memory *mem)
 985 {
 986         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
 987         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
 988 }
 989
 990
 991 static void intel_8xx_tlbflush(struct agp_memory *mem)
 992 {
 993         u32 temp;
 994         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
 995         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
 996         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
 997         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
 998 }
 999
1000
1001 static void intel_cleanup(void)
1002 {
1003         u16 temp;
1004         struct aper_size_info_16 *previous_size;
1005
1006         previous_size = A_SIZE_16(agp_bridge->previous_size);
1007         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1008         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1009         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1010 }
1011
1012
1013 static void intel_8xx_cleanup(void)
1014 {
1015         u16 temp;
1016         struct aper_size_info_8 *previous_size;
1017
1018         previous_size = A_SIZE_8(agp_bridge->previous_size);
1019         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1020         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1021         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1022 }
1023
1024
1025 static int intel_configure(void)
1026 {
1027         u32 temp;
1028         u16 temp2;
1029         struct aper_size_info_16 *current_size;
1030
1031         current_size = A_SIZE_16(agp_bridge->current_size);
1032
1033         /* aperture size */
1034         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1035
1036         /* address to map to */
1037         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1038         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1039
1040         /* attbase - aperture base */
1041         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1042
1043         /* agpctrl */
1044         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1045
1046         /* paccfg/nbxcfg */
1047         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1048         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1049                         (temp2 & ~(1 << 10)) | (1 << 9));
1050         /* clear any possible error conditions */
1051         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1052         return 0;
1053 }
1054
1055 static int intel_815_configure(void)
1056 {
1057         u32 temp, addr;
1058         u8 temp2;
1059         struct aper_size_info_8 *current_size;
1060
1061         /* attbase - aperture base */
1062         /* the Intel 815 chipset spec. says that bits 29-31 in the
1063         * ATTBASE register are reserved -> try not to write them */
1064         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1065                 printk (KERN_EMERG PFX "gatt bus addr too high");
1066                 return -EINVAL;
1067         }
1068
1069         current_size = A_SIZE_8(agp_bridge->current_size);
1070
1071         /* aperture size */
1072         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1073                         current_size->size_value);
1074
1075         /* address to map to */
1076         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1077         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1078
1079         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1080         addr &= INTEL_815_ATTBASE_MASK;
1081         addr |= agp_bridge->gatt_bus_addr;
1082         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1083
1084         /* agpctrl */
1085         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1086
1087         /* apcont */
1088         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1089         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1090
1091         /* clear any possible error conditions */
1092         /* Oddness : this chipset seems to have no ERRSTS register ! */
1093         return 0;
1094 }
1095
1096 static void intel_820_tlbflush(struct agp_memory *mem)
1097 {
1098         return;
1099 }
1100
1101 static void intel_820_cleanup(void)
1102 {
1103         u8 temp;
1104         struct aper_size_info_8 *previous_size;
1105
1106         previous_size = A_SIZE_8(agp_bridge->previous_size);
1107         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1108         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1109                         temp & ~(1 << 1));
1110         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1111                         previous_size->size_value);
1112 }
1113
1114
1115 static int intel_820_configure(void)
1116 {
1117         u32 temp;
1118         u8 temp2;
1119         struct aper_size_info_8 *current_size;
1120
1121         current_size = A_SIZE_8(agp_bridge->current_size);
1122
1123         /* aperture size */
1124         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1125
1126         /* address to map to */
1127         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1128         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1129
1130         /* attbase - aperture base */
1131         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1132
1133         /* agpctrl */
1134         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1135
1136         /* global enable aperture access */
1137         /* This flag is not accessed through MCHCFG register as in */
1138         /* i850 chipset. */
1139         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1140         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1141         /* clear any possible AGP-related error conditions */
1142         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1143         return 0;
1144 }
1145
1146 static int intel_840_configure(void)
1147 {
1148         u32 temp;
1149         u16 temp2;
1150         struct aper_size_info_8 *current_size;
1151
1152         current_size = A_SIZE_8(agp_bridge->current_size);
1153
1154         /* aperture size */
1155         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1156
1157         /* address to map to */
1158         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1159         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1160
1161         /* attbase - aperture base */
1162         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1163
1164         /* agpctrl */
1165         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1166
1167         /* mcgcfg */
1168         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1169         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1170         /* clear any possible error conditions */
1171         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1172         return 0;
1173 }
1174
1175 static int intel_845_configure(void)
1176 {
1177         u32 temp;
1178         u8 temp2;
1179         struct aper_size_info_8 *current_size;
1180
1181         current_size = A_SIZE_8(agp_bridge->current_size);
1182
1183         /* aperture size */
1184         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1185
1186         if (agp_bridge->apbase_config != 0) {
1187                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1188                                        agp_bridge->apbase_config);
1189         } else {
1190                 /* address to map to */
1191                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1192                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1193                 agp_bridge->apbase_config = temp;
1194         }
1195
1196         /* attbase - aperture base */
1197         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1198
1199         /* agpctrl */
1200         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1201
1202         /* agpm */
1203         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1204         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1205         /* clear any possible error conditions */
1206         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1207         return 0;
1208 }
1209
1210 static int intel_850_configure(void)
1211 {
1212         u32 temp;
1213         u16 temp2;
1214         struct aper_size_info_8 *current_size;
1215
1216         current_size = A_SIZE_8(agp_bridge->current_size);
1217
1218         /* aperture size */
1219         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1220
1221         /* address to map to */
1222         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1223         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1224
1225         /* attbase - aperture base */
1226         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1227
1228         /* agpctrl */
1229         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1230
1231         /* mcgcfg */
1232         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1233         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1234         /* clear any possible AGP-related error conditions */
1235         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1236         return 0;
1237 }
1238
1239 static int intel_860_configure(void)
1240 {
1241         u32 temp;
1242         u16 temp2;
1243         struct aper_size_info_8 *current_size;
1244
1245         current_size = A_SIZE_8(agp_bridge->current_size);
1246
1247         /* aperture size */
1248         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1249
1250         /* address to map to */
1251         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1252         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1253
1254         /* attbase - aperture base */
1255         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1256
1257         /* agpctrl */
1258         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1259
1260         /* mcgcfg */
1261         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1262         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1263         /* clear any possible AGP-related error conditions */
1264         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1265         return 0;
1266 }
1267
1268 static int intel_830mp_configure(void)
1269 {
1270         u32 temp;
1271         u16 temp2;
1272         struct aper_size_info_8 *current_size;
1273
1274         current_size = A_SIZE_8(agp_bridge->current_size);
1275
1276         /* aperture size */
1277         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1278
1279         /* address to map to */
1280         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1281         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1282
1283         /* attbase - aperture base */
1284         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1285
1286         /* agpctrl */
1287         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1288
1289         /* gmch */
1290         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1291         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1292         /* clear any possible AGP-related error conditions */
1293         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1294         return 0;
1295 }
1296
1297 static int intel_7505_configure(void)
1298 {
1299         u32 temp;
1300         u16 temp2;
1301         struct aper_size_info_8 *current_size;
1302
1303         current_size = A_SIZE_8(agp_bridge->current_size);
1304
1305         /* aperture size */
1306         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1307
1308         /* address to map to */
1309         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1310         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1311
1312         /* attbase - aperture base */
1313         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1314
1315         /* agpctrl */
1316         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1317
1318         /* mchcfg */
1319         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1320         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1321
1322         return 0;
1323 }
1324
1325 /* Setup function */
1326 static struct gatt_mask intel_generic_masks[] =
1327 {
1328         {.mask = 0x00000017, .type = 0}
1329 };
1330
1331 static struct aper_size_info_8 intel_815_sizes[2] =
1332 {
1333         {64, 16384, 4, 0},
1334         {32, 8192, 3, 8},
1335 };
1336
1337 static struct aper_size_info_8 intel_8xx_sizes[7] =
1338 {
1339         {256, 65536, 6, 0},
1340         {128, 32768, 5, 32},
1341         {64, 16384, 4, 48},
1342         {32, 8192, 3, 56},
1343         {16, 4096, 2, 60},
1344         {8, 2048, 1, 62},
1345         {4, 1024, 0, 63}
1346 };
1347
1348 static struct aper_size_info_16 intel_generic_sizes[7] =
1349 {
1350         {256, 65536, 6, 0},
1351         {128, 32768, 5, 32},
1352         {64, 16384, 4, 48},
1353         {32, 8192, 3, 56},
1354         {16, 4096, 2, 60},
1355         {8, 2048, 1, 62},
1356         {4, 1024, 0, 63}
1357 };
1358
1359 static struct aper_size_info_8 intel_830mp_sizes[4] =
1360 {
1361         {256, 65536, 6, 0},
1362         {128, 32768, 5, 32},
1363         {64, 16384, 4, 48},
1364         {32, 8192, 3, 56}
1365 };
1366
1367 static struct agp_bridge_driver intel_generic_driver = {
1368         .owner                  = THIS_MODULE,
1369         .aperture_sizes         = intel_generic_sizes,
1370         .size_type              = U16_APER_SIZE,
1371         .num_aperture_sizes     = 7,
1372         .configure              = intel_configure,
1373         .fetch_size             = intel_fetch_size,
1374         .cleanup                = intel_cleanup,
1375         .tlb_flush              = intel_tlbflush,
1376         .mask_memory            = agp_generic_mask_memory,
1377         .masks                  = intel_generic_masks,
1378         .agp_enable             = agp_generic_enable,
1379         .cache_flush            = global_cache_flush,
1380         .create_gatt_table      = agp_generic_create_gatt_table,
1381         .free_gatt_table        = agp_generic_free_gatt_table,
1382         .insert_memory          = agp_generic_insert_memory,
1383         .remove_memory          = agp_generic_remove_memory,
1384         .alloc_by_type          = agp_generic_alloc_by_type,
1385         .free_by_type           = agp_generic_free_by_type,
1386         .agp_alloc_page         = agp_generic_alloc_page,
1387         .agp_destroy_page       = agp_generic_destroy_page,
1388 };
1389
1390 static struct agp_bridge_driver intel_810_driver = {
1391         .owner                  = THIS_MODULE,
1392         .aperture_sizes         = intel_i810_sizes,
1393         .size_type              = FIXED_APER_SIZE,
1394         .num_aperture_sizes     = 2,
1395         .needs_scratch_page     = TRUE,
1396         .configure              = intel_i810_configure,
1397         .fetch_size             = intel_i810_fetch_size,
1398         .cleanup                = intel_i810_cleanup,
1399         .tlb_flush              = intel_i810_tlbflush,
1400         .mask_memory            = intel_i810_mask_memory,
1401         .masks                  = intel_i810_masks,
1402         .agp_enable             = intel_i810_agp_enable,
1403         .cache_flush            = global_cache_flush,
1404         .create_gatt_table      = agp_generic_create_gatt_table,
1405         .free_gatt_table        = agp_generic_free_gatt_table,
1406         .insert_memory          = intel_i810_insert_entries,
1407         .remove_memory          = intel_i810_remove_entries,
1408         .alloc_by_type          = intel_i810_alloc_by_type,
1409         .free_by_type           = intel_i810_free_by_type,
1410         .agp_alloc_page         = agp_generic_alloc_page,
1411         .agp_destroy_page       = agp_generic_destroy_page,
1412 };
1413
1414 static struct agp_bridge_driver intel_815_driver = {
1415         .owner                  = THIS_MODULE,
1416         .aperture_sizes         = intel_815_sizes,
1417         .size_type              = U8_APER_SIZE,
1418         .num_aperture_sizes     = 2,
1419         .configure              = intel_815_configure,
1420         .fetch_size             = intel_815_fetch_size,
1421         .cleanup                = intel_8xx_cleanup,
1422         .tlb_flush              = intel_8xx_tlbflush,
1423         .mask_memory            = agp_generic_mask_memory,
1424         .masks                  = intel_generic_masks,
1425         .agp_enable             = agp_generic_enable,
1426         .cache_flush            = global_cache_flush,
1427         .create_gatt_table      = agp_generic_create_gatt_table,
1428         .free_gatt_table        = agp_generic_free_gatt_table,
1429         .insert_memory          = agp_generic_insert_memory,
1430         .remove_memory          = agp_generic_remove_memory,
1431         .alloc_by_type          = agp_generic_alloc_by_type,
1432         .free_by_type           = agp_generic_free_by_type,
1433         .agp_alloc_page         = agp_generic_alloc_page,
1434         .agp_destroy_page       = agp_generic_destroy_page,
1435 };
1436
1437 static struct agp_bridge_driver intel_830_driver = {
1438         .owner                  = THIS_MODULE,
1439         .aperture_sizes         = intel_i830_sizes,
1440         .size_type              = FIXED_APER_SIZE,
1441         .num_aperture_sizes     = 4,
1442         .needs_scratch_page     = TRUE,
1443         .configure              = intel_i830_configure,
1444         .fetch_size             = intel_i830_fetch_size,
1445         .cleanup                = intel_i830_cleanup,
1446         .tlb_flush              = intel_i810_tlbflush,
1447         .mask_memory            = intel_i810_mask_memory,
1448         .masks                  = intel_i810_masks,
1449         .agp_enable             = intel_i810_agp_enable,
1450         .cache_flush            = global_cache_flush,
1451         .create_gatt_table      = intel_i830_create_gatt_table,
1452         .free_gatt_table        = intel_i830_free_gatt_table,
1453         .insert_memory          = intel_i830_insert_entries,
1454         .remove_memory          = intel_i830_remove_entries,
1455         .alloc_by_type          = intel_i830_alloc_by_type,
1456         .free_by_type           = intel_i810_free_by_type,
1457         .agp_alloc_page         = agp_generic_alloc_page,
1458         .agp_destroy_page       = agp_generic_destroy_page,
1459 };
1460
1461 static struct agp_bridge_driver intel_820_driver = {
1462         .owner                  = THIS_MODULE,
1463         .aperture_sizes         = intel_8xx_sizes,
1464         .size_type              = U8_APER_SIZE,
1465         .num_aperture_sizes     = 7,
1466         .configure              = intel_820_configure,
1467         .fetch_size             = intel_8xx_fetch_size,
1468         .cleanup                = intel_820_cleanup,
1469         .tlb_flush              = intel_820_tlbflush,
1470         .mask_memory            = agp_generic_mask_memory,
1471         .masks                  = intel_generic_masks,
1472         .agp_enable             = agp_generic_enable,
1473         .cache_flush            = global_cache_flush,
1474         .create_gatt_table      = agp_generic_create_gatt_table,
1475         .free_gatt_table        = agp_generic_free_gatt_table,
1476         .insert_memory          = agp_generic_insert_memory,
1477         .remove_memory          = agp_generic_remove_memory,
1478         .alloc_by_type          = agp_generic_alloc_by_type,
1479         .free_by_type           = agp_generic_free_by_type,
1480         .agp_alloc_page         = agp_generic_alloc_page,
1481         .agp_destroy_page       = agp_generic_destroy_page,
1482 };
1483
1484 static struct agp_bridge_driver intel_830mp_driver = {
1485         .owner                  = THIS_MODULE,
1486         .aperture_sizes         = intel_830mp_sizes,
1487         .size_type              = U8_APER_SIZE,
1488         .num_aperture_sizes     = 4,
1489         .configure              = intel_830mp_configure,
1490         .fetch_size             = intel_8xx_fetch_size,
1491         .cleanup                = intel_8xx_cleanup,
1492         .tlb_flush              = intel_8xx_tlbflush,
1493         .mask_memory            = agp_generic_mask_memory,
1494         .masks                  = intel_generic_masks,
1495         .agp_enable             = agp_generic_enable,
1496         .cache_flush            = global_cache_flush,
1497         .create_gatt_table      = agp_generic_create_gatt_table,
1498         .free_gatt_table        = agp_generic_free_gatt_table,
1499         .insert_memory          = agp_generic_insert_memory,
1500         .remove_memory          = agp_generic_remove_memory,
1501         .alloc_by_type          = agp_generic_alloc_by_type,
1502         .free_by_type           = agp_generic_free_by_type,
1503         .agp_alloc_page         = agp_generic_alloc_page,
1504         .agp_destroy_page       = agp_generic_destroy_page,
1505 };
1506
1507 static struct agp_bridge_driver intel_840_driver = {
1508         .owner                  = THIS_MODULE,
1509         .aperture_sizes         = intel_8xx_sizes,
1510         .size_type              = U8_APER_SIZE,
1511         .num_aperture_sizes     = 7,
1512         .configure              = intel_840_configure,
1513         .fetch_size             = intel_8xx_fetch_size,
1514         .cleanup                = intel_8xx_cleanup,
1515         .tlb_flush              = intel_8xx_tlbflush,
1516         .mask_memory            = agp_generic_mask_memory,
1517         .masks                  = intel_generic_masks,
1518         .agp_enable             = agp_generic_enable,
1519         .cache_flush            = global_cache_flush,
1520         .create_gatt_table      = agp_generic_create_gatt_table,
1521         .free_gatt_table        = agp_generic_free_gatt_table,
1522         .insert_memory          = agp_generic_insert_memory,
1523         .remove_memory          = agp_generic_remove_memory,
1524         .alloc_by_type          = agp_generic_alloc_by_type,
1525         .free_by_type           = agp_generic_free_by_type,
1526         .agp_alloc_page         = agp_generic_alloc_page,
1527         .agp_destroy_page       = agp_generic_destroy_page,
1528 };
1529
1530 static struct agp_bridge_driver intel_845_driver = {
1531         .owner                  = THIS_MODULE,
1532         .aperture_sizes         = intel_8xx_sizes,
1533         .size_type              = U8_APER_SIZE,
1534         .num_aperture_sizes     = 7,
1535         .configure              = intel_845_configure,
1536         .fetch_size             = intel_8xx_fetch_size,
1537         .cleanup                = intel_8xx_cleanup,
1538         .tlb_flush              = intel_8xx_tlbflush,
1539         .mask_memory            = agp_generic_mask_memory,
1540         .masks                  = intel_generic_masks,
1541         .agp_enable             = agp_generic_enable,
1542         .cache_flush            = global_cache_flush,
1543         .create_gatt_table      = agp_generic_create_gatt_table,
1544         .free_gatt_table        = agp_generic_free_gatt_table,
1545         .insert_memory          = agp_generic_insert_memory,
1546         .remove_memory          = agp_generic_remove_memory,
1547         .alloc_by_type          = agp_generic_alloc_by_type,
1548         .free_by_type           = agp_generic_free_by_type,
1549         .agp_alloc_page         = agp_generic_alloc_page,
1550         .agp_destroy_page       = agp_generic_destroy_page,
1551 };
1552
1553 static struct agp_bridge_driver intel_850_driver = {
1554         .owner                  = THIS_MODULE,
1555         .aperture_sizes         = intel_8xx_sizes,
1556         .size_type              = U8_APER_SIZE,
1557         .num_aperture_sizes     = 7,
1558         .configure              = intel_850_configure,
1559         .fetch_size             = intel_8xx_fetch_size,
1560         .cleanup                = intel_8xx_cleanup,
1561         .tlb_flush              = intel_8xx_tlbflush,
1562         .mask_memory            = agp_generic_mask_memory,
1563         .masks                  = intel_generic_masks,
1564         .agp_enable             = agp_generic_enable,
1565         .cache_flush            = global_cache_flush,
1566         .create_gatt_table      = agp_generic_create_gatt_table,
1567         .free_gatt_table        = agp_generic_free_gatt_table,
1568         .insert_memory          = agp_generic_insert_memory,
1569         .remove_memory          = agp_generic_remove_memory,
1570         .alloc_by_type          = agp_generic_alloc_by_type,
1571         .free_by_type           = agp_generic_free_by_type,
1572         .agp_alloc_page         = agp_generic_alloc_page,
1573         .agp_destroy_page       = agp_generic_destroy_page,
1574 };
1575
1576 static struct agp_bridge_driver intel_860_driver = {
1577         .owner                  = THIS_MODULE,
1578         .aperture_sizes         = intel_8xx_sizes,
1579         .size_type              = U8_APER_SIZE,
1580         .num_aperture_sizes     = 7,
1581         .configure              = intel_860_configure,
1582         .fetch_size             = intel_8xx_fetch_size,
1583         .cleanup                = intel_8xx_cleanup,
1584         .tlb_flush              = intel_8xx_tlbflush,
1585         .mask_memory            = agp_generic_mask_memory,
1586         .masks                  = intel_generic_masks,
1587         .agp_enable             = agp_generic_enable,
1588         .cache_flush            = global_cache_flush,
1589         .create_gatt_table      = agp_generic_create_gatt_table,
1590         .free_gatt_table        = agp_generic_free_gatt_table,
1591         .insert_memory          = agp_generic_insert_memory,
1592         .remove_memory          = agp_generic_remove_memory,
1593         .alloc_by_type          = agp_generic_alloc_by_type,
1594         .free_by_type           = agp_generic_free_by_type,
1595         .agp_alloc_page         = agp_generic_alloc_page,
1596         .agp_destroy_page       = agp_generic_destroy_page,
1597 };
1598
1599 static struct agp_bridge_driver intel_915_driver = {
1600         .owner                  = THIS_MODULE,
1601         .aperture_sizes         = intel_i830_sizes,
1602         .size_type              = FIXED_APER_SIZE,
1603         .num_aperture_sizes     = 4,
1604         .needs_scratch_page     = TRUE,
1605         .configure              = intel_i915_configure,
1606         .fetch_size             = intel_i9xx_fetch_size,
1607         .cleanup                = intel_i915_cleanup,
1608         .tlb_flush              = intel_i810_tlbflush,
1609         .mask_memory            = intel_i810_mask_memory,
1610         .masks                  = intel_i810_masks,
1611         .agp_enable             = intel_i810_agp_enable,
1612         .cache_flush            = global_cache_flush,
1613         .create_gatt_table      = intel_i915_create_gatt_table,
1614         .free_gatt_table        = intel_i830_free_gatt_table,
1615         .insert_memory          = intel_i915_insert_entries,
1616         .remove_memory          = intel_i915_remove_entries,
1617         .alloc_by_type          = intel_i830_alloc_by_type,
1618         .free_by_type           = intel_i810_free_by_type,
1619         .agp_alloc_page         = agp_generic_alloc_page,
1620         .agp_destroy_page       = agp_generic_destroy_page,
1621 };
1622
1623 static struct agp_bridge_driver intel_i965_driver = {
1624        .owner                  = THIS_MODULE,
1625        .aperture_sizes         = intel_i830_sizes,
1626        .size_type              = FIXED_APER_SIZE,
1627        .num_aperture_sizes     = 4,
1628        .needs_scratch_page     = TRUE,
1629        .configure              = intel_i915_configure,
1630        .fetch_size             = intel_i9xx_fetch_size,
1631        .cleanup                = intel_i915_cleanup,
1632        .tlb_flush              = intel_i810_tlbflush,
1633        .mask_memory            = intel_i965_mask_memory,
1634        .masks                  = intel_i810_masks,
1635        .agp_enable             = intel_i810_agp_enable,
1636        .cache_flush            = global_cache_flush,
1637        .create_gatt_table      = intel_i965_create_gatt_table,
1638        .free_gatt_table        = intel_i830_free_gatt_table,
1639        .insert_memory          = intel_i915_insert_entries,
1640        .remove_memory          = intel_i915_remove_entries,
1641        .alloc_by_type          = intel_i830_alloc_by_type,
1642        .free_by_type           = intel_i810_free_by_type,
1643        .agp_alloc_page         = agp_generic_alloc_page,
1644        .agp_destroy_page       = agp_generic_destroy_page,
1645 };
1646
1647 static struct agp_bridge_driver intel_7505_driver = {
1648         .owner                  = THIS_MODULE,
1649         .aperture_sizes         = intel_8xx_sizes,
1650         .size_type              = U8_APER_SIZE,
1651         .num_aperture_sizes     = 7,
1652         .configure              = intel_7505_configure,
1653         .fetch_size             = intel_8xx_fetch_size,
1654         .cleanup                = intel_8xx_cleanup,
1655         .tlb_flush              = intel_8xx_tlbflush,
1656         .mask_memory            = agp_generic_mask_memory,
1657         .masks                  = intel_generic_masks,
1658         .agp_enable             = agp_generic_enable,
1659         .cache_flush            = global_cache_flush,
1660         .create_gatt_table      = agp_generic_create_gatt_table,
1661         .free_gatt_table        = agp_generic_free_gatt_table,
1662         .insert_memory          = agp_generic_insert_memory,
1663         .remove_memory          = agp_generic_remove_memory,
1664         .alloc_by_type          = agp_generic_alloc_by_type,
1665         .free_by_type           = agp_generic_free_by_type,
1666         .agp_alloc_page         = agp_generic_alloc_page,
1667         .agp_destroy_page       = agp_generic_destroy_page,
1668 };
1669
1670 static int find_i810(u16 device)
1671 {
1672         struct pci_dev *i810_dev;
1673
1674         i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1675         if (!i810_dev)
1676                 return 0;
1677         intel_i810_private.i810_dev = i810_dev;
1678         return 1;
1679 }
1680
1681 static int find_i830(u16 device)
1682 {
1683         struct pci_dev *i830_dev;
1684
1685         i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1686         if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) {
1687                 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1688                                 device, i830_dev);
1689         }
1690
1691         if (!i830_dev)
1692                 return 0;
1693
1694         intel_i830_private.i830_dev = i830_dev;
1695         return 1;
1696 }
1697
1698 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1699                                      const struct pci_device_id *ent)
1700 {
1701         struct agp_bridge_data *bridge;
1702         char *name = "(unknown)";
1703         u8 cap_ptr = 0;
1704         struct resource *r;
1705
1706         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1707
1708         bridge = agp_alloc_bridge();
1709         if (!bridge)
1710                 return -ENOMEM;
1711
1712         switch (pdev->device) {
1713         case PCI_DEVICE_ID_INTEL_82443LX_0:
1714                 bridge->driver = &intel_generic_driver;
1715                 name = "440LX";
1716                 break;
1717         case PCI_DEVICE_ID_INTEL_82443BX_0:
1718                 bridge->driver = &intel_generic_driver;
1719                 name = "440BX";
1720                 break;
1721         case PCI_DEVICE_ID_INTEL_82443GX_0:
1722                 bridge->driver = &intel_generic_driver;
1723                 name = "440GX";
1724                 break;
1725         case PCI_DEVICE_ID_INTEL_82810_MC1:
1726                 name = "i810";
1727                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1))
1728                         goto fail;
1729                 bridge->driver = &intel_810_driver;
1730                 break;
1731         case PCI_DEVICE_ID_INTEL_82810_MC3:
1732                 name = "i810 DC100";
1733                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3))
1734                         goto fail;
1735                 bridge->driver = &intel_810_driver;
1736                 break;
1737         case PCI_DEVICE_ID_INTEL_82810E_MC:
1738                 name = "i810 E";
1739                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG))
1740                         goto fail;
1741                 bridge->driver = &intel_810_driver;
1742                 break;
1743          case PCI_DEVICE_ID_INTEL_82815_MC:
1744                 /*
1745                  * The i815 can operate either as an i810 style
1746                  * integrated device, or as an AGP4X motherboard.
1747                  */
1748                 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC))
1749                         bridge->driver = &intel_810_driver;
1750                 else
1751                         bridge->driver = &intel_815_driver;
1752                 name = "i815";
1753                 break;
1754         case PCI_DEVICE_ID_INTEL_82820_HB:
1755         case PCI_DEVICE_ID_INTEL_82820_UP_HB:
1756                 bridge->driver = &intel_820_driver;
1757                 name = "i820";
1758                 break;
1759         case PCI_DEVICE_ID_INTEL_82830_HB:
1760                 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC))
1761                         bridge->driver = &intel_830_driver;
1762                 else
1763                         bridge->driver = &intel_830mp_driver;
1764                 name = "830M";
1765                 break;
1766         case PCI_DEVICE_ID_INTEL_82840_HB:
1767                 bridge->driver = &intel_840_driver;
1768                 name = "i840";
1769                 break;
1770         case PCI_DEVICE_ID_INTEL_82845_HB:
1771                 bridge->driver = &intel_845_driver;
1772                 name = "i845";
1773                 break;
1774         case PCI_DEVICE_ID_INTEL_82845G_HB:
1775                 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG))
1776                         bridge->driver = &intel_830_driver;
1777                 else
1778                         bridge->driver = &intel_845_driver;
1779                 name = "845G";
1780                 break;
1781         case PCI_DEVICE_ID_INTEL_82850_HB:
1782                 bridge->driver = &intel_850_driver;
1783                 name = "i850";
1784                 break;
1785         case PCI_DEVICE_ID_INTEL_82855PM_HB:
1786                 bridge->driver = &intel_845_driver;
1787                 name = "855PM";
1788                 break;
1789         case PCI_DEVICE_ID_INTEL_82855GM_HB:
1790                 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) {
1791                         bridge->driver = &intel_830_driver;
1792                         name = "855";
1793                 } else {
1794                         bridge->driver = &intel_845_driver;
1795                         name = "855GM";
1796                 }
1797                 break;
1798         case PCI_DEVICE_ID_INTEL_82860_HB:
1799                 bridge->driver = &intel_860_driver;
1800                 name = "i860";
1801                 break;
1802         case PCI_DEVICE_ID_INTEL_82865_HB:
1803                 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG))
1804                         bridge->driver = &intel_830_driver;
1805                 else
1806                         bridge->driver = &intel_845_driver;
1807                 name = "865";
1808                 break;
1809         case PCI_DEVICE_ID_INTEL_82875_HB:
1810                 bridge->driver = &intel_845_driver;
1811                 name = "i875";
1812                 break;
1813         case PCI_DEVICE_ID_INTEL_82915G_HB:
1814                 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG))
1815                         bridge->driver = &intel_915_driver;
1816                 else
1817                         bridge->driver = &intel_845_driver;
1818                 name = "915G";
1819                 break;
1820         case PCI_DEVICE_ID_INTEL_82915GM_HB:
1821                 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG))
1822                         bridge->driver = &intel_915_driver;
1823                 else
1824                         bridge->driver = &intel_845_driver;
1825                 name = "915GM";
1826                 break;
1827         case PCI_DEVICE_ID_INTEL_82945G_HB:
1828                 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG))
1829                         bridge->driver = &intel_915_driver;
1830                 else
1831                         bridge->driver = &intel_845_driver;
1832                 name = "945G";
1833                 break;
1834         case PCI_DEVICE_ID_INTEL_82945GM_HB:
1835                 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG))
1836                         bridge->driver = &intel_915_driver;
1837                 else
1838                         bridge->driver = &intel_845_driver;
1839                 name = "945GM";
1840                 break;
1841         case PCI_DEVICE_ID_INTEL_82946GZ_HB:
1842                 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG))
1843                         bridge->driver = &intel_i965_driver;
1844                 else
1845                         bridge->driver = &intel_845_driver;
1846                 name = "946GZ";
1847                 break;
1848         case PCI_DEVICE_ID_INTEL_82965G_1_HB:
1849                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG))
1850                         bridge->driver = &intel_i965_driver;
1851                 else
1852                         bridge->driver = &intel_845_driver;
1853                 name = "965G";
1854                 break;
1855         case PCI_DEVICE_ID_INTEL_82965Q_HB:
1856                 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG))
1857                         bridge->driver = &intel_i965_driver;
1858                 else
1859                         bridge->driver = &intel_845_driver;
1860                 name = "965Q";
1861                 break;
1862         case PCI_DEVICE_ID_INTEL_82965G_HB:
1863                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG))
1864                         bridge->driver = &intel_i965_driver;
1865                 else
1866                         bridge->driver = &intel_845_driver;
1867                 name = "965G";
1868                 break;
1869
1870         case PCI_DEVICE_ID_INTEL_7505_0:
1871                 bridge->driver = &intel_7505_driver;
1872                 name = "E7505";
1873                 break;
1874         case PCI_DEVICE_ID_INTEL_7205_0:
1875                 bridge->driver = &intel_7505_driver;
1876                 name = "E7205";
1877                 break;
1878         default:
1879                 if (cap_ptr)
1880                         printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n",
1881                             pdev->device);
1882                 agp_put_bridge(bridge);
1883                 return -ENODEV;
1884         };
1885
1886         bridge->dev = pdev;
1887         bridge->capndx = cap_ptr;
1888
1889         if (bridge->driver == &intel_810_driver)
1890                 bridge->dev_private_data = &intel_i810_private;
1891         else if (bridge->driver == &intel_830_driver)
1892                 bridge->dev_private_data = &intel_i830_private;
1893
1894         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
1895
1896         /*
1897         * The following fixes the case where the BIOS has "forgotten" to
1898         * provide an address range for the GART.
1899         * 20030610 - hamish@zot.org
1900         */
1901         r = &pdev->resource[0];
1902         if (!r->start && r->end) {
1903                 if (pci_assign_resource(pdev, 0)) {
1904                         printk(KERN_ERR PFX "could not assign resource 0\n");
1905                         agp_put_bridge(bridge);
1906                         return -ENODEV;
1907                 }
1908         }
1909
1910         /*
1911         * If the device has not been properly setup, the following will catch
1912         * the problem and should stop the system from crashing.
1913         * 20030610 - hamish@zot.org
1914         */
1915         if (pci_enable_device(pdev)) {
1916                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1917                 agp_put_bridge(bridge);
1918                 return -ENODEV;
1919         }
1920
1921         /* Fill in the mode register */
1922         if (cap_ptr) {
1923                 pci_read_config_dword(pdev,
1924                                 bridge->capndx+PCI_AGP_STATUS,
1925                                 &bridge->mode);
1926         }
1927
1928         pci_set_drvdata(pdev, bridge);
1929         return agp_add_bridge(bridge);
1930
1931 fail:
1932         printk(KERN_ERR PFX "Detected an Intel %s chipset, "
1933                 "but could not find the secondary device.\n", name);
1934         agp_put_bridge(bridge);
1935         return -ENODEV;
1936 }
1937
1938 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1939 {
1940         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1941
1942         agp_remove_bridge(bridge);
1943
1944         if (intel_i810_private.i810_dev)
1945                 pci_dev_put(intel_i810_private.i810_dev);
1946         if (intel_i830_private.i830_dev)
1947                 pci_dev_put(intel_i830_private.i830_dev);
1948
1949         agp_put_bridge(bridge);
1950 }
1951
1952 #ifdef CONFIG_PM
1953 static int agp_intel_resume(struct pci_dev *pdev)
1954 {
1955         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1956
1957         pci_restore_state(pdev);
1958
1959         /* We should restore our graphics device's config space,
1960          * as host bridge (00:00) resumes before graphics device (02:00),
1961          * then our access to its pci space can work right.
1962          */
1963         if (intel_i810_private.i810_dev)
1964                 pci_restore_state(intel_i810_private.i810_dev);
1965         if (intel_i830_private.i830_dev)
1966                 pci_restore_state(intel_i830_private.i830_dev);
1967
1968         if (bridge->driver == &intel_generic_driver)
1969                 intel_configure();
1970         else if (bridge->driver == &intel_850_driver)
1971                 intel_850_configure();
1972         else if (bridge->driver == &intel_845_driver)
1973                 intel_845_configure();
1974         else if (bridge->driver == &intel_830mp_driver)
1975                 intel_830mp_configure();
1976         else if (bridge->driver == &intel_915_driver)
1977                 intel_i915_configure();
1978         else if (bridge->driver == &intel_830_driver)
1979                 intel_i830_configure();
1980         else if (bridge->driver == &intel_810_driver)
1981                 intel_i810_configure();
1982         else if (bridge->driver == &intel_i965_driver)
1983                 intel_i915_configure();
1984
1985         return 0;
1986 }
1987 #endif
1988
1989 static struct pci_device_id agp_intel_pci_table[] = {
1990 #define ID(x)                                           \
1991         {                                               \
1992         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
1993         .class_mask     = ~0,                           \
1994         .vendor         = PCI_VENDOR_ID_INTEL,          \
1995         .device         = x,                            \
1996         .subvendor      = PCI_ANY_ID,                   \
1997         .subdevice      = PCI_ANY_ID,                   \
1998         }
1999         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2000         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2001         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2002         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2003         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2004         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2005         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2006         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2007         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2008         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2009         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2010         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2011         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2012         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2013         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2014         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2015         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2016         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2017         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2018         ID(PCI_DEVICE_ID_INTEL_7505_0),
2019         ID(PCI_DEVICE_ID_INTEL_7205_0),
2020         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2021         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2022         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2023         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2024         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2025         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2026         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2027         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2028         { }
2029 };
2030
2031 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2032
2033 static struct pci_driver agp_intel_pci_driver = {
2034         .name           = "agpgart-intel",
2035         .id_table       = agp_intel_pci_table,
2036         .probe          = agp_intel_probe,
2037         .remove         = __devexit_p(agp_intel_remove),
2038 #ifdef CONFIG_PM
2039         .resume         = agp_intel_resume,
2040 #endif
2041 };
2042
2043 static int __init agp_intel_init(void)
2044 {
2045         if (agp_off)
2046                 return -EINVAL;
2047         return pci_register_driver(&agp_intel_pci_driver);
2048 }
2049
2050 static void __exit agp_intel_cleanup(void)
2051 {
2052         pci_unregister_driver(&agp_intel_pci_driver);
2053 }
2054
2055 module_init(agp_intel_init);
2056 module_exit(agp_intel_cleanup);
2057
2058 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2059 MODULE_LICENSE("GPL and additional rights");