drivers/char/agp/sworks-agp.c

   1 /*
   2  * Serverworks AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include "agp.h"
  10
  11 #define SVWRKS_COMMAND          0x04
  12 #define SVWRKS_APSIZE           0x10
  13 #define SVWRKS_MMBASE           0x14
  14 #define SVWRKS_CACHING          0x4b
  15 #define SVWRKS_AGP_ENABLE       0x60
  16 #define SVWRKS_FEATURE          0x68
  17
  18 #define SVWRKS_SIZE_MASK        0xfe000000
  19
  20 /* Memory mapped registers */
  21 #define SVWRKS_GART_CACHE       0x02
  22 #define SVWRKS_GATTBASE         0x04
  23 #define SVWRKS_TLBFLUSH         0x10
  24 #define SVWRKS_POSTFLUSH        0x14
  25 #define SVWRKS_DIRFLUSH         0x0c
  26
  27
  28 struct serverworks_page_map {
  29         unsigned long *real;
  30         unsigned long *remapped;
  31 };
  32
  33 static struct _serverworks_private {
  34         struct pci_dev *svrwrks_dev;    /* device one */
  35         volatile u8 *registers;
  36         struct serverworks_page_map **gatt_pages;
  37         int num_tables;
  38         struct serverworks_page_map scratch_dir;
  39
  40         int gart_addr_ofs;
  41         int mm_addr_ofs;
  42 } serverworks_private;
  43
  44 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
  45 {
  46         int i;
  47
  48         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  49         if (page_map->real == NULL) {
  50                 return -ENOMEM;
  51         }
  52         SetPageReserved(virt_to_page(page_map->real));
  53         global_cache_flush();
  54         page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
  55                                             PAGE_SIZE);
  56         if (page_map->remapped == NULL) {
  57                 ClearPageReserved(virt_to_page(page_map->real));
  58                 free_page((unsigned long) page_map->real);
  59                 page_map->real = NULL;
  60                 return -ENOMEM;
  61         }
  62         global_cache_flush();
  63
  64         for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
  65                 page_map->remapped[i] = agp_bridge->scratch_page;
  66         }
  67
  68         return 0;
  69 }
  70
  71 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
  72 {
  73         iounmap(page_map->remapped);
  74         ClearPageReserved(virt_to_page(page_map->real));
  75         free_page((unsigned long) page_map->real);
  76 }
  77
  78 static void serverworks_free_gatt_pages(void)
  79 {
  80         int i;
  81         struct serverworks_page_map **tables;
  82         struct serverworks_page_map *entry;
  83
  84         tables = serverworks_private.gatt_pages;
  85         for(i = 0; i < serverworks_private.num_tables; i++) {
  86                 entry = tables[i];
  87                 if (entry != NULL) {
  88                         if (entry->real != NULL) {
  89                                 serverworks_free_page_map(entry);
  90                         }
  91                         kfree(entry);
  92                 }
  93         }
  94         kfree(tables);
  95 }
  96
  97 static int serverworks_create_gatt_pages(int nr_tables)
  98 {
  99         struct serverworks_page_map **tables;
 100         struct serverworks_page_map *entry;
 101         int retval = 0;
 102         int i;
 103
 104         tables = kmalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 105                          GFP_KERNEL);
 106         if (tables == NULL) {
 107                 return -ENOMEM;
 108         }
 109         memset(tables, 0, sizeof(struct serverworks_page_map *) * (nr_tables + 1));
 110         for (i = 0; i < nr_tables; i++) {
 111                 entry = kmalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
 112                 if (entry == NULL) {
 113                         retval = -ENOMEM;
 114                         break;
 115                 }
 116                 memset(entry, 0, sizeof(struct serverworks_page_map));
 117                 tables[i] = entry;
 118                 retval = serverworks_create_page_map(entry);
 119                 if (retval != 0) break;
 120         }
 121         serverworks_private.num_tables = nr_tables;
 122         serverworks_private.gatt_pages = tables;
 123
 124         if (retval != 0) serverworks_free_gatt_pages();
 125
 126         return retval;
 127 }
 128
 129 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
 130         GET_PAGE_DIR_IDX(addr)]->remapped)
 131
 132 #ifndef GET_PAGE_DIR_OFF
 133 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 134 #endif
 135
 136 #ifndef GET_PAGE_DIR_IDX
 137 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 138         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 139 #endif
 140
 141 #ifndef GET_GATT_OFF
 142 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 143 #endif
 144
 145 static int serverworks_create_gatt_table(void)
 146 {
 147         struct aper_size_info_lvl2 *value;
 148         struct serverworks_page_map page_dir;
 149         int retval;
 150         u32 temp;
 151         int i;
 152
 153         value = A_SIZE_LVL2(agp_bridge->current_size);
 154         retval = serverworks_create_page_map(&page_dir);
 155         if (retval != 0) {
 156                 return retval;
 157         }
 158         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
 159         if (retval != 0) {
 160                 serverworks_free_page_map(&page_dir);
 161                 return retval;
 162         }
 163         /* Create a fake scratch directory */
 164         for(i = 0; i < 1024; i++) {
 165                 serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
 166                 page_dir.remapped[i] =
 167                         virt_to_phys(serverworks_private.scratch_dir.real);
 168                 page_dir.remapped[i] |= 0x00000001;
 169         }
 170
 171         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
 172         if (retval != 0) {
 173                 serverworks_free_page_map(&page_dir);
 174                 serverworks_free_page_map(&serverworks_private.scratch_dir);
 175                 return retval;
 176         }
 177
 178         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 179         agp_bridge->gatt_table = (u32 *)page_dir.remapped;
 180         agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
 181
 182         /* Get the address for the gart region.
 183          * This is a bus address even on the alpha, b/c its
 184          * used to program the agp master not the cpu
 185          */
 186
 187         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 188         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 189
 190         /* Calculate the agp offset */
 191
 192         for(i = 0; i < value->num_entries / 1024; i++) {
 193                 page_dir.remapped[i] =
 194                         virt_to_phys(serverworks_private.gatt_pages[i]->real);
 195                 page_dir.remapped[i] |= 0x00000001;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int serverworks_free_gatt_table(void)
 202 {
 203         struct serverworks_page_map page_dir;
 204
 205         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 206         page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
 207
 208         serverworks_free_gatt_pages();
 209         serverworks_free_page_map(&page_dir);
 210         serverworks_free_page_map(&serverworks_private.scratch_dir);
 211         return 0;
 212 }
 213
 214 static int serverworks_fetch_size(void)
 215 {
 216         int i;
 217         u32 temp;
 218         u32 temp2;
 219         struct aper_size_info_lvl2 *values;
 220
 221         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 222         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 223         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
 224                                         SVWRKS_SIZE_MASK);
 225         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
 226         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
 227         temp2 &= SVWRKS_SIZE_MASK;
 228
 229         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 230                 if (temp2 == values[i].size_value) {
 231                         agp_bridge->previous_size =
 232                             agp_bridge->current_size = (void *) (values + i);
 233
 234                         agp_bridge->aperture_size_idx = i;
 235                         return values[i].size;
 236                 }
 237         }
 238
 239         return 0;
 240 }
 241
 242 /*
 243  * This routine could be implemented by taking the addresses
 244  * written to the GATT, and flushing them individually.  However
 245  * currently it just flushes the whole table.  Which is probably
 246  * more efficent, since agp_memory blocks can be a large number of
 247  * entries.
 248  */
 249 static void serverworks_tlbflush(struct agp_memory *temp)
 250 {
 251         unsigned long end;
 252
 253         OUTREG8(serverworks_private.registers, SVWRKS_POSTFLUSH, 0x01);
 254         end = jiffies + 3*HZ;
 255         while(INREG8(serverworks_private.registers,
 256                      SVWRKS_POSTFLUSH) == 0x01) {
 257                 if((signed)(end - jiffies) <= 0) {
 258                         printk(KERN_ERR PFX "Posted write buffer flush took more"
 259                                "then 3 seconds\n");
 260                 }
 261         }
 262         OUTREG32(serverworks_private.registers, SVWRKS_DIRFLUSH, 0x00000001);
 263         end = jiffies + 3*HZ;
 264         while(INREG32(serverworks_private.registers,
 265                      SVWRKS_DIRFLUSH) == 0x00000001) {
 266                 if((signed)(end - jiffies) <= 0) {
 267                         printk(KERN_ERR PFX "TLB flush took more"
 268                                "then 3 seconds\n");
 269                 }
 270         }
 271 }
 272
 273 static int serverworks_configure(void)
 274 {
 275         struct aper_size_info_lvl2 *current_size;
 276         u32 temp;
 277         u8 enable_reg;
 278         u16 cap_reg;
 279
 280         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 281
 282         /* Get the memory mapped registers */
 283         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
 284         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 285         serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
 286         if (!serverworks_private.registers) {
 287                 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
 288                 return -ENOMEM;
 289         }
 290
 291         OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
 292
 293         OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
 294                  agp_bridge->gatt_bus_addr);
 295
 296         cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
 297         cap_reg &= ~0x0007;
 298         cap_reg |= 0x4;
 299         OUTREG16(serverworks_private.registers, SVWRKS_COMMAND, cap_reg);
 300
 301         pci_read_config_byte(serverworks_private.svrwrks_dev,
 302                              SVWRKS_AGP_ENABLE, &enable_reg);
 303         enable_reg |= 0x1; /* Agp Enable bit */
 304         pci_write_config_byte(serverworks_private.svrwrks_dev,
 305                               SVWRKS_AGP_ENABLE, enable_reg);
 306         serverworks_tlbflush(NULL);
 307
 308         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
 309
 310         /* Fill in the mode register */
 311         pci_read_config_dword(serverworks_private.svrwrks_dev,
 312                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 313
 314         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
 315         enable_reg &= ~0x3;
 316         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
 317
 318         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
 319         enable_reg |= (1<<6);
 320         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
 321
 322         return 0;
 323 }
 324
 325 static void serverworks_cleanup(void)
 326 {
 327         iounmap((void *) serverworks_private.registers);
 328 }
 329
 330 static int serverworks_insert_memory(struct agp_memory *mem,
 331                              off_t pg_start, int type)
 332 {
 333         int i, j, num_entries;
 334         unsigned long *cur_gatt;
 335         unsigned long addr;
 336
 337         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 338
 339         if (type != 0 || mem->type != 0) {
 340                 return -EINVAL;
 341         }
 342         if ((pg_start + mem->page_count) > num_entries) {
 343                 return -EINVAL;
 344         }
 345
 346         j = pg_start;
 347         while (j < (pg_start + mem->page_count)) {
 348                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 349                 cur_gatt = SVRWRKS_GET_GATT(addr);
 350                 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)])) {
 351                         return -EBUSY;
 352                 }
 353                 j++;
 354         }
 355
 356         if (mem->is_flushed == FALSE) {
 357                 global_cache_flush();
 358                 mem->is_flushed = TRUE;
 359         }
 360
 361         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 362                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 363                 cur_gatt = SVRWRKS_GET_GATT(addr);
 364                 cur_gatt[GET_GATT_OFF(addr)] =
 365                         agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
 366         }
 367         serverworks_tlbflush(mem);
 368         return 0;
 369 }
 370
 371 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
 372                              int type)
 373 {
 374         int i;
 375         unsigned long *cur_gatt;
 376         unsigned long addr;
 377
 378         if (type != 0 || mem->type != 0) {
 379                 return -EINVAL;
 380         }
 381
 382         global_cache_flush();
 383         serverworks_tlbflush(mem);
 384
 385         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 386                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 387                 cur_gatt = SVRWRKS_GET_GATT(addr);
 388                 cur_gatt[GET_GATT_OFF(addr)] =
 389                         (unsigned long) agp_bridge->scratch_page;
 390         }
 391
 392         serverworks_tlbflush(mem);
 393         return 0;
 394 }
 395
 396 static struct gatt_mask serverworks_masks[] =
 397 {
 398         {.mask = 1, .type = 0}
 399 };
 400
 401 static struct aper_size_info_lvl2 serverworks_sizes[7] =
 402 {
 403         {2048, 524288, 0x80000000},
 404         {1024, 262144, 0xc0000000},
 405         {512, 131072, 0xe0000000},
 406         {256, 65536, 0xf0000000},
 407         {128, 32768, 0xf8000000},
 408         {64, 16384, 0xfc000000},
 409         {32, 8192, 0xfe000000}
 410 };
 411
 412 static void serverworks_agp_enable(u32 mode)
 413 {
 414         u32 command;
 415
 416         pci_read_config_dword(serverworks_private.svrwrks_dev,
 417                               agp_bridge->capndx + PCI_AGP_STATUS,
 418                               &command);
 419
 420         command = agp_collect_device_status(mode, command);
 421
 422         command &= ~0x10;       /* disable FW */
 423         command &= ~0x08;
 424
 425         command |= 0x100;
 426
 427         pci_write_config_dword(serverworks_private.svrwrks_dev,
 428                                agp_bridge->capndx + PCI_AGP_COMMAND,
 429                                command);
 430
 431         agp_device_command(command, 0);
 432 }
 433
 434 struct agp_bridge_driver sworks_driver = {
 435         .owner                  = THIS_MODULE,
 436         .aperture_sizes         = serverworks_sizes,
 437         .size_type              = LVL2_APER_SIZE,
 438         .num_aperture_sizes     = 7,
 439         .configure              = serverworks_configure,
 440         .fetch_size             = serverworks_fetch_size,
 441         .cleanup                = serverworks_cleanup,
 442         .tlb_flush              = serverworks_tlbflush,
 443         .mask_memory            = agp_generic_mask_memory,
 444         .masks                  = serverworks_masks,
 445         .agp_enable             = serverworks_agp_enable,
 446         .cache_flush            = global_cache_flush,
 447         .create_gatt_table      = serverworks_create_gatt_table,
 448         .free_gatt_table        = serverworks_free_gatt_table,
 449         .insert_memory          = serverworks_insert_memory,
 450         .remove_memory          = serverworks_remove_memory,
 451         .alloc_by_type          = agp_generic_alloc_by_type,
 452         .free_by_type           = agp_generic_free_by_type,
 453         .agp_alloc_page         = agp_generic_alloc_page,
 454         .agp_destroy_page       = agp_generic_destroy_page,
 455 };
 456
 457 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
 458                                            const struct pci_device_id *ent)
 459 {
 460         struct agp_bridge_data *bridge;
 461         struct pci_dev *bridge_dev;
 462         u32 temp, temp2;
 463
 464         /* Everything is on func 1 here so we are hardcoding function one */
 465         bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
 466                         PCI_DEVFN(0, 1));
 467         if (!bridge_dev) {
 468                 printk(KERN_INFO PFX "Detected a Serverworks chipset "
 469                        "but could not find the secondary device.\n");
 470                 return -ENODEV;
 471         }
 472
 473         switch (pdev->device) {
 474         case 0x0006:
 475                 /* ServerWorks CNB20HE
 476                 Fail silently.*/
 477                 printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n");
 478                 return -ENODEV;
 479
 480         case PCI_DEVICE_ID_SERVERWORKS_HE:
 481         case PCI_DEVICE_ID_SERVERWORKS_LE:
 482         case 0x0007:
 483                 break;
 484
 485         default:
 486                 printk(KERN_ERR PFX "Unsupported Serverworks chipset "
 487                                 "(device id: %04x)\n", pdev->device);
 488                 return -ENODEV;
 489         }
 490
 491         serverworks_private.svrwrks_dev = bridge_dev;
 492         serverworks_private.gart_addr_ofs = 0x10;
 493
 494         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
 495         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 496                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
 497                 if (temp2 != 0) {
 498                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
 499                                "but top bits are not zero.  Disabling agp\n");
 500                         return -ENODEV;
 501                 }
 502                 serverworks_private.mm_addr_ofs = 0x18;
 503         } else
 504                 serverworks_private.mm_addr_ofs = 0x14;
 505
 506         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
 507         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 508                 pci_read_config_dword(pdev,
 509                                 serverworks_private.mm_addr_ofs + 4, &temp2);
 510                 if (temp2 != 0) {
 511                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
 512                                "but top bits are not zero.  Disabling agp\n");
 513                         return -ENODEV;
 514                 }
 515         }
 516
 517         bridge = agp_alloc_bridge();
 518         if (!bridge)
 519                 return -ENOMEM;
 520
 521         bridge->driver = &sworks_driver;
 522         bridge->dev_private_data = &serverworks_private,
 523         bridge->dev = pdev;
 524
 525         pci_set_drvdata(pdev, bridge);
 526         return agp_add_bridge(bridge);
 527 }
 528
 529 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
 530 {
 531         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 532
 533         agp_remove_bridge(bridge);
 534         agp_put_bridge(bridge);
 535 }
 536
 537 static struct pci_device_id agp_serverworks_pci_table[] = {
 538         {
 539         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 540         .class_mask     = ~0,
 541         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
 542         .device         = PCI_ANY_ID,
 543         .subvendor      = PCI_ANY_ID,
 544         .subdevice      = PCI_ANY_ID,
 545         },
 546         { }
 547 };
 548
 549 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 550
 551 static struct pci_driver agp_serverworks_pci_driver = {
 552         .name           = "agpgart-serverworks",
 553         .id_table       = agp_serverworks_pci_table,
 554         .probe          = agp_serverworks_probe,
 555         .remove         = agp_serverworks_remove,
 556 };
 557
 558 static int __init agp_serverworks_init(void)
 559 {
 560         return pci_module_init(&agp_serverworks_pci_driver);
 561 }
 562
 563 static void __exit agp_serverworks_cleanup(void)
 564 {
 565         pci_unregister_driver(&agp_serverworks_pci_driver);
 566 }
 567
 568 module_init(agp_serverworks_init);
 569 module_exit(agp_serverworks_cleanup);
 570
 571 MODULE_LICENSE("GPL and additional rights");
 572