ftp://ftp.kernel.org/pub/linux/kernel/v2.6/linux-2.6.6.tar.bz2
[linux-2.6.git] / drivers / char / agp / via-agp.c
1 /*
2  * VIA AGPGART routines. 
3  */
4
5 #include <linux/types.h>
6 #include <linux/module.h>
7 #include <linux/pci.h>
8 #include <linux/init.h>
9 #include <linux/agp_backend.h>
10 #include "agp.h"
11
12 #define VIA_GARTCTRL    0x80
13 #define VIA_APSIZE      0x84
14 #define VIA_ATTBASE     0x88
15
16 #define VIA_AGP3_GARTCTRL       0x90
17 #define VIA_AGP3_APSIZE         0x94
18 #define VIA_AGP3_ATTBASE        0x98
19 #define VIA_AGPSEL              0xfd
20
21 static int via_fetch_size(void)
22 {
23         int i;
24         u8 temp;
25         struct aper_size_info_8 *values;
26
27         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
28         pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
29         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
30                 if (temp == values[i].size_value) {
31                         agp_bridge->previous_size =
32                             agp_bridge->current_size = (void *) (values + i);
33                         agp_bridge->aperture_size_idx = i;
34                         return values[i].size;
35                 }
36         }
37         return 0;
38 }
39
40
41 static int via_configure(void)
42 {
43         u32 temp;
44         struct aper_size_info_8 *current_size;
45
46         current_size = A_SIZE_8(agp_bridge->current_size);
47         /* aperture size */
48         pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
49                               current_size->size_value);
50         /* address to map too */
51         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
52         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
53
54         /* GART control register */
55         pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
56
57         /* attbase - aperture GATT base */
58         pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
59                             (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
60         return 0;
61 }
62
63
64 static void via_cleanup(void)
65 {
66         struct aper_size_info_8 *previous_size;
67
68         previous_size = A_SIZE_8(agp_bridge->previous_size);
69         pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
70                               previous_size->size_value);
71         /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
72          * during reinitialization.
73          */
74 }
75
76
77 static void via_tlbflush(struct agp_memory *mem)
78 {
79         pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000008f);
80         pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
81 }
82
83
84 static struct aper_size_info_8 via_generic_sizes[7] =
85 {
86         {256, 65536, 6, 0},
87         {128, 32768, 5, 128},
88         {64, 16384, 4, 192},
89         {32, 8192, 3, 224},
90         {16, 4096, 2, 240},
91         {8, 2048, 1, 248},
92         {4, 1024, 0, 252}
93 };
94
95
96 static int via_fetch_size_agp3(void)
97 {
98         int i;
99         u16 temp;
100         struct aper_size_info_16 *values;
101
102         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
103         pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
104         temp &= 0xfff;
105
106         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
107                 if (temp == values[i].size_value) {
108                         agp_bridge->previous_size =
109                                 agp_bridge->current_size = (void *) (values + i);
110                         agp_bridge->aperture_size_idx = i;
111                         return values[i].size;
112                 }
113         }
114         return 0;
115 }
116
117
118 static int via_configure_agp3(void)
119 {
120         u32 temp;
121         struct aper_size_info_16 *current_size;
122     
123         current_size = A_SIZE_16(agp_bridge->current_size);
124
125         /* address to map too */
126         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
127         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
128
129         /* attbase - aperture GATT base */
130         pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
131                 agp_bridge->gatt_bus_addr & 0xfffff000);
132
133         /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch 
134          *    translation table first.
135          * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
136          *    graphics AGP aperture for the AGP3.0 port.
137          */
138         pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
139         pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));              
140         return 0;
141 }
142
143
144 static void via_cleanup_agp3(void)
145 {
146         struct aper_size_info_16 *previous_size;
147
148         previous_size = A_SIZE_16(agp_bridge->previous_size);
149         pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
150 }
151
152
153 static void via_tlbflush_agp3(struct agp_memory *mem)
154 {
155         u32 temp;
156
157         pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
158         pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
159         pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
160 }
161
162
163 struct agp_bridge_driver via_agp3_driver = {
164         .owner                  = THIS_MODULE,
165         .aperture_sizes         = agp3_generic_sizes,
166         .size_type              = U8_APER_SIZE,
167         .num_aperture_sizes     = 10,
168         .configure              = via_configure_agp3,
169         .fetch_size             = via_fetch_size_agp3,
170         .cleanup                = via_cleanup_agp3,
171         .tlb_flush              = via_tlbflush_agp3,
172         .mask_memory            = agp_generic_mask_memory,
173         .masks                  = NULL,
174         .agp_enable             = agp_generic_enable,
175         .cache_flush            = global_cache_flush,
176         .create_gatt_table      = agp_generic_create_gatt_table,
177         .free_gatt_table        = agp_generic_free_gatt_table,
178         .insert_memory          = agp_generic_insert_memory,
179         .remove_memory          = agp_generic_remove_memory,
180         .alloc_by_type          = agp_generic_alloc_by_type,
181         .free_by_type           = agp_generic_free_by_type,
182         .agp_alloc_page         = agp_generic_alloc_page,
183         .agp_destroy_page       = agp_generic_destroy_page,
184 };
185
186 struct agp_bridge_driver via_driver = {
187         .owner                  = THIS_MODULE,
188         .aperture_sizes         = via_generic_sizes,
189         .size_type              = U8_APER_SIZE,
190         .num_aperture_sizes     = 7,
191         .configure              = via_configure,
192         .fetch_size             = via_fetch_size,
193         .cleanup                = via_cleanup,
194         .tlb_flush              = via_tlbflush,
195         .mask_memory            = agp_generic_mask_memory,
196         .masks                  = NULL,
197         .agp_enable             = agp_generic_enable,
198         .cache_flush            = global_cache_flush,
199         .create_gatt_table      = agp_generic_create_gatt_table,
200         .free_gatt_table        = agp_generic_free_gatt_table,
201         .insert_memory          = agp_generic_insert_memory,
202         .remove_memory          = agp_generic_remove_memory,
203         .alloc_by_type          = agp_generic_alloc_by_type,
204         .free_by_type           = agp_generic_free_by_type,
205         .agp_alloc_page         = agp_generic_alloc_page,
206         .agp_destroy_page       = agp_generic_destroy_page,
207 };
208
209 static struct agp_device_ids via_agp_device_ids[] __devinitdata =
210 {
211         {
212                 .device_id      = PCI_DEVICE_ID_VIA_82C597_0,
213                 .chipset_name   = "Apollo VP3",
214         },
215
216         {
217                 .device_id      = PCI_DEVICE_ID_VIA_82C598_0,
218                 .chipset_name   = "Apollo MVP3",
219         },
220
221         {
222                 .device_id      = PCI_DEVICE_ID_VIA_8501_0,
223                 .chipset_name   = "Apollo MVP4",
224         },
225
226         /* VT8601 */
227         {
228                 .device_id      = PCI_DEVICE_ID_VIA_8601_0,
229                 .chipset_name   = "Apollo ProMedia/PLE133Ta",
230         },
231
232         /* VT82C693A / VT28C694T */
233         {
234                 .device_id      = PCI_DEVICE_ID_VIA_82C691_0,
235                 .chipset_name   = "Apollo Pro 133",
236         },
237
238         {
239                 .device_id      = PCI_DEVICE_ID_VIA_8371_0,
240                 .chipset_name   = "KX133",
241         },
242
243         /* VT8633 */
244         {
245                 .device_id      = PCI_DEVICE_ID_VIA_8633_0,
246                 .chipset_name   = "Pro 266",
247         },
248
249         {
250                 .device_id      = PCI_DEVICE_ID_VIA_XN266,
251                 .chipset_name   = "Apollo Pro266",
252         },
253
254         /* VT8361 */
255         {
256                 .device_id      = PCI_DEVICE_ID_VIA_8361,
257                 .chipset_name   = "KLE133",
258         },
259
260         /* VT8365 / VT8362 */
261         {
262                 .device_id      = PCI_DEVICE_ID_VIA_8363_0,
263                 .chipset_name   = "Twister-K/KT133x/KM133",
264         },
265
266         /* VT8753A */
267         {
268                 .device_id      = PCI_DEVICE_ID_VIA_8753_0,
269                 .chipset_name   = "P4X266",
270         },
271
272         /* VT8366 */
273         {
274                 .device_id      = PCI_DEVICE_ID_VIA_8367_0,
275                 .chipset_name   = "KT266/KY266x/KT333",
276         },
277
278         /* VT8633 (for CuMine/ Celeron) */
279         {
280                 .device_id      = PCI_DEVICE_ID_VIA_8653_0,
281                 .chipset_name   = "Pro266T",
282         },
283
284         /* KM266 / PM266 */
285         {
286                 .device_id      = PCI_DEVICE_ID_VIA_XM266,
287                 .chipset_name   = "PM266/KM266",
288         },
289
290         /* CLE266 */
291         {
292                 .device_id      = PCI_DEVICE_ID_VIA_862X_0,
293                 .chipset_name   = "CLE266",
294         },
295
296         {
297                 .device_id      = PCI_DEVICE_ID_VIA_8377_0,
298                 .chipset_name   = "KT400/KT400A/KT600",
299         },
300
301         /* VT8604 / VT8605 / VT8603
302          * (Apollo Pro133A chipset with S3 Savage4) */
303         {
304                 .device_id      = PCI_DEVICE_ID_VIA_8605_0,
305                 .chipset_name   = "ProSavage PM133/PL133/PN133"
306         },
307
308         /* P4M266x/P4N266 */
309         {
310                 .device_id      = PCI_DEVICE_ID_VIA_8703_51_0,
311                 .chipset_name   = "P4M266x/P4N266",
312         },
313
314         /* VT8754 */
315         {
316                 .device_id      = PCI_DEVICE_ID_VIA_8754C_0,
317                 .chipset_name   = "PT800",
318         },
319
320         /* P4X600 */
321         {
322                 .device_id      = PCI_DEVICE_ID_VIA_8763_0,
323                 .chipset_name   = "P4X600"
324         },
325
326         /* KM400 */
327         {
328                 .device_id      = PCI_DEVICE_ID_VIA_8378_0,
329                 .chipset_name   = "KM400/KM400A",
330         },
331
332         /* PT880 */
333         {
334                 .device_id      = PCI_DEVICE_ID_VIA_PT880,
335                 .chipset_name   = "PT880",
336         },
337
338         /* PT890 */
339         {
340                 .device_id      = PCI_DEVICE_ID_VIA_8783_0,
341                 .chipset_name   = "PT890",
342         },
343
344         /* PM800/PN800/PM880/PN880 */
345         {
346                 .device_id      = PCI_DEVICE_ID_VIA_PX8X0_0,
347                 .chipset_name   = "PM800/PN800/PM880/PN880",
348         },
349
350         { }, /* dummy final entry, always present */
351 };
352
353
354 /*
355  * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
356  * with the same standards version as the graphics card.
357  */
358 static void check_via_agp3 (struct agp_bridge_data *bridge)
359 {
360         u8 reg;
361
362         pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
363         /* Check AGP 2.0 compatibility mode. */
364         if ((reg & (1<<1))==0)
365                 bridge->driver = &via_agp3_driver;
366 }
367
368
369 static int __devinit agp_via_probe(struct pci_dev *pdev,
370                                    const struct pci_device_id *ent)
371 {
372         struct agp_device_ids *devs = via_agp_device_ids;
373         struct agp_bridge_data *bridge;
374         int j = 0;
375         u8 cap_ptr;
376
377         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
378         if (!cap_ptr)
379                 return -ENODEV;
380
381         /* probe for known chipsets */
382         for (j = 0; devs[j].chipset_name; j++) {
383                 if (pdev->device == devs[j].device_id) {
384                         printk (KERN_INFO PFX "Detected VIA %s chipset\n",
385                                         devs[j].chipset_name);
386                         goto found;
387                 }
388         }
389
390         printk(KERN_ERR PFX "Unsupported VIA chipset (device id: %04x)\n",
391                     pdev->device);
392         return -ENODEV;
393
394 found:
395         bridge = agp_alloc_bridge();
396         if (!bridge)
397                 return -ENOMEM;
398
399         bridge->dev = pdev;
400         bridge->capndx = cap_ptr;
401         bridge->driver = &via_driver;
402
403         /*
404          * Garg, there are KT400s with KT266 IDs.
405          */
406         if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
407                 /* Is there a KT400 subsystem ? */
408                 if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
409                         printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
410                         check_via_agp3(bridge);
411                 }
412         }
413
414         /* If this is an AGP3 bridge, check which mode its in and adjust. */
415         get_agp_version(bridge);
416         if (bridge->major_version >= 3)
417                 check_via_agp3(bridge);
418
419         /* Fill in the mode register */
420         pci_read_config_dword(pdev,
421                         bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
422
423         pci_set_drvdata(pdev, bridge);
424         return agp_add_bridge(bridge);
425 }
426
427 static void __devexit agp_via_remove(struct pci_dev *pdev)
428 {
429         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
430
431         agp_remove_bridge(bridge);
432         agp_put_bridge(bridge);
433 }
434
435 static struct pci_device_id agp_via_pci_table[] = {
436         {
437         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
438         .class_mask     = ~0,
439         .vendor         = PCI_VENDOR_ID_VIA,
440         .device         = PCI_ANY_ID,
441         .subvendor      = PCI_ANY_ID,
442         .subdevice      = PCI_ANY_ID,
443         },
444         { }
445 };
446
447 MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
448
449
450 static struct pci_driver agp_via_pci_driver = {
451         .name           = "agpgart-via",
452         .id_table       = agp_via_pci_table,
453         .probe          = agp_via_probe,
454         .remove         = agp_via_remove,
455 };
456
457
458 static int __init agp_via_init(void)
459 {
460         return pci_module_init(&agp_via_pci_driver);
461 }
462
463 static void __exit agp_via_cleanup(void)
464 {
465         pci_unregister_driver(&agp_via_pci_driver);
466 }
467
468 module_init(agp_via_init);
469 module_exit(agp_via_cleanup);
470
471 MODULE_LICENSE("GPL and additional rights");
472 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");