1 /* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
35 typedef struct drm_i830_buf_priv {
41 } drm_i830_buf_priv_t;
43 typedef struct _drm_i830_ring_buffer{
52 } drm_i830_ring_buffer_t;
54 typedef struct drm_i830_private {
58 drm_i830_sarea_t *sarea_priv;
59 drm_i830_ring_buffer_t ring;
61 void * hw_status_page;
62 unsigned long counter;
64 dma_addr_t dma_status_page;
66 drm_buf_t *mmap_buffer;
68 u32 front_di1, back_di1, zi1;
85 wait_queue_head_t irq_queue;
86 atomic_t irq_received;
89 int use_mi_batchbuffer_start;
94 extern int i830_dma_schedule(drm_device_t *dev, int locked);
95 extern int i830_getbuf(struct inode *inode, struct file *filp,
96 unsigned int cmd, unsigned long arg);
97 extern int i830_dma_init(struct inode *inode, struct file *filp,
98 unsigned int cmd, unsigned long arg);
99 extern int i830_dma_cleanup(drm_device_t *dev);
100 extern int i830_flush_ioctl(struct inode *inode, struct file *filp,
101 unsigned int cmd, unsigned long arg);
102 extern void i830_reclaim_buffers(struct file *filp);
103 extern int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
105 extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
106 extern int i830_copybuf(struct inode *inode, struct file *filp,
107 unsigned int cmd, unsigned long arg);
108 extern int i830_docopy(struct inode *inode, struct file *filp,
109 unsigned int cmd, unsigned long arg);
111 extern void i830_dma_quiescent(drm_device_t *dev);
113 extern int i830_dma_vertex(struct inode *inode, struct file *filp,
114 unsigned int cmd, unsigned long arg);
116 extern int i830_swap_bufs(struct inode *inode, struct file *filp,
117 unsigned int cmd, unsigned long arg);
119 extern int i830_clear_bufs(struct inode *inode, struct file *filp,
120 unsigned int cmd, unsigned long arg);
122 extern int i830_flip_bufs(struct inode *inode, struct file *filp,
123 unsigned int cmd, unsigned long arg);
125 extern int i830_getparam( struct inode *inode, struct file *filp,
126 unsigned int cmd, unsigned long arg );
128 extern int i830_setparam( struct inode *inode, struct file *filp,
129 unsigned int cmd, unsigned long arg );
132 extern int i830_irq_emit( struct inode *inode, struct file *filp,
133 unsigned int cmd, unsigned long arg );
134 extern int i830_irq_wait( struct inode *inode, struct file *filp,
135 unsigned int cmd, unsigned long arg );
136 extern int i830_wait_irq(drm_device_t *dev, int irq_nr);
137 extern int i830_emit_irq(drm_device_t *dev);
139 extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS );
140 extern void i830_driver_irq_preinstall( drm_device_t *dev );
141 extern void i830_driver_irq_postinstall( drm_device_t *dev );
142 extern void i830_driver_irq_uninstall( drm_device_t *dev );
144 #define I830_BASE(reg) ((unsigned long) \
145 dev_priv->mmio_map->handle)
146 #define I830_ADDR(reg) (I830_BASE(reg) + reg)
147 #define I830_DEREF(reg) *(__volatile__ unsigned int *)I830_ADDR(reg)
148 #define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg))
149 #define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg))
150 #define I830_DEREF16(reg) *(__volatile__ u16 *)I830_ADDR(reg)
151 #define I830_READ16(reg) I830_DEREF16(reg)
152 #define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0)
156 #define I830_VERBOSE 0
158 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
161 #define BEGIN_LP_RING(n) do { \
163 printk("BEGIN_LP_RING(%d) in %s\n", \
165 if (dev_priv->ring.space < n*4) \
166 i830_wait_ring(dev, n*4, __FUNCTION__); \
168 outring = dev_priv->ring.tail; \
169 ringmask = dev_priv->ring.tail_mask; \
170 virt = dev_priv->ring.virtual_start; \
174 #define OUT_RING(n) do { \
175 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
176 *(volatile unsigned int *)(virt + outring) = n; \
179 outring &= ringmask; \
182 #define ADVANCE_LP_RING() do { \
183 if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \
184 dev_priv->ring.tail = outring; \
185 dev_priv->ring.space -= outcount * 4; \
186 I830_WRITE(LP_RING + RING_TAIL, outring); \
189 extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
192 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
193 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
194 #define CMD_REPORT_HEAD (7<<23)
195 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
196 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
198 #define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
199 #define LOAD_TEXTURE_MAP0 (1<<11)
201 #define INST_PARSER_CLIENT 0x00000000
202 #define INST_OP_FLUSH 0x02000000
203 #define INST_FLUSH_MAP_CACHE 0x00000001
206 #define BB1_START_ADDR_MASK (~0x7)
207 #define BB1_PROTECTED (1<<0)
208 #define BB1_UNPROTECTED (0<<0)
209 #define BB2_END_ADDR_MASK (~0x7)
211 #define I830REG_HWSTAM 0x02098
212 #define I830REG_INT_IDENTITY_R 0x020a4
213 #define I830REG_INT_MASK_R 0x020a8
214 #define I830REG_INT_ENABLE_R 0x020a0
216 #define I830_IRQ_RESERVED ((1<<13)|(3<<2))
219 #define LP_RING 0x2030
220 #define HP_RING 0x2040
221 #define RING_TAIL 0x00
222 #define TAIL_ADDR 0x001FFFF8
223 #define RING_HEAD 0x04
224 #define HEAD_WRAP_COUNT 0xFFE00000
225 #define HEAD_WRAP_ONE 0x00200000
226 #define HEAD_ADDR 0x001FFFFC
227 #define RING_START 0x08
228 #define START_ADDR 0x0xFFFFF000
229 #define RING_LEN 0x0C
230 #define RING_NR_PAGES 0x001FF000
231 #define RING_REPORT_MASK 0x00000006
232 #define RING_REPORT_64K 0x00000002
233 #define RING_REPORT_128K 0x00000004
234 #define RING_NO_REPORT 0x00000000
235 #define RING_VALID_MASK 0x00000001
236 #define RING_VALID 0x00000001
237 #define RING_INVALID 0x00000000
239 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
240 #define SC_UPDATE_SCISSOR (0x1<<1)
241 #define SC_ENABLE_MASK (0x1<<0)
242 #define SC_ENABLE (0x1<<0)
244 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
245 #define SCI_YMIN_MASK (0xffff<<16)
246 #define SCI_XMIN_MASK (0xffff<<0)
247 #define SCI_YMAX_MASK (0xffff<<16)
248 #define SCI_XMAX_MASK (0xffff<<0)
250 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
251 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
252 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
253 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
254 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
255 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
256 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
257 #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
259 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
261 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
262 #define ASYNC_FLIP (1<<22)
264 #define CMD_3D (0x3<<29)
265 #define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16))
266 #define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
268 #define BR00_BITBLT_CLIENT 0x40000000
269 #define BR00_OP_COLOR_BLT 0x10000000
270 #define BR00_OP_SRC_COPY_BLT 0x10C00000
271 #define BR13_SOLID_PATTERN 0x80000000
273 #define BUF_3D_ID_COLOR_BACK (0x3<<24)
274 #define BUF_3D_ID_DEPTH (0x7<<24)
275 #define BUF_3D_USE_FENCE (1<<23)
276 #define BUF_3D_PITCH(x) (((x)/4)<<2)
278 #define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
279 #define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
280 #define MAP_PALETTE_BOTH (1<<11)
282 #define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4)
283 #define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
284 #define XY_COLOR_BLT_WRITE_RGB (1<<20)
286 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
287 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
288 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
290 #define MI_BATCH_BUFFER ((0x30<<23)|1)
291 #define MI_BATCH_BUFFER_START (0x31<<23)
292 #define MI_BATCH_BUFFER_END (0xA<<23)
293 #define MI_BATCH_NON_SECURE (1)
295 #define MI_WAIT_FOR_EVENT ((0x3<<23))
296 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
297 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
299 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))