4 /* Please note that modifications to all structs defined here are
5 * subject to backwards-compatibility constraints.
10 /* Each region is a minimum of 16k, and there are at most 255 of them.
12 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
13 * of chars for next/prev indices */
14 #define I915_LOG_MIN_TEX_REGION_SIZE 14
16 typedef struct _drm_i915_init {
19 I915_CLEANUP_DMA = 0x02,
20 I915_RESUME_DMA = 0x03
22 unsigned int mmio_offset;
23 int sarea_priv_offset;
24 unsigned int ring_start;
25 unsigned int ring_end;
26 unsigned int ring_size;
27 unsigned int front_offset;
28 unsigned int back_offset;
29 unsigned int depth_offset;
33 unsigned int pitch_bits;
34 unsigned int back_pitch;
35 unsigned int depth_pitch;
40 typedef struct _drm_i915_sarea {
41 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
42 int last_upload; /* last time texture was uploaded */
43 int last_enqueue; /* last time a buffer was enqueued */
44 int last_dispatch; /* age of the most recently dispatched buffer */
45 int ctxOwner; /* last context to upload state */
47 int pf_enabled; /* is pageflipping allowed? */
49 int pf_current_page; /* which buffer is being displayed? */
50 int perf_boxes; /* performance boxes to be displayed */
53 /* Flags for perf_boxes
55 #define I915_BOX_RING_EMPTY 0x1
56 #define I915_BOX_FLIP 0x2
57 #define I915_BOX_WAIT 0x4
58 #define I915_BOX_TEXTURE_LOAD 0x8
59 #define I915_BOX_LOST_CONTEXT 0x10
61 /* I915 specific ioctls
62 * The device specific ioctl range is 0x40 to 0x79.
64 #define DRM_IOCTL_I915_INIT DRM_IOW( 0x40, drm_i915_init_t)
65 #define DRM_IOCTL_I915_FLUSH DRM_IO ( 0x41)
66 #define DRM_IOCTL_I915_FLIP DRM_IO ( 0x42)
67 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( 0x43, drm_i915_batchbuffer_t)
68 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(0x44, drm_i915_irq_emit_t)
69 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( 0x45, drm_i915_irq_wait_t)
70 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(0x46, drm_i915_getparam_t)
71 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( 0x47, drm_i915_setparam_t)
72 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(0x48, drm_i915_mem_alloc_t)
73 #define DRM_IOCTL_I915_FREE DRM_IOW( 0x49, drm_i915_mem_free_t)
74 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( 0x4a, drm_i915_mem_init_heap_t)
75 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( 0x4b, drm_i915_cmdbuffer_t)
77 /* Allow drivers to submit batchbuffers directly to hardware, relying
78 * on the security mechanisms provided by hardware.
80 typedef struct _drm_i915_batchbuffer {
81 int start; /* agp offset */
82 int used; /* nr bytes in use */
83 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
84 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
85 int num_cliprects; /* mulitpass with multiple cliprects? */
86 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
87 } drm_i915_batchbuffer_t;
89 /* As above, but pass a pointer to userspace buffer which can be
90 * validated by the kernel prior to sending to hardware.
92 typedef struct _drm_i915_cmdbuffer {
93 char __user *buf; /* pointer to userspace command buffer */
94 int sz; /* nr bytes in buf */
95 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
96 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
97 int num_cliprects; /* mulitpass with multiple cliprects? */
98 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
99 } drm_i915_cmdbuffer_t;
101 /* Userspace can request & wait on irq's:
103 typedef struct drm_i915_irq_emit {
105 } drm_i915_irq_emit_t;
107 typedef struct drm_i915_irq_wait {
109 } drm_i915_irq_wait_t;
111 /* Ioctl to query kernel params:
113 #define I915_PARAM_IRQ_ACTIVE 1
114 #define I915_PARAM_ALLOW_BATCHBUFFER 2
116 typedef struct drm_i915_getparam {
119 } drm_i915_getparam_t;
121 /* Ioctl to set kernel params:
123 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
124 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
125 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
127 typedef struct drm_i915_setparam {
130 } drm_i915_setparam_t;
132 /* A memory manager for regions of shared memory:
134 #define I915_MEM_REGION_AGP 1
136 typedef struct drm_i915_mem_alloc {
140 int __user *region_offset; /* offset from start of fb or agp */
141 } drm_i915_mem_alloc_t;
143 typedef struct drm_i915_mem_free {
146 } drm_i915_mem_free_t;
148 typedef struct drm_i915_mem_init_heap {
152 } drm_i915_mem_init_heap_t;
154 #endif /* _I915_DRM_H_ */