drivers/char/drm/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /**************************************************************************
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  **************************************************************************/
   9
  10 #ifndef _I915_DRV_H_
  11 #define _I915_DRV_H_
  12
  13 typedef struct _drm_i915_ring_buffer {
  14         int tail_mask;
  15         unsigned long Start;
  16         unsigned long End;
  17         unsigned long Size;
  18         u8 *virtual_start;
  19         int head;
  20         int tail;
  21         int space;
  22         drm_local_map_t map;
  23 } drm_i915_ring_buffer_t;
  24
  25 struct mem_block {
  26         struct mem_block *next;
  27         struct mem_block *prev;
  28         int start;
  29         int size;
  30         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  31 };
  32
  33 typedef struct drm_i915_private {
  34         drm_local_map_t *sarea;
  35         drm_local_map_t *mmio_map;
  36
  37         drm_i915_sarea_t *sarea_priv;
  38         drm_i915_ring_buffer_t ring;
  39
  40         void *hw_status_page;
  41         unsigned long counter;
  42         dma_addr_t dma_status_page;
  43
  44         int back_offset;
  45         int front_offset;
  46         int current_page;
  47         int page_flipping;
  48         int use_mi_batchbuffer_start;
  49
  50         wait_queue_head_t irq_queue;
  51         atomic_t irq_received;
  52         atomic_t irq_emitted;
  53
  54         int tex_lru_log_granularity;
  55         int allow_batchbuffer;
  56         struct mem_block *agp_heap;
  57 } drm_i915_private_t;
  58
  59                                 /* i915_dma.c */
  60 extern int i915_dma_init(DRM_IOCTL_ARGS);
  61 extern int i915_dma_cleanup(drm_device_t * dev);
  62 extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
  63 extern int i915_batchbuffer(DRM_IOCTL_ARGS);
  64 extern int i915_flip_bufs(DRM_IOCTL_ARGS);
  65 extern int i915_getparam(DRM_IOCTL_ARGS);
  66 extern int i915_setparam(DRM_IOCTL_ARGS);
  67 extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
  68 extern void i915_kernel_lost_context(drm_device_t * dev);
  69
  70 /* i915_irq.c */
  71 extern int i915_irq_emit(DRM_IOCTL_ARGS);
  72 extern int i915_irq_wait(DRM_IOCTL_ARGS);
  73 extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
  74 extern int i915_emit_irq(drm_device_t * dev);
  75
  76 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  77 extern void i915_driver_irq_preinstall(drm_device_t *dev);
  78 extern void i915_driver_irq_postinstall(drm_device_t *dev);
  79 extern void i915_driver_irq_uninstall(drm_device_t *dev);
  80
  81 /* i915_mem.c */
  82 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
  83 extern int i915_mem_free(DRM_IOCTL_ARGS);
  84 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
  85 extern void i915_mem_takedown(struct mem_block **heap);
  86 extern void i915_mem_release(drm_device_t * dev,
  87                              DRMFILE filp, struct mem_block *heap);
  88
  89 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
  90 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
  91 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, reg)
  92 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, reg, val)
  93
  94 #define I915_VERBOSE 0
  95
  96 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
  97                         volatile char *virt;
  98
  99 #define BEGIN_LP_RING(n) do {                           \
 100         if (I915_VERBOSE)                               \
 101                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 102                           n, __FUNCTION__);             \
 103         if (dev_priv->ring.space < n*4)                 \
 104                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 105         outcount = 0;                                   \
 106         outring = dev_priv->ring.tail;                  \
 107         ringmask = dev_priv->ring.tail_mask;            \
 108         virt = dev_priv->ring.virtual_start;            \
 109 } while (0)
 110
 111 #define OUT_RING(n) do {                                        \
 112         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 113         *(volatile unsigned int *)(virt + outring) = n;         \
 114         outcount++;                                             \
 115         outring += 4;                                           \
 116         outring &= ringmask;                                    \
 117 } while (0)
 118
 119 #define ADVANCE_LP_RING() do {                                          \
 120         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 121         dev_priv->ring.tail = outring;                                  \
 122         dev_priv->ring.space -= outcount * 4;                           \
 123         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 124 } while(0)
 125
 126 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 127
 128 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 129 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 130 #define CMD_REPORT_HEAD                 (7<<23)
 131 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 132 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 133
 134 #define INST_PARSER_CLIENT   0x00000000
 135 #define INST_OP_FLUSH        0x02000000
 136 #define INST_FLUSH_MAP_CACHE 0x00000001
 137
 138 #define BB1_START_ADDR_MASK   (~0x7)
 139 #define BB1_PROTECTED         (1<<0)
 140 #define BB1_UNPROTECTED       (0<<0)
 141 #define BB2_END_ADDR_MASK     (~0x7)
 142
 143 #define I915REG_HWSTAM          0x02098
 144 #define I915REG_INT_IDENTITY_R  0x020a4
 145 #define I915REG_INT_MASK_R      0x020a8
 146 #define I915REG_INT_ENABLE_R    0x020a0
 147
 148 #define SRX_INDEX               0x3c4
 149 #define SRX_DATA                0x3c5
 150 #define SR01                    1
 151 #define SR01_SCREEN_OFF         (1<<5)
 152
 153 #define PPCR                    0x61204
 154 #define PPCR_ON                 (1<<0)
 155
 156 #define ADPA                    0x61100
 157 #define ADPA_DPMS_MASK          (~(3<<10))
 158 #define ADPA_DPMS_ON            (0<<10)
 159 #define ADPA_DPMS_SUSPEND       (1<<10)
 160 #define ADPA_DPMS_STANDBY       (2<<10)
 161 #define ADPA_DPMS_OFF           (3<<10)
 162
 163 #define NOPID                   0x2094
 164 #define LP_RING                 0x2030
 165 #define HP_RING                 0x2040
 166 #define RING_TAIL               0x00
 167 #define TAIL_ADDR               0x001FFFF8
 168 #define RING_HEAD               0x04
 169 #define HEAD_WRAP_COUNT         0xFFE00000
 170 #define HEAD_WRAP_ONE           0x00200000
 171 #define HEAD_ADDR               0x001FFFFC
 172 #define RING_START              0x08
 173 #define START_ADDR              0x0xFFFFF000
 174 #define RING_LEN                0x0C
 175 #define RING_NR_PAGES           0x001FF000
 176 #define RING_REPORT_MASK        0x00000006
 177 #define RING_REPORT_64K         0x00000002
 178 #define RING_REPORT_128K        0x00000004
 179 #define RING_NO_REPORT          0x00000000
 180 #define RING_VALID_MASK         0x00000001
 181 #define RING_VALID              0x00000001
 182 #define RING_INVALID            0x00000000
 183
 184 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 185 #define SC_UPDATE_SCISSOR       (0x1<<1)
 186 #define SC_ENABLE_MASK          (0x1<<0)
 187 #define SC_ENABLE               (0x1<<0)
 188
 189 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 190 #define SCI_YMIN_MASK      (0xffff<<16)
 191 #define SCI_XMIN_MASK      (0xffff<<0)
 192 #define SCI_YMAX_MASK      (0xffff<<16)
 193 #define SCI_XMAX_MASK      (0xffff<<0)
 194
 195 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 196 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 197 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 198 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 199 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 200 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 201 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 202
 203 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 204 #define MI_BATCH_BUFFER_START   (0x31<<23)
 205 #define MI_BATCH_BUFFER_END     (0xA<<23)
 206 #define MI_BATCH_NON_SECURE     (1)
 207
 208 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 209 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 210 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 211
 212 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 213
 214 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 215 #define ASYNC_FLIP                (1<<22)
 216
 217 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 218
 219 #endif