1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
39 #define DRIVER_NAME "mga"
40 #define DRIVER_DESC "Matrox G200/G400"
41 #define DRIVER_DATE "20021029"
43 #define DRIVER_MAJOR 3
44 #define DRIVER_MINOR 1
45 #define DRIVER_PATCHLEVEL 0
47 typedef struct drm_mga_primary_buffer {
54 volatile long wrapped;
62 } drm_mga_primary_buffer_t;
64 typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev;
72 drm_mga_freelist_t *list_entry;
77 typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv;
81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail;
84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
94 unsigned int front_offset;
95 unsigned int front_pitch;
96 unsigned int back_offset;
97 unsigned int back_pitch;
99 unsigned int depth_cpp;
100 unsigned int depth_offset;
101 unsigned int depth_pitch;
103 unsigned int texture_offset;
104 unsigned int texture_size;
106 drm_local_map_t *sarea;
107 drm_local_map_t *mmio;
108 drm_local_map_t *status;
109 drm_local_map_t *warp;
110 drm_local_map_t *primary;
111 drm_local_map_t *buffers;
112 drm_local_map_t *agp_textures;
116 extern int mga_dma_init( DRM_IOCTL_ARGS );
117 extern int mga_dma_flush( DRM_IOCTL_ARGS );
118 extern int mga_dma_reset( DRM_IOCTL_ARGS );
119 extern int mga_dma_buffers( DRM_IOCTL_ARGS );
120 extern void mga_driver_pretakedown(drm_device_t *dev);
121 extern int mga_driver_dma_quiescent(drm_device_t *dev);
123 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
124 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
125 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
126 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
127 extern int mga_do_cleanup_dma( drm_device_t *dev );
129 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
130 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
131 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
133 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
136 extern int mga_dma_clear( DRM_IOCTL_ARGS );
137 extern int mga_dma_swap( DRM_IOCTL_ARGS );
138 extern int mga_dma_vertex( DRM_IOCTL_ARGS );
139 extern int mga_dma_indices( DRM_IOCTL_ARGS );
140 extern int mga_dma_iload( DRM_IOCTL_ARGS );
141 extern int mga_dma_blit( DRM_IOCTL_ARGS );
142 extern int mga_getparam( DRM_IOCTL_ARGS );
145 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
146 extern int mga_warp_init( drm_mga_private_t *dev_priv );
148 extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
149 extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
150 extern void mga_driver_irq_preinstall( drm_device_t *dev );
151 extern void mga_driver_irq_postinstall( drm_device_t *dev );
152 extern void mga_driver_irq_uninstall( drm_device_t *dev );
154 #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
156 #if defined(__linux__) && defined(__alpha__)
157 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
158 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
160 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
161 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
163 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
164 #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
165 #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
166 #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
168 static inline u32 _MGA_READ(u32 *addr)
171 return *(volatile u32 *)addr;
174 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
175 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
176 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
177 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
180 #define DWGREG0 0x1c00
181 #define DWGREG0_END 0x1dff
182 #define DWGREG1 0x2c00
183 #define DWGREG1_END 0x2dff
185 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
186 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
187 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
188 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
192 /* ================================================================
196 #define MGA_EMIT_STATE( dev_priv, dirty ) \
198 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
199 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
200 mga_g400_emit_state( dev_priv ); \
202 mga_g200_emit_state( dev_priv ); \
207 #define WRAP_TEST_WITH_RETURN( dev_priv ) \
209 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
210 if ( mga_is_idle( dev_priv ) ) { \
211 mga_do_dma_wrap_end( dev_priv ); \
212 } else if ( dev_priv->prim.space < \
213 dev_priv->prim.high_mark ) { \
214 if ( MGA_DMA_DEBUG ) \
215 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
216 return DRM_ERR(EBUSY); \
221 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \
223 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
224 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
225 if ( MGA_DMA_DEBUG ) \
226 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
227 return DRM_ERR(EBUSY); \
229 mga_do_dma_wrap_end( dev_priv ); \
234 /* ================================================================
235 * Primary DMA command stream
238 #define MGA_VERBOSE 0
240 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
242 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
244 #define BEGIN_DMA( n ) \
246 if ( MGA_VERBOSE ) { \
247 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
248 (n), __FUNCTION__ ); \
249 DRM_INFO( " space=0x%x req=0x%Zx\n", \
250 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
252 prim = dev_priv->prim.start; \
253 write = dev_priv->prim.tail; \
256 #define BEGIN_DMA_WRAP() \
258 if ( MGA_VERBOSE ) { \
259 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
260 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
262 prim = dev_priv->prim.start; \
263 write = dev_priv->prim.tail; \
266 #define ADVANCE_DMA() \
268 dev_priv->prim.tail = write; \
269 if ( MGA_VERBOSE ) { \
270 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
271 write, dev_priv->prim.space ); \
275 #define FLUSH_DMA() \
278 DRM_INFO( "%s:\n", __FUNCTION__ ); \
279 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
280 dev_priv->prim.tail, \
281 MGA_READ( MGA_PRIMADDRESS ) - \
282 dev_priv->primary->offset ); \
284 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
285 if ( dev_priv->prim.space < \
286 dev_priv->prim.high_mark ) { \
287 mga_do_dma_wrap_start( dev_priv ); \
289 mga_do_dma_flush( dev_priv ); \
294 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
296 #define DMA_WRITE( offset, val ) \
298 if ( MGA_VERBOSE ) { \
299 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
300 (u32)(val), write + (offset) * sizeof(u32) ); \
302 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
305 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
307 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
308 (DMAREG( reg1 ) << 8) | \
309 (DMAREG( reg2 ) << 16) | \
310 (DMAREG( reg3 ) << 24)) ); \
311 DMA_WRITE( 1, val0 ); \
312 DMA_WRITE( 2, val1 ); \
313 DMA_WRITE( 3, val2 ); \
314 DMA_WRITE( 4, val3 ); \
315 write += DMA_BLOCK_SIZE; \
319 /* Buffer aging via primary DMA stream head pointer.
322 #define SET_AGE( age, h, w ) \
328 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
329 ( (age)->wrap == w && \
332 #define AGE_BUFFER( buf_priv ) \
334 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
335 if ( (buf_priv)->dispatched ) { \
336 entry->age.head = (dev_priv->prim.tail + \
337 dev_priv->primary->offset); \
338 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
340 entry->age.head = 0; \
341 entry->age.wrap = 0; \
346 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
349 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
352 #define MGA_DMA_DEBUG 0
356 /* A reduced set of the mga registers.
358 #define MGA_CRTC_INDEX 0x1fd4
359 #define MGA_CRTC_DATA 0x1fd5
362 #define MGA_VINTCLR (1 << 4)
363 #define MGA_VINTEN (1 << 5)
365 #define MGA_ALPHACTRL 0x2c7c
366 #define MGA_AR0 0x1c60
367 #define MGA_AR1 0x1c64
368 #define MGA_AR2 0x1c68
369 #define MGA_AR3 0x1c6c
370 #define MGA_AR4 0x1c70
371 #define MGA_AR5 0x1c74
372 #define MGA_AR6 0x1c78
374 #define MGA_CXBNDRY 0x1c80
375 #define MGA_CXLEFT 0x1ca0
376 #define MGA_CXRIGHT 0x1ca4
378 #define MGA_DMAPAD 0x1c54
379 #define MGA_DSTORG 0x2cb8
380 #define MGA_DWGCTL 0x1c00
381 # define MGA_OPCOD_MASK (15 << 0)
382 # define MGA_OPCOD_TRAP (4 << 0)
383 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
384 # define MGA_OPCOD_BITBLT (8 << 0)
385 # define MGA_OPCOD_ILOAD (9 << 0)
386 # define MGA_ATYPE_MASK (7 << 4)
387 # define MGA_ATYPE_RPL (0 << 4)
388 # define MGA_ATYPE_RSTR (1 << 4)
389 # define MGA_ATYPE_ZI (3 << 4)
390 # define MGA_ATYPE_BLK (4 << 4)
391 # define MGA_ATYPE_I (7 << 4)
392 # define MGA_LINEAR (1 << 7)
393 # define MGA_ZMODE_MASK (7 << 8)
394 # define MGA_ZMODE_NOZCMP (0 << 8)
395 # define MGA_ZMODE_ZE (2 << 8)
396 # define MGA_ZMODE_ZNE (3 << 8)
397 # define MGA_ZMODE_ZLT (4 << 8)
398 # define MGA_ZMODE_ZLTE (5 << 8)
399 # define MGA_ZMODE_ZGT (6 << 8)
400 # define MGA_ZMODE_ZGTE (7 << 8)
401 # define MGA_SOLID (1 << 11)
402 # define MGA_ARZERO (1 << 12)
403 # define MGA_SGNZERO (1 << 13)
404 # define MGA_SHIFTZERO (1 << 14)
405 # define MGA_BOP_MASK (15 << 16)
406 # define MGA_BOP_ZERO (0 << 16)
407 # define MGA_BOP_DST (10 << 16)
408 # define MGA_BOP_SRC (12 << 16)
409 # define MGA_BOP_ONE (15 << 16)
410 # define MGA_TRANS_SHIFT 20
411 # define MGA_TRANS_MASK (15 << 20)
412 # define MGA_BLTMOD_MASK (15 << 25)
413 # define MGA_BLTMOD_BMONOLEF (0 << 25)
414 # define MGA_BLTMOD_BMONOWF (4 << 25)
415 # define MGA_BLTMOD_PLAN (1 << 25)
416 # define MGA_BLTMOD_BFCOL (2 << 25)
417 # define MGA_BLTMOD_BU32BGR (3 << 25)
418 # define MGA_BLTMOD_BU32RGB (7 << 25)
419 # define MGA_BLTMOD_BU24BGR (11 << 25)
420 # define MGA_BLTMOD_BU24RGB (15 << 25)
421 # define MGA_PATTERN (1 << 29)
422 # define MGA_TRANSC (1 << 30)
423 # define MGA_CLIPDIS (1 << 31)
424 #define MGA_DWGSYNC 0x2c4c
426 #define MGA_FCOL 0x1c24
427 #define MGA_FIFOSTATUS 0x1e10
428 #define MGA_FOGCOL 0x1cf4
429 #define MGA_FXBNDRY 0x1c84
430 #define MGA_FXLEFT 0x1ca8
431 #define MGA_FXRIGHT 0x1cac
433 #define MGA_ICLEAR 0x1e18
434 # define MGA_SOFTRAPICLR (1 << 0)
435 # define MGA_VLINEICLR (1 << 5)
436 #define MGA_IEN 0x1e1c
437 # define MGA_SOFTRAPIEN (1 << 0)
438 # define MGA_VLINEIEN (1 << 5)
440 #define MGA_LEN 0x1c5c
442 #define MGA_MACCESS 0x1c04
444 #define MGA_PITCH 0x1c8c
445 #define MGA_PLNWT 0x1c1c
446 #define MGA_PRIMADDRESS 0x1e58
447 # define MGA_DMA_GENERAL (0 << 0)
448 # define MGA_DMA_BLIT (1 << 0)
449 # define MGA_DMA_VECTOR (2 << 0)
450 # define MGA_DMA_VERTEX (3 << 0)
451 #define MGA_PRIMEND 0x1e5c
452 # define MGA_PRIMNOSTART (1 << 0)
453 # define MGA_PAGPXFER (1 << 1)
454 #define MGA_PRIMPTR 0x1e50
455 # define MGA_PRIMPTREN0 (1 << 0)
456 # define MGA_PRIMPTREN1 (1 << 1)
458 #define MGA_RST 0x1e40
459 # define MGA_SOFTRESET (1 << 0)
460 # define MGA_SOFTEXTRST (1 << 1)
462 #define MGA_SECADDRESS 0x2c40
463 #define MGA_SECEND 0x2c44
464 #define MGA_SETUPADDRESS 0x2cd0
465 #define MGA_SETUPEND 0x2cd4
466 #define MGA_SGN 0x1c58
467 #define MGA_SOFTRAP 0x2c48
468 #define MGA_SRCORG 0x2cb4
469 # define MGA_SRMMAP_MASK (1 << 0)
470 # define MGA_SRCMAP_FB (0 << 0)
471 # define MGA_SRCMAP_SYSMEM (1 << 0)
472 # define MGA_SRCACC_MASK (1 << 1)
473 # define MGA_SRCACC_PCI (0 << 1)
474 # define MGA_SRCACC_AGP (1 << 1)
475 #define MGA_STATUS 0x1e14
476 # define MGA_SOFTRAPEN (1 << 0)
477 # define MGA_VSYNCPEN (1 << 4)
478 # define MGA_VLINEPEN (1 << 5)
479 # define MGA_DWGENGSTS (1 << 16)
480 # define MGA_ENDPRDMASTS (1 << 17)
481 #define MGA_STENCIL 0x2cc8
482 #define MGA_STENCILCTL 0x2ccc
484 #define MGA_TDUALSTAGE0 0x2cf8
485 #define MGA_TDUALSTAGE1 0x2cfc
486 #define MGA_TEXBORDERCOL 0x2c5c
487 #define MGA_TEXCTL 0x2c30
488 #define MGA_TEXCTL2 0x2c3c
489 # define MGA_DUALTEX (1 << 7)
490 # define MGA_G400_TC2_MAGIC (1 << 15)
491 # define MGA_MAP1_ENABLE (1 << 31)
492 #define MGA_TEXFILTER 0x2c58
493 #define MGA_TEXHEIGHT 0x2c2c
494 #define MGA_TEXORG 0x2c24
495 # define MGA_TEXORGMAP_MASK (1 << 0)
496 # define MGA_TEXORGMAP_FB (0 << 0)
497 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
498 # define MGA_TEXORGACC_MASK (1 << 1)
499 # define MGA_TEXORGACC_PCI (0 << 1)
500 # define MGA_TEXORGACC_AGP (1 << 1)
501 #define MGA_TEXORG1 0x2ca4
502 #define MGA_TEXORG2 0x2ca8
503 #define MGA_TEXORG3 0x2cac
504 #define MGA_TEXORG4 0x2cb0
505 #define MGA_TEXTRANS 0x2c34
506 #define MGA_TEXTRANSHIGH 0x2c38
507 #define MGA_TEXWIDTH 0x2c28
509 #define MGA_WACCEPTSEQ 0x1dd4
510 #define MGA_WCODEADDR 0x1e6c
511 #define MGA_WFLAG 0x1dc4
512 #define MGA_WFLAG1 0x1de0
513 #define MGA_WFLAGNB 0x1e64
514 #define MGA_WFLAGNB1 0x1e08
515 #define MGA_WGETMSB 0x1dc8
516 #define MGA_WIADDR 0x1dc0
517 #define MGA_WIADDR2 0x1dd8
518 # define MGA_WMODE_SUSPEND (0 << 0)
519 # define MGA_WMODE_RESUME (1 << 0)
520 # define MGA_WMODE_JUMP (2 << 0)
521 # define MGA_WMODE_START (3 << 0)
522 # define MGA_WAGP_ENABLE (1 << 2)
523 #define MGA_WMISC 0x1e70
524 # define MGA_WUCODECACHE_ENABLE (1 << 0)
525 # define MGA_WMASTER_ENABLE (1 << 1)
526 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
527 #define MGA_WVRTXSZ 0x1dcc
529 #define MGA_YBOT 0x1c9c
530 #define MGA_YDST 0x1c90
531 #define MGA_YDSTLEN 0x1c88
532 #define MGA_YDSTORG 0x1c94
533 #define MGA_YTOP 0x1c98
535 #define MGA_ZORG 0x1c0c
537 /* This finishes the current batch of commands
539 #define MGA_EXEC 0x0100
543 #define MGA_WR0 0x2d00
544 #define MGA_WR1 0x2d04
545 #define MGA_WR2 0x2d08
546 #define MGA_WR3 0x2d0c
547 #define MGA_WR4 0x2d10
548 #define MGA_WR5 0x2d14
549 #define MGA_WR6 0x2d18
550 #define MGA_WR7 0x2d1c
551 #define MGA_WR8 0x2d20
552 #define MGA_WR9 0x2d24
553 #define MGA_WR10 0x2d28
554 #define MGA_WR11 0x2d2c
555 #define MGA_WR12 0x2d30
556 #define MGA_WR13 0x2d34
557 #define MGA_WR14 0x2d38
558 #define MGA_WR15 0x2d3c
559 #define MGA_WR16 0x2d40
560 #define MGA_WR17 0x2d44
561 #define MGA_WR18 0x2d48
562 #define MGA_WR19 0x2d4c
563 #define MGA_WR20 0x2d50
564 #define MGA_WR21 0x2d54
565 #define MGA_WR22 0x2d58
566 #define MGA_WR23 0x2d5c
567 #define MGA_WR24 0x2d60
568 #define MGA_WR25 0x2d64
569 #define MGA_WR26 0x2d68
570 #define MGA_WR27 0x2d6c
571 #define MGA_WR28 0x2d70
572 #define MGA_WR29 0x2d74
573 #define MGA_WR30 0x2d78
574 #define MGA_WR31 0x2d7c
575 #define MGA_WR32 0x2d80
576 #define MGA_WR33 0x2d84
577 #define MGA_WR34 0x2d88
578 #define MGA_WR35 0x2d8c
579 #define MGA_WR36 0x2d90
580 #define MGA_WR37 0x2d94
581 #define MGA_WR38 0x2d98
582 #define MGA_WR39 0x2d9c
583 #define MGA_WR40 0x2da0
584 #define MGA_WR41 0x2da4
585 #define MGA_WR42 0x2da8
586 #define MGA_WR43 0x2dac
587 #define MGA_WR44 0x2db0
588 #define MGA_WR45 0x2db4
589 #define MGA_WR46 0x2db8
590 #define MGA_WR47 0x2dbc
591 #define MGA_WR48 0x2dc0
592 #define MGA_WR49 0x2dc4
593 #define MGA_WR50 0x2dc8
594 #define MGA_WR51 0x2dcc
595 #define MGA_WR52 0x2dd0
596 #define MGA_WR53 0x2dd4
597 #define MGA_WR54 0x2dd8
598 #define MGA_WR55 0x2ddc
599 #define MGA_WR56 0x2de0
600 #define MGA_WR57 0x2de4
601 #define MGA_WR58 0x2de8
602 #define MGA_WR59 0x2dec
603 #define MGA_WR60 0x2df0
604 #define MGA_WR61 0x2df4
605 #define MGA_WR62 0x2df8
606 #define MGA_WR63 0x2dfc
607 # define MGA_G400_WR_MAGIC (1 << 6)
608 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
611 #define MGA_ILOAD_ALIGN 64
612 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
614 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
620 (15 << MGA_TRANS_SHIFT))
622 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
629 (0 << MGA_TRANS_SHIFT) | \
630 MGA_BLTMOD_BMONOLEF | \
634 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
639 (0 << MGA_TRANS_SHIFT) | \
645 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
647 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
648 return ( status == MGA_ENDPRDMASTS );