drivers/char/drm/mga_state.c

   1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Jeff Hartmann <jhartmann@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *
  31  * Rewritten by:
  32  *    Gareth Hughes <gareth@valinux.com>
  33  */
  34
  35 #include "drmP.h"
  36 #include "drm.h"
  37 #include "mga_drm.h"
  38 #include "mga_drv.h"
  39
  40 drm_ioctl_desc_t mga_ioctls[] = {
  41         [DRM_IOCTL_NR(DRM_MGA_INIT)]    = { mga_dma_init,    1, 1 },
  42         [DRM_IOCTL_NR(DRM_MGA_FLUSH)]   = { mga_dma_flush,   1, 0 },
  43         [DRM_IOCTL_NR(DRM_MGA_RESET)]   = { mga_dma_reset,   1, 0 },
  44         [DRM_IOCTL_NR(DRM_MGA_SWAP)]    = { mga_dma_swap,    1, 0 },
  45         [DRM_IOCTL_NR(DRM_MGA_CLEAR)]   = { mga_dma_clear,   1, 0 },
  46         [DRM_IOCTL_NR(DRM_MGA_VERTEX)]  = { mga_dma_vertex,  1, 0 },
  47         [DRM_IOCTL_NR(DRM_MGA_INDICES)] = { mga_dma_indices, 1, 0 },
  48         [DRM_IOCTL_NR(DRM_MGA_ILOAD)]   = { mga_dma_iload,   1, 0 },
  49         [DRM_IOCTL_NR(DRM_MGA_BLIT)]    = { mga_dma_blit,    1, 0 },
  50         [DRM_IOCTL_NR(DRM_MGA_GETPARAM)]= { mga_getparam,    1, 0 },
  51 };
  52
  53 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
  54
  55 /* ================================================================
  56  * DMA hardware state programming functions
  57  */
  58
  59 static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
  60                                 drm_clip_rect_t *box )
  61 {
  62         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  63         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  64         unsigned int pitch = dev_priv->front_pitch;
  65         DMA_LOCALS;
  66
  67         BEGIN_DMA( 2 );
  68
  69         /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
  70          */
  71         if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
  72                 DMA_BLOCK( MGA_DWGCTL,          ctx->dwgctl,
  73                            MGA_LEN + MGA_EXEC,  0x80000000,
  74                            MGA_DWGCTL,          ctx->dwgctl,
  75                            MGA_LEN + MGA_EXEC,  0x80000000 );
  76         }
  77         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
  78                    MGA_CXBNDRY, (box->x2 << 16) | box->x1,
  79                    MGA_YTOP,    box->y1 * pitch,
  80                    MGA_YBOT,    box->y2 * pitch );
  81
  82         ADVANCE_DMA();
  83 }
  84
  85 static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
  86 {
  87         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  88         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  89         DMA_LOCALS;
  90
  91         BEGIN_DMA( 3 );
  92
  93         DMA_BLOCK( MGA_DSTORG,          ctx->dstorg,
  94                    MGA_MACCESS,         ctx->maccess,
  95                    MGA_PLNWT,           ctx->plnwt,
  96                    MGA_DWGCTL,          ctx->dwgctl );
  97
  98         DMA_BLOCK( MGA_ALPHACTRL,       ctx->alphactrl,
  99                    MGA_FOGCOL,          ctx->fogcolor,
 100                    MGA_WFLAG,           ctx->wflag,
 101                    MGA_ZORG,            dev_priv->depth_offset );
 102
 103         DMA_BLOCK( MGA_FCOL,            ctx->fcol,
 104                    MGA_DMAPAD,          0x00000000,
 105                    MGA_DMAPAD,          0x00000000,
 106                    MGA_DMAPAD,          0x00000000 );
 107
 108         ADVANCE_DMA();
 109 }
 110
 111 static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
 112 {
 113         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 114         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 115         DMA_LOCALS;
 116
 117         BEGIN_DMA( 4 );
 118
 119         DMA_BLOCK( MGA_DSTORG,          ctx->dstorg,
 120                    MGA_MACCESS,         ctx->maccess,
 121                    MGA_PLNWT,           ctx->plnwt,
 122                    MGA_DWGCTL,          ctx->dwgctl );
 123
 124         DMA_BLOCK( MGA_ALPHACTRL,       ctx->alphactrl,
 125                    MGA_FOGCOL,          ctx->fogcolor,
 126                    MGA_WFLAG,           ctx->wflag,
 127                    MGA_ZORG,            dev_priv->depth_offset );
 128
 129         DMA_BLOCK( MGA_WFLAG1,          ctx->wflag,
 130                    MGA_TDUALSTAGE0,     ctx->tdualstage0,
 131                    MGA_TDUALSTAGE1,     ctx->tdualstage1,
 132                    MGA_FCOL,            ctx->fcol );
 133
 134         DMA_BLOCK( MGA_STENCIL,         ctx->stencil,
 135                    MGA_STENCILCTL,      ctx->stencilctl,
 136                    MGA_DMAPAD,          0x00000000,
 137                    MGA_DMAPAD,          0x00000000 );
 138
 139         ADVANCE_DMA();
 140 }
 141
 142 static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
 143 {
 144         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 145         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 146         DMA_LOCALS;
 147
 148         BEGIN_DMA( 4 );
 149
 150         DMA_BLOCK( MGA_TEXCTL2,         tex->texctl2,
 151                    MGA_TEXCTL,          tex->texctl,
 152                    MGA_TEXFILTER,       tex->texfilter,
 153                    MGA_TEXBORDERCOL,    tex->texbordercol );
 154
 155         DMA_BLOCK( MGA_TEXORG,          tex->texorg,
 156                    MGA_TEXORG1,         tex->texorg1,
 157                    MGA_TEXORG2,         tex->texorg2,
 158                    MGA_TEXORG3,         tex->texorg3 );
 159
 160         DMA_BLOCK( MGA_TEXORG4,         tex->texorg4,
 161                    MGA_TEXWIDTH,        tex->texwidth,
 162                    MGA_TEXHEIGHT,       tex->texheight,
 163                    MGA_WR24,            tex->texwidth );
 164
 165         DMA_BLOCK( MGA_WR34,            tex->texheight,
 166                    MGA_TEXTRANS,        0x0000ffff,
 167                    MGA_TEXTRANSHIGH,    0x0000ffff,
 168                    MGA_DMAPAD,          0x00000000 );
 169
 170         ADVANCE_DMA();
 171 }
 172
 173 static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
 174 {
 175         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 176         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 177         DMA_LOCALS;
 178
 179 /*      printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
 180 /*             tex->texctl, tex->texctl2); */
 181
 182         BEGIN_DMA( 6 );
 183
 184         DMA_BLOCK( MGA_TEXCTL2,         tex->texctl2 | MGA_G400_TC2_MAGIC,
 185                    MGA_TEXCTL,          tex->texctl,
 186                    MGA_TEXFILTER,       tex->texfilter,
 187                    MGA_TEXBORDERCOL,    tex->texbordercol );
 188
 189         DMA_BLOCK( MGA_TEXORG,          tex->texorg,
 190                    MGA_TEXORG1,         tex->texorg1,
 191                    MGA_TEXORG2,         tex->texorg2,
 192                    MGA_TEXORG3,         tex->texorg3 );
 193
 194         DMA_BLOCK( MGA_TEXORG4,         tex->texorg4,
 195                    MGA_TEXWIDTH,        tex->texwidth,
 196                    MGA_TEXHEIGHT,       tex->texheight,
 197                    MGA_WR49,            0x00000000 );
 198
 199         DMA_BLOCK( MGA_WR57,            0x00000000,
 200                    MGA_WR53,            0x00000000,
 201                    MGA_WR61,            0x00000000,
 202                    MGA_WR52,            MGA_G400_WR_MAGIC );
 203
 204         DMA_BLOCK( MGA_WR60,            MGA_G400_WR_MAGIC,
 205                    MGA_WR54,            tex->texwidth | MGA_G400_WR_MAGIC,
 206                    MGA_WR62,            tex->texheight | MGA_G400_WR_MAGIC,
 207                    MGA_DMAPAD,          0x00000000 );
 208
 209         DMA_BLOCK( MGA_DMAPAD,          0x00000000,
 210                    MGA_DMAPAD,          0x00000000,
 211                    MGA_TEXTRANS,        0x0000ffff,
 212                    MGA_TEXTRANSHIGH,    0x0000ffff );
 213
 214         ADVANCE_DMA();
 215 }
 216
 217 static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
 218 {
 219         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 220         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
 221         DMA_LOCALS;
 222
 223 /*      printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
 224 /*             tex->texctl, tex->texctl2); */
 225
 226         BEGIN_DMA( 5 );
 227
 228         DMA_BLOCK( MGA_TEXCTL2,         (tex->texctl2 |
 229                                          MGA_MAP1_ENABLE |
 230                                          MGA_G400_TC2_MAGIC),
 231                    MGA_TEXCTL,          tex->texctl,
 232                    MGA_TEXFILTER,       tex->texfilter,
 233                    MGA_TEXBORDERCOL,    tex->texbordercol );
 234
 235         DMA_BLOCK( MGA_TEXORG,          tex->texorg,
 236                    MGA_TEXORG1,         tex->texorg1,
 237                    MGA_TEXORG2,         tex->texorg2,
 238                    MGA_TEXORG3,         tex->texorg3 );
 239
 240         DMA_BLOCK( MGA_TEXORG4,         tex->texorg4,
 241                    MGA_TEXWIDTH,        tex->texwidth,
 242                    MGA_TEXHEIGHT,       tex->texheight,
 243                    MGA_WR49,            0x00000000 );
 244
 245         DMA_BLOCK( MGA_WR57,            0x00000000,
 246                    MGA_WR53,            0x00000000,
 247                    MGA_WR61,            0x00000000,
 248                    MGA_WR52,            tex->texwidth | MGA_G400_WR_MAGIC );
 249
 250         DMA_BLOCK( MGA_WR60,            tex->texheight | MGA_G400_WR_MAGIC,
 251                    MGA_TEXTRANS,        0x0000ffff,
 252                    MGA_TEXTRANSHIGH,    0x0000ffff,
 253                    MGA_TEXCTL2,         tex->texctl2 | MGA_G400_TC2_MAGIC );
 254
 255         ADVANCE_DMA();
 256 }
 257
 258 static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
 259 {
 260         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 261         unsigned int pipe = sarea_priv->warp_pipe;
 262         DMA_LOCALS;
 263
 264         BEGIN_DMA( 3 );
 265
 266         DMA_BLOCK( MGA_WIADDR,  MGA_WMODE_SUSPEND,
 267                    MGA_WVRTXSZ, 0x00000007,
 268                    MGA_WFLAG,   0x00000000,
 269                    MGA_WR24,    0x00000000 );
 270
 271         DMA_BLOCK( MGA_WR25,    0x00000100,
 272                    MGA_WR34,    0x00000000,
 273                    MGA_WR42,    0x0000ffff,
 274                    MGA_WR60,    0x0000ffff );
 275
 276         /* Padding required to to hardware bug.
 277          */
 278         DMA_BLOCK( MGA_DMAPAD,  0xffffffff,
 279                    MGA_DMAPAD,  0xffffffff,
 280                    MGA_DMAPAD,  0xffffffff,
 281                    MGA_WIADDR,  (dev_priv->warp_pipe_phys[pipe] |
 282                                  MGA_WMODE_START |
 283                                  MGA_WAGP_ENABLE) );
 284
 285         ADVANCE_DMA();
 286 }
 287
 288 static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
 289 {
 290         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 291         unsigned int pipe = sarea_priv->warp_pipe;
 292         DMA_LOCALS;
 293
 294 /*      printk("mga_g400_emit_pipe %x\n", pipe); */
 295
 296         BEGIN_DMA( 10 );
 297
 298         DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND,
 299                    MGA_DMAPAD,  0x00000000,
 300                    MGA_DMAPAD,  0x00000000,
 301                    MGA_DMAPAD,  0x00000000 );
 302
 303         if ( pipe & MGA_T2 ) {
 304                 DMA_BLOCK( MGA_WVRTXSZ,         0x00001e09,
 305                            MGA_DMAPAD,          0x00000000,
 306                            MGA_DMAPAD,          0x00000000,
 307                            MGA_DMAPAD,          0x00000000 );
 308
 309                 DMA_BLOCK( MGA_WACCEPTSEQ,      0x00000000,
 310                            MGA_WACCEPTSEQ,      0x00000000,
 311                            MGA_WACCEPTSEQ,      0x00000000,
 312                            MGA_WACCEPTSEQ,      0x1e000000 );
 313         } else {
 314                 if ( dev_priv->warp_pipe & MGA_T2 ) {
 315                         /* Flush the WARP pipe */
 316                         DMA_BLOCK( MGA_YDST,            0x00000000,
 317                                    MGA_FXLEFT,          0x00000000,
 318                                    MGA_FXRIGHT,         0x00000001,
 319                                    MGA_DWGCTL,          MGA_DWGCTL_FLUSH );
 320
 321                         DMA_BLOCK( MGA_LEN + MGA_EXEC,  0x00000001,
 322                                    MGA_DWGSYNC,         0x00007000,
 323                                    MGA_TEXCTL2,         MGA_G400_TC2_MAGIC,
 324                                    MGA_LEN + MGA_EXEC,  0x00000000 );
 325
 326                         DMA_BLOCK( MGA_TEXCTL2,         (MGA_DUALTEX |
 327                                                          MGA_G400_TC2_MAGIC),
 328                                    MGA_LEN + MGA_EXEC,  0x00000000,
 329                                    MGA_TEXCTL2,         MGA_G400_TC2_MAGIC,
 330                                    MGA_DMAPAD,          0x00000000 );
 331                 }
 332
 333                 DMA_BLOCK( MGA_WVRTXSZ,         0x00001807,
 334                            MGA_DMAPAD,          0x00000000,
 335                            MGA_DMAPAD,          0x00000000,
 336                            MGA_DMAPAD,          0x00000000 );
 337
 338                 DMA_BLOCK( MGA_WACCEPTSEQ,      0x00000000,
 339                            MGA_WACCEPTSEQ,      0x00000000,
 340                            MGA_WACCEPTSEQ,      0x00000000,
 341                            MGA_WACCEPTSEQ,      0x18000000 );
 342         }
 343
 344         DMA_BLOCK( MGA_WFLAG,   0x00000000,
 345                    MGA_WFLAG1,  0x00000000,
 346                    MGA_WR56,    MGA_G400_WR56_MAGIC,
 347                    MGA_DMAPAD,  0x00000000 );
 348
 349         DMA_BLOCK( MGA_WR49,    0x00000000,             /* tex0              */
 350                    MGA_WR57,    0x00000000,             /* tex0              */
 351                    MGA_WR53,    0x00000000,             /* tex1              */
 352                    MGA_WR61,    0x00000000 );           /* tex1              */
 353
 354         DMA_BLOCK( MGA_WR54,    MGA_G400_WR_MAGIC,      /* tex0 width        */
 355                    MGA_WR62,    MGA_G400_WR_MAGIC,      /* tex0 height       */
 356                    MGA_WR52,    MGA_G400_WR_MAGIC,      /* tex1 width        */
 357                    MGA_WR60,    MGA_G400_WR_MAGIC );    /* tex1 height       */
 358
 359         /* Padding required to to hardware bug */
 360         DMA_BLOCK( MGA_DMAPAD,  0xffffffff,
 361                    MGA_DMAPAD,  0xffffffff,
 362                    MGA_DMAPAD,  0xffffffff,
 363                    MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
 364                                  MGA_WMODE_START |
 365                                  MGA_WAGP_ENABLE) );
 366
 367         ADVANCE_DMA();
 368 }
 369
 370 static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
 371 {
 372         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 373         unsigned int dirty = sarea_priv->dirty;
 374
 375         if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
 376                 mga_g200_emit_pipe( dev_priv );
 377                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 378         }
 379
 380         if ( dirty & MGA_UPLOAD_CONTEXT ) {
 381                 mga_g200_emit_context( dev_priv );
 382                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 383         }
 384
 385         if ( dirty & MGA_UPLOAD_TEX0 ) {
 386                 mga_g200_emit_tex0( dev_priv );
 387                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 388         }
 389 }
 390
 391 static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
 392 {
 393         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 394         unsigned int dirty = sarea_priv->dirty;
 395         int multitex = sarea_priv->warp_pipe & MGA_T2;
 396
 397         if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
 398                 mga_g400_emit_pipe( dev_priv );
 399                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 400         }
 401
 402         if ( dirty & MGA_UPLOAD_CONTEXT ) {
 403                 mga_g400_emit_context( dev_priv );
 404                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 405         }
 406
 407         if ( dirty & MGA_UPLOAD_TEX0 ) {
 408                 mga_g400_emit_tex0( dev_priv );
 409                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 410         }
 411
 412         if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
 413                 mga_g400_emit_tex1( dev_priv );
 414                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
 415         }
 416 }
 417
 418
 419 /* ================================================================
 420  * SAREA state verification
 421  */
 422
 423 /* Disallow all write destinations except the front and backbuffer.
 424  */
 425 static int mga_verify_context( drm_mga_private_t *dev_priv )
 426 {
 427         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 428         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 429
 430         if ( ctx->dstorg != dev_priv->front_offset &&
 431              ctx->dstorg != dev_priv->back_offset ) {
 432                 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
 433                            ctx->dstorg, dev_priv->front_offset,
 434                            dev_priv->back_offset );
 435                 ctx->dstorg = 0;
 436                 return DRM_ERR(EINVAL);
 437         }
 438
 439         return 0;
 440 }
 441
 442 /* Disallow texture reads from PCI space.
 443  */
 444 static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
 445 {
 446         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 447         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
 448         unsigned int org;
 449
 450         org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
 451
 452         if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
 453                 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
 454                            tex->texorg, unit );
 455                 tex->texorg = 0;
 456                 return DRM_ERR(EINVAL);
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int mga_verify_state( drm_mga_private_t *dev_priv )
 463 {
 464         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 465         unsigned int dirty = sarea_priv->dirty;
 466         int ret = 0;
 467
 468         if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
 469                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 470
 471         if ( dirty & MGA_UPLOAD_CONTEXT )
 472                 ret |= mga_verify_context( dev_priv );
 473
 474         if ( dirty & MGA_UPLOAD_TEX0 )
 475                 ret |= mga_verify_tex( dev_priv, 0 );
 476
 477         if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
 478                 if ( dirty & MGA_UPLOAD_TEX1 )
 479                         ret |= mga_verify_tex( dev_priv, 1 );
 480
 481                 if ( dirty & MGA_UPLOAD_PIPE )
 482                         ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
 483         } else {
 484                 if ( dirty & MGA_UPLOAD_PIPE )
 485                         ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
 486         }
 487
 488         return ( ret == 0 );
 489 }
 490
 491 static int mga_verify_iload( drm_mga_private_t *dev_priv,
 492                              unsigned int dstorg, unsigned int length )
 493 {
 494         if ( dstorg < dev_priv->texture_offset ||
 495              dstorg + length > (dev_priv->texture_offset +
 496                                 dev_priv->texture_size) ) {
 497                 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
 498                 return DRM_ERR(EINVAL);
 499         }
 500
 501         if ( length & MGA_ILOAD_MASK ) {
 502                 DRM_ERROR( "*** bad iload length: 0x%x\n",
 503                            length & MGA_ILOAD_MASK );
 504                 return DRM_ERR(EINVAL);
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int mga_verify_blit( drm_mga_private_t *dev_priv,
 511                             unsigned int srcorg, unsigned int dstorg )
 512 {
 513         if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
 514              (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
 515                 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
 516                            srcorg, dstorg );
 517                 return DRM_ERR(EINVAL);
 518         }
 519         return 0;
 520 }
 521
 522
 523 /* ================================================================
 524  *
 525  */
 526
 527 static void mga_dma_dispatch_clear( drm_device_t *dev,
 528                                     drm_mga_clear_t *clear )
 529 {
 530         drm_mga_private_t *dev_priv = dev->dev_private;
 531         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 532         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 533         drm_clip_rect_t *pbox = sarea_priv->boxes;
 534         int nbox = sarea_priv->nbox;
 535         int i;
 536         DMA_LOCALS;
 537         DRM_DEBUG( "\n" );
 538
 539         BEGIN_DMA( 1 );
 540
 541         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 542                    MGA_DMAPAD,  0x00000000,
 543                    MGA_DWGSYNC, 0x00007100,
 544                    MGA_DWGSYNC, 0x00007000 );
 545
 546         ADVANCE_DMA();
 547
 548         for ( i = 0 ; i < nbox ; i++ ) {
 549                 drm_clip_rect_t *box = &pbox[i];
 550                 u32 height = box->y2 - box->y1;
 551
 552                 DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
 553                            box->x1, box->y1, box->x2, box->y2 );
 554
 555                 if ( clear->flags & MGA_FRONT ) {
 556                         BEGIN_DMA( 2 );
 557
 558                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 559                                    MGA_PLNWT,   clear->color_mask,
 560                                    MGA_YDSTLEN, (box->y1 << 16) | height,
 561                                    MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
 562
 563                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 564                                    MGA_FCOL,    clear->clear_color,
 565                                    MGA_DSTORG,  dev_priv->front_offset,
 566                                    MGA_DWGCTL + MGA_EXEC,
 567                                                 dev_priv->clear_cmd );
 568
 569                         ADVANCE_DMA();
 570                 }
 571
 572
 573                 if ( clear->flags & MGA_BACK ) {
 574                         BEGIN_DMA( 2 );
 575
 576                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 577                                    MGA_PLNWT,   clear->color_mask,
 578                                    MGA_YDSTLEN, (box->y1 << 16) | height,
 579                                    MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
 580
 581                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 582                                    MGA_FCOL,    clear->clear_color,
 583                                    MGA_DSTORG,  dev_priv->back_offset,
 584                                    MGA_DWGCTL + MGA_EXEC,
 585                                                 dev_priv->clear_cmd );
 586
 587                         ADVANCE_DMA();
 588                 }
 589
 590                 if ( clear->flags & MGA_DEPTH ) {
 591                         BEGIN_DMA( 2 );
 592
 593                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 594                                    MGA_PLNWT,   clear->depth_mask,
 595                                    MGA_YDSTLEN, (box->y1 << 16) | height,
 596                                    MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
 597
 598                         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 599                                    MGA_FCOL,    clear->clear_depth,
 600                                    MGA_DSTORG,  dev_priv->depth_offset,
 601                                    MGA_DWGCTL + MGA_EXEC,
 602                                                 dev_priv->clear_cmd );
 603
 604                         ADVANCE_DMA();
 605                 }
 606
 607         }
 608
 609         BEGIN_DMA( 1 );
 610
 611         /* Force reset of DWGCTL */
 612         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 613                    MGA_DMAPAD,  0x00000000,
 614                    MGA_PLNWT,   ctx->plnwt,
 615                    MGA_DWGCTL,  ctx->dwgctl );
 616
 617         ADVANCE_DMA();
 618
 619         FLUSH_DMA();
 620 }
 621
 622 static void mga_dma_dispatch_swap( drm_device_t *dev )
 623 {
 624         drm_mga_private_t *dev_priv = dev->dev_private;
 625         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 626         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 627         drm_clip_rect_t *pbox = sarea_priv->boxes;
 628         int nbox = sarea_priv->nbox;
 629         int i;
 630         DMA_LOCALS;
 631         DRM_DEBUG( "\n" );
 632
 633         sarea_priv->last_frame.head = dev_priv->prim.tail;
 634         sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
 635
 636         BEGIN_DMA( 4 + nbox );
 637
 638         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 639                    MGA_DMAPAD,  0x00000000,
 640                    MGA_DWGSYNC, 0x00007100,
 641                    MGA_DWGSYNC, 0x00007000 );
 642
 643         DMA_BLOCK( MGA_DSTORG,  dev_priv->front_offset,
 644                    MGA_MACCESS, dev_priv->maccess,
 645                    MGA_SRCORG,  dev_priv->back_offset,
 646                    MGA_AR5,     dev_priv->front_pitch );
 647
 648         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 649                    MGA_DMAPAD,  0x00000000,
 650                    MGA_PLNWT,   0xffffffff,
 651                    MGA_DWGCTL,  MGA_DWGCTL_COPY );
 652
 653         for ( i = 0 ; i < nbox ; i++ ) {
 654                 drm_clip_rect_t *box = &pbox[i];
 655                 u32 height = box->y2 - box->y1;
 656                 u32 start = box->y1 * dev_priv->front_pitch;
 657
 658                 DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
 659                            box->x1, box->y1, box->x2, box->y2 );
 660
 661                 DMA_BLOCK( MGA_AR0,     start + box->x2 - 1,
 662                            MGA_AR3,     start + box->x1,
 663                            MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
 664                            MGA_YDSTLEN + MGA_EXEC,
 665                                         (box->y1 << 16) | height );
 666         }
 667
 668         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 669                    MGA_PLNWT,   ctx->plnwt,
 670                    MGA_SRCORG,  dev_priv->front_offset,
 671                    MGA_DWGCTL,  ctx->dwgctl );
 672
 673         ADVANCE_DMA();
 674
 675         FLUSH_DMA();
 676
 677         DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
 678 }
 679
 680 static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
 681 {
 682         drm_mga_private_t *dev_priv = dev->dev_private;
 683         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 684         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 685         u32 address = (u32) buf->bus_address;
 686         u32 length = (u32) buf->used;
 687         int i = 0;
 688         DMA_LOCALS;
 689         DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
 690
 691         if ( buf->used ) {
 692                 buf_priv->dispatched = 1;
 693
 694                 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
 695
 696                 do {
 697                         if ( i < sarea_priv->nbox ) {
 698                                 mga_emit_clip_rect( dev_priv,
 699                                                     &sarea_priv->boxes[i] );
 700                         }
 701
 702                         BEGIN_DMA( 1 );
 703
 704                         DMA_BLOCK( MGA_DMAPAD,          0x00000000,
 705                                    MGA_DMAPAD,          0x00000000,
 706                                    MGA_SECADDRESS,      (address |
 707                                                          MGA_DMA_VERTEX),
 708                                    MGA_SECEND,          ((address + length) |
 709                                                          MGA_PAGPXFER) );
 710
 711                         ADVANCE_DMA();
 712                 } while ( ++i < sarea_priv->nbox );
 713         }
 714
 715         if ( buf_priv->discard ) {
 716                 AGE_BUFFER( buf_priv );
 717                 buf->pending = 0;
 718                 buf->used = 0;
 719                 buf_priv->dispatched = 0;
 720
 721                 mga_freelist_put( dev, buf );
 722         }
 723
 724         FLUSH_DMA();
 725 }
 726
 727 static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
 728                                       unsigned int start, unsigned int end )
 729 {
 730         drm_mga_private_t *dev_priv = dev->dev_private;
 731         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 732         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 733         u32 address = (u32) buf->bus_address;
 734         int i = 0;
 735         DMA_LOCALS;
 736         DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
 737
 738         if ( start != end ) {
 739                 buf_priv->dispatched = 1;
 740
 741                 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
 742
 743                 do {
 744                         if ( i < sarea_priv->nbox ) {
 745                                 mga_emit_clip_rect( dev_priv,
 746                                                     &sarea_priv->boxes[i] );
 747                         }
 748
 749                         BEGIN_DMA( 1 );
 750
 751                         DMA_BLOCK( MGA_DMAPAD,          0x00000000,
 752                                    MGA_DMAPAD,          0x00000000,
 753                                    MGA_SETUPADDRESS,    address + start,
 754                                    MGA_SETUPEND,        ((address + end) |
 755                                                          MGA_PAGPXFER) );
 756
 757                         ADVANCE_DMA();
 758                 } while ( ++i < sarea_priv->nbox );
 759         }
 760
 761         if ( buf_priv->discard ) {
 762                 AGE_BUFFER( buf_priv );
 763                 buf->pending = 0;
 764                 buf->used = 0;
 765                 buf_priv->dispatched = 0;
 766
 767                 mga_freelist_put( dev, buf );
 768         }
 769
 770         FLUSH_DMA();
 771 }
 772
 773 /* This copies a 64 byte aligned agp region to the frambuffer with a
 774  * standard blit, the ioctl needs to do checking.
 775  */
 776 static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
 777                                     unsigned int dstorg, unsigned int length )
 778 {
 779         drm_mga_private_t *dev_priv = dev->dev_private;
 780         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 781         drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
 782         u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
 783         u32 y2;
 784         DMA_LOCALS;
 785         DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
 786
 787         y2 = length / 64;
 788
 789         BEGIN_DMA( 5 );
 790
 791         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 792                    MGA_DMAPAD,  0x00000000,
 793                    MGA_DWGSYNC, 0x00007100,
 794                    MGA_DWGSYNC, 0x00007000 );
 795
 796         DMA_BLOCK( MGA_DSTORG,  dstorg,
 797                    MGA_MACCESS, 0x00000000,
 798                    MGA_SRCORG,  srcorg,
 799                    MGA_AR5,     64 );
 800
 801         DMA_BLOCK( MGA_PITCH,   64,
 802                    MGA_PLNWT,   0xffffffff,
 803                    MGA_DMAPAD,  0x00000000,
 804                    MGA_DWGCTL,  MGA_DWGCTL_COPY );
 805
 806         DMA_BLOCK( MGA_AR0,     63,
 807                    MGA_AR3,     0,
 808                    MGA_FXBNDRY, (63 << 16) | 0,
 809                    MGA_YDSTLEN + MGA_EXEC, y2 );
 810
 811         DMA_BLOCK( MGA_PLNWT,   ctx->plnwt,
 812                    MGA_SRCORG,  dev_priv->front_offset,
 813                    MGA_PITCH,   dev_priv->front_pitch,
 814                    MGA_DWGSYNC, 0x00007000 );
 815
 816         ADVANCE_DMA();
 817
 818         AGE_BUFFER( buf_priv );
 819
 820         buf->pending = 0;
 821         buf->used = 0;
 822         buf_priv->dispatched = 0;
 823
 824         mga_freelist_put( dev, buf );
 825
 826         FLUSH_DMA();
 827 }
 828
 829 static void mga_dma_dispatch_blit( drm_device_t *dev,
 830                                    drm_mga_blit_t *blit )
 831 {
 832         drm_mga_private_t *dev_priv = dev->dev_private;
 833         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 834         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 835         drm_clip_rect_t *pbox = sarea_priv->boxes;
 836         int nbox = sarea_priv->nbox;
 837         u32 scandir = 0, i;
 838         DMA_LOCALS;
 839         DRM_DEBUG( "\n" );
 840
 841         BEGIN_DMA( 4 + nbox );
 842
 843         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 844                    MGA_DMAPAD,  0x00000000,
 845                    MGA_DWGSYNC, 0x00007100,
 846                    MGA_DWGSYNC, 0x00007000 );
 847
 848         DMA_BLOCK( MGA_DWGCTL,  MGA_DWGCTL_COPY,
 849                    MGA_PLNWT,   blit->planemask,
 850                    MGA_SRCORG,  blit->srcorg,
 851                    MGA_DSTORG,  blit->dstorg );
 852
 853         DMA_BLOCK( MGA_SGN,     scandir,
 854                    MGA_MACCESS, dev_priv->maccess,
 855                    MGA_AR5,     blit->ydir * blit->src_pitch,
 856                    MGA_PITCH,   blit->dst_pitch );
 857
 858         for ( i = 0 ; i < nbox ; i++ ) {
 859                 int srcx = pbox[i].x1 + blit->delta_sx;
 860                 int srcy = pbox[i].y1 + blit->delta_sy;
 861                 int dstx = pbox[i].x1 + blit->delta_dx;
 862                 int dsty = pbox[i].y1 + blit->delta_dy;
 863                 int h = pbox[i].y2 - pbox[i].y1;
 864                 int w = pbox[i].x2 - pbox[i].x1 - 1;
 865                 int start;
 866
 867                 if ( blit->ydir == -1 ) {
 868                         srcy = blit->height - srcy - 1;
 869                 }
 870
 871                 start = srcy * blit->src_pitch + srcx;
 872
 873                 DMA_BLOCK( MGA_AR0,     start + w,
 874                            MGA_AR3,     start,
 875                            MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
 876                            MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
 877         }
 878
 879         /* Do something to flush AGP?
 880          */
 881
 882         /* Force reset of DWGCTL */
 883         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 884                    MGA_PLNWT,   ctx->plnwt,
 885                    MGA_PITCH,   dev_priv->front_pitch,
 886                    MGA_DWGCTL,  ctx->dwgctl );
 887
 888         ADVANCE_DMA();
 889 }
 890
 891
 892 /* ================================================================
 893  *
 894  */
 895
 896 int mga_dma_clear( DRM_IOCTL_ARGS )
 897 {
 898         DRM_DEVICE;
 899         drm_mga_private_t *dev_priv = dev->dev_private;
 900         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 901         drm_mga_clear_t clear;
 902
 903         LOCK_TEST_WITH_RETURN( dev, filp );
 904
 905         DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) );
 906
 907         if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
 908                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 909
 910         WRAP_TEST_WITH_RETURN( dev_priv );
 911
 912         mga_dma_dispatch_clear( dev, &clear );
 913
 914         /* Make sure we restore the 3D state next time.
 915          */
 916         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 917
 918         return 0;
 919 }
 920
 921 int mga_dma_swap( DRM_IOCTL_ARGS )
 922 {
 923         DRM_DEVICE;
 924         drm_mga_private_t *dev_priv = dev->dev_private;
 925         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 926
 927         LOCK_TEST_WITH_RETURN( dev, filp );
 928
 929         if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
 930                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 931
 932         WRAP_TEST_WITH_RETURN( dev_priv );
 933
 934         mga_dma_dispatch_swap( dev );
 935
 936         /* Make sure we restore the 3D state next time.
 937          */
 938         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 939
 940         return 0;
 941 }
 942
 943 int mga_dma_vertex( DRM_IOCTL_ARGS )
 944 {
 945         DRM_DEVICE;
 946         drm_mga_private_t *dev_priv = dev->dev_private;
 947         drm_device_dma_t *dma = dev->dma;
 948         drm_buf_t *buf;
 949         drm_mga_buf_priv_t *buf_priv;
 950         drm_mga_vertex_t vertex;
 951
 952         LOCK_TEST_WITH_RETURN( dev, filp );
 953
 954         DRM_COPY_FROM_USER_IOCTL( vertex,
 955                              (drm_mga_vertex_t __user *)data,
 956                              sizeof(vertex) );
 957
 958         if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
 959         buf = dma->buflist[vertex.idx];
 960         buf_priv = buf->dev_private;
 961
 962         buf->used = vertex.used;
 963         buf_priv->discard = vertex.discard;
 964
 965         if ( !mga_verify_state( dev_priv ) ) {
 966                 if ( vertex.discard ) {
 967                         if ( buf_priv->dispatched == 1 )
 968                                 AGE_BUFFER( buf_priv );
 969                         buf_priv->dispatched = 0;
 970                         mga_freelist_put( dev, buf );
 971                 }
 972                 return DRM_ERR(EINVAL);
 973         }
 974
 975         WRAP_TEST_WITH_RETURN( dev_priv );
 976
 977         mga_dma_dispatch_vertex( dev, buf );
 978
 979         return 0;
 980 }
 981
 982 int mga_dma_indices( DRM_IOCTL_ARGS )
 983 {
 984         DRM_DEVICE;
 985         drm_mga_private_t *dev_priv = dev->dev_private;
 986         drm_device_dma_t *dma = dev->dma;
 987         drm_buf_t *buf;
 988         drm_mga_buf_priv_t *buf_priv;
 989         drm_mga_indices_t indices;
 990
 991         LOCK_TEST_WITH_RETURN( dev, filp );
 992
 993         DRM_COPY_FROM_USER_IOCTL( indices,
 994                              (drm_mga_indices_t __user *)data,
 995                              sizeof(indices) );
 996
 997         if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
 998
 999         buf = dma->buflist[indices.idx];
1000         buf_priv = buf->dev_private;
1001
1002         buf_priv->discard = indices.discard;
1003
1004         if ( !mga_verify_state( dev_priv ) ) {
1005                 if ( indices.discard ) {
1006                         if ( buf_priv->dispatched == 1 )
1007                                 AGE_BUFFER( buf_priv );
1008                         buf_priv->dispatched = 0;
1009                         mga_freelist_put( dev, buf );
1010                 }
1011                 return DRM_ERR(EINVAL);
1012         }
1013
1014         WRAP_TEST_WITH_RETURN( dev_priv );
1015
1016         mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
1017
1018         return 0;
1019 }
1020
1021 int mga_dma_iload( DRM_IOCTL_ARGS )
1022 {
1023         DRM_DEVICE;
1024         drm_device_dma_t *dma = dev->dma;
1025         drm_mga_private_t *dev_priv = dev->dev_private;
1026         drm_buf_t *buf;
1027         drm_mga_buf_priv_t *buf_priv;
1028         drm_mga_iload_t iload;
1029         DRM_DEBUG( "\n" );
1030
1031         LOCK_TEST_WITH_RETURN( dev, filp );
1032
1033         DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) );
1034
1035 #if 0
1036         if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
1037                 if ( MGA_DMA_DEBUG )
1038                         DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
1039                 return DRM_ERR(EBUSY);
1040         }
1041 #endif
1042         if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
1043
1044         buf = dma->buflist[iload.idx];
1045         buf_priv = buf->dev_private;
1046
1047         if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
1048                 mga_freelist_put( dev, buf );
1049                 return DRM_ERR(EINVAL);
1050         }
1051
1052         WRAP_TEST_WITH_RETURN( dev_priv );
1053
1054         mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
1055
1056         /* Make sure we restore the 3D state next time.
1057          */
1058         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1059
1060         return 0;
1061 }
1062
1063 int mga_dma_blit( DRM_IOCTL_ARGS )
1064 {
1065         DRM_DEVICE;
1066         drm_mga_private_t *dev_priv = dev->dev_private;
1067         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1068         drm_mga_blit_t blit;
1069         DRM_DEBUG( "\n" );
1070
1071         LOCK_TEST_WITH_RETURN( dev, filp );
1072
1073         DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) );
1074
1075         if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
1076                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1077
1078         if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
1079                 return DRM_ERR(EINVAL);
1080
1081         WRAP_TEST_WITH_RETURN( dev_priv );
1082
1083         mga_dma_dispatch_blit( dev, &blit );
1084
1085         /* Make sure we restore the 3D state next time.
1086          */
1087         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1088
1089         return 0;
1090 }
1091
1092 int mga_getparam( DRM_IOCTL_ARGS )
1093 {
1094         DRM_DEVICE;
1095         drm_mga_private_t *dev_priv = dev->dev_private;
1096         drm_mga_getparam_t param;
1097         int value;
1098
1099         if ( !dev_priv ) {
1100                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1101                 return DRM_ERR(EINVAL);
1102         }
1103
1104         DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data,
1105                              sizeof(param) );
1106
1107         DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
1108
1109         switch( param.param ) {
1110         case MGA_PARAM_IRQ_NR:
1111                 value = dev->irq;
1112                 break;
1113         default:
1114                 return DRM_ERR(EINVAL);
1115         }
1116
1117         if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
1118                 DRM_ERROR( "copy_to_user\n" );
1119                 return DRM_ERR(EFAULT);
1120         }
1121
1122         return 0;
1123 }