1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
37 #define R128_FIFO_DEBUG 0
39 /* CCE microcode (from ATI) */
40 static u32 r128_cce_microcode[] = {
41 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
42 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
43 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
44 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
45 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
46 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
47 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
48 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
49 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
50 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
51 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
52 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
53 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
54 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
55 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
56 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
57 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
58 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
59 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
60 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
61 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
62 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
63 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
64 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
65 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
66 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
67 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
68 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
69 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
70 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
71 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
72 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
73 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
74 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
75 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
84 int R128_READ_PLL(drm_device_t *dev, int addr)
86 drm_r128_private_t *dev_priv = dev->dev_private;
88 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
89 return R128_READ(R128_CLOCK_CNTL_DATA);
93 static void r128_status( drm_r128_private_t *dev_priv )
95 printk( "GUI_STAT = 0x%08x\n",
96 (unsigned int)R128_READ( R128_GUI_STAT ) );
97 printk( "PM4_STAT = 0x%08x\n",
98 (unsigned int)R128_READ( R128_PM4_STAT ) );
99 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
100 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
101 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
102 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
103 printk( "PM4_MICRO_CNTL = 0x%08x\n",
104 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
105 printk( "PM4_BUFFER_CNTL = 0x%08x\n",
106 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
111 /* ================================================================
112 * Engine, FIFO control
115 static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
120 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
121 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
123 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
124 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
131 DRM_ERROR( "failed!\n" );
133 return DRM_ERR(EBUSY);
136 static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
140 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
141 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
142 if ( slots >= entries ) return 0;
147 DRM_ERROR( "failed!\n" );
149 return DRM_ERR(EBUSY);
152 static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
156 ret = r128_do_wait_for_fifo( dev_priv, 64 );
157 if ( ret ) return ret;
159 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
160 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
161 r128_do_pixcache_flush( dev_priv );
168 DRM_ERROR( "failed!\n" );
170 return DRM_ERR(EBUSY);
174 /* ================================================================
175 * CCE control, initialization
178 /* Load the microcode for the CCE */
179 static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
185 r128_do_wait_for_idle( dev_priv );
187 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
188 for ( i = 0 ; i < 256 ; i++ ) {
189 R128_WRITE( R128_PM4_MICROCODE_DATAH,
190 r128_cce_microcode[i * 2] );
191 R128_WRITE( R128_PM4_MICROCODE_DATAL,
192 r128_cce_microcode[i * 2 + 1] );
196 /* Flush any pending commands to the CCE. This should only be used just
197 * prior to a wait for idle, as it informs the engine that the command
200 static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
204 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
205 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
208 /* Wait for the CCE to go idle.
210 int r128_do_cce_idle( drm_r128_private_t *dev_priv )
214 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
215 if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) {
216 int pm4stat = R128_READ( R128_PM4_STAT );
217 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
218 dev_priv->cce_fifo_size ) &&
219 !(pm4stat & (R128_PM4_BUSY |
220 R128_PM4_GUI_ACTIVE)) ) {
221 return r128_do_pixcache_flush( dev_priv );
228 DRM_ERROR( "failed!\n" );
229 r128_status( dev_priv );
231 return DRM_ERR(EBUSY);
234 /* Start the Concurrent Command Engine.
236 static void r128_do_cce_start( drm_r128_private_t *dev_priv )
238 r128_do_wait_for_idle( dev_priv );
240 R128_WRITE( R128_PM4_BUFFER_CNTL,
241 dev_priv->cce_mode | dev_priv->ring.size_l2qw
242 | R128_PM4_BUFFER_CNTL_NOUPDATE );
243 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
244 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
246 dev_priv->cce_running = 1;
249 /* Reset the Concurrent Command Engine. This will not flush any pending
250 * commands, so you must wait for the CCE command stream to complete
251 * before calling this routine.
253 static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
255 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
256 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
257 dev_priv->ring.tail = 0;
260 /* Stop the Concurrent Command Engine. This will not flush any pending
261 * commands, so you must flush the command stream and wait for the CCE
262 * to go idle before calling this routine.
264 static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
266 R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
267 R128_WRITE( R128_PM4_BUFFER_CNTL,
268 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE );
270 dev_priv->cce_running = 0;
273 /* Reset the engine. This will stop the CCE if it is running.
275 static int r128_do_engine_reset( drm_device_t *dev )
277 drm_r128_private_t *dev_priv = dev->dev_private;
278 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
280 r128_do_pixcache_flush( dev_priv );
282 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
283 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
285 R128_WRITE_PLL( R128_MCLK_CNTL,
286 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
288 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
290 /* Taken from the sample code - do not change */
291 R128_WRITE( R128_GEN_RESET_CNTL,
292 gen_reset_cntl | R128_SOFT_RESET_GUI );
293 R128_READ( R128_GEN_RESET_CNTL );
294 R128_WRITE( R128_GEN_RESET_CNTL,
295 gen_reset_cntl & ~R128_SOFT_RESET_GUI );
296 R128_READ( R128_GEN_RESET_CNTL );
298 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
299 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
300 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
302 /* Reset the CCE ring */
303 r128_do_cce_reset( dev_priv );
305 /* The CCE is no longer running after an engine reset */
306 dev_priv->cce_running = 0;
308 /* Reset any pending vertex, indirect buffers */
309 r128_freelist_reset( dev );
314 static void r128_cce_init_ring_buffer( drm_device_t *dev,
315 drm_r128_private_t *dev_priv )
322 /* The manual (p. 2) says this address is in "VM space". This
323 * means it's an offset from the start of AGP space.
326 if ( !dev_priv->is_pci )
327 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
330 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
332 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
334 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
335 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
337 /* Set watermark control */
338 R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
339 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
340 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
341 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
342 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
344 /* Force read. Why? Because it's in the examples... */
345 R128_READ( R128_PM4_BUFFER_ADDR );
347 /* Turn on bus mastering */
348 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
349 R128_WRITE( R128_BUS_CNTL, tmp );
352 static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
354 drm_r128_private_t *dev_priv;
358 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
359 if ( dev_priv == NULL )
360 return DRM_ERR(ENOMEM);
362 memset( dev_priv, 0, sizeof(drm_r128_private_t) );
364 dev_priv->is_pci = init->is_pci;
366 if ( dev_priv->is_pci && !dev->sg ) {
367 DRM_ERROR( "PCI GART memory not allocated!\n" );
368 dev->dev_private = (void *)dev_priv;
369 r128_do_cleanup_cce( dev );
370 return DRM_ERR(EINVAL);
373 dev_priv->usec_timeout = init->usec_timeout;
374 if ( dev_priv->usec_timeout < 1 ||
375 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
376 DRM_DEBUG( "TIMEOUT problem!\n" );
377 dev->dev_private = (void *)dev_priv;
378 r128_do_cleanup_cce( dev );
379 return DRM_ERR(EINVAL);
382 dev_priv->cce_mode = init->cce_mode;
384 /* GH: Simple idle check.
386 atomic_set( &dev_priv->idle_count, 0 );
388 /* We don't support anything other than bus-mastering ring mode,
389 * but the ring can be in either AGP or PCI space for the ring
392 if ( ( init->cce_mode != R128_PM4_192BM ) &&
393 ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
394 ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
395 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
396 DRM_DEBUG( "Bad cce_mode!\n" );
397 dev->dev_private = (void *)dev_priv;
398 r128_do_cleanup_cce( dev );
399 return DRM_ERR(EINVAL);
402 switch ( init->cce_mode ) {
403 case R128_PM4_NONPM4:
404 dev_priv->cce_fifo_size = 0;
406 case R128_PM4_192PIO:
408 dev_priv->cce_fifo_size = 192;
410 case R128_PM4_128PIO_64INDBM:
411 case R128_PM4_128BM_64INDBM:
412 dev_priv->cce_fifo_size = 128;
414 case R128_PM4_64PIO_128INDBM:
415 case R128_PM4_64BM_128INDBM:
416 case R128_PM4_64PIO_64VCBM_64INDBM:
417 case R128_PM4_64BM_64VCBM_64INDBM:
418 case R128_PM4_64PIO_64VCPIO_64INDPIO:
419 dev_priv->cce_fifo_size = 64;
423 switch ( init->fb_bpp ) {
425 dev_priv->color_fmt = R128_DATATYPE_RGB565;
429 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
432 dev_priv->front_offset = init->front_offset;
433 dev_priv->front_pitch = init->front_pitch;
434 dev_priv->back_offset = init->back_offset;
435 dev_priv->back_pitch = init->back_pitch;
437 switch ( init->depth_bpp ) {
439 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
444 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
447 dev_priv->depth_offset = init->depth_offset;
448 dev_priv->depth_pitch = init->depth_pitch;
449 dev_priv->span_offset = init->span_offset;
451 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
452 (dev_priv->front_offset >> 5));
453 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
454 (dev_priv->back_offset >> 5));
455 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
456 (dev_priv->depth_offset >> 5) |
458 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
459 (dev_priv->span_offset >> 5));
463 if(!dev_priv->sarea) {
464 DRM_ERROR("could not find sarea!\n");
465 dev->dev_private = (void *)dev_priv;
466 r128_do_cleanup_cce( dev );
467 return DRM_ERR(EINVAL);
470 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
471 if(!dev_priv->mmio) {
472 DRM_ERROR("could not find mmio region!\n");
473 dev->dev_private = (void *)dev_priv;
474 r128_do_cleanup_cce( dev );
475 return DRM_ERR(EINVAL);
477 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
478 if(!dev_priv->cce_ring) {
479 DRM_ERROR("could not find cce ring region!\n");
480 dev->dev_private = (void *)dev_priv;
481 r128_do_cleanup_cce( dev );
482 return DRM_ERR(EINVAL);
484 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
485 if(!dev_priv->ring_rptr) {
486 DRM_ERROR("could not find ring read pointer!\n");
487 dev->dev_private = (void *)dev_priv;
488 r128_do_cleanup_cce( dev );
489 return DRM_ERR(EINVAL);
491 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
492 if(!dev->agp_buffer_map) {
493 DRM_ERROR("could not find dma buffer region!\n");
494 dev->dev_private = (void *)dev_priv;
495 r128_do_cleanup_cce( dev );
496 return DRM_ERR(EINVAL);
499 if ( !dev_priv->is_pci ) {
500 dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset);
501 if(!dev_priv->agp_textures) {
502 DRM_ERROR("could not find agp texture region!\n");
503 dev->dev_private = (void *)dev_priv;
504 r128_do_cleanup_cce( dev );
505 return DRM_ERR(EINVAL);
509 dev_priv->sarea_priv =
510 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
511 init->sarea_priv_offset);
514 if ( !dev_priv->is_pci ) {
515 drm_core_ioremap( dev_priv->cce_ring, dev );
516 drm_core_ioremap( dev_priv->ring_rptr, dev );
517 drm_core_ioremap( dev->agp_buffer_map, dev );
518 if(!dev_priv->cce_ring->handle ||
519 !dev_priv->ring_rptr->handle ||
520 !dev->agp_buffer_map->handle) {
521 DRM_ERROR("Could not ioremap agp regions!\n");
522 dev->dev_private = (void *)dev_priv;
523 r128_do_cleanup_cce( dev );
524 return DRM_ERR(ENOMEM);
529 dev_priv->cce_ring->handle =
530 (void *)dev_priv->cce_ring->offset;
531 dev_priv->ring_rptr->handle =
532 (void *)dev_priv->ring_rptr->offset;
533 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
537 if ( !dev_priv->is_pci )
538 dev_priv->cce_buffers_offset = dev->agp->base;
541 dev_priv->cce_buffers_offset = dev->sg->handle;
543 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
544 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
545 + init->ring_size / sizeof(u32));
546 dev_priv->ring.size = init->ring_size;
547 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
549 dev_priv->ring.tail_mask =
550 (dev_priv->ring.size / sizeof(u32)) - 1;
552 dev_priv->ring.high_mark = 128;
554 dev_priv->sarea_priv->last_frame = 0;
555 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
557 dev_priv->sarea_priv->last_dispatch = 0;
558 R128_WRITE( R128_LAST_DISPATCH_REG,
559 dev_priv->sarea_priv->last_dispatch );
562 if ( dev_priv->is_pci ) {
564 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
565 &dev_priv->bus_pci_gart) ) {
566 DRM_ERROR( "failed to init PCI GART!\n" );
567 dev->dev_private = (void *)dev_priv;
568 r128_do_cleanup_cce( dev );
569 return DRM_ERR(ENOMEM);
571 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
576 r128_cce_init_ring_buffer( dev, dev_priv );
577 r128_cce_load_microcode( dev_priv );
579 dev->dev_private = (void *)dev_priv;
581 r128_do_engine_reset( dev );
586 int r128_do_cleanup_cce( drm_device_t *dev )
589 /* Make sure interrupts are disabled here because the uninstall ioctl
590 * may not have been called from userspace and after dev_private
591 * is freed, it's too late.
593 if ( dev->irq_enabled ) DRM(irq_uninstall)(dev);
595 if ( dev->dev_private ) {
596 drm_r128_private_t *dev_priv = dev->dev_private;
599 if ( !dev_priv->is_pci ) {
600 if ( dev_priv->cce_ring != NULL )
601 drm_core_ioremapfree( dev_priv->cce_ring, dev );
602 if ( dev_priv->ring_rptr != NULL )
603 drm_core_ioremapfree( dev_priv->ring_rptr, dev );
604 if ( dev->agp_buffer_map != NULL )
605 drm_core_ioremapfree( dev->agp_buffer_map, dev );
609 if (!DRM(ati_pcigart_cleanup)( dev,
610 dev_priv->phys_pci_gart,
611 dev_priv->bus_pci_gart ))
612 DRM_ERROR( "failed to cleanup PCI GART!\n" );
615 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
617 dev->dev_private = NULL;
623 int r128_cce_init( DRM_IOCTL_ARGS )
626 drm_r128_init_t init;
630 LOCK_TEST_WITH_RETURN( dev, filp );
632 DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) );
634 switch ( init.func ) {
636 return r128_do_init_cce( dev, &init );
637 case R128_CLEANUP_CCE:
638 return r128_do_cleanup_cce( dev );
641 return DRM_ERR(EINVAL);
644 int r128_cce_start( DRM_IOCTL_ARGS )
647 drm_r128_private_t *dev_priv = dev->dev_private;
650 LOCK_TEST_WITH_RETURN( dev, filp );
652 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
653 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
657 r128_do_cce_start( dev_priv );
662 /* Stop the CCE. The engine must have been idled before calling this
665 int r128_cce_stop( DRM_IOCTL_ARGS )
668 drm_r128_private_t *dev_priv = dev->dev_private;
669 drm_r128_cce_stop_t stop;
673 LOCK_TEST_WITH_RETURN( dev, filp );
675 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) );
677 /* Flush any pending CCE commands. This ensures any outstanding
678 * commands are exectuted by the engine before we turn it off.
681 r128_do_cce_flush( dev_priv );
684 /* If we fail to make the engine go idle, we return an error
685 * code so that the DRM ioctl wrapper can try again.
688 ret = r128_do_cce_idle( dev_priv );
689 if ( ret ) return ret;
692 /* Finally, we can turn off the CCE. If the engine isn't idle,
693 * we will get some dropped triangles as they won't be fully
694 * rendered before the CCE is shut down.
696 r128_do_cce_stop( dev_priv );
698 /* Reset the engine */
699 r128_do_engine_reset( dev );
704 /* Just reset the CCE ring. Called as part of an X Server engine reset.
706 int r128_cce_reset( DRM_IOCTL_ARGS )
709 drm_r128_private_t *dev_priv = dev->dev_private;
712 LOCK_TEST_WITH_RETURN( dev, filp );
715 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
716 return DRM_ERR(EINVAL);
719 r128_do_cce_reset( dev_priv );
721 /* The CCE is no longer running after an engine reset */
722 dev_priv->cce_running = 0;
727 int r128_cce_idle( DRM_IOCTL_ARGS )
730 drm_r128_private_t *dev_priv = dev->dev_private;
733 LOCK_TEST_WITH_RETURN( dev, filp );
735 if ( dev_priv->cce_running ) {
736 r128_do_cce_flush( dev_priv );
739 return r128_do_cce_idle( dev_priv );
742 int r128_engine_reset( DRM_IOCTL_ARGS )
747 LOCK_TEST_WITH_RETURN( dev, filp );
749 return r128_do_engine_reset( dev );
752 int r128_fullscreen( DRM_IOCTL_ARGS )
754 return DRM_ERR(EINVAL);
758 /* ================================================================
759 * Freelist management
761 #define R128_BUFFER_USED 0xffffffff
762 #define R128_BUFFER_FREE 0
765 static int r128_freelist_init( drm_device_t *dev )
767 drm_device_dma_t *dma = dev->dma;
768 drm_r128_private_t *dev_priv = dev->dev_private;
770 drm_r128_buf_priv_t *buf_priv;
771 drm_r128_freelist_t *entry;
774 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
776 if ( dev_priv->head == NULL )
777 return DRM_ERR(ENOMEM);
779 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
780 dev_priv->head->age = R128_BUFFER_USED;
782 for ( i = 0 ; i < dma->buf_count ; i++ ) {
783 buf = dma->buflist[i];
784 buf_priv = buf->dev_private;
786 entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
788 if ( !entry ) return DRM_ERR(ENOMEM);
790 entry->age = R128_BUFFER_FREE;
792 entry->prev = dev_priv->head;
793 entry->next = dev_priv->head->next;
795 dev_priv->tail = entry;
797 buf_priv->discard = 0;
798 buf_priv->dispatched = 0;
799 buf_priv->list_entry = entry;
801 dev_priv->head->next = entry;
803 if ( dev_priv->head->next )
804 dev_priv->head->next->prev = entry;
812 drm_buf_t *r128_freelist_get( drm_device_t *dev )
814 drm_device_dma_t *dma = dev->dma;
815 drm_r128_private_t *dev_priv = dev->dev_private;
816 drm_r128_buf_priv_t *buf_priv;
820 /* FIXME: Optimize -- use freelist code */
822 for ( i = 0 ; i < dma->buf_count ; i++ ) {
823 buf = dma->buflist[i];
824 buf_priv = buf->dev_private;
825 if ( buf->filp == 0 )
829 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
830 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
832 for ( i = 0 ; i < dma->buf_count ; i++ ) {
833 buf = dma->buflist[i];
834 buf_priv = buf->dev_private;
835 if ( buf->pending && buf_priv->age <= done_age ) {
836 /* The buffer has been processed, so it
846 DRM_DEBUG( "returning NULL!\n" );
850 void r128_freelist_reset( drm_device_t *dev )
852 drm_device_dma_t *dma = dev->dma;
855 for ( i = 0 ; i < dma->buf_count ; i++ ) {
856 drm_buf_t *buf = dma->buflist[i];
857 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
863 /* ================================================================
864 * CCE command submission
867 int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
869 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
872 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
873 r128_update_ring_snapshot( dev_priv );
874 if ( ring->space >= n )
879 /* FIXME: This is being ignored... */
880 DRM_ERROR( "failed!\n" );
881 return DRM_ERR(EBUSY);
884 static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
889 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
890 buf = r128_freelist_get( dev );
891 if ( !buf ) return DRM_ERR(EAGAIN);
895 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
897 return DRM_ERR(EFAULT);
898 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
899 sizeof(buf->total) ) )
900 return DRM_ERR(EFAULT);
907 int r128_cce_buffers( DRM_IOCTL_ARGS )
910 drm_device_dma_t *dma = dev->dma;
912 drm_dma_t __user *argp = (void __user *)data;
915 LOCK_TEST_WITH_RETURN( dev, filp );
917 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
919 /* Please don't send us buffers.
921 if ( d.send_count != 0 ) {
922 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
923 DRM_CURRENTPID, d.send_count );
924 return DRM_ERR(EINVAL);
927 /* We'll send you buffers.
929 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
930 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
931 DRM_CURRENTPID, d.request_count, dma->buf_count );
932 return DRM_ERR(EINVAL);
937 if ( d.request_count ) {
938 ret = r128_cce_get_buffers( filp, dev, &d );
941 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) );