drivers/char/drm/r128_drv.h

   1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Rickard E. (Rik) Faith <faith@valinux.com>
  29  *    Kevin E. Martin <martin@valinux.com>
  30  *    Gareth Hughes <gareth@valinux.com>
  31  *    Michel Dänzer <daenzerm@student.ethz.ch>
  32  */
  33
  34 #ifndef __R128_DRV_H__
  35 #define __R128_DRV_H__
  36
  37 #define GET_RING_HEAD(dev_priv)         R128_READ( R128_PM4_BUFFER_DL_RPTR )
  38
  39 typedef struct drm_r128_freelist {
  40         unsigned int age;
  41         drm_buf_t *buf;
  42         struct drm_r128_freelist *next;
  43         struct drm_r128_freelist *prev;
  44 } drm_r128_freelist_t;
  45
  46 typedef struct drm_r128_ring_buffer {
  47         u32 *start;
  48         u32 *end;
  49         int size;
  50         int size_l2qw;
  51
  52         u32 tail;
  53         u32 tail_mask;
  54         int space;
  55
  56         int high_mark;
  57 } drm_r128_ring_buffer_t;
  58
  59 typedef struct drm_r128_private {
  60         drm_r128_ring_buffer_t ring;
  61         drm_r128_sarea_t *sarea_priv;
  62
  63         int cce_mode;
  64         int cce_fifo_size;
  65         int cce_running;
  66
  67         drm_r128_freelist_t *head;
  68         drm_r128_freelist_t *tail;
  69
  70         int usec_timeout;
  71         int is_pci;
  72         unsigned long phys_pci_gart;
  73         dma_addr_t bus_pci_gart;
  74         unsigned long cce_buffers_offset;
  75
  76         atomic_t idle_count;
  77
  78         int page_flipping;
  79         int current_page;
  80         u32 crtc_offset;
  81         u32 crtc_offset_cntl;
  82
  83         u32 color_fmt;
  84         unsigned int front_offset;
  85         unsigned int front_pitch;
  86         unsigned int back_offset;
  87         unsigned int back_pitch;
  88
  89         u32 depth_fmt;
  90         unsigned int depth_offset;
  91         unsigned int depth_pitch;
  92         unsigned int span_offset;
  93
  94         u32 front_pitch_offset_c;
  95         u32 back_pitch_offset_c;
  96         u32 depth_pitch_offset_c;
  97         u32 span_pitch_offset_c;
  98
  99         drm_local_map_t *sarea;
 100         drm_local_map_t *mmio;
 101         drm_local_map_t *cce_ring;
 102         drm_local_map_t *ring_rptr;
 103         drm_local_map_t *buffers;
 104         drm_local_map_t *agp_textures;
 105 } drm_r128_private_t;
 106
 107 typedef struct drm_r128_buf_priv {
 108         u32 age;
 109         int prim;
 110         int discard;
 111         int dispatched;
 112         drm_r128_freelist_t *list_entry;
 113 } drm_r128_buf_priv_t;
 114
 115                                 /* r128_cce.c */
 116 extern int r128_cce_init( DRM_IOCTL_ARGS );
 117 extern int r128_cce_start( DRM_IOCTL_ARGS );
 118 extern int r128_cce_stop( DRM_IOCTL_ARGS );
 119 extern int r128_cce_reset( DRM_IOCTL_ARGS );
 120 extern int r128_cce_idle( DRM_IOCTL_ARGS );
 121 extern int r128_engine_reset( DRM_IOCTL_ARGS );
 122 extern int r128_fullscreen( DRM_IOCTL_ARGS );
 123 extern int r128_cce_buffers( DRM_IOCTL_ARGS );
 124 extern int r128_getparam( DRM_IOCTL_ARGS );
 125
 126 extern void r128_freelist_reset( drm_device_t *dev );
 127 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
 128
 129 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
 130
 131 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
 132 extern int r128_do_cleanup_cce( drm_device_t *dev );
 133 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
 134
 135                                 /* r128_state.c */
 136 extern int r128_cce_clear( DRM_IOCTL_ARGS );
 137 extern int r128_cce_swap( DRM_IOCTL_ARGS );
 138 extern int r128_cce_flip( DRM_IOCTL_ARGS );
 139 extern int r128_cce_vertex( DRM_IOCTL_ARGS );
 140 extern int r128_cce_indices( DRM_IOCTL_ARGS );
 141 extern int r128_cce_blit( DRM_IOCTL_ARGS );
 142 extern int r128_cce_depth( DRM_IOCTL_ARGS );
 143 extern int r128_cce_stipple( DRM_IOCTL_ARGS );
 144 extern int r128_cce_indirect( DRM_IOCTL_ARGS );
 145
 146
 147 /* Register definitions, register access macros and drmAddMap constants
 148  * for Rage 128 kernel driver.
 149  */
 150
 151 #define R128_AUX_SC_CNTL                0x1660
 152 #       define R128_AUX1_SC_EN                  (1 << 0)
 153 #       define R128_AUX1_SC_MODE_OR             (0 << 1)
 154 #       define R128_AUX1_SC_MODE_NAND           (1 << 1)
 155 #       define R128_AUX2_SC_EN                  (1 << 2)
 156 #       define R128_AUX2_SC_MODE_OR             (0 << 3)
 157 #       define R128_AUX2_SC_MODE_NAND           (1 << 3)
 158 #       define R128_AUX3_SC_EN                  (1 << 4)
 159 #       define R128_AUX3_SC_MODE_OR             (0 << 5)
 160 #       define R128_AUX3_SC_MODE_NAND           (1 << 5)
 161 #define R128_AUX1_SC_LEFT               0x1664
 162 #define R128_AUX1_SC_RIGHT              0x1668
 163 #define R128_AUX1_SC_TOP                0x166c
 164 #define R128_AUX1_SC_BOTTOM             0x1670
 165 #define R128_AUX2_SC_LEFT               0x1674
 166 #define R128_AUX2_SC_RIGHT              0x1678
 167 #define R128_AUX2_SC_TOP                0x167c
 168 #define R128_AUX2_SC_BOTTOM             0x1680
 169 #define R128_AUX3_SC_LEFT               0x1684
 170 #define R128_AUX3_SC_RIGHT              0x1688
 171 #define R128_AUX3_SC_TOP                0x168c
 172 #define R128_AUX3_SC_BOTTOM             0x1690
 173
 174 #define R128_BRUSH_DATA0                0x1480
 175 #define R128_BUS_CNTL                   0x0030
 176 #       define R128_BUS_MASTER_DIS              (1 << 6)
 177
 178 #define R128_CLOCK_CNTL_INDEX           0x0008
 179 #define R128_CLOCK_CNTL_DATA            0x000c
 180 #       define R128_PLL_WR_EN                   (1 << 7)
 181 #define R128_CONSTANT_COLOR_C           0x1d34
 182 #define R128_CRTC_OFFSET                0x0224
 183 #define R128_CRTC_OFFSET_CNTL           0x0228
 184 #       define R128_CRTC_OFFSET_FLIP_CNTL       (1 << 16)
 185
 186 #define R128_DP_GUI_MASTER_CNTL         0x146c
 187 #       define R128_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
 188 #       define R128_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)
 189 #       define R128_GMC_BRUSH_SOLID_COLOR       (13   <<  4)
 190 #       define R128_GMC_BRUSH_NONE              (15   <<  4)
 191 #       define R128_GMC_DST_16BPP               (4    <<  8)
 192 #       define R128_GMC_DST_24BPP               (5    <<  8)
 193 #       define R128_GMC_DST_32BPP               (6    <<  8)
 194 #       define R128_GMC_DST_DATATYPE_SHIFT      8
 195 #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
 196 #       define R128_DP_SRC_SOURCE_MEMORY        (2    << 24)
 197 #       define R128_DP_SRC_SOURCE_HOST_DATA     (3    << 24)
 198 #       define R128_GMC_CLR_CMP_CNTL_DIS        (1    << 28)
 199 #       define R128_GMC_AUX_CLIP_DIS            (1    << 29)
 200 #       define R128_GMC_WR_MSK_DIS              (1    << 30)
 201 #       define R128_ROP3_S                      0x00cc0000
 202 #       define R128_ROP3_P                      0x00f00000
 203 #define R128_DP_WRITE_MASK              0x16cc
 204 #define R128_DST_PITCH_OFFSET_C         0x1c80
 205 #       define R128_DST_TILE                    (1 << 31)
 206
 207 #define R128_GEN_INT_CNTL               0x0040
 208 #       define R128_CRTC_VBLANK_INT_EN          (1 <<  0)
 209 #define R128_GEN_INT_STATUS             0x0044
 210 #       define R128_CRTC_VBLANK_INT             (1 <<  0)
 211 #       define R128_CRTC_VBLANK_INT_AK          (1 <<  0)
 212 #define R128_GEN_RESET_CNTL             0x00f0
 213 #       define R128_SOFT_RESET_GUI              (1 <<  0)
 214
 215 #define R128_GUI_SCRATCH_REG0           0x15e0
 216 #define R128_GUI_SCRATCH_REG1           0x15e4
 217 #define R128_GUI_SCRATCH_REG2           0x15e8
 218 #define R128_GUI_SCRATCH_REG3           0x15ec
 219 #define R128_GUI_SCRATCH_REG4           0x15f0
 220 #define R128_GUI_SCRATCH_REG5           0x15f4
 221
 222 #define R128_GUI_STAT                   0x1740
 223 #       define R128_GUI_FIFOCNT_MASK            0x0fff
 224 #       define R128_GUI_ACTIVE                  (1 << 31)
 225
 226 #define R128_MCLK_CNTL                  0x000f
 227 #       define R128_FORCE_GCP                   (1 << 16)
 228 #       define R128_FORCE_PIPE3D_CP             (1 << 17)
 229 #       define R128_FORCE_RCP                   (1 << 18)
 230
 231 #define R128_PC_GUI_CTLSTAT             0x1748
 232 #define R128_PC_NGUI_CTLSTAT            0x0184
 233 #       define R128_PC_FLUSH_GUI                (3 << 0)
 234 #       define R128_PC_RI_GUI                   (1 << 2)
 235 #       define R128_PC_FLUSH_ALL                0x00ff
 236 #       define R128_PC_BUSY                     (1 << 31)
 237
 238 #define R128_PCI_GART_PAGE              0x017c
 239 #define R128_PRIM_TEX_CNTL_C            0x1cb0
 240
 241 #define R128_SCALE_3D_CNTL              0x1a00
 242 #define R128_SEC_TEX_CNTL_C             0x1d00
 243 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
 244 #define R128_SETUP_CNTL                 0x1bc4
 245 #define R128_STEN_REF_MASK_C            0x1d40
 246
 247 #define R128_TEX_CNTL_C                 0x1c9c
 248 #       define R128_TEX_CACHE_FLUSH             (1 << 23)
 249
 250 #define R128_WAIT_UNTIL                 0x1720
 251 #       define R128_EVENT_CRTC_OFFSET           (1 << 0)
 252 #define R128_WINDOW_XY_OFFSET           0x1bcc
 253
 254
 255 /* CCE registers
 256  */
 257 #define R128_PM4_BUFFER_OFFSET          0x0700
 258 #define R128_PM4_BUFFER_CNTL            0x0704
 259 #       define R128_PM4_MASK                    (15 << 28)
 260 #       define R128_PM4_NONPM4                  (0  << 28)
 261 #       define R128_PM4_192PIO                  (1  << 28)
 262 #       define R128_PM4_192BM                   (2  << 28)
 263 #       define R128_PM4_128PIO_64INDBM          (3  << 28)
 264 #       define R128_PM4_128BM_64INDBM           (4  << 28)
 265 #       define R128_PM4_64PIO_128INDBM          (5  << 28)
 266 #       define R128_PM4_64BM_128INDBM           (6  << 28)
 267 #       define R128_PM4_64PIO_64VCBM_64INDBM    (7  << 28)
 268 #       define R128_PM4_64BM_64VCBM_64INDBM     (8  << 28)
 269 #       define R128_PM4_64PIO_64VCPIO_64INDPIO  (15 << 28)
 270 #       define R128_PM4_BUFFER_CNTL_NOUPDATE    (1  << 27)
 271
 272 #define R128_PM4_BUFFER_WM_CNTL         0x0708
 273 #       define R128_WMA_SHIFT                   0
 274 #       define R128_WMB_SHIFT                   8
 275 #       define R128_WMC_SHIFT                   16
 276 #       define R128_WB_WM_SHIFT                 24
 277
 278 #define R128_PM4_BUFFER_DL_RPTR_ADDR    0x070c
 279 #define R128_PM4_BUFFER_DL_RPTR         0x0710
 280 #define R128_PM4_BUFFER_DL_WPTR         0x0714
 281 #       define R128_PM4_BUFFER_DL_DONE          (1 << 31)
 282
 283 #define R128_PM4_VC_FPU_SETUP           0x071c
 284
 285 #define R128_PM4_IW_INDOFF              0x0738
 286 #define R128_PM4_IW_INDSIZE             0x073c
 287
 288 #define R128_PM4_STAT                   0x07b8
 289 #       define R128_PM4_FIFOCNT_MASK            0x0fff
 290 #       define R128_PM4_BUSY                    (1 << 16)
 291 #       define R128_PM4_GUI_ACTIVE              (1 << 31)
 292
 293 #define R128_PM4_MICROCODE_ADDR         0x07d4
 294 #define R128_PM4_MICROCODE_RADDR        0x07d8
 295 #define R128_PM4_MICROCODE_DATAH        0x07dc
 296 #define R128_PM4_MICROCODE_DATAL        0x07e0
 297
 298 #define R128_PM4_BUFFER_ADDR            0x07f0
 299 #define R128_PM4_MICRO_CNTL             0x07fc
 300 #       define R128_PM4_MICRO_FREERUN           (1 << 30)
 301
 302 #define R128_PM4_FIFO_DATA_EVEN         0x1000
 303 #define R128_PM4_FIFO_DATA_ODD          0x1004
 304
 305
 306 /* CCE command packets
 307  */
 308 #define R128_CCE_PACKET0                0x00000000
 309 #define R128_CCE_PACKET1                0x40000000
 310 #define R128_CCE_PACKET2                0x80000000
 311 #define R128_CCE_PACKET3                0xC0000000
 312 #       define R128_CNTL_HOSTDATA_BLT           0x00009400
 313 #       define R128_CNTL_PAINT_MULTI            0x00009A00
 314 #       define R128_CNTL_BITBLT_MULTI           0x00009B00
 315 #       define R128_3D_RNDR_GEN_INDX_PRIM       0x00002300
 316
 317 #define R128_CCE_PACKET_MASK            0xC0000000
 318 #define R128_CCE_PACKET_COUNT_MASK      0x3fff0000
 319 #define R128_CCE_PACKET0_REG_MASK       0x000007ff
 320 #define R128_CCE_PACKET1_REG0_MASK      0x000007ff
 321 #define R128_CCE_PACKET1_REG1_MASK      0x003ff800
 322
 323 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE         0x00000000
 324 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT        0x00000001
 325 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE         0x00000002
 326 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE    0x00000003
 327 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST     0x00000004
 328 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN      0x00000005
 329 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP    0x00000006
 330 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2    0x00000007
 331 #define R128_CCE_VC_CNTL_PRIM_WALK_IND          0x00000010
 332 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST         0x00000020
 333 #define R128_CCE_VC_CNTL_PRIM_WALK_RING         0x00000030
 334 #define R128_CCE_VC_CNTL_NUM_SHIFT              16
 335
 336 #define R128_DATATYPE_VQ                0
 337 #define R128_DATATYPE_CI4               1
 338 #define R128_DATATYPE_CI8               2
 339 #define R128_DATATYPE_ARGB1555          3
 340 #define R128_DATATYPE_RGB565            4
 341 #define R128_DATATYPE_RGB888            5
 342 #define R128_DATATYPE_ARGB8888          6
 343 #define R128_DATATYPE_RGB332            7
 344 #define R128_DATATYPE_Y8                8
 345 #define R128_DATATYPE_RGB8              9
 346 #define R128_DATATYPE_CI16              10
 347 #define R128_DATATYPE_YVYU422           11
 348 #define R128_DATATYPE_VYUY422           12
 349 #define R128_DATATYPE_AYUV444           14
 350 #define R128_DATATYPE_ARGB4444          15
 351
 352 /* Constants */
 353 #define R128_AGP_OFFSET                 0x02000000
 354
 355 #define R128_WATERMARK_L                16
 356 #define R128_WATERMARK_M                8
 357 #define R128_WATERMARK_N                8
 358 #define R128_WATERMARK_K                128
 359
 360 #define R128_MAX_USEC_TIMEOUT           100000  /* 100 ms */
 361
 362 #define R128_LAST_FRAME_REG             R128_GUI_SCRATCH_REG0
 363 #define R128_LAST_DISPATCH_REG          R128_GUI_SCRATCH_REG1
 364 #define R128_MAX_VB_AGE                 0x7fffffff
 365 #define R128_MAX_VB_VERTS               (0xffff)
 366
 367 #define R128_RING_HIGH_MARK             128
 368
 369 #define R128_PERFORMANCE_BOXES          0
 370
 371 #define R128_READ(reg)          DRM_READ32(  dev_priv->mmio, (reg) )
 372 #define R128_WRITE(reg,val)     DRM_WRITE32( dev_priv->mmio, (reg), (val) )
 373 #define R128_READ8(reg)         DRM_READ8(   dev_priv->mmio, (reg) )
 374 #define R128_WRITE8(reg,val)    DRM_WRITE8(  dev_priv->mmio, (reg), (val) )
 375
 376 #define R128_WRITE_PLL(addr,val)                                        \
 377 do {                                                                    \
 378         R128_WRITE8(R128_CLOCK_CNTL_INDEX,                              \
 379                     ((addr) & 0x1f) | R128_PLL_WR_EN);                  \
 380         R128_WRITE(R128_CLOCK_CNTL_DATA, (val));                        \
 381 } while (0)
 382
 383 extern int R128_READ_PLL(drm_device_t *dev, int addr);
 384
 385
 386 #define CCE_PACKET0( reg, n )           (R128_CCE_PACKET0 |             \
 387                                          ((n) << 16) | ((reg) >> 2))
 388 #define CCE_PACKET1( reg0, reg1 )       (R128_CCE_PACKET1 |             \
 389                                          (((reg1) >> 2) << 11) | ((reg0) >> 2))
 390 #define CCE_PACKET2()                   (R128_CCE_PACKET2)
 391 #define CCE_PACKET3( pkt, n )           (R128_CCE_PACKET3 |             \
 392                                          (pkt) | ((n) << 16))
 393
 394
 395 static __inline__ void
 396 r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
 397 {
 398         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
 399         ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32);
 400         if ( ring->space <= 0 )
 401                 ring->space += ring->size;
 402 }
 403
 404 /* ================================================================
 405  * Misc helper macros
 406  */
 407
 408 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )                         \
 409 do {                                                                    \
 410         drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;          \
 411         if ( ring->space < ring->high_mark ) {                          \
 412                 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {      \
 413                         r128_update_ring_snapshot( dev_priv );          \
 414                         if ( ring->space >= ring->high_mark )           \
 415                                 goto __ring_space_done;                 \
 416                         DRM_UDELAY(1);                          \
 417                 }                                                       \
 418                 DRM_ERROR( "ring space check failed!\n" );              \
 419                 return DRM_ERR(EBUSY);                          \
 420         }                                                               \
 421  __ring_space_done:                                                     \
 422         ;                                                               \
 423 } while (0)
 424
 425 #define VB_AGE_TEST_WITH_RETURN( dev_priv )                             \
 426 do {                                                                    \
 427         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;            \
 428         if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) {           \
 429                 int __ret = r128_do_cce_idle( dev_priv );               \
 430                 if ( __ret ) return __ret;                              \
 431                 sarea_priv->last_dispatch = 0;                          \
 432                 r128_freelist_reset( dev );                             \
 433         }                                                               \
 434 } while (0)
 435
 436 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do {                             \
 437         OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) );                  \
 438         OUT_RING( R128_EVENT_CRTC_OFFSET );                             \
 439 } while (0)
 440
 441
 442 /* ================================================================
 443  * Ring control
 444  */
 445
 446 #define R128_VERBOSE    0
 447
 448 #define RING_LOCALS                                                     \
 449         int write, _nr; unsigned int tail_mask; volatile u32 *ring;
 450
 451 #define BEGIN_RING( n ) do {                                            \
 452         if ( R128_VERBOSE ) {                                           \
 453                 DRM_INFO( "BEGIN_RING( %d ) in %s\n",                   \
 454                            (n), __FUNCTION__ );                         \
 455         }                                                               \
 456         if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {              \
 457                 COMMIT_RING();                                          \
 458                 r128_wait_ring( dev_priv, (n) * sizeof(u32) );          \
 459         }                                                               \
 460         _nr = n; dev_priv->ring.space -= (n) * sizeof(u32);             \
 461         ring = dev_priv->ring.start;                                    \
 462         write = dev_priv->ring.tail;                                    \
 463         tail_mask = dev_priv->ring.tail_mask;                           \
 464 } while (0)
 465
 466 /* You can set this to zero if you want.  If the card locks up, you'll
 467  * need to keep this set.  It works around a bug in early revs of the
 468  * Rage 128 chipset, where the CCE would read 32 dwords past the end of
 469  * the ring buffer before wrapping around.
 470  */
 471 #define R128_BROKEN_CCE 1
 472
 473 #define ADVANCE_RING() do {                                             \
 474         if ( R128_VERBOSE ) {                                           \
 475                 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",     \
 476                           write, dev_priv->ring.tail );                 \
 477         }                                                               \
 478         if ( R128_BROKEN_CCE && write < 32 ) {                          \
 479                 memcpy( dev_priv->ring.end,                             \
 480                         dev_priv->ring.start,                           \
 481                         write * sizeof(u32) );                          \
 482         }                                                               \
 483         if (((dev_priv->ring.tail + _nr) & tail_mask) != write) {       \
 484                 DRM_ERROR(                                              \
 485                         "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",        \
 486                         ((dev_priv->ring.tail + _nr) & tail_mask),      \
 487                         write, __LINE__);                               \
 488         } else                                                          \
 489                 dev_priv->ring.tail = write;                            \
 490 } while (0)
 491
 492 #define COMMIT_RING() do {                                              \
 493         if ( R128_VERBOSE ) {                                           \
 494                 DRM_INFO( "COMMIT_RING() tail=0x%06x\n",                \
 495                         dev_priv->ring.tail );                          \
 496         }                                                               \
 497         DRM_MEMORYBARRIER();                                            \
 498         R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail );     \
 499         R128_READ( R128_PM4_BUFFER_DL_WPTR );                           \
 500 } while (0)
 501
 502 #define OUT_RING( x ) do {                                              \
 503         if ( R128_VERBOSE ) {                                           \
 504                 DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",            \
 505                            (unsigned int)(x), write );                  \
 506         }                                                               \
 507         ring[write++] = cpu_to_le32( x );                               \
 508         write &= tail_mask;                                             \
 509 } while (0)
 510
 511 #endif /* __R128_DRV_H__ */