1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel D�zer <daenzerm@student.ethz.ch>
34 #ifndef __R128_DRV_H__
35 #define __R128_DRV_H__
37 /* General customization:
39 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
41 #define DRIVER_NAME "r128"
42 #define DRIVER_DESC "ATI Rage 128"
43 #define DRIVER_DATE "20030725"
48 * 2.4 - Add support for ycbcr textures (no new ioctls)
49 * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
51 #define DRIVER_MAJOR 2
52 #define DRIVER_MINOR 5
53 #define DRIVER_PATCHLEVEL 0
56 #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR )
58 typedef struct drm_r128_freelist {
61 struct drm_r128_freelist *next;
62 struct drm_r128_freelist *prev;
63 } drm_r128_freelist_t;
65 typedef struct drm_r128_ring_buffer {
76 } drm_r128_ring_buffer_t;
78 typedef struct drm_r128_private {
79 drm_r128_ring_buffer_t ring;
80 drm_r128_sarea_t *sarea_priv;
86 drm_r128_freelist_t *head;
87 drm_r128_freelist_t *tail;
91 unsigned long phys_pci_gart;
92 dma_addr_t bus_pci_gart;
93 unsigned long cce_buffers_offset;
100 u32 crtc_offset_cntl;
103 unsigned int front_offset;
104 unsigned int front_pitch;
105 unsigned int back_offset;
106 unsigned int back_pitch;
109 unsigned int depth_offset;
110 unsigned int depth_pitch;
111 unsigned int span_offset;
113 u32 front_pitch_offset_c;
114 u32 back_pitch_offset_c;
115 u32 depth_pitch_offset_c;
116 u32 span_pitch_offset_c;
118 drm_local_map_t *sarea;
119 drm_local_map_t *mmio;
120 drm_local_map_t *cce_ring;
121 drm_local_map_t *ring_rptr;
122 drm_local_map_t *agp_textures;
123 } drm_r128_private_t;
125 typedef struct drm_r128_buf_priv {
130 drm_r128_freelist_t *list_entry;
131 } drm_r128_buf_priv_t;
134 extern int r128_cce_init( DRM_IOCTL_ARGS );
135 extern int r128_cce_start( DRM_IOCTL_ARGS );
136 extern int r128_cce_stop( DRM_IOCTL_ARGS );
137 extern int r128_cce_reset( DRM_IOCTL_ARGS );
138 extern int r128_cce_idle( DRM_IOCTL_ARGS );
139 extern int r128_engine_reset( DRM_IOCTL_ARGS );
140 extern int r128_fullscreen( DRM_IOCTL_ARGS );
141 extern int r128_cce_buffers( DRM_IOCTL_ARGS );
142 extern int r128_getparam( DRM_IOCTL_ARGS );
144 extern void r128_freelist_reset( drm_device_t *dev );
145 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
147 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
149 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
150 extern int r128_do_cleanup_cce( drm_device_t *dev );
151 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
154 extern int r128_cce_clear( DRM_IOCTL_ARGS );
155 extern int r128_cce_swap( DRM_IOCTL_ARGS );
156 extern int r128_cce_flip( DRM_IOCTL_ARGS );
157 extern int r128_cce_vertex( DRM_IOCTL_ARGS );
158 extern int r128_cce_indices( DRM_IOCTL_ARGS );
159 extern int r128_cce_blit( DRM_IOCTL_ARGS );
160 extern int r128_cce_depth( DRM_IOCTL_ARGS );
161 extern int r128_cce_stipple( DRM_IOCTL_ARGS );
162 extern int r128_cce_indirect( DRM_IOCTL_ARGS );
164 extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
166 extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS );
167 extern void r128_driver_irq_preinstall( drm_device_t *dev );
168 extern void r128_driver_irq_postinstall( drm_device_t *dev );
169 extern void r128_driver_irq_uninstall( drm_device_t *dev );
170 extern void r128_driver_pretakedown(drm_device_t *dev);
171 extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
173 /* Register definitions, register access macros and drmAddMap constants
174 * for Rage 128 kernel driver.
177 #define R128_AUX_SC_CNTL 0x1660
178 # define R128_AUX1_SC_EN (1 << 0)
179 # define R128_AUX1_SC_MODE_OR (0 << 1)
180 # define R128_AUX1_SC_MODE_NAND (1 << 1)
181 # define R128_AUX2_SC_EN (1 << 2)
182 # define R128_AUX2_SC_MODE_OR (0 << 3)
183 # define R128_AUX2_SC_MODE_NAND (1 << 3)
184 # define R128_AUX3_SC_EN (1 << 4)
185 # define R128_AUX3_SC_MODE_OR (0 << 5)
186 # define R128_AUX3_SC_MODE_NAND (1 << 5)
187 #define R128_AUX1_SC_LEFT 0x1664
188 #define R128_AUX1_SC_RIGHT 0x1668
189 #define R128_AUX1_SC_TOP 0x166c
190 #define R128_AUX1_SC_BOTTOM 0x1670
191 #define R128_AUX2_SC_LEFT 0x1674
192 #define R128_AUX2_SC_RIGHT 0x1678
193 #define R128_AUX2_SC_TOP 0x167c
194 #define R128_AUX2_SC_BOTTOM 0x1680
195 #define R128_AUX3_SC_LEFT 0x1684
196 #define R128_AUX3_SC_RIGHT 0x1688
197 #define R128_AUX3_SC_TOP 0x168c
198 #define R128_AUX3_SC_BOTTOM 0x1690
200 #define R128_BRUSH_DATA0 0x1480
201 #define R128_BUS_CNTL 0x0030
202 # define R128_BUS_MASTER_DIS (1 << 6)
204 #define R128_CLOCK_CNTL_INDEX 0x0008
205 #define R128_CLOCK_CNTL_DATA 0x000c
206 # define R128_PLL_WR_EN (1 << 7)
207 #define R128_CONSTANT_COLOR_C 0x1d34
208 #define R128_CRTC_OFFSET 0x0224
209 #define R128_CRTC_OFFSET_CNTL 0x0228
210 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
212 #define R128_DP_GUI_MASTER_CNTL 0x146c
213 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
214 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
215 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
216 # define R128_GMC_BRUSH_NONE (15 << 4)
217 # define R128_GMC_DST_16BPP (4 << 8)
218 # define R128_GMC_DST_24BPP (5 << 8)
219 # define R128_GMC_DST_32BPP (6 << 8)
220 # define R128_GMC_DST_DATATYPE_SHIFT 8
221 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
222 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
223 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
224 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
225 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
226 # define R128_GMC_WR_MSK_DIS (1 << 30)
227 # define R128_ROP3_S 0x00cc0000
228 # define R128_ROP3_P 0x00f00000
229 #define R128_DP_WRITE_MASK 0x16cc
230 #define R128_DST_PITCH_OFFSET_C 0x1c80
231 # define R128_DST_TILE (1 << 31)
233 #define R128_GEN_INT_CNTL 0x0040
234 # define R128_CRTC_VBLANK_INT_EN (1 << 0)
235 #define R128_GEN_INT_STATUS 0x0044
236 # define R128_CRTC_VBLANK_INT (1 << 0)
237 # define R128_CRTC_VBLANK_INT_AK (1 << 0)
238 #define R128_GEN_RESET_CNTL 0x00f0
239 # define R128_SOFT_RESET_GUI (1 << 0)
241 #define R128_GUI_SCRATCH_REG0 0x15e0
242 #define R128_GUI_SCRATCH_REG1 0x15e4
243 #define R128_GUI_SCRATCH_REG2 0x15e8
244 #define R128_GUI_SCRATCH_REG3 0x15ec
245 #define R128_GUI_SCRATCH_REG4 0x15f0
246 #define R128_GUI_SCRATCH_REG5 0x15f4
248 #define R128_GUI_STAT 0x1740
249 # define R128_GUI_FIFOCNT_MASK 0x0fff
250 # define R128_GUI_ACTIVE (1 << 31)
252 #define R128_MCLK_CNTL 0x000f
253 # define R128_FORCE_GCP (1 << 16)
254 # define R128_FORCE_PIPE3D_CP (1 << 17)
255 # define R128_FORCE_RCP (1 << 18)
257 #define R128_PC_GUI_CTLSTAT 0x1748
258 #define R128_PC_NGUI_CTLSTAT 0x0184
259 # define R128_PC_FLUSH_GUI (3 << 0)
260 # define R128_PC_RI_GUI (1 << 2)
261 # define R128_PC_FLUSH_ALL 0x00ff
262 # define R128_PC_BUSY (1 << 31)
264 #define R128_PCI_GART_PAGE 0x017c
265 #define R128_PRIM_TEX_CNTL_C 0x1cb0
267 #define R128_SCALE_3D_CNTL 0x1a00
268 #define R128_SEC_TEX_CNTL_C 0x1d00
269 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
270 #define R128_SETUP_CNTL 0x1bc4
271 #define R128_STEN_REF_MASK_C 0x1d40
273 #define R128_TEX_CNTL_C 0x1c9c
274 # define R128_TEX_CACHE_FLUSH (1 << 23)
276 #define R128_WAIT_UNTIL 0x1720
277 # define R128_EVENT_CRTC_OFFSET (1 << 0)
278 #define R128_WINDOW_XY_OFFSET 0x1bcc
283 #define R128_PM4_BUFFER_OFFSET 0x0700
284 #define R128_PM4_BUFFER_CNTL 0x0704
285 # define R128_PM4_MASK (15 << 28)
286 # define R128_PM4_NONPM4 (0 << 28)
287 # define R128_PM4_192PIO (1 << 28)
288 # define R128_PM4_192BM (2 << 28)
289 # define R128_PM4_128PIO_64INDBM (3 << 28)
290 # define R128_PM4_128BM_64INDBM (4 << 28)
291 # define R128_PM4_64PIO_128INDBM (5 << 28)
292 # define R128_PM4_64BM_128INDBM (6 << 28)
293 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
294 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
295 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
296 # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27)
298 #define R128_PM4_BUFFER_WM_CNTL 0x0708
299 # define R128_WMA_SHIFT 0
300 # define R128_WMB_SHIFT 8
301 # define R128_WMC_SHIFT 16
302 # define R128_WB_WM_SHIFT 24
304 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
305 #define R128_PM4_BUFFER_DL_RPTR 0x0710
306 #define R128_PM4_BUFFER_DL_WPTR 0x0714
307 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
309 #define R128_PM4_VC_FPU_SETUP 0x071c
311 #define R128_PM4_IW_INDOFF 0x0738
312 #define R128_PM4_IW_INDSIZE 0x073c
314 #define R128_PM4_STAT 0x07b8
315 # define R128_PM4_FIFOCNT_MASK 0x0fff
316 # define R128_PM4_BUSY (1 << 16)
317 # define R128_PM4_GUI_ACTIVE (1 << 31)
319 #define R128_PM4_MICROCODE_ADDR 0x07d4
320 #define R128_PM4_MICROCODE_RADDR 0x07d8
321 #define R128_PM4_MICROCODE_DATAH 0x07dc
322 #define R128_PM4_MICROCODE_DATAL 0x07e0
324 #define R128_PM4_BUFFER_ADDR 0x07f0
325 #define R128_PM4_MICRO_CNTL 0x07fc
326 # define R128_PM4_MICRO_FREERUN (1 << 30)
328 #define R128_PM4_FIFO_DATA_EVEN 0x1000
329 #define R128_PM4_FIFO_DATA_ODD 0x1004
332 /* CCE command packets
334 #define R128_CCE_PACKET0 0x00000000
335 #define R128_CCE_PACKET1 0x40000000
336 #define R128_CCE_PACKET2 0x80000000
337 #define R128_CCE_PACKET3 0xC0000000
338 # define R128_CNTL_HOSTDATA_BLT 0x00009400
339 # define R128_CNTL_PAINT_MULTI 0x00009A00
340 # define R128_CNTL_BITBLT_MULTI 0x00009B00
341 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
343 #define R128_CCE_PACKET_MASK 0xC0000000
344 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
345 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
346 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
347 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
349 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
350 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
351 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
352 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
353 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
354 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
355 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
356 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
357 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
358 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
359 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
360 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
362 #define R128_DATATYPE_VQ 0
363 #define R128_DATATYPE_CI4 1
364 #define R128_DATATYPE_CI8 2
365 #define R128_DATATYPE_ARGB1555 3
366 #define R128_DATATYPE_RGB565 4
367 #define R128_DATATYPE_RGB888 5
368 #define R128_DATATYPE_ARGB8888 6
369 #define R128_DATATYPE_RGB332 7
370 #define R128_DATATYPE_Y8 8
371 #define R128_DATATYPE_RGB8 9
372 #define R128_DATATYPE_CI16 10
373 #define R128_DATATYPE_YVYU422 11
374 #define R128_DATATYPE_VYUY422 12
375 #define R128_DATATYPE_AYUV444 14
376 #define R128_DATATYPE_ARGB4444 15
379 #define R128_AGP_OFFSET 0x02000000
381 #define R128_WATERMARK_L 16
382 #define R128_WATERMARK_M 8
383 #define R128_WATERMARK_N 8
384 #define R128_WATERMARK_K 128
386 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
388 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
389 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
390 #define R128_MAX_VB_AGE 0x7fffffff
391 #define R128_MAX_VB_VERTS (0xffff)
393 #define R128_RING_HIGH_MARK 128
395 #define R128_PERFORMANCE_BOXES 0
397 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
398 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
399 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
400 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
402 #define R128_WRITE_PLL(addr,val) \
404 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
405 ((addr) & 0x1f) | R128_PLL_WR_EN); \
406 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
409 extern int R128_READ_PLL(drm_device_t *dev, int addr);
412 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
413 ((n) << 16) | ((reg) >> 2))
414 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
415 (((reg1) >> 2) << 11) | ((reg0) >> 2))
416 #define CCE_PACKET2() (R128_CCE_PACKET2)
417 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
421 static __inline__ void
422 r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
424 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
425 ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32);
426 if ( ring->space <= 0 )
427 ring->space += ring->size;
430 /* ================================================================
434 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
436 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
437 if ( ring->space < ring->high_mark ) { \
438 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
439 r128_update_ring_snapshot( dev_priv ); \
440 if ( ring->space >= ring->high_mark ) \
441 goto __ring_space_done; \
444 DRM_ERROR( "ring space check failed!\n" ); \
445 return DRM_ERR(EBUSY); \
451 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
453 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
454 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
455 int __ret = r128_do_cce_idle( dev_priv ); \
456 if ( __ret ) return __ret; \
457 sarea_priv->last_dispatch = 0; \
458 r128_freelist_reset( dev ); \
462 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
463 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
464 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
468 /* ================================================================
472 #define R128_VERBOSE 0
474 #define RING_LOCALS \
475 int write, _nr; unsigned int tail_mask; volatile u32 *ring;
477 #define BEGIN_RING( n ) do { \
478 if ( R128_VERBOSE ) { \
479 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
480 (n), __FUNCTION__ ); \
482 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
484 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
486 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
487 ring = dev_priv->ring.start; \
488 write = dev_priv->ring.tail; \
489 tail_mask = dev_priv->ring.tail_mask; \
492 /* You can set this to zero if you want. If the card locks up, you'll
493 * need to keep this set. It works around a bug in early revs of the
494 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
495 * the ring buffer before wrapping around.
497 #define R128_BROKEN_CCE 1
499 #define ADVANCE_RING() do { \
500 if ( R128_VERBOSE ) { \
501 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
502 write, dev_priv->ring.tail ); \
504 if ( R128_BROKEN_CCE && write < 32 ) { \
505 memcpy( dev_priv->ring.end, \
506 dev_priv->ring.start, \
507 write * sizeof(u32) ); \
509 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
511 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
512 ((dev_priv->ring.tail + _nr) & tail_mask), \
515 dev_priv->ring.tail = write; \
518 #define COMMIT_RING() do { \
519 if ( R128_VERBOSE ) { \
520 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \
521 dev_priv->ring.tail ); \
523 DRM_MEMORYBARRIER(); \
524 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \
525 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \
528 #define OUT_RING( x ) do { \
529 if ( R128_VERBOSE ) { \
530 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
531 (unsigned int)(x), write ); \
533 ring[write++] = cpu_to_le32( x ); \
534 write &= tail_mask; \
537 #endif /* __R128_DRV_H__ */