drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35
  36 #define RADEON_FIFO_DEBUG       0
  37
  38
  39 /* CP microcode (from ATI) */
  40 static u32 R200_cp_microcode[][2] = {
  41         { 0x21007000, 0000000000 },
  42         { 0x20007000, 0000000000 },
  43         { 0x000000ab, 0x00000004 },
  44         { 0x000000af, 0x00000004 },
  45         { 0x66544a49, 0000000000 },
  46         { 0x49494174, 0000000000 },
  47         { 0x54517d83, 0000000000 },
  48         { 0x498d8b64, 0000000000 },
  49         { 0x49494949, 0000000000 },
  50         { 0x49da493c, 0000000000 },
  51         { 0x49989898, 0000000000 },
  52         { 0xd34949d5, 0000000000 },
  53         { 0x9dc90e11, 0000000000 },
  54         { 0xce9b9b9b, 0000000000 },
  55         { 0x000f0000, 0x00000016 },
  56         { 0x352e232c, 0000000000 },
  57         { 0x00000013, 0x00000004 },
  58         { 0x000f0000, 0x00000016 },
  59         { 0x352e272c, 0000000000 },
  60         { 0x000f0001, 0x00000016 },
  61         { 0x3239362f, 0000000000 },
  62         { 0x000077ef, 0x00000002 },
  63         { 0x00061000, 0x00000002 },
  64         { 0x00000020, 0x0000001a },
  65         { 0x00004000, 0x0000001e },
  66         { 0x00061000, 0x00000002 },
  67         { 0x00000020, 0x0000001a },
  68         { 0x00004000, 0x0000001e },
  69         { 0x00061000, 0x00000002 },
  70         { 0x00000020, 0x0000001a },
  71         { 0x00004000, 0x0000001e },
  72         { 0x00000016, 0x00000004 },
  73         { 0x0003802a, 0x00000002 },
  74         { 0x040067e0, 0x00000002 },
  75         { 0x00000016, 0x00000004 },
  76         { 0x000077e0, 0x00000002 },
  77         { 0x00065000, 0x00000002 },
  78         { 0x000037e1, 0x00000002 },
  79         { 0x040067e1, 0x00000006 },
  80         { 0x000077e0, 0x00000002 },
  81         { 0x000077e1, 0x00000002 },
  82         { 0x000077e1, 0x00000006 },
  83         { 0xffffffff, 0000000000 },
  84         { 0x10000000, 0000000000 },
  85         { 0x0003802a, 0x00000002 },
  86         { 0x040067e0, 0x00000006 },
  87         { 0x00007675, 0x00000002 },
  88         { 0x00007676, 0x00000002 },
  89         { 0x00007677, 0x00000002 },
  90         { 0x00007678, 0x00000006 },
  91         { 0x0003802b, 0x00000002 },
  92         { 0x04002676, 0x00000002 },
  93         { 0x00007677, 0x00000002 },
  94         { 0x00007678, 0x00000006 },
  95         { 0x0000002e, 0x00000018 },
  96         { 0x0000002e, 0x00000018 },
  97         { 0000000000, 0x00000006 },
  98         { 0x0000002f, 0x00000018 },
  99         { 0x0000002f, 0x00000018 },
 100         { 0000000000, 0x00000006 },
 101         { 0x01605000, 0x00000002 },
 102         { 0x00065000, 0x00000002 },
 103         { 0x00098000, 0x00000002 },
 104         { 0x00061000, 0x00000002 },
 105         { 0x64c0603d, 0x00000004 },
 106         { 0x00080000, 0x00000016 },
 107         { 0000000000, 0000000000 },
 108         { 0x0400251d, 0x00000002 },
 109         { 0x00007580, 0x00000002 },
 110         { 0x00067581, 0x00000002 },
 111         { 0x04002580, 0x00000002 },
 112         { 0x00067581, 0x00000002 },
 113         { 0x00000046, 0x00000004 },
 114         { 0x00005000, 0000000000 },
 115         { 0x00061000, 0x00000002 },
 116         { 0x0000750e, 0x00000002 },
 117         { 0x00019000, 0x00000002 },
 118         { 0x00011055, 0x00000014 },
 119         { 0x00000055, 0x00000012 },
 120         { 0x0400250f, 0x00000002 },
 121         { 0x0000504a, 0x00000004 },
 122         { 0x00007565, 0x00000002 },
 123         { 0x00007566, 0x00000002 },
 124         { 0x00000051, 0x00000004 },
 125         { 0x01e655b4, 0x00000002 },
 126         { 0x4401b0dc, 0x00000002 },
 127         { 0x01c110dc, 0x00000002 },
 128         { 0x2666705d, 0x00000018 },
 129         { 0x040c2565, 0x00000002 },
 130         { 0x0000005d, 0x00000018 },
 131         { 0x04002564, 0x00000002 },
 132         { 0x00007566, 0x00000002 },
 133         { 0x00000054, 0x00000004 },
 134         { 0x00401060, 0x00000008 },
 135         { 0x00101000, 0x00000002 },
 136         { 0x000d80ff, 0x00000002 },
 137         { 0x00800063, 0x00000008 },
 138         { 0x000f9000, 0x00000002 },
 139         { 0x000e00ff, 0x00000002 },
 140         { 0000000000, 0x00000006 },
 141         { 0x00000080, 0x00000018 },
 142         { 0x00000054, 0x00000004 },
 143         { 0x00007576, 0x00000002 },
 144         { 0x00065000, 0x00000002 },
 145         { 0x00009000, 0x00000002 },
 146         { 0x00041000, 0x00000002 },
 147         { 0x0c00350e, 0x00000002 },
 148         { 0x00049000, 0x00000002 },
 149         { 0x00051000, 0x00000002 },
 150         { 0x01e785f8, 0x00000002 },
 151         { 0x00200000, 0x00000002 },
 152         { 0x00600073, 0x0000000c },
 153         { 0x00007563, 0x00000002 },
 154         { 0x006075f0, 0x00000021 },
 155         { 0x20007068, 0x00000004 },
 156         { 0x00005068, 0x00000004 },
 157         { 0x00007576, 0x00000002 },
 158         { 0x00007577, 0x00000002 },
 159         { 0x0000750e, 0x00000002 },
 160         { 0x0000750f, 0x00000002 },
 161         { 0x00a05000, 0x00000002 },
 162         { 0x00600076, 0x0000000c },
 163         { 0x006075f0, 0x00000021 },
 164         { 0x000075f8, 0x00000002 },
 165         { 0x00000076, 0x00000004 },
 166         { 0x000a750e, 0x00000002 },
 167         { 0x0020750f, 0x00000002 },
 168         { 0x00600079, 0x00000004 },
 169         { 0x00007570, 0x00000002 },
 170         { 0x00007571, 0x00000002 },
 171         { 0x00007572, 0x00000006 },
 172         { 0x00005000, 0x00000002 },
 173         { 0x00a05000, 0x00000002 },
 174         { 0x00007568, 0x00000002 },
 175         { 0x00061000, 0x00000002 },
 176         { 0x00000084, 0x0000000c },
 177         { 0x00058000, 0x00000002 },
 178         { 0x0c607562, 0x00000002 },
 179         { 0x00000086, 0x00000004 },
 180         { 0x00600085, 0x00000004 },
 181         { 0x400070dd, 0000000000 },
 182         { 0x000380dd, 0x00000002 },
 183         { 0x00000093, 0x0000001c },
 184         { 0x00065095, 0x00000018 },
 185         { 0x040025bb, 0x00000002 },
 186         { 0x00061096, 0x00000018 },
 187         { 0x040075bc, 0000000000 },
 188         { 0x000075bb, 0x00000002 },
 189         { 0x000075bc, 0000000000 },
 190         { 0x00090000, 0x00000006 },
 191         { 0x00090000, 0x00000002 },
 192         { 0x000d8002, 0x00000006 },
 193         { 0x00005000, 0x00000002 },
 194         { 0x00007821, 0x00000002 },
 195         { 0x00007800, 0000000000 },
 196         { 0x00007821, 0x00000002 },
 197         { 0x00007800, 0000000000 },
 198         { 0x01665000, 0x00000002 },
 199         { 0x000a0000, 0x00000002 },
 200         { 0x000671cc, 0x00000002 },
 201         { 0x0286f1cd, 0x00000002 },
 202         { 0x000000a3, 0x00000010 },
 203         { 0x21007000, 0000000000 },
 204         { 0x000000aa, 0x0000001c },
 205         { 0x00065000, 0x00000002 },
 206         { 0x000a0000, 0x00000002 },
 207         { 0x00061000, 0x00000002 },
 208         { 0x000b0000, 0x00000002 },
 209         { 0x38067000, 0x00000002 },
 210         { 0x000a00a6, 0x00000004 },
 211         { 0x20007000, 0000000000 },
 212         { 0x01200000, 0x00000002 },
 213         { 0x20077000, 0x00000002 },
 214         { 0x01200000, 0x00000002 },
 215         { 0x20007000, 0000000000 },
 216         { 0x00061000, 0x00000002 },
 217         { 0x0120751b, 0x00000002 },
 218         { 0x8040750a, 0x00000002 },
 219         { 0x8040750b, 0x00000002 },
 220         { 0x00110000, 0x00000002 },
 221         { 0x000380dd, 0x00000002 },
 222         { 0x000000bd, 0x0000001c },
 223         { 0x00061096, 0x00000018 },
 224         { 0x844075bd, 0x00000002 },
 225         { 0x00061095, 0x00000018 },
 226         { 0x840075bb, 0x00000002 },
 227         { 0x00061096, 0x00000018 },
 228         { 0x844075bc, 0x00000002 },
 229         { 0x000000c0, 0x00000004 },
 230         { 0x804075bd, 0x00000002 },
 231         { 0x800075bb, 0x00000002 },
 232         { 0x804075bc, 0x00000002 },
 233         { 0x00108000, 0x00000002 },
 234         { 0x01400000, 0x00000002 },
 235         { 0x006000c4, 0x0000000c },
 236         { 0x20c07000, 0x00000020 },
 237         { 0x000000c6, 0x00000012 },
 238         { 0x00800000, 0x00000006 },
 239         { 0x0080751d, 0x00000006 },
 240         { 0x000025bb, 0x00000002 },
 241         { 0x000040c0, 0x00000004 },
 242         { 0x0000775c, 0x00000002 },
 243         { 0x00a05000, 0x00000002 },
 244         { 0x00661000, 0x00000002 },
 245         { 0x0460275d, 0x00000020 },
 246         { 0x00004000, 0000000000 },
 247         { 0x00007999, 0x00000002 },
 248         { 0x00a05000, 0x00000002 },
 249         { 0x00661000, 0x00000002 },
 250         { 0x0460299b, 0x00000020 },
 251         { 0x00004000, 0000000000 },
 252         { 0x01e00830, 0x00000002 },
 253         { 0x21007000, 0000000000 },
 254         { 0x00005000, 0x00000002 },
 255         { 0x00038042, 0x00000002 },
 256         { 0x040025e0, 0x00000002 },
 257         { 0x000075e1, 0000000000 },
 258         { 0x00000001, 0000000000 },
 259         { 0x000380d9, 0x00000002 },
 260         { 0x04007394, 0000000000 },
 261         { 0000000000, 0000000000 },
 262         { 0000000000, 0000000000 },
 263         { 0000000000, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297 };
 298
 299
 300 static u32 radeon_cp_microcode[][2] = {
 301         { 0x21007000, 0000000000 },
 302         { 0x20007000, 0000000000 },
 303         { 0x000000b4, 0x00000004 },
 304         { 0x000000b8, 0x00000004 },
 305         { 0x6f5b4d4c, 0000000000 },
 306         { 0x4c4c427f, 0000000000 },
 307         { 0x5b568a92, 0000000000 },
 308         { 0x4ca09c6d, 0000000000 },
 309         { 0xad4c4c4c, 0000000000 },
 310         { 0x4ce1af3d, 0000000000 },
 311         { 0xd8afafaf, 0000000000 },
 312         { 0xd64c4cdc, 0000000000 },
 313         { 0x4cd10d10, 0000000000 },
 314         { 0x000f0000, 0x00000016 },
 315         { 0x362f242d, 0000000000 },
 316         { 0x00000012, 0x00000004 },
 317         { 0x000f0000, 0x00000016 },
 318         { 0x362f282d, 0000000000 },
 319         { 0x000380e7, 0x00000002 },
 320         { 0x04002c97, 0x00000002 },
 321         { 0x000f0001, 0x00000016 },
 322         { 0x333a3730, 0000000000 },
 323         { 0x000077ef, 0x00000002 },
 324         { 0x00061000, 0x00000002 },
 325         { 0x00000021, 0x0000001a },
 326         { 0x00004000, 0x0000001e },
 327         { 0x00061000, 0x00000002 },
 328         { 0x00000021, 0x0000001a },
 329         { 0x00004000, 0x0000001e },
 330         { 0x00061000, 0x00000002 },
 331         { 0x00000021, 0x0000001a },
 332         { 0x00004000, 0x0000001e },
 333         { 0x00000017, 0x00000004 },
 334         { 0x0003802b, 0x00000002 },
 335         { 0x040067e0, 0x00000002 },
 336         { 0x00000017, 0x00000004 },
 337         { 0x000077e0, 0x00000002 },
 338         { 0x00065000, 0x00000002 },
 339         { 0x000037e1, 0x00000002 },
 340         { 0x040067e1, 0x00000006 },
 341         { 0x000077e0, 0x00000002 },
 342         { 0x000077e1, 0x00000002 },
 343         { 0x000077e1, 0x00000006 },
 344         { 0xffffffff, 0000000000 },
 345         { 0x10000000, 0000000000 },
 346         { 0x0003802b, 0x00000002 },
 347         { 0x040067e0, 0x00000006 },
 348         { 0x00007675, 0x00000002 },
 349         { 0x00007676, 0x00000002 },
 350         { 0x00007677, 0x00000002 },
 351         { 0x00007678, 0x00000006 },
 352         { 0x0003802c, 0x00000002 },
 353         { 0x04002676, 0x00000002 },
 354         { 0x00007677, 0x00000002 },
 355         { 0x00007678, 0x00000006 },
 356         { 0x0000002f, 0x00000018 },
 357         { 0x0000002f, 0x00000018 },
 358         { 0000000000, 0x00000006 },
 359         { 0x00000030, 0x00000018 },
 360         { 0x00000030, 0x00000018 },
 361         { 0000000000, 0x00000006 },
 362         { 0x01605000, 0x00000002 },
 363         { 0x00065000, 0x00000002 },
 364         { 0x00098000, 0x00000002 },
 365         { 0x00061000, 0x00000002 },
 366         { 0x64c0603e, 0x00000004 },
 367         { 0x000380e6, 0x00000002 },
 368         { 0x040025c5, 0x00000002 },
 369         { 0x00080000, 0x00000016 },
 370         { 0000000000, 0000000000 },
 371         { 0x0400251d, 0x00000002 },
 372         { 0x00007580, 0x00000002 },
 373         { 0x00067581, 0x00000002 },
 374         { 0x04002580, 0x00000002 },
 375         { 0x00067581, 0x00000002 },
 376         { 0x00000049, 0x00000004 },
 377         { 0x00005000, 0000000000 },
 378         { 0x000380e6, 0x00000002 },
 379         { 0x040025c5, 0x00000002 },
 380         { 0x00061000, 0x00000002 },
 381         { 0x0000750e, 0x00000002 },
 382         { 0x00019000, 0x00000002 },
 383         { 0x00011055, 0x00000014 },
 384         { 0x00000055, 0x00000012 },
 385         { 0x0400250f, 0x00000002 },
 386         { 0x0000504f, 0x00000004 },
 387         { 0x000380e6, 0x00000002 },
 388         { 0x040025c5, 0x00000002 },
 389         { 0x00007565, 0x00000002 },
 390         { 0x00007566, 0x00000002 },
 391         { 0x00000058, 0x00000004 },
 392         { 0x000380e6, 0x00000002 },
 393         { 0x040025c5, 0x00000002 },
 394         { 0x01e655b4, 0x00000002 },
 395         { 0x4401b0e4, 0x00000002 },
 396         { 0x01c110e4, 0x00000002 },
 397         { 0x26667066, 0x00000018 },
 398         { 0x040c2565, 0x00000002 },
 399         { 0x00000066, 0x00000018 },
 400         { 0x04002564, 0x00000002 },
 401         { 0x00007566, 0x00000002 },
 402         { 0x0000005d, 0x00000004 },
 403         { 0x00401069, 0x00000008 },
 404         { 0x00101000, 0x00000002 },
 405         { 0x000d80ff, 0x00000002 },
 406         { 0x0080006c, 0x00000008 },
 407         { 0x000f9000, 0x00000002 },
 408         { 0x000e00ff, 0x00000002 },
 409         { 0000000000, 0x00000006 },
 410         { 0x0000008f, 0x00000018 },
 411         { 0x0000005b, 0x00000004 },
 412         { 0x000380e6, 0x00000002 },
 413         { 0x040025c5, 0x00000002 },
 414         { 0x00007576, 0x00000002 },
 415         { 0x00065000, 0x00000002 },
 416         { 0x00009000, 0x00000002 },
 417         { 0x00041000, 0x00000002 },
 418         { 0x0c00350e, 0x00000002 },
 419         { 0x00049000, 0x00000002 },
 420         { 0x00051000, 0x00000002 },
 421         { 0x01e785f8, 0x00000002 },
 422         { 0x00200000, 0x00000002 },
 423         { 0x0060007e, 0x0000000c },
 424         { 0x00007563, 0x00000002 },
 425         { 0x006075f0, 0x00000021 },
 426         { 0x20007073, 0x00000004 },
 427         { 0x00005073, 0x00000004 },
 428         { 0x000380e6, 0x00000002 },
 429         { 0x040025c5, 0x00000002 },
 430         { 0x00007576, 0x00000002 },
 431         { 0x00007577, 0x00000002 },
 432         { 0x0000750e, 0x00000002 },
 433         { 0x0000750f, 0x00000002 },
 434         { 0x00a05000, 0x00000002 },
 435         { 0x00600083, 0x0000000c },
 436         { 0x006075f0, 0x00000021 },
 437         { 0x000075f8, 0x00000002 },
 438         { 0x00000083, 0x00000004 },
 439         { 0x000a750e, 0x00000002 },
 440         { 0x000380e6, 0x00000002 },
 441         { 0x040025c5, 0x00000002 },
 442         { 0x0020750f, 0x00000002 },
 443         { 0x00600086, 0x00000004 },
 444         { 0x00007570, 0x00000002 },
 445         { 0x00007571, 0x00000002 },
 446         { 0x00007572, 0x00000006 },
 447         { 0x000380e6, 0x00000002 },
 448         { 0x040025c5, 0x00000002 },
 449         { 0x00005000, 0x00000002 },
 450         { 0x00a05000, 0x00000002 },
 451         { 0x00007568, 0x00000002 },
 452         { 0x00061000, 0x00000002 },
 453         { 0x00000095, 0x0000000c },
 454         { 0x00058000, 0x00000002 },
 455         { 0x0c607562, 0x00000002 },
 456         { 0x00000097, 0x00000004 },
 457         { 0x000380e6, 0x00000002 },
 458         { 0x040025c5, 0x00000002 },
 459         { 0x00600096, 0x00000004 },
 460         { 0x400070e5, 0000000000 },
 461         { 0x000380e6, 0x00000002 },
 462         { 0x040025c5, 0x00000002 },
 463         { 0x000380e5, 0x00000002 },
 464         { 0x000000a8, 0x0000001c },
 465         { 0x000650aa, 0x00000018 },
 466         { 0x040025bb, 0x00000002 },
 467         { 0x000610ab, 0x00000018 },
 468         { 0x040075bc, 0000000000 },
 469         { 0x000075bb, 0x00000002 },
 470         { 0x000075bc, 0000000000 },
 471         { 0x00090000, 0x00000006 },
 472         { 0x00090000, 0x00000002 },
 473         { 0x000d8002, 0x00000006 },
 474         { 0x00007832, 0x00000002 },
 475         { 0x00005000, 0x00000002 },
 476         { 0x000380e7, 0x00000002 },
 477         { 0x04002c97, 0x00000002 },
 478         { 0x00007820, 0x00000002 },
 479         { 0x00007821, 0x00000002 },
 480         { 0x00007800, 0000000000 },
 481         { 0x01200000, 0x00000002 },
 482         { 0x20077000, 0x00000002 },
 483         { 0x01200000, 0x00000002 },
 484         { 0x20007000, 0x00000002 },
 485         { 0x00061000, 0x00000002 },
 486         { 0x0120751b, 0x00000002 },
 487         { 0x8040750a, 0x00000002 },
 488         { 0x8040750b, 0x00000002 },
 489         { 0x00110000, 0x00000002 },
 490         { 0x000380e5, 0x00000002 },
 491         { 0x000000c6, 0x0000001c },
 492         { 0x000610ab, 0x00000018 },
 493         { 0x844075bd, 0x00000002 },
 494         { 0x000610aa, 0x00000018 },
 495         { 0x840075bb, 0x00000002 },
 496         { 0x000610ab, 0x00000018 },
 497         { 0x844075bc, 0x00000002 },
 498         { 0x000000c9, 0x00000004 },
 499         { 0x804075bd, 0x00000002 },
 500         { 0x800075bb, 0x00000002 },
 501         { 0x804075bc, 0x00000002 },
 502         { 0x00108000, 0x00000002 },
 503         { 0x01400000, 0x00000002 },
 504         { 0x006000cd, 0x0000000c },
 505         { 0x20c07000, 0x00000020 },
 506         { 0x000000cf, 0x00000012 },
 507         { 0x00800000, 0x00000006 },
 508         { 0x0080751d, 0x00000006 },
 509         { 0000000000, 0000000000 },
 510         { 0x0000775c, 0x00000002 },
 511         { 0x00a05000, 0x00000002 },
 512         { 0x00661000, 0x00000002 },
 513         { 0x0460275d, 0x00000020 },
 514         { 0x00004000, 0000000000 },
 515         { 0x01e00830, 0x00000002 },
 516         { 0x21007000, 0000000000 },
 517         { 0x6464614d, 0000000000 },
 518         { 0x69687420, 0000000000 },
 519         { 0x00000073, 0000000000 },
 520         { 0000000000, 0000000000 },
 521         { 0x00005000, 0x00000002 },
 522         { 0x000380d0, 0x00000002 },
 523         { 0x040025e0, 0x00000002 },
 524         { 0x000075e1, 0000000000 },
 525         { 0x00000001, 0000000000 },
 526         { 0x000380e0, 0x00000002 },
 527         { 0x04002394, 0x00000002 },
 528         { 0x00005000, 0000000000 },
 529         { 0000000000, 0000000000 },
 530         { 0000000000, 0000000000 },
 531         { 0x00000008, 0000000000 },
 532         { 0x00000004, 0000000000 },
 533         { 0000000000, 0000000000 },
 534         { 0000000000, 0000000000 },
 535         { 0000000000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557 };
 558
 559 static u32 R300_cp_microcode[][2] = {
 560         { 0x4200e000, 0000000000 },
 561         { 0x4000e000, 0000000000 },
 562         { 0x000000af, 0x00000008 },
 563         { 0x000000b3, 0x00000008 },
 564         { 0x6c5a504f, 0000000000 },
 565         { 0x4f4f497a, 0000000000 },
 566         { 0x5a578288, 0000000000 },
 567         { 0x4f91906a, 0000000000 },
 568         { 0x4f4f4f4f, 0000000000 },
 569         { 0x4fe24f44, 0000000000 },
 570         { 0x4f9c9c9c, 0000000000 },
 571         { 0xdc4f4fde, 0000000000 },
 572         { 0xa1cd4f4f, 0000000000 },
 573         { 0xd29d9d9d, 0000000000 },
 574         { 0x4f0f9fd7, 0000000000 },
 575         { 0x000ca000, 0x00000004 },
 576         { 0x000d0012, 0x00000038 },
 577         { 0x0000e8b4, 0x00000004 },
 578         { 0x000d0014, 0x00000038 },
 579         { 0x0000e8b6, 0x00000004 },
 580         { 0x000d0016, 0x00000038 },
 581         { 0x0000e854, 0x00000004 },
 582         { 0x000d0018, 0x00000038 },
 583         { 0x0000e855, 0x00000004 },
 584         { 0x000d001a, 0x00000038 },
 585         { 0x0000e856, 0x00000004 },
 586         { 0x000d001c, 0x00000038 },
 587         { 0x0000e857, 0x00000004 },
 588         { 0x000d001e, 0x00000038 },
 589         { 0x0000e824, 0x00000004 },
 590         { 0x000d0020, 0x00000038 },
 591         { 0x0000e825, 0x00000004 },
 592         { 0x000d0022, 0x00000038 },
 593         { 0x0000e830, 0x00000004 },
 594         { 0x000d0024, 0x00000038 },
 595         { 0x0000f0c0, 0x00000004 },
 596         { 0x000d0026, 0x00000038 },
 597         { 0x0000f0c1, 0x00000004 },
 598         { 0x000d0028, 0x00000038 },
 599         { 0x0000f041, 0x00000004 },
 600         { 0x000d002a, 0x00000038 },
 601         { 0x0000f184, 0x00000004 },
 602         { 0x000d002c, 0x00000038 },
 603         { 0x0000f185, 0x00000004 },
 604         { 0x000d002e, 0x00000038 },
 605         { 0x0000f186, 0x00000004 },
 606         { 0x000d0030, 0x00000038 },
 607         { 0x0000f187, 0x00000004 },
 608         { 0x000d0032, 0x00000038 },
 609         { 0x0000f180, 0x00000004 },
 610         { 0x000d0034, 0x00000038 },
 611         { 0x0000f393, 0x00000004 },
 612         { 0x000d0036, 0x00000038 },
 613         { 0x0000f38a, 0x00000004 },
 614         { 0x000d0038, 0x00000038 },
 615         { 0x0000f38e, 0x00000004 },
 616         { 0x0000e821, 0x00000004 },
 617         { 0x0140a000, 0x00000004 },
 618         { 0x00000043, 0x00000018 },
 619         { 0x00cce800, 0x00000004 },
 620         { 0x001b0001, 0x00000004 },
 621         { 0x08004800, 0x00000004 },
 622         { 0x001b0001, 0x00000004 },
 623         { 0x08004800, 0x00000004 },
 624         { 0x001b0001, 0x00000004 },
 625         { 0x08004800, 0x00000004 },
 626         { 0x0000003a, 0x00000008 },
 627         { 0x0000a000, 0000000000 },
 628         { 0x02c0a000, 0x00000004 },
 629         { 0x000ca000, 0x00000004 },
 630         { 0x00130000, 0x00000004 },
 631         { 0x000c2000, 0x00000004 },
 632         { 0xc980c045, 0x00000008 },
 633         { 0x2000451d, 0x00000004 },
 634         { 0x0000e580, 0x00000004 },
 635         { 0x000ce581, 0x00000004 },
 636         { 0x08004580, 0x00000004 },
 637         { 0x000ce581, 0x00000004 },
 638         { 0x0000004c, 0x00000008 },
 639         { 0x0000a000, 0000000000 },
 640         { 0x000c2000, 0x00000004 },
 641         { 0x0000e50e, 0x00000004 },
 642         { 0x00032000, 0x00000004 },
 643         { 0x00022056, 0x00000028 },
 644         { 0x00000056, 0x00000024 },
 645         { 0x0800450f, 0x00000004 },
 646         { 0x0000a050, 0x00000008 },
 647         { 0x0000e565, 0x00000004 },
 648         { 0x0000e566, 0x00000004 },
 649         { 0x00000057, 0x00000008 },
 650         { 0x03cca5b4, 0x00000004 },
 651         { 0x05432000, 0x00000004 },
 652         { 0x00022000, 0x00000004 },
 653         { 0x4ccce063, 0x00000030 },
 654         { 0x08274565, 0x00000004 },
 655         { 0x00000063, 0x00000030 },
 656         { 0x08004564, 0x00000004 },
 657         { 0x0000e566, 0x00000004 },
 658         { 0x0000005a, 0x00000008 },
 659         { 0x00802066, 0x00000010 },
 660         { 0x00202000, 0x00000004 },
 661         { 0x001b00ff, 0x00000004 },
 662         { 0x01000069, 0x00000010 },
 663         { 0x001f2000, 0x00000004 },
 664         { 0x001c00ff, 0x00000004 },
 665         { 0000000000, 0x0000000c },
 666         { 0x00000085, 0x00000030 },
 667         { 0x0000005a, 0x00000008 },
 668         { 0x0000e576, 0x00000004 },
 669         { 0x000ca000, 0x00000004 },
 670         { 0x00012000, 0x00000004 },
 671         { 0x00082000, 0x00000004 },
 672         { 0x1800650e, 0x00000004 },
 673         { 0x00092000, 0x00000004 },
 674         { 0x000a2000, 0x00000004 },
 675         { 0x000f0000, 0x00000004 },
 676         { 0x00400000, 0x00000004 },
 677         { 0x00000079, 0x00000018 },
 678         { 0x0000e563, 0x00000004 },
 679         { 0x00c0e5f9, 0x000000c2 },
 680         { 0x0000006e, 0x00000008 },
 681         { 0x0000a06e, 0x00000008 },
 682         { 0x0000e576, 0x00000004 },
 683         { 0x0000e577, 0x00000004 },
 684         { 0x0000e50e, 0x00000004 },
 685         { 0x0000e50f, 0x00000004 },
 686         { 0x0140a000, 0x00000004 },
 687         { 0x0000007c, 0x00000018 },
 688         { 0x00c0e5f9, 0x000000c2 },
 689         { 0x0000007c, 0x00000008 },
 690         { 0x0014e50e, 0x00000004 },
 691         { 0x0040e50f, 0x00000004 },
 692         { 0x00c0007f, 0x00000008 },
 693         { 0x0000e570, 0x00000004 },
 694         { 0x0000e571, 0x00000004 },
 695         { 0x0000e572, 0x0000000c },
 696         { 0x0000a000, 0x00000004 },
 697         { 0x0140a000, 0x00000004 },
 698         { 0x0000e568, 0x00000004 },
 699         { 0x000c2000, 0x00000004 },
 700         { 0x00000089, 0x00000018 },
 701         { 0x000b0000, 0x00000004 },
 702         { 0x18c0e562, 0x00000004 },
 703         { 0x0000008b, 0x00000008 },
 704         { 0x00c0008a, 0x00000008 },
 705         { 0x000700e4, 0x00000004 },
 706         { 0x00000097, 0x00000038 },
 707         { 0x000ca099, 0x00000030 },
 708         { 0x080045bb, 0x00000004 },
 709         { 0x000c209a, 0x00000030 },
 710         { 0x0800e5bc, 0000000000 },
 711         { 0x0000e5bb, 0x00000004 },
 712         { 0x0000e5bc, 0000000000 },
 713         { 0x00120000, 0x0000000c },
 714         { 0x00120000, 0x00000004 },
 715         { 0x001b0002, 0x0000000c },
 716         { 0x0000a000, 0x00000004 },
 717         { 0x0000e821, 0x00000004 },
 718         { 0x0000e800, 0000000000 },
 719         { 0x0000e821, 0x00000004 },
 720         { 0x0000e82e, 0000000000 },
 721         { 0x02cca000, 0x00000004 },
 722         { 0x00140000, 0x00000004 },
 723         { 0x000ce1cc, 0x00000004 },
 724         { 0x050de1cd, 0x00000004 },
 725         { 0x000000a7, 0x00000020 },
 726         { 0x4200e000, 0000000000 },
 727         { 0x000000ae, 0x00000038 },
 728         { 0x000ca000, 0x00000004 },
 729         { 0x00140000, 0x00000004 },
 730         { 0x000c2000, 0x00000004 },
 731         { 0x00160000, 0x00000004 },
 732         { 0x700ce000, 0x00000004 },
 733         { 0x001400aa, 0x00000008 },
 734         { 0x4000e000, 0000000000 },
 735         { 0x02400000, 0x00000004 },
 736         { 0x400ee000, 0x00000004 },
 737         { 0x02400000, 0x00000004 },
 738         { 0x4000e000, 0000000000 },
 739         { 0x000c2000, 0x00000004 },
 740         { 0x0240e51b, 0x00000004 },
 741         { 0x0080e50a, 0x00000005 },
 742         { 0x0080e50b, 0x00000005 },
 743         { 0x00220000, 0x00000004 },
 744         { 0x000700e4, 0x00000004 },
 745         { 0x000000c1, 0x00000038 },
 746         { 0x000c209a, 0x00000030 },
 747         { 0x0880e5bd, 0x00000005 },
 748         { 0x000c2099, 0x00000030 },
 749         { 0x0800e5bb, 0x00000005 },
 750         { 0x000c209a, 0x00000030 },
 751         { 0x0880e5bc, 0x00000005 },
 752         { 0x000000c4, 0x00000008 },
 753         { 0x0080e5bd, 0x00000005 },
 754         { 0x0000e5bb, 0x00000005 },
 755         { 0x0080e5bc, 0x00000005 },
 756         { 0x00210000, 0x00000004 },
 757         { 0x02800000, 0x00000004 },
 758         { 0x00c000c8, 0x00000018 },
 759         { 0x4180e000, 0x00000040 },
 760         { 0x000000ca, 0x00000024 },
 761         { 0x01000000, 0x0000000c },
 762         { 0x0100e51d, 0x0000000c },
 763         { 0x000045bb, 0x00000004 },
 764         { 0x000080c4, 0x00000008 },
 765         { 0x0000f3ce, 0x00000004 },
 766         { 0x0140a000, 0x00000004 },
 767         { 0x00cc2000, 0x00000004 },
 768         { 0x08c053cf, 0x00000040 },
 769         { 0x00008000, 0000000000 },
 770         { 0x0000f3d2, 0x00000004 },
 771         { 0x0140a000, 0x00000004 },
 772         { 0x00cc2000, 0x00000004 },
 773         { 0x08c053d3, 0x00000040 },
 774         { 0x00008000, 0000000000 },
 775         { 0x0000f39d, 0x00000004 },
 776         { 0x0140a000, 0x00000004 },
 777         { 0x00cc2000, 0x00000004 },
 778         { 0x08c0539e, 0x00000040 },
 779         { 0x00008000, 0000000000 },
 780         { 0x03c00830, 0x00000004 },
 781         { 0x4200e000, 0000000000 },
 782         { 0x0000a000, 0x00000004 },
 783         { 0x200045e0, 0x00000004 },
 784         { 0x0000e5e1, 0000000000 },
 785         { 0x00000001, 0000000000 },
 786         { 0x000700e1, 0x00000004 },
 787         { 0x0800e394, 0000000000 },
 788         { 0000000000, 0000000000 },
 789         { 0000000000, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816 };
 817
 818 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 819 {
 820         drm_radeon_private_t *dev_priv = dev->dev_private;
 821
 822         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 823         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 824 }
 825
 826 #if RADEON_FIFO_DEBUG
 827 static void radeon_status( drm_radeon_private_t *dev_priv )
 828 {
 829         printk( "%s:\n", __FUNCTION__ );
 830         printk( "RBBM_STATUS = 0x%08x\n",
 831                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 832         printk( "CP_RB_RTPR = 0x%08x\n",
 833                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 834         printk( "CP_RB_WTPR = 0x%08x\n",
 835                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 836         printk( "AIC_CNTL = 0x%08x\n",
 837                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 838         printk( "AIC_STAT = 0x%08x\n",
 839                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 840         printk( "AIC_PT_BASE = 0x%08x\n",
 841                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 842         printk( "TLB_ADDR = 0x%08x\n",
 843                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 844         printk( "TLB_DATA = 0x%08x\n",
 845                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 846 }
 847 #endif
 848
 849
 850 /* ================================================================
 851  * Engine, FIFO control
 852  */
 853
 854 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 855 {
 856         u32 tmp;
 857         int i;
 858
 859         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 860
 861         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 862         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 863         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 864
 865         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 866                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 867                        & RADEON_RB2D_DC_BUSY) ) {
 868                         return 0;
 869                 }
 870                 DRM_UDELAY( 1 );
 871         }
 872
 873 #if RADEON_FIFO_DEBUG
 874         DRM_ERROR( "failed!\n" );
 875         radeon_status( dev_priv );
 876 #endif
 877         return DRM_ERR(EBUSY);
 878 }
 879
 880 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 881                                     int entries )
 882 {
 883         int i;
 884
 885         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 886
 887         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 888                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 889                               & RADEON_RBBM_FIFOCNT_MASK );
 890                 if ( slots >= entries ) return 0;
 891                 DRM_UDELAY( 1 );
 892         }
 893
 894 #if RADEON_FIFO_DEBUG
 895         DRM_ERROR( "failed!\n" );
 896         radeon_status( dev_priv );
 897 #endif
 898         return DRM_ERR(EBUSY);
 899 }
 900
 901 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 902 {
 903         int i, ret;
 904
 905         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 906
 907         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 908         if ( ret ) return ret;
 909
 910         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 911                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 912                        & RADEON_RBBM_ACTIVE) ) {
 913                         radeon_do_pixcache_flush( dev_priv );
 914                         return 0;
 915                 }
 916                 DRM_UDELAY( 1 );
 917         }
 918
 919 #if RADEON_FIFO_DEBUG
 920         DRM_ERROR( "failed!\n" );
 921         radeon_status( dev_priv );
 922 #endif
 923         return DRM_ERR(EBUSY);
 924 }
 925
 926
 927 /* ================================================================
 928  * CP control, initialization
 929  */
 930
 931 /* Load the microcode for the CP */
 932 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 933 {
 934         int i;
 935         DRM_DEBUG( "\n" );
 936
 937         radeon_do_wait_for_idle( dev_priv );
 938
 939         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 940
 941         if (dev_priv->microcode_version==UCODE_R200) {
 942                 DRM_INFO("Loading R200 Microcode\n");
 943                 for ( i = 0 ; i < 256 ; i++ )
 944                 {
 945                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 946                                       R200_cp_microcode[i][1] );
 947                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 948                                       R200_cp_microcode[i][0] );
 949                 }
 950         } else if (dev_priv->microcode_version==UCODE_R300) {
 951                 DRM_INFO("Loading R300 Microcode\n");
 952                 for ( i = 0 ; i < 256 ; i++ )
 953                 {
 954                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 955                                       R300_cp_microcode[i][1] );
 956                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 957                                       R300_cp_microcode[i][0] );
 958                 }
 959         } else {
 960                 for ( i = 0 ; i < 256 ; i++ ) {
 961                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 962                                       radeon_cp_microcode[i][1] );
 963                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 964                                       radeon_cp_microcode[i][0] );
 965                 }
 966         }
 967 }
 968
 969 /* Flush any pending commands to the CP.  This should only be used just
 970  * prior to a wait for idle, as it informs the engine that the command
 971  * stream is ending.
 972  */
 973 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 974 {
 975         DRM_DEBUG( "\n" );
 976 #if 0
 977         u32 tmp;
 978
 979         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 980         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 981 #endif
 982 }
 983
 984 /* Wait for the CP to go idle.
 985  */
 986 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 987 {
 988         RING_LOCALS;
 989         DRM_DEBUG( "\n" );
 990
 991         BEGIN_RING( 6 );
 992
 993         RADEON_PURGE_CACHE();
 994         RADEON_PURGE_ZCACHE();
 995         RADEON_WAIT_UNTIL_IDLE();
 996
 997         ADVANCE_RING();
 998         COMMIT_RING();
 999
1000         return radeon_do_wait_for_idle( dev_priv );
1001 }
1002
1003 /* Start the Command Processor.
1004  */
1005 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1006 {
1007         RING_LOCALS;
1008         DRM_DEBUG( "\n" );
1009
1010         radeon_do_wait_for_idle( dev_priv );
1011
1012         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
1013
1014         dev_priv->cp_running = 1;
1015
1016         BEGIN_RING( 6 );
1017
1018         RADEON_PURGE_CACHE();
1019         RADEON_PURGE_ZCACHE();
1020         RADEON_WAIT_UNTIL_IDLE();
1021
1022         ADVANCE_RING();
1023         COMMIT_RING();
1024 }
1025
1026 /* Reset the Command Processor.  This will not flush any pending
1027  * commands, so you must wait for the CP command stream to complete
1028  * before calling this routine.
1029  */
1030 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1031 {
1032         u32 cur_read_ptr;
1033         DRM_DEBUG( "\n" );
1034
1035         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1036         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1037         SET_RING_HEAD( dev_priv, cur_read_ptr );
1038         dev_priv->ring.tail = cur_read_ptr;
1039 }
1040
1041 /* Stop the Command Processor.  This will not flush any pending
1042  * commands, so you must flush the command stream and wait for the CP
1043  * to go idle before calling this routine.
1044  */
1045 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
1046 {
1047         DRM_DEBUG( "\n" );
1048
1049         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
1050
1051         dev_priv->cp_running = 0;
1052 }
1053
1054 /* Reset the engine.  This will stop the CP if it is running.
1055  */
1056 static int radeon_do_engine_reset( drm_device_t *dev )
1057 {
1058         drm_radeon_private_t *dev_priv = dev->dev_private;
1059         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1060         DRM_DEBUG( "\n" );
1061
1062         radeon_do_pixcache_flush( dev_priv );
1063
1064         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1065         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1066
1067         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1068                                               RADEON_FORCEON_MCLKA |
1069                                               RADEON_FORCEON_MCLKB |
1070                                               RADEON_FORCEON_YCLKA |
1071                                               RADEON_FORCEON_YCLKB |
1072                                               RADEON_FORCEON_MC |
1073                                               RADEON_FORCEON_AIC ) );
1074
1075         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1076
1077         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
1078                                                 RADEON_SOFT_RESET_CP |
1079                                                 RADEON_SOFT_RESET_HI |
1080                                                 RADEON_SOFT_RESET_SE |
1081                                                 RADEON_SOFT_RESET_RE |
1082                                                 RADEON_SOFT_RESET_PP |
1083                                                 RADEON_SOFT_RESET_E2 |
1084                                                 RADEON_SOFT_RESET_RB ) );
1085         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1086         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
1087                                                 ~( RADEON_SOFT_RESET_CP |
1088                                                    RADEON_SOFT_RESET_HI |
1089                                                    RADEON_SOFT_RESET_SE |
1090                                                    RADEON_SOFT_RESET_RE |
1091                                                    RADEON_SOFT_RESET_PP |
1092                                                    RADEON_SOFT_RESET_E2 |
1093                                                    RADEON_SOFT_RESET_RB ) ) );
1094         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1095
1096
1097         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1098         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1099         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
1100
1101         /* Reset the CP ring */
1102         radeon_do_cp_reset( dev_priv );
1103
1104         /* The CP is no longer running after an engine reset */
1105         dev_priv->cp_running = 0;
1106
1107         /* Reset any pending vertex, indirect buffers */
1108         radeon_freelist_reset( dev );
1109
1110         return 0;
1111 }
1112
1113 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1114                                         drm_radeon_private_t *dev_priv )
1115 {
1116         u32 ring_start, cur_read_ptr;
1117         u32 tmp;
1118
1119         /* Initialize the memory controller */
1120         RADEON_WRITE( RADEON_MC_FB_LOCATION,
1121                       ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
1122                     | ( dev_priv->fb_location >> 16 ) );
1123
1124 #if __OS_HAS_AGP
1125         if ( !dev_priv->is_pci ) {
1126                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
1127                               (((dev_priv->gart_vm_start - 1 +
1128                                  dev_priv->gart_size) & 0xffff0000) |
1129                                (dev_priv->gart_vm_start >> 16)) );
1130
1131                 ring_start = (dev_priv->cp_ring->offset
1132                               - dev->agp->base
1133                               + dev_priv->gart_vm_start);
1134        } else
1135 #endif
1136                 ring_start = (dev_priv->cp_ring->offset
1137                               - dev->sg->handle
1138                               + dev_priv->gart_vm_start);
1139
1140         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
1141
1142         /* Set the write pointer delay */
1143         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
1144
1145         /* Initialize the ring buffer's read and write pointers */
1146         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1147         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1148         SET_RING_HEAD( dev_priv, cur_read_ptr );
1149         dev_priv->ring.tail = cur_read_ptr;
1150
1151 #if __OS_HAS_AGP
1152         if ( !dev_priv->is_pci ) {
1153                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1154                               dev_priv->ring_rptr->offset
1155                               - dev->agp->base
1156                               + dev_priv->gart_vm_start);
1157         } else
1158 #endif
1159         {
1160                 drm_sg_mem_t *entry = dev->sg;
1161                 unsigned long tmp_ofs, page_ofs;
1162
1163                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1164                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1165
1166                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1167                              entry->busaddr[page_ofs]);
1168                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
1169                            (unsigned long) entry->busaddr[page_ofs],
1170                            entry->handle + tmp_ofs );
1171         }
1172
1173         /* Initialize the scratch register pointer.  This will cause
1174          * the scratch register values to be written out to memory
1175          * whenever they are updated.
1176          *
1177          * We simply put this behind the ring read pointer, this works
1178          * with PCI GART as well as (whatever kind of) AGP GART
1179          */
1180         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
1181                                          + RADEON_SCRATCH_REG_OFFSET );
1182
1183         dev_priv->scratch = ((__volatile__ u32 *)
1184                              dev_priv->ring_rptr->handle +
1185                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1186
1187         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
1188
1189         /* Writeback doesn't seem to work everywhere, test it first */
1190         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
1191         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
1192
1193         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
1194                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
1195                         break;
1196                 DRM_UDELAY( 1 );
1197         }
1198
1199         if ( tmp < dev_priv->usec_timeout ) {
1200                 dev_priv->writeback_works = 1;
1201                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
1202         } else {
1203                 dev_priv->writeback_works = 0;
1204                 DRM_DEBUG( "writeback test failed\n" );
1205         }
1206
1207         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1208         RADEON_WRITE( RADEON_LAST_FRAME_REG,
1209                       dev_priv->sarea_priv->last_frame );
1210
1211         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1212         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
1213                       dev_priv->sarea_priv->last_dispatch );
1214
1215         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1216         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
1217                       dev_priv->sarea_priv->last_clear );
1218
1219         /* Set ring buffer size */
1220 #ifdef __BIG_ENDIAN
1221         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
1222 #else
1223         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
1224 #endif
1225
1226         radeon_do_wait_for_idle( dev_priv );
1227
1228         /* Turn on bus mastering */
1229         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
1230         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
1231
1232         /* Sync everything up */
1233         RADEON_WRITE( RADEON_ISYNC_CNTL,
1234                       (RADEON_ISYNC_ANY2D_IDLE3D |
1235                        RADEON_ISYNC_ANY3D_IDLE2D |
1236                        RADEON_ISYNC_WAIT_IDLEGUI |
1237                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
1238 }
1239
1240 /* Enable or disable PCI GART on the chip */
1241 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1242 {
1243         u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
1244
1245         if ( on ) {
1246                 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
1247
1248                 /* set PCI GART page-table base address
1249                  */
1250                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1251
1252                 /* set address range for PCI address translate
1253                  */
1254                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
1255                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1256                                                   + dev_priv->gart_size - 1);
1257
1258                 /* Turn off AGP aperture -- is this required for PCI GART?
1259                  */
1260                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1261                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1262         } else {
1263                 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1264         }
1265 }
1266
1267 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1268 {
1269         drm_radeon_private_t *dev_priv = dev->dev_private;;
1270         DRM_DEBUG( "\n" );
1271
1272         dev_priv->is_pci = init->is_pci;
1273
1274         if ( dev_priv->is_pci && !dev->sg ) {
1275                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1276                 dev->dev_private = (void *)dev_priv;
1277                 radeon_do_cleanup_cp(dev);
1278                 return DRM_ERR(EINVAL);
1279         }
1280
1281         dev_priv->usec_timeout = init->usec_timeout;
1282         if ( dev_priv->usec_timeout < 1 ||
1283              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1284                 DRM_DEBUG( "TIMEOUT problem!\n" );
1285                 dev->dev_private = (void *)dev_priv;
1286                 radeon_do_cleanup_cp(dev);
1287                 return DRM_ERR(EINVAL);
1288         }
1289
1290         switch(init->func) {
1291         case RADEON_INIT_R200_CP:
1292                 dev_priv->microcode_version=UCODE_R200;
1293                 break;
1294         case RADEON_INIT_R300_CP:
1295                 dev_priv->microcode_version=UCODE_R300;
1296                 break;
1297         default:
1298                 dev_priv->microcode_version=UCODE_R100;
1299         }
1300
1301         dev_priv->do_boxes = 0;
1302         dev_priv->cp_mode = init->cp_mode;
1303
1304         /* We don't support anything other than bus-mastering ring mode,
1305          * but the ring can be in either AGP or PCI space for the ring
1306          * read pointer.
1307          */
1308         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1309              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1310                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1311                 dev->dev_private = (void *)dev_priv;
1312                 radeon_do_cleanup_cp(dev);
1313                 return DRM_ERR(EINVAL);
1314         }
1315
1316         switch ( init->fb_bpp ) {
1317         case 16:
1318                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1319                 break;
1320         case 32:
1321         default:
1322                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1323                 break;
1324         }
1325         dev_priv->front_offset  = init->front_offset;
1326         dev_priv->front_pitch   = init->front_pitch;
1327         dev_priv->back_offset   = init->back_offset;
1328         dev_priv->back_pitch    = init->back_pitch;
1329
1330         switch ( init->depth_bpp ) {
1331         case 16:
1332                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1333                 break;
1334         case 32:
1335         default:
1336                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1337                 break;
1338         }
1339         dev_priv->depth_offset  = init->depth_offset;
1340         dev_priv->depth_pitch   = init->depth_pitch;
1341
1342         /* Hardware state for depth clears.  Remove this if/when we no
1343          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1344          * all values to prevent unwanted 3D state from slipping through
1345          * and screwing with the clear operation.
1346          */
1347         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1348                                            (dev_priv->color_fmt << 10) |
1349                                            (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1350
1351         dev_priv->depth_clear.rb3d_zstencilcntl =
1352                 (dev_priv->depth_fmt |
1353                  RADEON_Z_TEST_ALWAYS |
1354                  RADEON_STENCIL_TEST_ALWAYS |
1355                  RADEON_STENCIL_S_FAIL_REPLACE |
1356                  RADEON_STENCIL_ZPASS_REPLACE |
1357                  RADEON_STENCIL_ZFAIL_REPLACE |
1358                  RADEON_Z_WRITE_ENABLE);
1359
1360         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1361                                          RADEON_BFACE_SOLID |
1362                                          RADEON_FFACE_SOLID |
1363                                          RADEON_FLAT_SHADE_VTX_LAST |
1364                                          RADEON_DIFFUSE_SHADE_FLAT |
1365                                          RADEON_ALPHA_SHADE_FLAT |
1366                                          RADEON_SPECULAR_SHADE_FLAT |
1367                                          RADEON_FOG_SHADE_FLAT |
1368                                          RADEON_VTX_PIX_CENTER_OGL |
1369                                          RADEON_ROUND_MODE_TRUNC |
1370                                          RADEON_ROUND_PREC_8TH_PIX);
1371
1372         DRM_GETSAREA();
1373
1374         dev_priv->fb_offset = init->fb_offset;
1375         dev_priv->mmio_offset = init->mmio_offset;
1376         dev_priv->ring_offset = init->ring_offset;
1377         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1378         dev_priv->buffers_offset = init->buffers_offset;
1379         dev_priv->gart_textures_offset = init->gart_textures_offset;
1380
1381         if(!dev_priv->sarea) {
1382                 DRM_ERROR("could not find sarea!\n");
1383                 dev->dev_private = (void *)dev_priv;
1384                 radeon_do_cleanup_cp(dev);
1385                 return DRM_ERR(EINVAL);
1386         }
1387
1388         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1389         if(!dev_priv->mmio) {
1390                 DRM_ERROR("could not find mmio region!\n");
1391                 dev->dev_private = (void *)dev_priv;
1392                 radeon_do_cleanup_cp(dev);
1393                 return DRM_ERR(EINVAL);
1394         }
1395         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1396         if(!dev_priv->cp_ring) {
1397                 DRM_ERROR("could not find cp ring region!\n");
1398                 dev->dev_private = (void *)dev_priv;
1399                 radeon_do_cleanup_cp(dev);
1400                 return DRM_ERR(EINVAL);
1401         }
1402         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1403         if(!dev_priv->ring_rptr) {
1404                 DRM_ERROR("could not find ring read pointer!\n");
1405                 dev->dev_private = (void *)dev_priv;
1406                 radeon_do_cleanup_cp(dev);
1407                 return DRM_ERR(EINVAL);
1408         }
1409         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1410         if(!dev->agp_buffer_map) {
1411                 DRM_ERROR("could not find dma buffer region!\n");
1412                 dev->dev_private = (void *)dev_priv;
1413                 radeon_do_cleanup_cp(dev);
1414                 return DRM_ERR(EINVAL);
1415         }
1416
1417         if ( init->gart_textures_offset ) {
1418                 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1419                 if ( !dev_priv->gart_textures ) {
1420                         DRM_ERROR("could not find GART texture region!\n");
1421                         dev->dev_private = (void *)dev_priv;
1422                         radeon_do_cleanup_cp(dev);
1423                         return DRM_ERR(EINVAL);
1424                 }
1425         }
1426
1427         dev_priv->sarea_priv =
1428                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1429                                        init->sarea_priv_offset);
1430
1431 #if __OS_HAS_AGP
1432         if ( !dev_priv->is_pci ) {
1433                 drm_core_ioremap( dev_priv->cp_ring, dev );
1434                 drm_core_ioremap( dev_priv->ring_rptr, dev );
1435                 drm_core_ioremap( dev->agp_buffer_map, dev );
1436                 if(!dev_priv->cp_ring->handle ||
1437                    !dev_priv->ring_rptr->handle ||
1438                    !dev->agp_buffer_map->handle) {
1439                         DRM_ERROR("could not find ioremap agp regions!\n");
1440                         dev->dev_private = (void *)dev_priv;
1441                         radeon_do_cleanup_cp(dev);
1442                         return DRM_ERR(EINVAL);
1443                 }
1444         } else
1445 #endif
1446         {
1447                 dev_priv->cp_ring->handle =
1448                         (void *)dev_priv->cp_ring->offset;
1449                 dev_priv->ring_rptr->handle =
1450                         (void *)dev_priv->ring_rptr->offset;
1451                 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1452
1453                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1454                            dev_priv->cp_ring->handle );
1455                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1456                            dev_priv->ring_rptr->handle );
1457                 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1458                            dev->agp_buffer_map->handle );
1459         }
1460
1461         dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1462                                 & 0xffff ) << 16;
1463
1464         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1465                                         ( ( dev_priv->front_offset
1466                                           + dev_priv->fb_location ) >> 10 ) );
1467
1468         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1469                                        ( ( dev_priv->back_offset
1470                                          + dev_priv->fb_location ) >> 10 ) );
1471
1472         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1473                                         ( ( dev_priv->depth_offset
1474                                           + dev_priv->fb_location ) >> 10 ) );
1475
1476
1477         dev_priv->gart_size = init->gart_size;
1478         dev_priv->gart_vm_start = dev_priv->fb_location
1479                                 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1480
1481 #if __OS_HAS_AGP
1482         if ( !dev_priv->is_pci )
1483                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1484                                                 - dev->agp->base
1485                                                 + dev_priv->gart_vm_start);
1486         else
1487 #endif
1488                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1489                                                 - dev->sg->handle
1490                                                 + dev_priv->gart_vm_start);
1491
1492         DRM_DEBUG( "dev_priv->gart_size %d\n",
1493                    dev_priv->gart_size );
1494         DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1495                    dev_priv->gart_vm_start );
1496         DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1497                    dev_priv->gart_buffers_offset );
1498
1499         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1500         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1501                               + init->ring_size / sizeof(u32));
1502         dev_priv->ring.size = init->ring_size;
1503         dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
1504
1505         dev_priv->ring.tail_mask =
1506                 (dev_priv->ring.size / sizeof(u32)) - 1;
1507
1508         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1509
1510 #if __OS_HAS_AGP
1511         if ( !dev_priv->is_pci ) {
1512                 /* Turn off PCI GART */
1513                 radeon_set_pcigart( dev_priv, 0 );
1514         } else
1515 #endif
1516         {
1517                 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
1518                                             &dev_priv->bus_pci_gart)) {
1519                         DRM_ERROR( "failed to init PCI GART!\n" );
1520                         dev->dev_private = (void *)dev_priv;
1521                         radeon_do_cleanup_cp(dev);
1522                         return DRM_ERR(ENOMEM);
1523                 }
1524
1525                 /* Turn on PCI GART */
1526                 radeon_set_pcigart( dev_priv, 1 );
1527         }
1528
1529         radeon_cp_load_microcode( dev_priv );
1530         radeon_cp_init_ring_buffer( dev, dev_priv );
1531
1532         dev_priv->last_buf = 0;
1533
1534         dev->dev_private = (void *)dev_priv;
1535
1536         radeon_do_engine_reset( dev );
1537
1538         return 0;
1539 }
1540
1541 int radeon_do_cleanup_cp( drm_device_t *dev )
1542 {
1543         drm_radeon_private_t *dev_priv = dev->dev_private;
1544         DRM_DEBUG( "\n" );
1545
1546         /* Make sure interrupts are disabled here because the uninstall ioctl
1547          * may not have been called from userspace and after dev_private
1548          * is freed, it's too late.
1549          */
1550         if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1551
1552 #if __OS_HAS_AGP
1553         if ( !dev_priv->is_pci ) {
1554                 if ( dev_priv->cp_ring != NULL )
1555                         drm_core_ioremapfree( dev_priv->cp_ring, dev );
1556                 if ( dev_priv->ring_rptr != NULL )
1557                         drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1558                 if ( dev->agp_buffer_map != NULL )
1559                 {
1560                         drm_core_ioremapfree( dev->agp_buffer_map, dev );
1561                         dev->agp_buffer_map = NULL;
1562                 }
1563         } else
1564 #endif
1565         {
1566                 if (!drm_ati_pcigart_cleanup( dev,
1567                                               dev_priv->phys_pci_gart,
1568                                               dev_priv->bus_pci_gart ))
1569                         DRM_ERROR( "failed to cleanup PCI GART!\n" );
1570         }
1571
1572         /* only clear to the start of flags */
1573         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1574
1575         return 0;
1576 }
1577
1578 /* This code will reinit the Radeon CP hardware after a resume from disc.
1579  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1580  * here we make sure that all Radeon hardware initialisation is re-done without
1581  * affecting running applications.
1582  *
1583  * Charl P. Botha <http://cpbotha.net>
1584  */
1585 static int radeon_do_resume_cp( drm_device_t *dev )
1586 {
1587         drm_radeon_private_t *dev_priv = dev->dev_private;
1588
1589         if ( !dev_priv ) {
1590                 DRM_ERROR( "Called with no initialization\n" );
1591                 return DRM_ERR( EINVAL );
1592         }
1593
1594         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1595
1596 #if __OS_HAS_AGP
1597         if ( !dev_priv->is_pci ) {
1598                 /* Turn off PCI GART */
1599                 radeon_set_pcigart( dev_priv, 0 );
1600         } else
1601 #endif
1602         {
1603                 /* Turn on PCI GART */
1604                 radeon_set_pcigart( dev_priv, 1 );
1605         }
1606
1607         radeon_cp_load_microcode( dev_priv );
1608         radeon_cp_init_ring_buffer( dev, dev_priv );
1609
1610         radeon_do_engine_reset( dev );
1611
1612         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1613
1614         return 0;
1615 }
1616
1617
1618 int radeon_cp_init( DRM_IOCTL_ARGS )
1619 {
1620         DRM_DEVICE;
1621         drm_radeon_init_t init;
1622
1623         LOCK_TEST_WITH_RETURN( dev, filp );
1624
1625         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1626
1627         switch ( init.func ) {
1628         case RADEON_INIT_CP:
1629         case RADEON_INIT_R200_CP:
1630         case RADEON_INIT_R300_CP:
1631                 return radeon_do_init_cp( dev, &init );
1632         case RADEON_CLEANUP_CP:
1633                 return radeon_do_cleanup_cp( dev );
1634         }
1635
1636         return DRM_ERR(EINVAL);
1637 }
1638
1639 int radeon_cp_start( DRM_IOCTL_ARGS )
1640 {
1641         DRM_DEVICE;
1642         drm_radeon_private_t *dev_priv = dev->dev_private;
1643         DRM_DEBUG( "\n" );
1644
1645         LOCK_TEST_WITH_RETURN( dev, filp );
1646
1647         if ( dev_priv->cp_running ) {
1648                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1649                 return 0;
1650         }
1651         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1652                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1653                            __FUNCTION__, dev_priv->cp_mode );
1654                 return 0;
1655         }
1656
1657         radeon_do_cp_start( dev_priv );
1658
1659         return 0;
1660 }
1661
1662 /* Stop the CP.  The engine must have been idled before calling this
1663  * routine.
1664  */
1665 int radeon_cp_stop( DRM_IOCTL_ARGS )
1666 {
1667         DRM_DEVICE;
1668         drm_radeon_private_t *dev_priv = dev->dev_private;
1669         drm_radeon_cp_stop_t stop;
1670         int ret;
1671         DRM_DEBUG( "\n" );
1672
1673         LOCK_TEST_WITH_RETURN( dev, filp );
1674
1675         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1676
1677         if (!dev_priv->cp_running)
1678                 return 0;
1679
1680         /* Flush any pending CP commands.  This ensures any outstanding
1681          * commands are exectuted by the engine before we turn it off.
1682          */
1683         if ( stop.flush ) {
1684                 radeon_do_cp_flush( dev_priv );
1685         }
1686
1687         /* If we fail to make the engine go idle, we return an error
1688          * code so that the DRM ioctl wrapper can try again.
1689          */
1690         if ( stop.idle ) {
1691                 ret = radeon_do_cp_idle( dev_priv );
1692                 if ( ret ) return ret;
1693         }
1694
1695         /* Finally, we can turn off the CP.  If the engine isn't idle,
1696          * we will get some dropped triangles as they won't be fully
1697          * rendered before the CP is shut down.
1698          */
1699         radeon_do_cp_stop( dev_priv );
1700
1701         /* Reset the engine */
1702         radeon_do_engine_reset( dev );
1703
1704         return 0;
1705 }
1706
1707
1708 void radeon_do_release( drm_device_t *dev )
1709 {
1710         drm_radeon_private_t *dev_priv = dev->dev_private;
1711         int i, ret;
1712
1713         if (dev_priv) {
1714                 if (dev_priv->cp_running) {
1715                         /* Stop the cp */
1716                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1717                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1718 #ifdef __linux__
1719                                 schedule();
1720 #else
1721                                 tsleep(&ret, PZERO, "rdnrel", 1);
1722 #endif
1723                         }
1724                         radeon_do_cp_stop( dev_priv );
1725                         radeon_do_engine_reset( dev );
1726                 }
1727
1728                 /* Disable *all* interrupts */
1729                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1730                         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1731
1732                 if (dev_priv->mmio) {/* remove all surfaces */
1733                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1734                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1735                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1736                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1737                         }
1738                 }
1739
1740                 /* Free memory heap structures */
1741                 radeon_mem_takedown( &(dev_priv->gart_heap) );
1742                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1743
1744                 /* deallocate kernel resources */
1745                 radeon_do_cleanup_cp( dev );
1746         }
1747 }
1748
1749 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1750  */
1751 int radeon_cp_reset( DRM_IOCTL_ARGS )
1752 {
1753         DRM_DEVICE;
1754         drm_radeon_private_t *dev_priv = dev->dev_private;
1755         DRM_DEBUG( "\n" );
1756
1757         LOCK_TEST_WITH_RETURN( dev, filp );
1758
1759         if ( !dev_priv ) {
1760                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1761                 return DRM_ERR(EINVAL);
1762         }
1763
1764         radeon_do_cp_reset( dev_priv );
1765
1766         /* The CP is no longer running after an engine reset */
1767         dev_priv->cp_running = 0;
1768
1769         return 0;
1770 }
1771
1772 int radeon_cp_idle( DRM_IOCTL_ARGS )
1773 {
1774         DRM_DEVICE;
1775         drm_radeon_private_t *dev_priv = dev->dev_private;
1776         DRM_DEBUG( "\n" );
1777
1778         LOCK_TEST_WITH_RETURN( dev, filp );
1779
1780         return radeon_do_cp_idle( dev_priv );
1781 }
1782
1783 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1784  */
1785 int radeon_cp_resume( DRM_IOCTL_ARGS )
1786 {
1787         DRM_DEVICE;
1788
1789         return radeon_do_resume_cp(dev);
1790 }
1791
1792
1793 int radeon_engine_reset( DRM_IOCTL_ARGS )
1794 {
1795         DRM_DEVICE;
1796         DRM_DEBUG( "\n" );
1797
1798         LOCK_TEST_WITH_RETURN( dev, filp );
1799
1800         return radeon_do_engine_reset( dev );
1801 }
1802
1803
1804 /* ================================================================
1805  * Fullscreen mode
1806  */
1807
1808 /* KW: Deprecated to say the least:
1809  */
1810 int radeon_fullscreen( DRM_IOCTL_ARGS )
1811 {
1812         return 0;
1813 }
1814
1815
1816 /* ================================================================
1817  * Freelist management
1818  */
1819
1820 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1821  *   bufs until freelist code is used.  Note this hides a problem with
1822  *   the scratch register * (used to keep track of last buffer
1823  *   completed) being written to before * the last buffer has actually
1824  *   completed rendering.
1825  *
1826  * KW:  It's also a good way to find free buffers quickly.
1827  *
1828  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1829  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1830  * we essentially have to do this, else old clients will break.
1831  *
1832  * However, it does leave open a potential deadlock where all the
1833  * buffers are held by other clients, which can't release them because
1834  * they can't get the lock.
1835  */
1836
1837 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1838 {
1839         drm_device_dma_t *dma = dev->dma;
1840         drm_radeon_private_t *dev_priv = dev->dev_private;
1841         drm_radeon_buf_priv_t *buf_priv;
1842         drm_buf_t *buf;
1843         int i, t;
1844         int start;
1845
1846         if ( ++dev_priv->last_buf >= dma->buf_count )
1847                 dev_priv->last_buf = 0;
1848
1849         start = dev_priv->last_buf;
1850
1851         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1852                 u32 done_age = GET_SCRATCH( 1 );
1853                 DRM_DEBUG("done_age = %d\n",done_age);
1854                 for ( i = start ; i < dma->buf_count ; i++ ) {
1855                         buf = dma->buflist[i];
1856                         buf_priv = buf->dev_private;
1857                         if ( buf->filp == 0 || (buf->pending &&
1858                                                buf_priv->age <= done_age) ) {
1859                                 dev_priv->stats.requested_bufs++;
1860                                 buf->pending = 0;
1861                                 return buf;
1862                         }
1863                         start = 0;
1864                 }
1865
1866                 if (t) {
1867                         DRM_UDELAY( 1 );
1868                         dev_priv->stats.freelist_loops++;
1869                 }
1870         }
1871
1872         DRM_DEBUG( "returning NULL!\n" );
1873         return NULL;
1874 }
1875 #if 0
1876 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1877 {
1878         drm_device_dma_t *dma = dev->dma;
1879         drm_radeon_private_t *dev_priv = dev->dev_private;
1880         drm_radeon_buf_priv_t *buf_priv;
1881         drm_buf_t *buf;
1882         int i, t;
1883         int start;
1884         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1885
1886         if ( ++dev_priv->last_buf >= dma->buf_count )
1887                 dev_priv->last_buf = 0;
1888
1889         start = dev_priv->last_buf;
1890         dev_priv->stats.freelist_loops++;
1891
1892         for ( t = 0 ; t < 2 ; t++ ) {
1893                 for ( i = start ; i < dma->buf_count ; i++ ) {
1894                         buf = dma->buflist[i];
1895                         buf_priv = buf->dev_private;
1896                         if ( buf->filp == 0 || (buf->pending &&
1897                                                buf_priv->age <= done_age) ) {
1898                                 dev_priv->stats.requested_bufs++;
1899                                 buf->pending = 0;
1900                                 return buf;
1901                         }
1902                 }
1903                 start = 0;
1904         }
1905
1906         return NULL;
1907 }
1908 #endif
1909
1910 void radeon_freelist_reset( drm_device_t *dev )
1911 {
1912         drm_device_dma_t *dma = dev->dma;
1913         drm_radeon_private_t *dev_priv = dev->dev_private;
1914         int i;
1915
1916         dev_priv->last_buf = 0;
1917         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1918                 drm_buf_t *buf = dma->buflist[i];
1919                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1920                 buf_priv->age = 0;
1921         }
1922 }
1923
1924
1925 /* ================================================================
1926  * CP command submission
1927  */
1928
1929 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1930 {
1931         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1932         int i;
1933         u32 last_head = GET_RING_HEAD( dev_priv );
1934
1935         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1936                 u32 head = GET_RING_HEAD( dev_priv );
1937
1938                 ring->space = (head - ring->tail) * sizeof(u32);
1939                 if ( ring->space <= 0 )
1940                         ring->space += ring->size;
1941                 if ( ring->space > n )
1942                         return 0;
1943
1944                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1945
1946                 if (head != last_head)
1947                         i = 0;
1948                 last_head = head;
1949
1950                 DRM_UDELAY( 1 );
1951         }
1952
1953         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1954 #if RADEON_FIFO_DEBUG
1955         radeon_status( dev_priv );
1956         DRM_ERROR( "failed!\n" );
1957 #endif
1958         return DRM_ERR(EBUSY);
1959 }
1960
1961 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1962 {
1963         int i;
1964         drm_buf_t *buf;
1965
1966         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1967                 buf = radeon_freelist_get( dev );
1968                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1969
1970                 buf->filp = filp;
1971
1972                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1973                                    sizeof(buf->idx) ) )
1974                         return DRM_ERR(EFAULT);
1975                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1976                                    sizeof(buf->total) ) )
1977                         return DRM_ERR(EFAULT);
1978
1979                 d->granted_count++;
1980         }
1981         return 0;
1982 }
1983
1984 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1985 {
1986         DRM_DEVICE;
1987         drm_device_dma_t *dma = dev->dma;
1988         int ret = 0;
1989         drm_dma_t __user *argp = (void __user *)data;
1990         drm_dma_t d;
1991
1992         LOCK_TEST_WITH_RETURN( dev, filp );
1993
1994         DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
1995
1996         /* Please don't send us buffers.
1997          */
1998         if ( d.send_count != 0 ) {
1999                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
2000                            DRM_CURRENTPID, d.send_count );
2001                 return DRM_ERR(EINVAL);
2002         }
2003
2004         /* We'll send you buffers.
2005          */
2006         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
2007                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
2008                            DRM_CURRENTPID, d.request_count, dma->buf_count );
2009                 return DRM_ERR(EINVAL);
2010         }
2011
2012         d.granted_count = 0;
2013
2014         if ( d.request_count ) {
2015                 ret = radeon_cp_get_buffers( filp, dev, &d );
2016         }
2017
2018         DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
2019
2020         return ret;
2021 }
2022
2023 int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2024 {
2025         drm_radeon_private_t *dev_priv;
2026         int ret = 0;
2027
2028         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2029         if (dev_priv == NULL)
2030                 return DRM_ERR(ENOMEM);
2031
2032         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2033         dev->dev_private = (void *)dev_priv;
2034         dev_priv->flags = flags;
2035
2036         switch (flags & CHIP_FAMILY_MASK) {
2037         case CHIP_R100:
2038         case CHIP_RV200:
2039         case CHIP_R200:
2040         case CHIP_R300:
2041                 dev_priv->flags |= CHIP_HAS_HIERZ;
2042                 break;
2043         default:
2044         /* all other chips have no hierarchical z buffer */
2045                 break;
2046         }
2047         return ret;
2048 }
2049
2050 int radeon_driver_postcleanup(struct drm_device *dev)
2051 {
2052         drm_radeon_private_t *dev_priv = dev->dev_private;
2053
2054         DRM_DEBUG("\n");
2055
2056         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2057
2058         dev->dev_private = NULL;
2059         return 0;
2060 }