1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20050125"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
82 #define DRIVER_MAJOR 1
83 #define DRIVER_MINOR 14
84 #define DRIVER_PATCHLEVEL 0
86 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
87 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
90 * Radeon chip families
109 enum radeon_cp_microcode_version {
118 enum radeon_chip_flags {
119 CHIP_FAMILY_MASK = 0x0000ffffUL,
120 CHIP_FLAGS_MASK = 0xffff0000UL,
121 CHIP_IS_MOBILITY = 0x00010000UL,
122 CHIP_IS_IGP = 0x00020000UL,
123 CHIP_SINGLE_CRTC = 0x00040000UL,
124 CHIP_IS_AGP = 0x00080000UL,
125 CHIP_HAS_HIERZ = 0x00100000UL,
128 typedef struct drm_radeon_freelist {
131 struct drm_radeon_freelist *next;
132 struct drm_radeon_freelist *prev;
133 } drm_radeon_freelist_t;
135 typedef struct drm_radeon_ring_buffer {
146 } drm_radeon_ring_buffer_t;
148 typedef struct drm_radeon_depth_clear_t {
150 u32 rb3d_zstencilcntl;
152 } drm_radeon_depth_clear_t;
154 struct drm_radeon_driver_file_fields {
155 int64_t radeon_fb_delta;
159 struct mem_block *next;
160 struct mem_block *prev;
163 DRMFILE filp; /* 0: free, -1: heap, other: real files */
166 struct radeon_surface {
173 struct radeon_virt_surface {
181 typedef struct drm_radeon_private {
182 drm_radeon_ring_buffer_t ring;
183 drm_radeon_sarea_t *sarea_priv;
189 unsigned long gart_buffers_offset;
194 drm_radeon_freelist_t *head;
195 drm_radeon_freelist_t *tail;
197 volatile u32 *scratch;
202 int microcode_version;
205 unsigned long phys_pci_gart;
206 dma_addr_t bus_pci_gart;
210 int freelist_timeouts;
213 int last_frame_reads;
214 int last_clear_reads;
224 unsigned int front_offset;
225 unsigned int front_pitch;
226 unsigned int back_offset;
227 unsigned int back_pitch;
230 unsigned int depth_offset;
231 unsigned int depth_pitch;
233 u32 front_pitch_offset;
234 u32 back_pitch_offset;
235 u32 depth_pitch_offset;
237 drm_radeon_depth_clear_t depth_clear;
239 unsigned long fb_offset;
240 unsigned long mmio_offset;
241 unsigned long ring_offset;
242 unsigned long ring_rptr_offset;
243 unsigned long buffers_offset;
244 unsigned long gart_textures_offset;
246 drm_local_map_t *sarea;
247 drm_local_map_t *mmio;
248 drm_local_map_t *cp_ring;
249 drm_local_map_t *ring_rptr;
250 drm_local_map_t *gart_textures;
252 struct mem_block *gart_heap;
253 struct mem_block *fb_heap;
256 wait_queue_head_t swi_queue;
257 atomic_t swi_emitted;
259 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
260 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
262 /* starting from here on, data is preserved accross an open */
263 uint32_t flags; /* see radeon_chip_flags */
264 } drm_radeon_private_t;
266 typedef struct drm_radeon_buf_priv {
268 } drm_radeon_buf_priv_t;
271 extern int radeon_cp_init( DRM_IOCTL_ARGS );
272 extern int radeon_cp_start( DRM_IOCTL_ARGS );
273 extern int radeon_cp_stop( DRM_IOCTL_ARGS );
274 extern int radeon_cp_reset( DRM_IOCTL_ARGS );
275 extern int radeon_cp_idle( DRM_IOCTL_ARGS );
276 extern int radeon_cp_resume( DRM_IOCTL_ARGS );
277 extern int radeon_engine_reset( DRM_IOCTL_ARGS );
278 extern int radeon_fullscreen( DRM_IOCTL_ARGS );
279 extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
281 extern void radeon_freelist_reset( drm_device_t *dev );
282 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
284 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
286 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
287 extern int radeon_do_cleanup_cp( drm_device_t *dev );
288 extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
290 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
291 extern int radeon_driver_postcleanup(struct drm_device *dev);
294 extern int radeon_cp_clear( DRM_IOCTL_ARGS );
295 extern int radeon_cp_swap( DRM_IOCTL_ARGS );
296 extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
297 extern int radeon_cp_indices( DRM_IOCTL_ARGS );
298 extern int radeon_cp_texture( DRM_IOCTL_ARGS );
299 extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
300 extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
301 extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
302 extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
303 extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
304 extern int radeon_cp_setparam( DRM_IOCTL_ARGS );
305 extern int radeon_cp_flip( DRM_IOCTL_ARGS );
307 extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
308 extern int radeon_mem_free( DRM_IOCTL_ARGS );
309 extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
310 extern void radeon_mem_takedown( struct mem_block **heap );
311 extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
312 extern int radeon_surface_alloc(DRM_IOCTL_ARGS);
313 extern int radeon_surface_free(DRM_IOCTL_ARGS);
316 extern int radeon_irq_emit( DRM_IOCTL_ARGS );
317 extern int radeon_irq_wait( DRM_IOCTL_ARGS );
319 extern int radeon_emit_and_wait_irq(drm_device_t *dev);
320 extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
321 extern int radeon_emit_irq(drm_device_t *dev);
323 extern void radeon_do_release(drm_device_t *dev);
324 extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
325 extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
326 extern void radeon_driver_irq_preinstall( drm_device_t *dev );
327 extern void radeon_driver_irq_postinstall( drm_device_t *dev );
328 extern void radeon_driver_irq_uninstall( drm_device_t *dev );
329 extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
330 extern void radeon_driver_pretakedown(drm_device_t *dev);
331 extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
332 extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
334 extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
335 extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
336 extern int radeon_postcleanup( struct drm_device *dev );
338 /* Flags for stats.boxes
340 #define RADEON_BOX_DMA_IDLE 0x1
341 #define RADEON_BOX_RING_FULL 0x2
342 #define RADEON_BOX_FLIP 0x4
343 #define RADEON_BOX_WAIT_IDLE 0x8
344 #define RADEON_BOX_TEXTURE_LOAD 0x10
348 /* Register definitions, register access macros and drmAddMap constants
349 * for Radeon kernel driver.
352 #define RADEON_AGP_COMMAND 0x0f60
353 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
354 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
355 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
356 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
357 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
358 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
359 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
361 #define RADEON_BUS_CNTL 0x0030
362 # define RADEON_BUS_MASTER_DIS (1 << 6)
364 #define RADEON_CLOCK_CNTL_DATA 0x000c
365 # define RADEON_PLL_WR_EN (1 << 7)
366 #define RADEON_CLOCK_CNTL_INDEX 0x0008
367 #define RADEON_CONFIG_APER_SIZE 0x0108
368 #define RADEON_CRTC_OFFSET 0x0224
369 #define RADEON_CRTC_OFFSET_CNTL 0x0228
370 # define RADEON_CRTC_TILE_EN (1 << 15)
371 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
372 #define RADEON_CRTC2_OFFSET 0x0324
373 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
375 #define RADEON_RB3D_COLOROFFSET 0x1c40
376 #define RADEON_RB3D_COLORPITCH 0x1c48
378 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
379 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
380 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
381 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
382 # define RADEON_GMC_BRUSH_NONE (15 << 4)
383 # define RADEON_GMC_DST_16BPP (4 << 8)
384 # define RADEON_GMC_DST_24BPP (5 << 8)
385 # define RADEON_GMC_DST_32BPP (6 << 8)
386 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
387 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
388 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
389 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
390 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
391 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
392 # define RADEON_ROP3_S 0x00cc0000
393 # define RADEON_ROP3_P 0x00f00000
394 #define RADEON_DP_WRITE_MASK 0x16cc
395 #define RADEON_DST_PITCH_OFFSET 0x142c
396 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
397 # define RADEON_DST_TILE_LINEAR (0 << 30)
398 # define RADEON_DST_TILE_MACRO (1 << 30)
399 # define RADEON_DST_TILE_MICRO (2 << 30)
400 # define RADEON_DST_TILE_BOTH (3 << 30)
402 #define RADEON_SCRATCH_REG0 0x15e0
403 #define RADEON_SCRATCH_REG1 0x15e4
404 #define RADEON_SCRATCH_REG2 0x15e8
405 #define RADEON_SCRATCH_REG3 0x15ec
406 #define RADEON_SCRATCH_REG4 0x15f0
407 #define RADEON_SCRATCH_REG5 0x15f4
408 #define RADEON_SCRATCH_UMSK 0x0770
409 #define RADEON_SCRATCH_ADDR 0x0774
411 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
413 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
414 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
415 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
418 #define RADEON_GEN_INT_CNTL 0x0040
419 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
420 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
421 # define RADEON_SW_INT_ENABLE (1 << 25)
423 #define RADEON_GEN_INT_STATUS 0x0044
424 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
425 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
426 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
427 # define RADEON_SW_INT_TEST (1 << 25)
428 # define RADEON_SW_INT_TEST_ACK (1 << 25)
429 # define RADEON_SW_INT_FIRE (1 << 26)
431 #define RADEON_HOST_PATH_CNTL 0x0130
432 # define RADEON_HDP_SOFT_RESET (1 << 26)
433 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
434 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
436 #define RADEON_ISYNC_CNTL 0x1724
437 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
438 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
439 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
440 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
441 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
442 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
444 #define RADEON_RBBM_GUICNTL 0x172c
445 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
446 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
447 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
448 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
450 #define RADEON_MC_AGP_LOCATION 0x014c
451 #define RADEON_MC_FB_LOCATION 0x0148
452 #define RADEON_MCLK_CNTL 0x0012
453 # define RADEON_FORCEON_MCLKA (1 << 16)
454 # define RADEON_FORCEON_MCLKB (1 << 17)
455 # define RADEON_FORCEON_YCLKA (1 << 18)
456 # define RADEON_FORCEON_YCLKB (1 << 19)
457 # define RADEON_FORCEON_MC (1 << 20)
458 # define RADEON_FORCEON_AIC (1 << 21)
460 #define RADEON_PP_BORDER_COLOR_0 0x1d40
461 #define RADEON_PP_BORDER_COLOR_1 0x1d44
462 #define RADEON_PP_BORDER_COLOR_2 0x1d48
463 #define RADEON_PP_CNTL 0x1c38
464 # define RADEON_SCISSOR_ENABLE (1 << 1)
465 #define RADEON_PP_LUM_MATRIX 0x1d00
466 #define RADEON_PP_MISC 0x1c14
467 #define RADEON_PP_ROT_MATRIX_0 0x1d58
468 #define RADEON_PP_TXFILTER_0 0x1c54
469 #define RADEON_PP_TXOFFSET_0 0x1c5c
470 #define RADEON_PP_TXFILTER_1 0x1c6c
471 #define RADEON_PP_TXFILTER_2 0x1c84
473 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
474 # define RADEON_RB2D_DC_FLUSH (3 << 0)
475 # define RADEON_RB2D_DC_FREE (3 << 2)
476 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
477 # define RADEON_RB2D_DC_BUSY (1 << 31)
478 #define RADEON_RB3D_CNTL 0x1c3c
479 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
480 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
481 # define RADEON_DITHER_ENABLE (1 << 2)
482 # define RADEON_ROUND_ENABLE (1 << 3)
483 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
484 # define RADEON_DITHER_INIT (1 << 5)
485 # define RADEON_ROP_ENABLE (1 << 6)
486 # define RADEON_STENCIL_ENABLE (1 << 7)
487 # define RADEON_Z_ENABLE (1 << 8)
488 # define RADEON_ZBLOCK16 (1 << 15)
489 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
490 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
491 #define RADEON_RB3D_DEPTHPITCH 0x1c28
492 #define RADEON_RB3D_PLANEMASK 0x1d84
493 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
494 #define RADEON_RB3D_ZCACHE_MODE 0x3250
495 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
496 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
497 # define RADEON_RB3D_ZC_FREE (1 << 2)
498 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
499 # define RADEON_RB3D_ZC_BUSY (1 << 31)
500 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
501 # define RADEON_Z_TEST_MASK (7 << 4)
502 # define RADEON_Z_TEST_ALWAYS (7 << 4)
503 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
504 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
505 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
506 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
507 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
508 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
509 # define RADEON_FORCE_Z_DIRTY (1 << 29)
510 # define RADEON_Z_WRITE_ENABLE (1 << 30)
511 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
512 #define RADEON_RBBM_SOFT_RESET 0x00f0
513 # define RADEON_SOFT_RESET_CP (1 << 0)
514 # define RADEON_SOFT_RESET_HI (1 << 1)
515 # define RADEON_SOFT_RESET_SE (1 << 2)
516 # define RADEON_SOFT_RESET_RE (1 << 3)
517 # define RADEON_SOFT_RESET_PP (1 << 4)
518 # define RADEON_SOFT_RESET_E2 (1 << 5)
519 # define RADEON_SOFT_RESET_RB (1 << 6)
520 # define RADEON_SOFT_RESET_HDP (1 << 7)
521 #define RADEON_RBBM_STATUS 0x0e40
522 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
523 # define RADEON_RBBM_ACTIVE (1 << 31)
524 #define RADEON_RE_LINE_PATTERN 0x1cd0
525 #define RADEON_RE_MISC 0x26c4
526 #define RADEON_RE_TOP_LEFT 0x26c0
527 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
528 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
529 #define RADEON_RE_STIPPLE_DATA 0x1ccc
531 #define RADEON_SCISSOR_TL_0 0x1cd8
532 #define RADEON_SCISSOR_BR_0 0x1cdc
533 #define RADEON_SCISSOR_TL_1 0x1ce0
534 #define RADEON_SCISSOR_BR_1 0x1ce4
535 #define RADEON_SCISSOR_TL_2 0x1ce8
536 #define RADEON_SCISSOR_BR_2 0x1cec
537 #define RADEON_SE_COORD_FMT 0x1c50
538 #define RADEON_SE_CNTL 0x1c4c
539 # define RADEON_FFACE_CULL_CW (0 << 0)
540 # define RADEON_BFACE_SOLID (3 << 1)
541 # define RADEON_FFACE_SOLID (3 << 3)
542 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
543 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
544 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
545 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
546 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
547 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
548 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
549 # define RADEON_FOG_SHADE_FLAT (1 << 14)
550 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
551 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
552 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
553 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
554 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
555 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
556 #define RADEON_SE_CNTL_STATUS 0x2140
557 #define RADEON_SE_LINE_WIDTH 0x1db8
558 #define RADEON_SE_VPORT_XSCALE 0x1d98
559 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
560 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
561 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
562 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
563 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
564 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
565 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
566 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
567 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
568 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
569 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
570 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
571 #define RADEON_SURFACE_CNTL 0x0b00
572 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
573 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
574 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
575 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
576 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
577 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
578 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
579 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
580 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
581 #define RADEON_SURFACE0_INFO 0x0b0c
582 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
583 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
584 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
585 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
586 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
587 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
588 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
589 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
590 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
591 #define RADEON_SURFACE1_INFO 0x0b1c
592 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
593 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
594 #define RADEON_SURFACE2_INFO 0x0b2c
595 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
596 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
597 #define RADEON_SURFACE3_INFO 0x0b3c
598 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
599 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
600 #define RADEON_SURFACE4_INFO 0x0b4c
601 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
602 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
603 #define RADEON_SURFACE5_INFO 0x0b5c
604 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
605 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
606 #define RADEON_SURFACE6_INFO 0x0b6c
607 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
608 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
609 #define RADEON_SURFACE7_INFO 0x0b7c
610 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
611 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
612 #define RADEON_SW_SEMAPHORE 0x013c
614 #define RADEON_WAIT_UNTIL 0x1720
615 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
616 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
617 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
618 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
620 #define RADEON_RB3D_ZMASKOFFSET 0x3234
621 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
622 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
623 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
627 #define RADEON_CP_ME_RAM_ADDR 0x07d4
628 #define RADEON_CP_ME_RAM_RADDR 0x07d8
629 #define RADEON_CP_ME_RAM_DATAH 0x07dc
630 #define RADEON_CP_ME_RAM_DATAL 0x07e0
632 #define RADEON_CP_RB_BASE 0x0700
633 #define RADEON_CP_RB_CNTL 0x0704
634 # define RADEON_BUF_SWAP_32BIT (2 << 16)
635 #define RADEON_CP_RB_RPTR_ADDR 0x070c
636 #define RADEON_CP_RB_RPTR 0x0710
637 #define RADEON_CP_RB_WPTR 0x0714
639 #define RADEON_CP_RB_WPTR_DELAY 0x0718
640 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
641 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
643 #define RADEON_CP_IB_BASE 0x0738
645 #define RADEON_CP_CSQ_CNTL 0x0740
646 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
647 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
648 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
649 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
650 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
651 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
652 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
654 #define RADEON_AIC_CNTL 0x01d0
655 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
656 #define RADEON_AIC_STAT 0x01d4
657 #define RADEON_AIC_PT_BASE 0x01d8
658 #define RADEON_AIC_LO_ADDR 0x01dc
659 #define RADEON_AIC_HI_ADDR 0x01e0
660 #define RADEON_AIC_TLB_ADDR 0x01e4
661 #define RADEON_AIC_TLB_DATA 0x01e8
663 /* CP command packets */
664 #define RADEON_CP_PACKET0 0x00000000
665 # define RADEON_ONE_REG_WR (1 << 15)
666 #define RADEON_CP_PACKET1 0x40000000
667 #define RADEON_CP_PACKET2 0x80000000
668 #define RADEON_CP_PACKET3 0xC0000000
669 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
670 # define RADEON_WAIT_FOR_IDLE 0x00002600
671 # define RADEON_3D_DRAW_VBUF 0x00002800
672 # define RADEON_3D_DRAW_IMMD 0x00002900
673 # define RADEON_3D_DRAW_INDX 0x00002A00
674 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
675 # define RADEON_3D_CLEAR_ZMASK 0x00003200
676 # define RADEON_3D_CLEAR_HIZ 0x00003700
677 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
678 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
679 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
680 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
682 #define RADEON_CP_PACKET_MASK 0xC0000000
683 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
684 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
685 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
686 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
688 #define RADEON_VTX_Z_PRESENT (1 << 31)
689 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
691 #define RADEON_PRIM_TYPE_NONE (0 << 0)
692 #define RADEON_PRIM_TYPE_POINT (1 << 0)
693 #define RADEON_PRIM_TYPE_LINE (2 << 0)
694 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
695 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
696 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
697 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
698 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
699 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
700 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
701 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
702 #define RADEON_PRIM_TYPE_MASK 0xf
703 #define RADEON_PRIM_WALK_IND (1 << 4)
704 #define RADEON_PRIM_WALK_LIST (2 << 4)
705 #define RADEON_PRIM_WALK_RING (3 << 4)
706 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
707 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
708 #define RADEON_MAOS_ENABLE (1 << 7)
709 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
710 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
711 #define RADEON_NUM_VERTICES_SHIFT 16
713 #define RADEON_COLOR_FORMAT_CI8 2
714 #define RADEON_COLOR_FORMAT_ARGB1555 3
715 #define RADEON_COLOR_FORMAT_RGB565 4
716 #define RADEON_COLOR_FORMAT_ARGB8888 6
717 #define RADEON_COLOR_FORMAT_RGB332 7
718 #define RADEON_COLOR_FORMAT_RGB8 9
719 #define RADEON_COLOR_FORMAT_ARGB4444 15
721 #define RADEON_TXFORMAT_I8 0
722 #define RADEON_TXFORMAT_AI88 1
723 #define RADEON_TXFORMAT_RGB332 2
724 #define RADEON_TXFORMAT_ARGB1555 3
725 #define RADEON_TXFORMAT_RGB565 4
726 #define RADEON_TXFORMAT_ARGB4444 5
727 #define RADEON_TXFORMAT_ARGB8888 6
728 #define RADEON_TXFORMAT_RGBA8888 7
729 #define RADEON_TXFORMAT_Y8 8
730 #define RADEON_TXFORMAT_VYUY422 10
731 #define RADEON_TXFORMAT_YVYU422 11
732 #define RADEON_TXFORMAT_DXT1 12
733 #define RADEON_TXFORMAT_DXT23 14
734 #define RADEON_TXFORMAT_DXT45 15
736 #define R200_PP_TXCBLEND_0 0x2f00
737 #define R200_PP_TXCBLEND_1 0x2f10
738 #define R200_PP_TXCBLEND_2 0x2f20
739 #define R200_PP_TXCBLEND_3 0x2f30
740 #define R200_PP_TXCBLEND_4 0x2f40
741 #define R200_PP_TXCBLEND_5 0x2f50
742 #define R200_PP_TXCBLEND_6 0x2f60
743 #define R200_PP_TXCBLEND_7 0x2f70
744 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
745 #define R200_PP_TFACTOR_0 0x2ee0
746 #define R200_SE_VTX_FMT_0 0x2088
747 #define R200_SE_VAP_CNTL 0x2080
748 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
749 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
750 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
751 #define R200_PP_TXFILTER_5 0x2ca0
752 #define R200_PP_TXFILTER_4 0x2c80
753 #define R200_PP_TXFILTER_3 0x2c60
754 #define R200_PP_TXFILTER_2 0x2c40
755 #define R200_PP_TXFILTER_1 0x2c20
756 #define R200_PP_TXFILTER_0 0x2c00
757 #define R200_PP_TXOFFSET_5 0x2d78
758 #define R200_PP_TXOFFSET_4 0x2d60
759 #define R200_PP_TXOFFSET_3 0x2d48
760 #define R200_PP_TXOFFSET_2 0x2d30
761 #define R200_PP_TXOFFSET_1 0x2d18
762 #define R200_PP_TXOFFSET_0 0x2d00
764 #define R200_PP_CUBIC_FACES_0 0x2c18
765 #define R200_PP_CUBIC_FACES_1 0x2c38
766 #define R200_PP_CUBIC_FACES_2 0x2c58
767 #define R200_PP_CUBIC_FACES_3 0x2c78
768 #define R200_PP_CUBIC_FACES_4 0x2c98
769 #define R200_PP_CUBIC_FACES_5 0x2cb8
770 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
771 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
772 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
773 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
774 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
775 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
776 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
777 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
778 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
779 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
780 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
781 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
782 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
783 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
784 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
785 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
786 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
787 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
788 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
789 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
790 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
791 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
792 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
793 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
794 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
795 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
796 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
797 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
798 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
799 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
801 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
802 #define R200_SE_VTE_CNTL 0x20b0
803 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
804 #define R200_PP_TAM_DEBUG3 0x2d9c
805 #define R200_PP_CNTL_X 0x2cc4
806 #define R200_SE_VAP_CNTL_STATUS 0x2140
807 #define R200_RE_SCISSOR_TL_0 0x1cd8
808 #define R200_RE_SCISSOR_TL_1 0x1ce0
809 #define R200_RE_SCISSOR_TL_2 0x1ce8
810 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
811 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
812 #define R200_SE_VTX_STATE_CNTL 0x2180
813 #define R200_RE_POINTSIZE 0x2648
814 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
816 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
817 #define RADEON_PP_TEX_SIZE_1 0x1d0c
818 #define RADEON_PP_TEX_SIZE_2 0x1d14
821 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
822 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
823 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
824 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
825 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
826 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
827 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
828 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
829 #define R200_3D_DRAW_IMMD_2 0xC0003500
830 #define R200_SE_VTX_FMT_1 0x208c
831 #define R200_RE_CNTL 0x1c50
833 #define R200_RB3D_BLENDCOLOR 0x3218
835 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
838 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
840 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
841 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
842 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
843 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
844 #define RADEON_LAST_DISPATCH 1
846 #define RADEON_MAX_VB_AGE 0x7fffffff
847 #define RADEON_MAX_VB_VERTS (0xffff)
849 #define RADEON_RING_HIGH_MARK 128
851 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
852 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
853 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
854 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
856 #define RADEON_WRITE_PLL( addr, val ) \
858 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
859 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
860 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
863 extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
866 #define CP_PACKET0( reg, n ) \
867 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
868 #define CP_PACKET0_TABLE( reg, n ) \
869 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
870 #define CP_PACKET1( reg0, reg1 ) \
871 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
872 #define CP_PACKET2() \
874 #define CP_PACKET3( pkt, n ) \
875 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
878 /* ================================================================
879 * Engine control helper macros
882 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
883 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
884 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
885 RADEON_WAIT_HOST_IDLECLEAN) ); \
888 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
889 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
890 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
891 RADEON_WAIT_HOST_IDLECLEAN) ); \
894 #define RADEON_WAIT_UNTIL_IDLE() do { \
895 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
896 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
897 RADEON_WAIT_3D_IDLECLEAN | \
898 RADEON_WAIT_HOST_IDLECLEAN) ); \
901 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
902 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
903 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
906 #define RADEON_FLUSH_CACHE() do { \
907 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
908 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
911 #define RADEON_PURGE_CACHE() do { \
912 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
913 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
916 #define RADEON_FLUSH_ZCACHE() do { \
917 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
918 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
921 #define RADEON_PURGE_ZCACHE() do { \
922 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
923 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
927 /* ================================================================
931 /* Perfbox functionality only.
933 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
935 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
936 u32 head = GET_RING_HEAD( dev_priv ); \
937 if (head == dev_priv->ring.tail) \
938 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
942 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
944 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
945 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
946 int __ret = radeon_do_cp_idle( dev_priv ); \
947 if ( __ret ) return __ret; \
948 sarea_priv->last_dispatch = 0; \
949 radeon_freelist_reset( dev ); \
953 #define RADEON_DISPATCH_AGE( age ) do { \
954 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
958 #define RADEON_FRAME_AGE( age ) do { \
959 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
963 #define RADEON_CLEAR_AGE( age ) do { \
964 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
969 /* ================================================================
973 #define RADEON_VERBOSE 0
975 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
977 #define BEGIN_RING( n ) do { \
978 if ( RADEON_VERBOSE ) { \
979 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
982 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
984 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
986 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
987 ring = dev_priv->ring.start; \
988 write = dev_priv->ring.tail; \
989 mask = dev_priv->ring.tail_mask; \
992 #define ADVANCE_RING() do { \
993 if ( RADEON_VERBOSE ) { \
994 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
995 write, dev_priv->ring.tail ); \
997 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
999 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1000 ((dev_priv->ring.tail + _nr) & mask), \
1003 dev_priv->ring.tail = write; \
1006 #define COMMIT_RING() do { \
1007 /* Flush writes to ring */ \
1008 DRM_MEMORYBARRIER(); \
1009 GET_RING_HEAD( dev_priv ); \
1010 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1011 /* read from PCI bus to ensure correct posting */ \
1012 RADEON_READ( RADEON_CP_RB_RPTR ); \
1015 #define OUT_RING( x ) do { \
1016 if ( RADEON_VERBOSE ) { \
1017 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1018 (unsigned int)(x), write ); \
1020 ring[write++] = (x); \
1024 #define OUT_RING_REG( reg, val ) do { \
1025 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1030 #define OUT_RING_TABLE( tab, sz ) do { \
1032 int *_tab = (int *)(tab); \
1034 if (write + _size > mask) { \
1035 int _i = (mask+1) - write; \
1038 *(int *)(ring + write) = *_tab++; \
1046 while (_size > 0) { \
1047 *(ring + write) = *_tab++; \
1055 #endif /* __RADEON_DRV_H__ */