1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
35 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
37 typedef struct drm_radeon_freelist {
40 struct drm_radeon_freelist *next;
41 struct drm_radeon_freelist *prev;
42 } drm_radeon_freelist_t;
44 typedef struct drm_radeon_ring_buffer {
55 } drm_radeon_ring_buffer_t;
57 typedef struct drm_radeon_depth_clear_t {
59 u32 rb3d_zstencilcntl;
61 } drm_radeon_depth_clear_t;
65 struct mem_block *next;
66 struct mem_block *prev;
69 DRMFILE filp; /* 0: free, -1: heap, other: real files */
72 typedef struct drm_radeon_private {
73 drm_radeon_ring_buffer_t ring;
74 drm_radeon_sarea_t *sarea_priv;
78 unsigned long gart_buffers_offset;
83 drm_radeon_freelist_t *head;
84 drm_radeon_freelist_t *tail;
86 volatile u32 *scratch;
94 unsigned long phys_pci_gart;
95 dma_addr_t bus_pci_gart;
99 int freelist_timeouts;
102 int last_frame_reads;
103 int last_clear_reads;
113 unsigned int front_offset;
114 unsigned int front_pitch;
115 unsigned int back_offset;
116 unsigned int back_pitch;
119 unsigned int depth_offset;
120 unsigned int depth_pitch;
122 u32 front_pitch_offset;
123 u32 back_pitch_offset;
124 u32 depth_pitch_offset;
126 drm_radeon_depth_clear_t depth_clear;
128 unsigned long fb_offset;
129 unsigned long mmio_offset;
130 unsigned long ring_offset;
131 unsigned long ring_rptr_offset;
132 unsigned long buffers_offset;
133 unsigned long gart_textures_offset;
135 drm_local_map_t *sarea;
137 drm_local_map_t *mmio;
138 drm_local_map_t *cp_ring;
139 drm_local_map_t *ring_rptr;
140 drm_local_map_t *buffers;
141 drm_local_map_t *gart_textures;
143 struct mem_block *gart_heap;
144 struct mem_block *fb_heap;
147 wait_queue_head_t swi_queue;
148 atomic_t swi_emitted;
150 } drm_radeon_private_t;
152 typedef struct drm_radeon_buf_priv {
154 } drm_radeon_buf_priv_t;
157 extern int radeon_cp_init( DRM_IOCTL_ARGS );
158 extern int radeon_cp_start( DRM_IOCTL_ARGS );
159 extern int radeon_cp_stop( DRM_IOCTL_ARGS );
160 extern int radeon_cp_reset( DRM_IOCTL_ARGS );
161 extern int radeon_cp_idle( DRM_IOCTL_ARGS );
162 extern int radeon_cp_resume( DRM_IOCTL_ARGS );
163 extern int radeon_engine_reset( DRM_IOCTL_ARGS );
164 extern int radeon_fullscreen( DRM_IOCTL_ARGS );
165 extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
167 extern void radeon_freelist_reset( drm_device_t *dev );
168 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
170 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
172 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
173 extern int radeon_do_cleanup_cp( drm_device_t *dev );
174 extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
177 extern int radeon_cp_clear( DRM_IOCTL_ARGS );
178 extern int radeon_cp_swap( DRM_IOCTL_ARGS );
179 extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
180 extern int radeon_cp_indices( DRM_IOCTL_ARGS );
181 extern int radeon_cp_texture( DRM_IOCTL_ARGS );
182 extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
183 extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
184 extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
185 extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
186 extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
187 extern int radeon_cp_flip( DRM_IOCTL_ARGS );
189 extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
190 extern int radeon_mem_free( DRM_IOCTL_ARGS );
191 extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
192 extern void radeon_mem_takedown( struct mem_block **heap );
193 extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
196 extern int radeon_irq_emit( DRM_IOCTL_ARGS );
197 extern int radeon_irq_wait( DRM_IOCTL_ARGS );
199 extern int radeon_emit_and_wait_irq(drm_device_t *dev);
200 extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
201 extern int radeon_emit_irq(drm_device_t *dev);
203 extern void radeon_do_release(drm_device_t *dev);
205 /* Flags for stats.boxes
207 #define RADEON_BOX_DMA_IDLE 0x1
208 #define RADEON_BOX_RING_FULL 0x2
209 #define RADEON_BOX_FLIP 0x4
210 #define RADEON_BOX_WAIT_IDLE 0x8
211 #define RADEON_BOX_TEXTURE_LOAD 0x10
215 /* Register definitions, register access macros and drmAddMap constants
216 * for Radeon kernel driver.
219 #define RADEON_AGP_COMMAND 0x0f60
220 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
221 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
222 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
223 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
224 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
225 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
226 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
228 #define RADEON_BUS_CNTL 0x0030
229 # define RADEON_BUS_MASTER_DIS (1 << 6)
231 #define RADEON_CLOCK_CNTL_DATA 0x000c
232 # define RADEON_PLL_WR_EN (1 << 7)
233 #define RADEON_CLOCK_CNTL_INDEX 0x0008
234 #define RADEON_CONFIG_APER_SIZE 0x0108
235 #define RADEON_CRTC_OFFSET 0x0224
236 #define RADEON_CRTC_OFFSET_CNTL 0x0228
237 # define RADEON_CRTC_TILE_EN (1 << 15)
238 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
239 #define RADEON_CRTC2_OFFSET 0x0324
240 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
242 #define RADEON_RB3D_COLORPITCH 0x1c48
244 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
245 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
246 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
247 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
248 # define RADEON_GMC_BRUSH_NONE (15 << 4)
249 # define RADEON_GMC_DST_16BPP (4 << 8)
250 # define RADEON_GMC_DST_24BPP (5 << 8)
251 # define RADEON_GMC_DST_32BPP (6 << 8)
252 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
253 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
254 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
255 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
256 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
257 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
258 # define RADEON_ROP3_S 0x00cc0000
259 # define RADEON_ROP3_P 0x00f00000
260 #define RADEON_DP_WRITE_MASK 0x16cc
261 #define RADEON_DST_PITCH_OFFSET 0x142c
262 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
263 # define RADEON_DST_TILE_LINEAR (0 << 30)
264 # define RADEON_DST_TILE_MACRO (1 << 30)
265 # define RADEON_DST_TILE_MICRO (2 << 30)
266 # define RADEON_DST_TILE_BOTH (3 << 30)
268 #define RADEON_SCRATCH_REG0 0x15e0
269 #define RADEON_SCRATCH_REG1 0x15e4
270 #define RADEON_SCRATCH_REG2 0x15e8
271 #define RADEON_SCRATCH_REG3 0x15ec
272 #define RADEON_SCRATCH_REG4 0x15f0
273 #define RADEON_SCRATCH_REG5 0x15f4
274 #define RADEON_SCRATCH_UMSK 0x0770
275 #define RADEON_SCRATCH_ADDR 0x0774
277 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
279 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
280 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
281 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
284 #define RADEON_GEN_INT_CNTL 0x0040
285 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
286 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
287 # define RADEON_SW_INT_ENABLE (1 << 25)
289 #define RADEON_GEN_INT_STATUS 0x0044
290 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
291 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
292 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
293 # define RADEON_SW_INT_TEST (1 << 25)
294 # define RADEON_SW_INT_TEST_ACK (1 << 25)
295 # define RADEON_SW_INT_FIRE (1 << 26)
297 #define RADEON_HOST_PATH_CNTL 0x0130
298 # define RADEON_HDP_SOFT_RESET (1 << 26)
299 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
300 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
302 #define RADEON_ISYNC_CNTL 0x1724
303 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
304 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
305 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
306 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
307 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
308 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
310 #define RADEON_RBBM_GUICNTL 0x172c
311 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
312 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
313 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
314 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
316 #define RADEON_MC_AGP_LOCATION 0x014c
317 #define RADEON_MC_FB_LOCATION 0x0148
318 #define RADEON_MCLK_CNTL 0x0012
319 # define RADEON_FORCEON_MCLKA (1 << 16)
320 # define RADEON_FORCEON_MCLKB (1 << 17)
321 # define RADEON_FORCEON_YCLKA (1 << 18)
322 # define RADEON_FORCEON_YCLKB (1 << 19)
323 # define RADEON_FORCEON_MC (1 << 20)
324 # define RADEON_FORCEON_AIC (1 << 21)
326 #define RADEON_PP_BORDER_COLOR_0 0x1d40
327 #define RADEON_PP_BORDER_COLOR_1 0x1d44
328 #define RADEON_PP_BORDER_COLOR_2 0x1d48
329 #define RADEON_PP_CNTL 0x1c38
330 # define RADEON_SCISSOR_ENABLE (1 << 1)
331 #define RADEON_PP_LUM_MATRIX 0x1d00
332 #define RADEON_PP_MISC 0x1c14
333 #define RADEON_PP_ROT_MATRIX_0 0x1d58
334 #define RADEON_PP_TXFILTER_0 0x1c54
335 #define RADEON_PP_TXFILTER_1 0x1c6c
336 #define RADEON_PP_TXFILTER_2 0x1c84
338 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
339 # define RADEON_RB2D_DC_FLUSH (3 << 0)
340 # define RADEON_RB2D_DC_FREE (3 << 2)
341 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
342 # define RADEON_RB2D_DC_BUSY (1 << 31)
343 #define RADEON_RB3D_CNTL 0x1c3c
344 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
345 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
346 # define RADEON_DITHER_ENABLE (1 << 2)
347 # define RADEON_ROUND_ENABLE (1 << 3)
348 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
349 # define RADEON_DITHER_INIT (1 << 5)
350 # define RADEON_ROP_ENABLE (1 << 6)
351 # define RADEON_STENCIL_ENABLE (1 << 7)
352 # define RADEON_Z_ENABLE (1 << 8)
353 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
354 #define RADEON_RB3D_DEPTHPITCH 0x1c28
355 #define RADEON_RB3D_PLANEMASK 0x1d84
356 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
357 #define RADEON_RB3D_ZCACHE_MODE 0x3250
358 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
359 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
360 # define RADEON_RB3D_ZC_FREE (1 << 2)
361 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
362 # define RADEON_RB3D_ZC_BUSY (1 << 31)
363 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
364 # define RADEON_Z_TEST_MASK (7 << 4)
365 # define RADEON_Z_TEST_ALWAYS (7 << 4)
366 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
367 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
368 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
369 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
370 # define RADEON_Z_WRITE_ENABLE (1 << 30)
371 #define RADEON_RBBM_SOFT_RESET 0x00f0
372 # define RADEON_SOFT_RESET_CP (1 << 0)
373 # define RADEON_SOFT_RESET_HI (1 << 1)
374 # define RADEON_SOFT_RESET_SE (1 << 2)
375 # define RADEON_SOFT_RESET_RE (1 << 3)
376 # define RADEON_SOFT_RESET_PP (1 << 4)
377 # define RADEON_SOFT_RESET_E2 (1 << 5)
378 # define RADEON_SOFT_RESET_RB (1 << 6)
379 # define RADEON_SOFT_RESET_HDP (1 << 7)
380 #define RADEON_RBBM_STATUS 0x0e40
381 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
382 # define RADEON_RBBM_ACTIVE (1 << 31)
383 #define RADEON_RE_LINE_PATTERN 0x1cd0
384 #define RADEON_RE_MISC 0x26c4
385 #define RADEON_RE_TOP_LEFT 0x26c0
386 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
387 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
388 #define RADEON_RE_STIPPLE_DATA 0x1ccc
390 #define RADEON_SCISSOR_TL_0 0x1cd8
391 #define RADEON_SCISSOR_BR_0 0x1cdc
392 #define RADEON_SCISSOR_TL_1 0x1ce0
393 #define RADEON_SCISSOR_BR_1 0x1ce4
394 #define RADEON_SCISSOR_TL_2 0x1ce8
395 #define RADEON_SCISSOR_BR_2 0x1cec
396 #define RADEON_SE_COORD_FMT 0x1c50
397 #define RADEON_SE_CNTL 0x1c4c
398 # define RADEON_FFACE_CULL_CW (0 << 0)
399 # define RADEON_BFACE_SOLID (3 << 1)
400 # define RADEON_FFACE_SOLID (3 << 3)
401 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
402 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
403 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
404 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
405 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
406 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
407 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
408 # define RADEON_FOG_SHADE_FLAT (1 << 14)
409 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
410 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
411 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
412 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
413 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
414 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
415 #define RADEON_SE_CNTL_STATUS 0x2140
416 #define RADEON_SE_LINE_WIDTH 0x1db8
417 #define RADEON_SE_VPORT_XSCALE 0x1d98
418 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
419 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
420 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
421 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
422 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
423 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
424 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
425 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
426 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
427 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
428 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
429 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
430 #define RADEON_SURFACE_CNTL 0x0b00
431 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
432 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
433 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
434 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
435 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
436 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
437 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
438 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
439 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
440 #define RADEON_SURFACE0_INFO 0x0b0c
441 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
442 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
443 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
444 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
445 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
446 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
447 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
448 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
449 #define RADEON_SURFACE1_INFO 0x0b1c
450 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
451 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
452 #define RADEON_SURFACE2_INFO 0x0b2c
453 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
454 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
455 #define RADEON_SURFACE3_INFO 0x0b3c
456 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
457 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
458 #define RADEON_SURFACE4_INFO 0x0b4c
459 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
460 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
461 #define RADEON_SURFACE5_INFO 0x0b5c
462 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
463 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
464 #define RADEON_SURFACE6_INFO 0x0b6c
465 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
466 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
467 #define RADEON_SURFACE7_INFO 0x0b7c
468 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
469 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
470 #define RADEON_SW_SEMAPHORE 0x013c
472 #define RADEON_WAIT_UNTIL 0x1720
473 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
474 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
475 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
476 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
478 #define RADEON_RB3D_ZMASKOFFSET 0x1c34
479 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
480 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
481 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
485 #define RADEON_CP_ME_RAM_ADDR 0x07d4
486 #define RADEON_CP_ME_RAM_RADDR 0x07d8
487 #define RADEON_CP_ME_RAM_DATAH 0x07dc
488 #define RADEON_CP_ME_RAM_DATAL 0x07e0
490 #define RADEON_CP_RB_BASE 0x0700
491 #define RADEON_CP_RB_CNTL 0x0704
492 # define RADEON_BUF_SWAP_32BIT (2 << 16)
493 #define RADEON_CP_RB_RPTR_ADDR 0x070c
494 #define RADEON_CP_RB_RPTR 0x0710
495 #define RADEON_CP_RB_WPTR 0x0714
497 #define RADEON_CP_RB_WPTR_DELAY 0x0718
498 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
499 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
501 #define RADEON_CP_IB_BASE 0x0738
503 #define RADEON_CP_CSQ_CNTL 0x0740
504 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
505 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
506 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
507 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
508 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
509 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
510 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
512 #define RADEON_AIC_CNTL 0x01d0
513 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
514 #define RADEON_AIC_STAT 0x01d4
515 #define RADEON_AIC_PT_BASE 0x01d8
516 #define RADEON_AIC_LO_ADDR 0x01dc
517 #define RADEON_AIC_HI_ADDR 0x01e0
518 #define RADEON_AIC_TLB_ADDR 0x01e4
519 #define RADEON_AIC_TLB_DATA 0x01e8
521 /* CP command packets */
522 #define RADEON_CP_PACKET0 0x00000000
523 # define RADEON_ONE_REG_WR (1 << 15)
524 #define RADEON_CP_PACKET1 0x40000000
525 #define RADEON_CP_PACKET2 0x80000000
526 #define RADEON_CP_PACKET3 0xC0000000
527 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
528 # define RADEON_WAIT_FOR_IDLE 0x00002600
529 # define RADEON_3D_DRAW_VBUF 0x00002800
530 # define RADEON_3D_DRAW_IMMD 0x00002900
531 # define RADEON_3D_DRAW_INDX 0x00002A00
532 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
533 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
534 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
535 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
536 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
538 #define RADEON_CP_PACKET_MASK 0xC0000000
539 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
540 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
541 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
542 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
544 #define RADEON_VTX_Z_PRESENT (1 << 31)
545 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
547 #define RADEON_PRIM_TYPE_NONE (0 << 0)
548 #define RADEON_PRIM_TYPE_POINT (1 << 0)
549 #define RADEON_PRIM_TYPE_LINE (2 << 0)
550 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
551 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
552 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
553 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
554 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
555 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
556 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
557 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
558 #define RADEON_PRIM_TYPE_MASK 0xf
559 #define RADEON_PRIM_WALK_IND (1 << 4)
560 #define RADEON_PRIM_WALK_LIST (2 << 4)
561 #define RADEON_PRIM_WALK_RING (3 << 4)
562 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
563 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
564 #define RADEON_MAOS_ENABLE (1 << 7)
565 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
566 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
567 #define RADEON_NUM_VERTICES_SHIFT 16
569 #define RADEON_COLOR_FORMAT_CI8 2
570 #define RADEON_COLOR_FORMAT_ARGB1555 3
571 #define RADEON_COLOR_FORMAT_RGB565 4
572 #define RADEON_COLOR_FORMAT_ARGB8888 6
573 #define RADEON_COLOR_FORMAT_RGB332 7
574 #define RADEON_COLOR_FORMAT_RGB8 9
575 #define RADEON_COLOR_FORMAT_ARGB4444 15
577 #define RADEON_TXFORMAT_I8 0
578 #define RADEON_TXFORMAT_AI88 1
579 #define RADEON_TXFORMAT_RGB332 2
580 #define RADEON_TXFORMAT_ARGB1555 3
581 #define RADEON_TXFORMAT_RGB565 4
582 #define RADEON_TXFORMAT_ARGB4444 5
583 #define RADEON_TXFORMAT_ARGB8888 6
584 #define RADEON_TXFORMAT_RGBA8888 7
585 #define RADEON_TXFORMAT_Y8 8
586 #define RADEON_TXFORMAT_VYUY422 10
587 #define RADEON_TXFORMAT_YVYU422 11
588 #define RADEON_TXFORMAT_DXT1 12
589 #define RADEON_TXFORMAT_DXT23 14
590 #define RADEON_TXFORMAT_DXT45 15
592 #define R200_PP_TXCBLEND_0 0x2f00
593 #define R200_PP_TXCBLEND_1 0x2f10
594 #define R200_PP_TXCBLEND_2 0x2f20
595 #define R200_PP_TXCBLEND_3 0x2f30
596 #define R200_PP_TXCBLEND_4 0x2f40
597 #define R200_PP_TXCBLEND_5 0x2f50
598 #define R200_PP_TXCBLEND_6 0x2f60
599 #define R200_PP_TXCBLEND_7 0x2f70
600 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
601 #define R200_PP_TFACTOR_0 0x2ee0
602 #define R200_SE_VTX_FMT_0 0x2088
603 #define R200_SE_VAP_CNTL 0x2080
604 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
605 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
606 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
607 #define R200_PP_TXFILTER_5 0x2ca0
608 #define R200_PP_TXFILTER_4 0x2c80
609 #define R200_PP_TXFILTER_3 0x2c60
610 #define R200_PP_TXFILTER_2 0x2c40
611 #define R200_PP_TXFILTER_1 0x2c20
612 #define R200_PP_TXFILTER_0 0x2c00
613 #define R200_PP_TXOFFSET_5 0x2d78
614 #define R200_PP_TXOFFSET_4 0x2d60
615 #define R200_PP_TXOFFSET_3 0x2d48
616 #define R200_PP_TXOFFSET_2 0x2d30
617 #define R200_PP_TXOFFSET_1 0x2d18
618 #define R200_PP_TXOFFSET_0 0x2d00
620 #define R200_PP_CUBIC_FACES_0 0x2c18
621 #define R200_PP_CUBIC_FACES_1 0x2c38
622 #define R200_PP_CUBIC_FACES_2 0x2c58
623 #define R200_PP_CUBIC_FACES_3 0x2c78
624 #define R200_PP_CUBIC_FACES_4 0x2c98
625 #define R200_PP_CUBIC_FACES_5 0x2cb8
626 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
627 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
628 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
629 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
630 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
631 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
632 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
633 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
634 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
635 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
636 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
637 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
638 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
639 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
640 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
641 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
642 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
643 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
644 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
645 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
646 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
647 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
648 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
649 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
650 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
651 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
652 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
653 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
654 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
655 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
657 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
658 #define R200_SE_VTE_CNTL 0x20b0
659 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
660 #define R200_PP_TAM_DEBUG3 0x2d9c
661 #define R200_PP_CNTL_X 0x2cc4
662 #define R200_SE_VAP_CNTL_STATUS 0x2140
663 #define R200_RE_SCISSOR_TL_0 0x1cd8
664 #define R200_RE_SCISSOR_TL_1 0x1ce0
665 #define R200_RE_SCISSOR_TL_2 0x1ce8
666 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
667 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
668 #define R200_SE_VTX_STATE_CNTL 0x2180
669 #define R200_RE_POINTSIZE 0x2648
670 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
672 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
673 #define RADEON_PP_TEX_SIZE_1 0x1d0c
674 #define RADEON_PP_TEX_SIZE_2 0x1d14
677 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
678 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
679 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
680 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
681 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
682 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
683 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
684 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
685 #define R200_3D_DRAW_IMMD_2 0xC0003500
686 #define R200_SE_VTX_FMT_1 0x208c
687 #define R200_RE_CNTL 0x1c50
691 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
693 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
694 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
695 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
696 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
697 #define RADEON_LAST_DISPATCH 1
699 #define RADEON_MAX_VB_AGE 0x7fffffff
700 #define RADEON_MAX_VB_VERTS (0xffff)
702 #define RADEON_RING_HIGH_MARK 128
704 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
705 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
706 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
707 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
709 #define RADEON_WRITE_PLL( addr, val ) \
711 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
712 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
713 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
716 extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
719 #define CP_PACKET0( reg, n ) \
720 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
721 #define CP_PACKET0_TABLE( reg, n ) \
722 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
723 #define CP_PACKET1( reg0, reg1 ) \
724 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
725 #define CP_PACKET2() \
727 #define CP_PACKET3( pkt, n ) \
728 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
731 /* ================================================================
732 * Engine control helper macros
735 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
736 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
737 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
738 RADEON_WAIT_HOST_IDLECLEAN) ); \
741 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
742 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
743 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
744 RADEON_WAIT_HOST_IDLECLEAN) ); \
747 #define RADEON_WAIT_UNTIL_IDLE() do { \
748 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
749 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
750 RADEON_WAIT_3D_IDLECLEAN | \
751 RADEON_WAIT_HOST_IDLECLEAN) ); \
754 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
755 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
756 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
759 #define RADEON_FLUSH_CACHE() do { \
760 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
761 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
764 #define RADEON_PURGE_CACHE() do { \
765 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
766 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
769 #define RADEON_FLUSH_ZCACHE() do { \
770 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
771 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
774 #define RADEON_PURGE_ZCACHE() do { \
775 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
776 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
780 /* ================================================================
784 /* Perfbox functionality only.
786 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
788 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
789 u32 head = GET_RING_HEAD( dev_priv ); \
790 if (head == dev_priv->ring.tail) \
791 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
795 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
797 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
798 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
799 int __ret = radeon_do_cp_idle( dev_priv ); \
800 if ( __ret ) return __ret; \
801 sarea_priv->last_dispatch = 0; \
802 radeon_freelist_reset( dev ); \
806 #define RADEON_DISPATCH_AGE( age ) do { \
807 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
811 #define RADEON_FRAME_AGE( age ) do { \
812 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
816 #define RADEON_CLEAR_AGE( age ) do { \
817 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
822 /* ================================================================
826 #define RADEON_VERBOSE 0
828 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
830 #define BEGIN_RING( n ) do { \
831 if ( RADEON_VERBOSE ) { \
832 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
835 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
837 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
839 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
840 ring = dev_priv->ring.start; \
841 write = dev_priv->ring.tail; \
842 mask = dev_priv->ring.tail_mask; \
845 #define ADVANCE_RING() do { \
846 if ( RADEON_VERBOSE ) { \
847 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
848 write, dev_priv->ring.tail ); \
850 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
852 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
853 ((dev_priv->ring.tail + _nr) & mask), \
856 dev_priv->ring.tail = write; \
859 #define COMMIT_RING() do { \
860 /* Flush writes to ring */ \
861 DRM_MEMORYBARRIER(); \
862 GET_RING_HEAD( dev_priv ); \
863 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
864 /* read from PCI bus to ensure correct posting */ \
865 RADEON_READ( RADEON_CP_RB_RPTR ); \
868 #define OUT_RING( x ) do { \
869 if ( RADEON_VERBOSE ) { \
870 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
871 (unsigned int)(x), write ); \
873 ring[write++] = (x); \
877 #define OUT_RING_REG( reg, val ) do { \
878 OUT_RING( CP_PACKET0( reg, 0 ) ); \
883 #define OUT_RING_USER_TABLE( tab, sz ) do { \
887 if (write + _size > mask) { \
888 int i = (mask+1) - write; \
889 if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
891 return DRM_ERR(EFAULT); \
897 if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
899 return DRM_ERR(EFAULT); \
906 #endif /* __RADEON_DRV_H__ */