drivers/char/drm/radeon_state.c

   1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *    Gareth Hughes <gareth@valinux.com>
  27  *    Kevin E. Martin <martin@valinux.com>
  28  */
  29
  30 #include "radeon.h"
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_sarea.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36
  37
  38 /* ================================================================
  39  * CP hardware state programming functions
  40  */
  41
  42 static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
  43                                           drm_clip_rect_t *box )
  44 {
  45         RING_LOCALS;
  46
  47         DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
  48                    box->x1, box->y1, box->x2, box->y2 );
  49
  50         BEGIN_RING( 4 );
  51         OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
  52         OUT_RING( (box->y1 << 16) | box->x1 );
  53         OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
  54         OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
  55         ADVANCE_RING();
  56 }
  57
  58 /* Emit 1.1 state
  59  */
  60 static void radeon_emit_state( drm_radeon_private_t *dev_priv,
  61                                drm_radeon_context_regs_t *ctx,
  62                                drm_radeon_texture_regs_t *tex,
  63                                unsigned int dirty )
  64 {
  65         RING_LOCALS;
  66         DRM_DEBUG( "dirty=0x%08x\n", dirty );
  67
  68         if ( dirty & RADEON_UPLOAD_CONTEXT ) {
  69                 BEGIN_RING( 14 );
  70                 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
  71                 OUT_RING( ctx->pp_misc );
  72                 OUT_RING( ctx->pp_fog_color );
  73                 OUT_RING( ctx->re_solid_color );
  74                 OUT_RING( ctx->rb3d_blendcntl );
  75                 OUT_RING( ctx->rb3d_depthoffset );
  76                 OUT_RING( ctx->rb3d_depthpitch );
  77                 OUT_RING( ctx->rb3d_zstencilcntl );
  78                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
  79                 OUT_RING( ctx->pp_cntl );
  80                 OUT_RING( ctx->rb3d_cntl );
  81                 OUT_RING( ctx->rb3d_coloroffset );
  82                 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
  83                 OUT_RING( ctx->rb3d_colorpitch );
  84                 ADVANCE_RING();
  85         }
  86
  87         if ( dirty & RADEON_UPLOAD_VERTFMT ) {
  88                 BEGIN_RING( 2 );
  89                 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
  90                 OUT_RING( ctx->se_coord_fmt );
  91                 ADVANCE_RING();
  92         }
  93
  94         if ( dirty & RADEON_UPLOAD_LINE ) {
  95                 BEGIN_RING( 5 );
  96                 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
  97                 OUT_RING( ctx->re_line_pattern );
  98                 OUT_RING( ctx->re_line_state );
  99                 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
 100                 OUT_RING( ctx->se_line_width );
 101                 ADVANCE_RING();
 102         }
 103
 104         if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
 105                 BEGIN_RING( 5 );
 106                 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
 107                 OUT_RING( ctx->pp_lum_matrix );
 108                 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
 109                 OUT_RING( ctx->pp_rot_matrix_0 );
 110                 OUT_RING( ctx->pp_rot_matrix_1 );
 111                 ADVANCE_RING();
 112         }
 113
 114         if ( dirty & RADEON_UPLOAD_MASKS ) {
 115                 BEGIN_RING( 4 );
 116                 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
 117                 OUT_RING( ctx->rb3d_stencilrefmask );
 118                 OUT_RING( ctx->rb3d_ropcntl );
 119                 OUT_RING( ctx->rb3d_planemask );
 120                 ADVANCE_RING();
 121         }
 122
 123         if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
 124                 BEGIN_RING( 7 );
 125                 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
 126                 OUT_RING( ctx->se_vport_xscale );
 127                 OUT_RING( ctx->se_vport_xoffset );
 128                 OUT_RING( ctx->se_vport_yscale );
 129                 OUT_RING( ctx->se_vport_yoffset );
 130                 OUT_RING( ctx->se_vport_zscale );
 131                 OUT_RING( ctx->se_vport_zoffset );
 132                 ADVANCE_RING();
 133         }
 134
 135         if ( dirty & RADEON_UPLOAD_SETUP ) {
 136                 BEGIN_RING( 4 );
 137                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 138                 OUT_RING( ctx->se_cntl );
 139                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
 140                 OUT_RING( ctx->se_cntl_status );
 141                 ADVANCE_RING();
 142         }
 143
 144         if ( dirty & RADEON_UPLOAD_MISC ) {
 145                 BEGIN_RING( 2 );
 146                 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
 147                 OUT_RING( ctx->re_misc );
 148                 ADVANCE_RING();
 149         }
 150
 151         if ( dirty & RADEON_UPLOAD_TEX0 ) {
 152                 BEGIN_RING( 9 );
 153                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
 154                 OUT_RING( tex[0].pp_txfilter );
 155                 OUT_RING( tex[0].pp_txformat );
 156                 OUT_RING( tex[0].pp_txoffset );
 157                 OUT_RING( tex[0].pp_txcblend );
 158                 OUT_RING( tex[0].pp_txablend );
 159                 OUT_RING( tex[0].pp_tfactor );
 160                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
 161                 OUT_RING( tex[0].pp_border_color );
 162                 ADVANCE_RING();
 163         }
 164
 165         if ( dirty & RADEON_UPLOAD_TEX1 ) {
 166                 BEGIN_RING( 9 );
 167                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
 168                 OUT_RING( tex[1].pp_txfilter );
 169                 OUT_RING( tex[1].pp_txformat );
 170                 OUT_RING( tex[1].pp_txoffset );
 171                 OUT_RING( tex[1].pp_txcblend );
 172                 OUT_RING( tex[1].pp_txablend );
 173                 OUT_RING( tex[1].pp_tfactor );
 174                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
 175                 OUT_RING( tex[1].pp_border_color );
 176                 ADVANCE_RING();
 177         }
 178
 179         if ( dirty & RADEON_UPLOAD_TEX2 ) {
 180                 BEGIN_RING( 9 );
 181                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
 182                 OUT_RING( tex[2].pp_txfilter );
 183                 OUT_RING( tex[2].pp_txformat );
 184                 OUT_RING( tex[2].pp_txoffset );
 185                 OUT_RING( tex[2].pp_txcblend );
 186                 OUT_RING( tex[2].pp_txablend );
 187                 OUT_RING( tex[2].pp_tfactor );
 188                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
 189                 OUT_RING( tex[2].pp_border_color );
 190                 ADVANCE_RING();
 191         }
 192 }
 193
 194 /* Emit 1.2 state
 195  */
 196 static void radeon_emit_state2( drm_radeon_private_t *dev_priv,
 197                                 drm_radeon_state_t *state )
 198 {
 199         RING_LOCALS;
 200
 201         if (state->dirty & RADEON_UPLOAD_ZBIAS) {
 202                 BEGIN_RING( 3 );
 203                 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
 204                 OUT_RING( state->context2.se_zbias_factor );
 205                 OUT_RING( state->context2.se_zbias_constant );
 206                 ADVANCE_RING();
 207         }
 208
 209         radeon_emit_state( dev_priv, &state->context,
 210                            state->tex, state->dirty );
 211 }
 212
 213 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
 214  * 1.3 cmdbuffers allow all previous state to be updated as well as
 215  * the tcl scalar and vector areas.
 216  */
 217 static struct {
 218         int start;
 219         int len;
 220         const char *name;
 221 } packet[RADEON_MAX_STATE_PACKETS] = {
 222         { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
 223         { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
 224         { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
 225         { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
 226         { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
 227         { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
 228         { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
 229         { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
 230         { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
 231         { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
 232         { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
 233         { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
 234         { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
 235         { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
 236         { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
 237         { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
 238         { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
 239         { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
 240         { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
 241         { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
 242         { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
 243         { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
 244         { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
 245         { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
 246         { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
 247         { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
 248         { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
 249         { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
 250         { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
 251         { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 252         { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
 253         { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 254         { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 255         { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 256         { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 257         { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 258         { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 259         { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 260         { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 261         { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 262         { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 263         { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 264         { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 265         { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 266         { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 267         { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 268         { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 269         { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 270         { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 271         { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 272         { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 273         { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 274         { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 275         { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 276         { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 277         { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 278         { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 279         { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 280         { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 281         { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 282         { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 283         { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 284         { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 285         { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 286         { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 287         { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 288         { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 289         { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 290         { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 291         { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 292         { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 293         { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 294         { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 295         { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 296         { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
 297         { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
 298 };
 299
 300
 301
 302 /* ================================================================
 303  * Performance monitoring functions
 304  */
 305
 306 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 307                               int x, int y, int w, int h,
 308                               int r, int g, int b )
 309 {
 310         u32 color;
 311         RING_LOCALS;
 312
 313         x += dev_priv->sarea_priv->boxes[0].x1;
 314         y += dev_priv->sarea_priv->boxes[0].y1;
 315
 316         switch ( dev_priv->color_fmt ) {
 317         case RADEON_COLOR_FORMAT_RGB565:
 318                 color = (((r & 0xf8) << 8) |
 319                          ((g & 0xfc) << 3) |
 320                          ((b & 0xf8) >> 3));
 321                 break;
 322         case RADEON_COLOR_FORMAT_ARGB8888:
 323         default:
 324                 color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
 325                 break;
 326         }
 327
 328         BEGIN_RING( 4 );
 329         RADEON_WAIT_UNTIL_3D_IDLE();
 330         OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 331         OUT_RING( 0xffffffff );
 332         ADVANCE_RING();
 333
 334         BEGIN_RING( 6 );
 335
 336         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 337         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 338                   RADEON_GMC_BRUSH_SOLID_COLOR |
 339                   (dev_priv->color_fmt << 8) |
 340                   RADEON_GMC_SRC_DATATYPE_COLOR |
 341                   RADEON_ROP3_P |
 342                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 343
 344         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 345                 OUT_RING( dev_priv->front_pitch_offset );
 346         } else {
 347                 OUT_RING( dev_priv->back_pitch_offset );
 348         }
 349
 350         OUT_RING( color );
 351
 352         OUT_RING( (x << 16) | y );
 353         OUT_RING( (w << 16) | h );
 354
 355         ADVANCE_RING();
 356 }
 357
 358 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
 359 {
 360         /* Collapse various things into a wait flag -- trying to
 361          * guess if userspase slept -- better just to have them tell us.
 362          */
 363         if (dev_priv->stats.last_frame_reads > 1 ||
 364             dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
 365                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 366         }
 367
 368         if (dev_priv->stats.freelist_loops) {
 369                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 370         }
 371
 372         /* Purple box for page flipping
 373          */
 374         if ( dev_priv->stats.boxes & RADEON_BOX_FLIP )
 375                 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
 376
 377         /* Red box if we have to wait for idle at any point
 378          */
 379         if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE )
 380                 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
 381
 382         /* Blue box: lost context?
 383          */
 384
 385         /* Yellow box for texture swaps
 386          */
 387         if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD )
 388                 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
 389
 390         /* Green box if hardware never idles (as far as we can tell)
 391          */
 392         if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) )
 393                 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
 394
 395
 396         /* Draw bars indicating number of buffers allocated
 397          * (not a great measure, easily confused)
 398          */
 399         if (dev_priv->stats.requested_bufs) {
 400                 if (dev_priv->stats.requested_bufs > 100)
 401                         dev_priv->stats.requested_bufs = 100;
 402
 403                 radeon_clear_box( dev_priv, 4, 16,
 404                                   dev_priv->stats.requested_bufs, 4,
 405                                   196, 128, 128 );
 406         }
 407
 408         memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
 409
 410 }
 411 /* ================================================================
 412  * CP command dispatch functions
 413  */
 414
 415 static void radeon_cp_dispatch_clear( drm_device_t *dev,
 416                                       drm_radeon_clear_t *clear,
 417                                       drm_radeon_clear_rect_t *depth_boxes )
 418 {
 419         drm_radeon_private_t *dev_priv = dev->dev_private;
 420         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 421         drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
 422         int nbox = sarea_priv->nbox;
 423         drm_clip_rect_t *pbox = sarea_priv->boxes;
 424         unsigned int flags = clear->flags;
 425         u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
 426         int i;
 427         RING_LOCALS;
 428         DRM_DEBUG( "flags = 0x%x\n", flags );
 429
 430         dev_priv->stats.clears++;
 431
 432         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 433                 unsigned int tmp = flags;
 434
 435                 flags &= ~(RADEON_FRONT | RADEON_BACK);
 436                 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
 437                 if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
 438         }
 439
 440         if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
 441
 442                 BEGIN_RING( 4 );
 443
 444                 /* Ensure the 3D stream is idle before doing a
 445                  * 2D fill to clear the front or back buffer.
 446                  */
 447                 RADEON_WAIT_UNTIL_3D_IDLE();
 448
 449                 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 450                 OUT_RING( clear->color_mask );
 451
 452                 ADVANCE_RING();
 453
 454                 /* Make sure we restore the 3D state next time.
 455                  */
 456                 dev_priv->sarea_priv->ctx_owner = 0;
 457
 458                 for ( i = 0 ; i < nbox ; i++ ) {
 459                         int x = pbox[i].x1;
 460                         int y = pbox[i].y1;
 461                         int w = pbox[i].x2 - x;
 462                         int h = pbox[i].y2 - y;
 463
 464                         DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
 465                                    x, y, w, h, flags );
 466
 467                         if ( flags & RADEON_FRONT ) {
 468                                 BEGIN_RING( 6 );
 469
 470                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 471                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 472                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 473                                           (dev_priv->color_fmt << 8) |
 474                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 475                                           RADEON_ROP3_P |
 476                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 477
 478                                 OUT_RING( dev_priv->front_pitch_offset );
 479                                 OUT_RING( clear->clear_color );
 480
 481                                 OUT_RING( (x << 16) | y );
 482                                 OUT_RING( (w << 16) | h );
 483
 484                                 ADVANCE_RING();
 485                         }
 486
 487                         if ( flags & RADEON_BACK ) {
 488                                 BEGIN_RING( 6 );
 489
 490                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 491                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 492                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 493                                           (dev_priv->color_fmt << 8) |
 494                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 495                                           RADEON_ROP3_P |
 496                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 497
 498                                 OUT_RING( dev_priv->back_pitch_offset );
 499                                 OUT_RING( clear->clear_color );
 500
 501                                 OUT_RING( (x << 16) | y );
 502                                 OUT_RING( (w << 16) | h );
 503
 504                                 ADVANCE_RING();
 505                         }
 506                 }
 507         }
 508
 509         /* We have to clear the depth and/or stencil buffers by
 510          * rendering a quad into just those buffers.  Thus, we have to
 511          * make sure the 3D engine is configured correctly.
 512          */
 513         if ( dev_priv->is_r200 &&
 514              (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 515
 516                 int tempPP_CNTL;
 517                 int tempRE_CNTL;
 518                 int tempRB3D_CNTL;
 519                 int tempRB3D_ZSTENCILCNTL;
 520                 int tempRB3D_STENCILREFMASK;
 521                 int tempRB3D_PLANEMASK;
 522                 int tempSE_CNTL;
 523                 int tempSE_VTE_CNTL;
 524                 int tempSE_VTX_FMT_0;
 525                 int tempSE_VTX_FMT_1;
 526                 int tempSE_VAP_CNTL;
 527                 int tempRE_AUX_SCISSOR_CNTL;
 528
 529                 tempPP_CNTL = 0;
 530                 tempRE_CNTL = 0;
 531
 532                 tempRB3D_CNTL = depth_clear->rb3d_cntl;
 533                 tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
 534
 535                 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
 536                 tempRB3D_STENCILREFMASK = 0x0;
 537
 538                 tempSE_CNTL = depth_clear->se_cntl;
 539
 540
 541
 542                 /* Disable TCL */
 543
 544                 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
 545                                    (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
 546
 547                 tempRB3D_PLANEMASK = 0x0;
 548
 549                 tempRE_AUX_SCISSOR_CNTL = 0x0;
 550
 551                 tempSE_VTE_CNTL =
 552                         SE_VTE_CNTL__VTX_XY_FMT_MASK |
 553                         SE_VTE_CNTL__VTX_Z_FMT_MASK;
 554
 555                 /* Vertex format (X, Y, Z, W)*/
 556                 tempSE_VTX_FMT_0 =
 557                         SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
 558                         SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
 559                 tempSE_VTX_FMT_1 = 0x0;
 560
 561
 562                 /*
 563                  * Depth buffer specific enables
 564                  */
 565                 if (flags & RADEON_DEPTH) {
 566                         /* Enable depth buffer */
 567                         tempRB3D_CNTL |= RADEON_Z_ENABLE;
 568                 } else {
 569                         /* Disable depth buffer */
 570                         tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
 571                 }
 572
 573                 /*
 574                  * Stencil buffer specific enables
 575                  */
 576                 if ( flags & RADEON_STENCIL ) {
 577                         tempRB3D_CNTL |=  RADEON_STENCIL_ENABLE;
 578                         tempRB3D_STENCILREFMASK = clear->depth_mask;
 579                 } else {
 580                         tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
 581                         tempRB3D_STENCILREFMASK = 0x00000000;
 582                 }
 583
 584                 BEGIN_RING( 26 );
 585                 RADEON_WAIT_UNTIL_2D_IDLE();
 586
 587                 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
 588                 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
 589                 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
 590                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 591                               tempRB3D_ZSTENCILCNTL );
 592                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 593                               tempRB3D_STENCILREFMASK );
 594                 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
 595                 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
 596                 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
 597                 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
 598                 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
 599                 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
 600                 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
 601                               tempRE_AUX_SCISSOR_CNTL );
 602                 ADVANCE_RING();
 603
 604                 /* Make sure we restore the 3D state next time.
 605                  */
 606                 dev_priv->sarea_priv->ctx_owner = 0;
 607
 608                 for ( i = 0 ; i < nbox ; i++ ) {
 609
 610                         /* Funny that this should be required --
 611                          *  sets top-left?
 612                          */
 613                         radeon_emit_clip_rect( dev_priv,
 614                                                &sarea_priv->boxes[i] );
 615
 616                         BEGIN_RING( 14 );
 617                         OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
 618                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 619                                    RADEON_PRIM_WALK_RING |
 620                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 621                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 622                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 623                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 624                         OUT_RING( 0x3f800000 );
 625                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 626                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 627                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 628                         OUT_RING( 0x3f800000 );
 629                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 630                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 631                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 632                         OUT_RING( 0x3f800000 );
 633                         ADVANCE_RING();
 634                 }
 635         }
 636         else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 637
 638                 rb3d_cntl = depth_clear->rb3d_cntl;
 639
 640                 if ( flags & RADEON_DEPTH ) {
 641                         rb3d_cntl |=  RADEON_Z_ENABLE;
 642                 } else {
 643                         rb3d_cntl &= ~RADEON_Z_ENABLE;
 644                 }
 645
 646                 if ( flags & RADEON_STENCIL ) {
 647                         rb3d_cntl |=  RADEON_STENCIL_ENABLE;
 648                         rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
 649                 } else {
 650                         rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
 651                         rb3d_stencilrefmask = 0x00000000;
 652                 }
 653
 654                 BEGIN_RING( 13 );
 655                 RADEON_WAIT_UNTIL_2D_IDLE();
 656
 657                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
 658                 OUT_RING( 0x00000000 );
 659                 OUT_RING( rb3d_cntl );
 660
 661                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 662                               depth_clear->rb3d_zstencilcntl );
 663                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 664                               rb3d_stencilrefmask );
 665                 OUT_RING_REG( RADEON_RB3D_PLANEMASK,
 666                               0x00000000 );
 667                 OUT_RING_REG( RADEON_SE_CNTL,
 668                               depth_clear->se_cntl );
 669                 ADVANCE_RING();
 670
 671                 /* Make sure we restore the 3D state next time.
 672                  */
 673                 dev_priv->sarea_priv->ctx_owner = 0;
 674
 675                 for ( i = 0 ; i < nbox ; i++ ) {
 676
 677                         /* Funny that this should be required --
 678                          *  sets top-left?
 679                          */
 680                         radeon_emit_clip_rect( dev_priv,
 681                                                &sarea_priv->boxes[i] );
 682
 683                         BEGIN_RING( 15 );
 684
 685                         OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
 686                         OUT_RING( RADEON_VTX_Z_PRESENT |
 687                                   RADEON_VTX_PKCOLOR_PRESENT);
 688                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 689                                    RADEON_PRIM_WALK_RING |
 690                                    RADEON_MAOS_ENABLE |
 691                                    RADEON_VTX_FMT_RADEON_MODE |
 692                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 693
 694
 695                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 696                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 697                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 698                         OUT_RING( 0x0 );
 699
 700                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 701                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 702                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 703                         OUT_RING( 0x0 );
 704
 705                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 706                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 707                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 708                         OUT_RING( 0x0 );
 709
 710                         ADVANCE_RING();
 711                 }
 712         }
 713
 714         /* Increment the clear counter.  The client-side 3D driver must
 715          * wait on this value before performing the clear ioctl.  We
 716          * need this because the card's so damned fast...
 717          */
 718         dev_priv->sarea_priv->last_clear++;
 719
 720         BEGIN_RING( 4 );
 721
 722         RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
 723         RADEON_WAIT_UNTIL_IDLE();
 724
 725         ADVANCE_RING();
 726 }
 727
 728 static void radeon_cp_dispatch_swap( drm_device_t *dev )
 729 {
 730         drm_radeon_private_t *dev_priv = dev->dev_private;
 731         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 732         int nbox = sarea_priv->nbox;
 733         drm_clip_rect_t *pbox = sarea_priv->boxes;
 734         int i;
 735         RING_LOCALS;
 736         DRM_DEBUG( "\n" );
 737
 738         /* Do some trivial performance monitoring...
 739          */
 740         if (dev_priv->do_boxes)
 741                 radeon_cp_performance_boxes( dev_priv );
 742
 743
 744         /* Wait for the 3D stream to idle before dispatching the bitblt.
 745          * This will prevent data corruption between the two streams.
 746          */
 747         BEGIN_RING( 2 );
 748
 749         RADEON_WAIT_UNTIL_3D_IDLE();
 750
 751         ADVANCE_RING();
 752
 753         for ( i = 0 ; i < nbox ; i++ ) {
 754                 int x = pbox[i].x1;
 755                 int y = pbox[i].y1;
 756                 int w = pbox[i].x2 - x;
 757                 int h = pbox[i].y2 - y;
 758
 759                 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
 760                            x, y, w, h );
 761
 762                 BEGIN_RING( 7 );
 763
 764                 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
 765                 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 766                           RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 767                           RADEON_GMC_BRUSH_NONE |
 768                           (dev_priv->color_fmt << 8) |
 769                           RADEON_GMC_SRC_DATATYPE_COLOR |
 770                           RADEON_ROP3_S |
 771                           RADEON_DP_SRC_SOURCE_MEMORY |
 772                           RADEON_GMC_CLR_CMP_CNTL_DIS |
 773                           RADEON_GMC_WR_MSK_DIS );
 774
 775                 /* Make this work even if front & back are flipped:
 776                  */
 777                 if (dev_priv->current_page == 0) {
 778                         OUT_RING( dev_priv->back_pitch_offset );
 779                         OUT_RING( dev_priv->front_pitch_offset );
 780                 }
 781                 else {
 782                         OUT_RING( dev_priv->front_pitch_offset );
 783                         OUT_RING( dev_priv->back_pitch_offset );
 784                 }
 785
 786                 OUT_RING( (x << 16) | y );
 787                 OUT_RING( (x << 16) | y );
 788                 OUT_RING( (w << 16) | h );
 789
 790                 ADVANCE_RING();
 791         }
 792
 793         /* Increment the frame counter.  The client-side 3D driver must
 794          * throttle the framerate by waiting for this value before
 795          * performing the swapbuffer ioctl.
 796          */
 797         dev_priv->sarea_priv->last_frame++;
 798
 799         BEGIN_RING( 4 );
 800
 801         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 802         RADEON_WAIT_UNTIL_2D_IDLE();
 803
 804         ADVANCE_RING();
 805 }
 806
 807 static void radeon_cp_dispatch_flip( drm_device_t *dev )
 808 {
 809         drm_radeon_private_t *dev_priv = dev->dev_private;
 810         drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
 811         int offset = (dev_priv->current_page == 1)
 812                    ? dev_priv->front_offset : dev_priv->back_offset;
 813         RING_LOCALS;
 814         DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
 815                 __FUNCTION__,
 816                 dev_priv->current_page,
 817                 dev_priv->sarea_priv->pfCurrentPage);
 818
 819         /* Do some trivial performance monitoring...
 820          */
 821         if (dev_priv->do_boxes) {
 822                 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
 823                 radeon_cp_performance_boxes( dev_priv );
 824         }
 825
 826         /* Update the frame offsets for both CRTCs
 827          */
 828         BEGIN_RING( 6 );
 829
 830         RADEON_WAIT_UNTIL_3D_IDLE();
 831         OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
 832                                               + sarea->frame.x
 833                                               * ( dev_priv->color_fmt - 2 ) ) & ~7 )
 834                                           + offset );
 835         OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
 836                                            + offset );
 837
 838         ADVANCE_RING();
 839
 840         /* Increment the frame counter.  The client-side 3D driver must
 841          * throttle the framerate by waiting for this value before
 842          * performing the swapbuffer ioctl.
 843          */
 844         dev_priv->sarea_priv->last_frame++;
 845         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
 846                                               1 - dev_priv->current_page;
 847
 848         BEGIN_RING( 2 );
 849
 850         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 851
 852         ADVANCE_RING();
 853 }
 854
 855 static int bad_prim_vertex_nr( int primitive, int nr )
 856 {
 857         switch (primitive & RADEON_PRIM_TYPE_MASK) {
 858         case RADEON_PRIM_TYPE_NONE:
 859         case RADEON_PRIM_TYPE_POINT:
 860                 return nr < 1;
 861         case RADEON_PRIM_TYPE_LINE:
 862                 return (nr & 1) || nr == 0;
 863         case RADEON_PRIM_TYPE_LINE_STRIP:
 864                 return nr < 2;
 865         case RADEON_PRIM_TYPE_TRI_LIST:
 866         case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
 867         case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
 868         case RADEON_PRIM_TYPE_RECT_LIST:
 869                 return nr % 3 || nr == 0;
 870         case RADEON_PRIM_TYPE_TRI_FAN:
 871         case RADEON_PRIM_TYPE_TRI_STRIP:
 872                 return nr < 3;
 873         default:
 874                 return 1;
 875         }
 876 }
 877
 878
 879
 880 typedef struct {
 881         unsigned int start;
 882         unsigned int finish;
 883         unsigned int prim;
 884         unsigned int numverts;
 885         unsigned int offset;
 886         unsigned int vc_format;
 887 } drm_radeon_tcl_prim_t;
 888
 889 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 890                                        drm_buf_t *buf,
 891                                        drm_radeon_tcl_prim_t *prim )
 892
 893 {
 894         drm_radeon_private_t *dev_priv = dev->dev_private;
 895         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 896         int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
 897         int numverts = (int)prim->numverts;
 898         int nbox = sarea_priv->nbox;
 899         int i = 0;
 900         RING_LOCALS;
 901
 902         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
 903                   prim->prim,
 904                   prim->vc_format,
 905                   prim->start,
 906                   prim->finish,
 907                   prim->numverts);
 908
 909         if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
 910                 DRM_ERROR( "bad prim %x numverts %d\n",
 911                            prim->prim, prim->numverts );
 912                 return;
 913         }
 914
 915         do {
 916                 /* Emit the next cliprect */
 917                 if ( i < nbox ) {
 918                         radeon_emit_clip_rect( dev_priv,
 919                                                &sarea_priv->boxes[i] );
 920                 }
 921
 922                 /* Emit the vertex buffer rendering commands */
 923                 BEGIN_RING( 5 );
 924
 925                 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
 926                 OUT_RING( offset );
 927                 OUT_RING( numverts );
 928                 OUT_RING( prim->vc_format );
 929                 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
 930                           RADEON_COLOR_ORDER_RGBA |
 931                           RADEON_VTX_FMT_RADEON_MODE |
 932                           (numverts << RADEON_NUM_VERTICES_SHIFT) );
 933
 934                 ADVANCE_RING();
 935
 936                 i++;
 937         } while ( i < nbox );
 938 }
 939
 940
 941
 942 static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
 943 {
 944         drm_radeon_private_t *dev_priv = dev->dev_private;
 945         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 946         RING_LOCALS;
 947
 948         buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 949
 950         /* Emit the vertex buffer age */
 951         BEGIN_RING( 2 );
 952         RADEON_DISPATCH_AGE( buf_priv->age );
 953         ADVANCE_RING();
 954
 955         buf->pending = 1;
 956         buf->used = 0;
 957 }
 958
 959 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 960                                          drm_buf_t *buf,
 961                                          int start, int end )
 962 {
 963         drm_radeon_private_t *dev_priv = dev->dev_private;
 964         RING_LOCALS;
 965         DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
 966                    buf->idx, start, end );
 967
 968         if ( start != end ) {
 969                 int offset = (dev_priv->gart_buffers_offset
 970                               + buf->offset + start);
 971                 int dwords = (end - start + 3) / sizeof(u32);
 972
 973                 /* Indirect buffer data must be an even number of
 974                  * dwords, so if we've been given an odd number we must
 975                  * pad the data with a Type-2 CP packet.
 976                  */
 977                 if ( dwords & 1 ) {
 978                         u32 *data = (u32 *)
 979                                 ((char *)dev_priv->buffers->handle
 980                                  + buf->offset + start);
 981                         data[dwords++] = RADEON_CP_PACKET2;
 982                 }
 983
 984                 /* Fire off the indirect buffer */
 985                 BEGIN_RING( 3 );
 986
 987                 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
 988                 OUT_RING( offset );
 989                 OUT_RING( dwords );
 990
 991                 ADVANCE_RING();
 992         }
 993 }
 994
 995
 996 static void radeon_cp_dispatch_indices( drm_device_t *dev,
 997                                         drm_buf_t *elt_buf,
 998                                         drm_radeon_tcl_prim_t *prim )
 999 {
1000         drm_radeon_private_t *dev_priv = dev->dev_private;
1001         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1002         int offset = dev_priv->gart_buffers_offset + prim->offset;
1003         u32 *data;
1004         int dwords;
1005         int i = 0;
1006         int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1007         int count = (prim->finish - start) / sizeof(u16);
1008         int nbox = sarea_priv->nbox;
1009
1010         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1011                   prim->prim,
1012                   prim->vc_format,
1013                   prim->start,
1014                   prim->finish,
1015                   prim->offset,
1016                   prim->numverts);
1017
1018         if (bad_prim_vertex_nr( prim->prim, count )) {
1019                 DRM_ERROR( "bad prim %x count %d\n",
1020                            prim->prim, count );
1021                 return;
1022         }
1023
1024
1025         if ( start >= prim->finish ||
1026              (prim->start & 0x7) ) {
1027                 DRM_ERROR( "buffer prim %d\n", prim->prim );
1028                 return;
1029         }
1030
1031         dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1032
1033         data = (u32 *)((char *)dev_priv->buffers->handle +
1034                        elt_buf->offset + prim->start);
1035
1036         data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
1037         data[1] = offset;
1038         data[2] = prim->numverts;
1039         data[3] = prim->vc_format;
1040         data[4] = (prim->prim |
1041                    RADEON_PRIM_WALK_IND |
1042                    RADEON_COLOR_ORDER_RGBA |
1043                    RADEON_VTX_FMT_RADEON_MODE |
1044                    (count << RADEON_NUM_VERTICES_SHIFT) );
1045
1046         do {
1047                 if ( i < nbox )
1048                         radeon_emit_clip_rect( dev_priv,
1049                                                &sarea_priv->boxes[i] );
1050
1051                 radeon_cp_dispatch_indirect( dev, elt_buf,
1052                                              prim->start,
1053                                              prim->finish );
1054
1055                 i++;
1056         } while ( i < nbox );
1057
1058 }
1059
1060 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
1061
1062 static int radeon_cp_dispatch_texture( DRMFILE filp,
1063                                        drm_device_t *dev,
1064                                        drm_radeon_texture_t *tex,
1065                                        drm_radeon_tex_image_t *image )
1066 {
1067         drm_radeon_private_t *dev_priv = dev->dev_private;
1068         drm_buf_t *buf;
1069         u32 format;
1070         u32 *buffer;
1071         const u8 *data;
1072         int size, dwords, tex_width, blit_width;
1073         u32 height;
1074         int i;
1075         RING_LOCALS;
1076
1077         dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1078
1079         /* Flush the pixel cache.  This ensures no pixel data gets mixed
1080          * up with the texture data from the host data blit, otherwise
1081          * part of the texture image may be corrupted.
1082          */
1083         BEGIN_RING( 4 );
1084         RADEON_FLUSH_CACHE();
1085         RADEON_WAIT_UNTIL_IDLE();
1086         ADVANCE_RING();
1087
1088 #ifdef __BIG_ENDIAN
1089         /* The Mesa texture functions provide the data in little endian as the
1090          * chip wants it, but we need to compensate for the fact that the CP
1091          * ring gets byte-swapped
1092          */
1093         BEGIN_RING( 2 );
1094         OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
1095         ADVANCE_RING();
1096 #endif
1097
1098
1099         /* The compiler won't optimize away a division by a variable,
1100          * even if the only legal values are powers of two.  Thus, we'll
1101          * use a shift instead.
1102          */
1103         switch ( tex->format ) {
1104         case RADEON_TXFORMAT_ARGB8888:
1105         case RADEON_TXFORMAT_RGBA8888:
1106                 format = RADEON_COLOR_FORMAT_ARGB8888;
1107                 tex_width = tex->width * 4;
1108                 blit_width = image->width * 4;
1109                 break;
1110         case RADEON_TXFORMAT_AI88:
1111         case RADEON_TXFORMAT_ARGB1555:
1112         case RADEON_TXFORMAT_RGB565:
1113         case RADEON_TXFORMAT_ARGB4444:
1114         case RADEON_TXFORMAT_VYUY422:
1115         case RADEON_TXFORMAT_YVYU422:
1116                 format = RADEON_COLOR_FORMAT_RGB565;
1117                 tex_width = tex->width * 2;
1118                 blit_width = image->width * 2;
1119                 break;
1120         case RADEON_TXFORMAT_I8:
1121         case RADEON_TXFORMAT_RGB332:
1122                 format = RADEON_COLOR_FORMAT_CI8;
1123                 tex_width = tex->width * 1;
1124                 blit_width = image->width * 1;
1125                 break;
1126         default:
1127                 DRM_ERROR( "invalid texture format %d\n", tex->format );
1128                 return DRM_ERR(EINVAL);
1129         }
1130
1131         DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
1132
1133         do {
1134                 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1135                            tex->offset >> 10, tex->pitch, tex->format,
1136                            image->x, image->y, image->width, image->height );
1137
1138                 /* Make a copy of some parameters in case we have to
1139                  * update them for a multi-pass texture blit.
1140                  */
1141                 height = image->height;
1142                 data = (const u8 *)image->data;
1143
1144                 size = height * blit_width;
1145
1146                 if ( size > RADEON_MAX_TEXTURE_SIZE ) {
1147                         height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1148                         size = height * blit_width;
1149                 } else if ( size < 4 && size > 0 ) {
1150                         size = 4;
1151                 } else if ( size == 0 ) {
1152                         return 0;
1153                 }
1154
1155                 buf = radeon_freelist_get( dev );
1156                 if ( 0 && !buf ) {
1157                         radeon_do_cp_idle( dev_priv );
1158                         buf = radeon_freelist_get( dev );
1159                 }
1160                 if ( !buf ) {
1161                         DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1162                         DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
1163                         return DRM_ERR(EAGAIN);
1164                 }
1165
1166
1167                 /* Dispatch the indirect buffer.
1168                  */
1169                 buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);
1170                 dwords = size / 4;
1171                 buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1172                 buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1173                              RADEON_GMC_BRUSH_NONE |
1174                              (format << 8) |
1175                              RADEON_GMC_SRC_DATATYPE_COLOR |
1176                              RADEON_ROP3_S |
1177                              RADEON_DP_SRC_SOURCE_HOST_DATA |
1178                              RADEON_GMC_CLR_CMP_CNTL_DIS |
1179                              RADEON_GMC_WR_MSK_DIS);
1180
1181                 buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
1182                 buffer[3] = 0xffffffff;
1183                 buffer[4] = 0xffffffff;
1184                 buffer[5] = (image->y << 16) | image->x;
1185                 buffer[6] = (height << 16) | image->width;
1186                 buffer[7] = dwords;
1187                 buffer += 8;
1188
1189                 if ( tex_width >= 32 ) {
1190                         /* Texture image width is larger than the minimum, so we
1191                          * can upload it directly.
1192                          */
1193                         if ( DRM_COPY_FROM_USER( buffer, data,
1194                                                  dwords * sizeof(u32) ) ) {
1195                                 DRM_ERROR( "EFAULT on data, %d dwords\n",
1196                                            dwords );
1197                                 return DRM_ERR(EFAULT);
1198                         }
1199                 } else {
1200                         /* Texture image width is less than the minimum, so we
1201                          * need to pad out each image scanline to the minimum
1202                          * width.
1203                          */
1204                         for ( i = 0 ; i < tex->height ; i++ ) {
1205                                 if ( DRM_COPY_FROM_USER( buffer, data,
1206                                                          tex_width ) ) {
1207                                         DRM_ERROR( "EFAULT on pad, %d bytes\n",
1208                                                    tex_width );
1209                                         return DRM_ERR(EFAULT);
1210                                 }
1211                                 buffer += 8;
1212                                 data += tex_width;
1213                         }
1214                 }
1215
1216                 buf->filp = filp;
1217                 buf->used = (dwords + 8) * sizeof(u32);
1218                 radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1219                 radeon_cp_discard_buffer( dev, buf );
1220
1221                 /* Update the input parameters for next time */
1222                 image->y += height;
1223                 image->height -= height;
1224                 image->data = (const u8 *)image->data + size;
1225         } while (image->height > 0);
1226
1227         /* Flush the pixel cache after the blit completes.  This ensures
1228          * the texture data is written out to memory before rendering
1229          * continues.
1230          */
1231         BEGIN_RING( 4 );
1232         RADEON_FLUSH_CACHE();
1233         RADEON_WAIT_UNTIL_2D_IDLE();
1234         ADVANCE_RING();
1235         return 0;
1236 }
1237
1238
1239 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1240 {
1241         drm_radeon_private_t *dev_priv = dev->dev_private;
1242         int i;
1243         RING_LOCALS;
1244         DRM_DEBUG( "\n" );
1245
1246         BEGIN_RING( 35 );
1247
1248         OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1249         OUT_RING( 0x00000000 );
1250
1251         OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1252         for ( i = 0 ; i < 32 ; i++ ) {
1253                 OUT_RING( stipple[i] );
1254         }
1255
1256         ADVANCE_RING();
1257 }
1258
1259
1260 /* ================================================================
1261  * IOCTL functions
1262  */
1263
1264 int radeon_cp_clear( DRM_IOCTL_ARGS )
1265 {
1266         DRM_DEVICE;
1267         drm_radeon_private_t *dev_priv = dev->dev_private;
1268         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1269         drm_radeon_clear_t clear;
1270         drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1271         DRM_DEBUG( "\n" );
1272
1273         LOCK_TEST_WITH_RETURN( dev, filp );
1274
1275         DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t *)data,
1276                              sizeof(clear) );
1277
1278         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1279
1280         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1281                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1282
1283         if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
1284                              sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1285                 return DRM_ERR(EFAULT);
1286
1287         radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1288
1289         COMMIT_RING();
1290         return 0;
1291 }
1292
1293
1294 /* Not sure why this isn't set all the time:
1295  */
1296 static int radeon_do_init_pageflip( drm_device_t *dev )
1297 {
1298         drm_radeon_private_t *dev_priv = dev->dev_private;
1299         RING_LOCALS;
1300
1301         DRM_DEBUG( "\n" );
1302
1303         BEGIN_RING( 6 );
1304         RADEON_WAIT_UNTIL_3D_IDLE();
1305         OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
1306         OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1307         OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
1308         OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1309         ADVANCE_RING();
1310
1311         dev_priv->page_flipping = 1;
1312         dev_priv->current_page = 0;
1313         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1314
1315         return 0;
1316 }
1317
1318 /* Called whenever a client dies, from DRM(release).
1319  * NOTE:  Lock isn't necessarily held when this is called!
1320  */
1321 int radeon_do_cleanup_pageflip( drm_device_t *dev )
1322 {
1323         drm_radeon_private_t *dev_priv = dev->dev_private;
1324         DRM_DEBUG( "\n" );
1325
1326         if (dev_priv->current_page != 0)
1327                 radeon_cp_dispatch_flip( dev );
1328
1329         dev_priv->page_flipping = 0;
1330         return 0;
1331 }
1332
1333 /* Swapping and flipping are different operations, need different ioctls.
1334  * They can & should be intermixed to support multiple 3d windows.
1335  */
1336 int radeon_cp_flip( DRM_IOCTL_ARGS )
1337 {
1338         DRM_DEVICE;
1339         drm_radeon_private_t *dev_priv = dev->dev_private;
1340         DRM_DEBUG( "\n" );
1341
1342         LOCK_TEST_WITH_RETURN( dev, filp );
1343
1344         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1345
1346         if (!dev_priv->page_flipping)
1347                 radeon_do_init_pageflip( dev );
1348
1349         radeon_cp_dispatch_flip( dev );
1350
1351         COMMIT_RING();
1352         return 0;
1353 }
1354
1355 int radeon_cp_swap( DRM_IOCTL_ARGS )
1356 {
1357         DRM_DEVICE;
1358         drm_radeon_private_t *dev_priv = dev->dev_private;
1359         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1360         DRM_DEBUG( "\n" );
1361
1362         LOCK_TEST_WITH_RETURN( dev, filp );
1363
1364         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1365
1366         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1367                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1368
1369         radeon_cp_dispatch_swap( dev );
1370         dev_priv->sarea_priv->ctx_owner = 0;
1371
1372         COMMIT_RING();
1373         return 0;
1374 }
1375
1376 int radeon_cp_vertex( DRM_IOCTL_ARGS )
1377 {
1378         DRM_DEVICE;
1379         drm_radeon_private_t *dev_priv = dev->dev_private;
1380         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1381         drm_device_dma_t *dma = dev->dma;
1382         drm_buf_t *buf;
1383         drm_radeon_vertex_t vertex;
1384         drm_radeon_tcl_prim_t prim;
1385
1386         LOCK_TEST_WITH_RETURN( dev, filp );
1387
1388         if ( !dev_priv ) {
1389                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1390                 return DRM_ERR(EINVAL);
1391         }
1392
1393         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t *)data,
1394                              sizeof(vertex) );
1395
1396         DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
1397                    DRM_CURRENTPID,
1398                    vertex.idx, vertex.count, vertex.discard );
1399
1400         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1401                 DRM_ERROR( "buffer index %d (of %d max)\n",
1402                            vertex.idx, dma->buf_count - 1 );
1403                 return DRM_ERR(EINVAL);
1404         }
1405         if ( vertex.prim < 0 ||
1406              vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1407                 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1408                 return DRM_ERR(EINVAL);
1409         }
1410
1411         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1412         VB_AGE_TEST_WITH_RETURN( dev_priv );
1413
1414         buf = dma->buflist[vertex.idx];
1415
1416         if ( buf->filp != filp ) {
1417                 DRM_ERROR( "process %d using buffer owned by %p\n",
1418                            DRM_CURRENTPID, buf->filp );
1419                 return DRM_ERR(EINVAL);
1420         }
1421         if ( buf->pending ) {
1422                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1423                 return DRM_ERR(EINVAL);
1424         }
1425
1426         /* Build up a prim_t record:
1427          */
1428         if (vertex.count) {
1429                 buf->used = vertex.count; /* not used? */
1430
1431                 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1432                         radeon_emit_state( dev_priv,
1433                                            &sarea_priv->context_state,
1434                                            sarea_priv->tex_state,
1435                                            sarea_priv->dirty );
1436
1437                         sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1438                                                RADEON_UPLOAD_TEX1IMAGES |
1439                                                RADEON_UPLOAD_TEX2IMAGES |
1440                                                RADEON_REQUIRE_QUIESCENCE);
1441                 }
1442
1443                 prim.start = 0;
1444                 prim.finish = vertex.count; /* unused */
1445                 prim.prim = vertex.prim;
1446                 prim.numverts = vertex.count;
1447                 prim.vc_format = dev_priv->sarea_priv->vc_format;
1448
1449                 radeon_cp_dispatch_vertex( dev, buf, &prim );
1450         }
1451
1452         if (vertex.discard) {
1453                 radeon_cp_discard_buffer( dev, buf );
1454         }
1455
1456         COMMIT_RING();
1457         return 0;
1458 }
1459
1460 int radeon_cp_indices( DRM_IOCTL_ARGS )
1461 {
1462         DRM_DEVICE;
1463         drm_radeon_private_t *dev_priv = dev->dev_private;
1464         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1465         drm_device_dma_t *dma = dev->dma;
1466         drm_buf_t *buf;
1467         drm_radeon_indices_t elts;
1468         drm_radeon_tcl_prim_t prim;
1469         int count;
1470
1471         LOCK_TEST_WITH_RETURN( dev, filp );
1472
1473         if ( !dev_priv ) {
1474                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1475                 return DRM_ERR(EINVAL);
1476         }
1477
1478         DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t *)data,
1479                              sizeof(elts) );
1480
1481         DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
1482                    DRM_CURRENTPID,
1483                    elts.idx, elts.start, elts.end, elts.discard );
1484
1485         if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1486                 DRM_ERROR( "buffer index %d (of %d max)\n",
1487                            elts.idx, dma->buf_count - 1 );
1488                 return DRM_ERR(EINVAL);
1489         }
1490         if ( elts.prim < 0 ||
1491              elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1492                 DRM_ERROR( "buffer prim %d\n", elts.prim );
1493                 return DRM_ERR(EINVAL);
1494         }
1495
1496         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1497         VB_AGE_TEST_WITH_RETURN( dev_priv );
1498
1499         buf = dma->buflist[elts.idx];
1500
1501         if ( buf->filp != filp ) {
1502                 DRM_ERROR( "process %d using buffer owned by %p\n",
1503                            DRM_CURRENTPID, buf->filp );
1504                 return DRM_ERR(EINVAL);
1505         }
1506         if ( buf->pending ) {
1507                 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1508                 return DRM_ERR(EINVAL);
1509         }
1510
1511         count = (elts.end - elts.start) / sizeof(u16);
1512         elts.start -= RADEON_INDEX_PRIM_OFFSET;
1513
1514         if ( elts.start & 0x7 ) {
1515                 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1516                 return DRM_ERR(EINVAL);
1517         }
1518         if ( elts.start < buf->used ) {
1519                 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1520                 return DRM_ERR(EINVAL);
1521         }
1522
1523         buf->used = elts.end;
1524
1525         if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1526                 radeon_emit_state( dev_priv,
1527                                    &sarea_priv->context_state,
1528                                    sarea_priv->tex_state,
1529                                    sarea_priv->dirty );
1530
1531                 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1532                                        RADEON_UPLOAD_TEX1IMAGES |
1533                                        RADEON_UPLOAD_TEX2IMAGES |
1534                                        RADEON_REQUIRE_QUIESCENCE);
1535         }
1536
1537
1538         /* Build up a prim_t record:
1539          */
1540         prim.start = elts.start;
1541         prim.finish = elts.end;
1542         prim.prim = elts.prim;
1543         prim.offset = 0;        /* offset from start of dma buffers */
1544         prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1545         prim.vc_format = dev_priv->sarea_priv->vc_format;
1546
1547         radeon_cp_dispatch_indices( dev, buf, &prim );
1548         if (elts.discard) {
1549                 radeon_cp_discard_buffer( dev, buf );
1550         }
1551
1552         COMMIT_RING();
1553         return 0;
1554 }
1555
1556 int radeon_cp_texture( DRM_IOCTL_ARGS )
1557 {
1558         DRM_DEVICE;
1559         drm_radeon_private_t *dev_priv = dev->dev_private;
1560         drm_radeon_texture_t tex;
1561         drm_radeon_tex_image_t image;
1562         int ret;
1563
1564         LOCK_TEST_WITH_RETURN( dev, filp );
1565
1566         DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t *)data, sizeof(tex) );
1567
1568         if ( tex.image == NULL ) {
1569                 DRM_ERROR( "null texture image!\n" );
1570                 return DRM_ERR(EINVAL);
1571         }
1572
1573         if ( DRM_COPY_FROM_USER( &image,
1574                              (drm_radeon_tex_image_t *)tex.image,
1575                              sizeof(image) ) )
1576                 return DRM_ERR(EFAULT);
1577
1578         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1579         VB_AGE_TEST_WITH_RETURN( dev_priv );
1580
1581         ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image );
1582
1583         COMMIT_RING();
1584         return ret;
1585 }
1586
1587 int radeon_cp_stipple( DRM_IOCTL_ARGS )
1588 {
1589         DRM_DEVICE;
1590         drm_radeon_private_t *dev_priv = dev->dev_private;
1591         drm_radeon_stipple_t stipple;
1592         u32 mask[32];
1593
1594         LOCK_TEST_WITH_RETURN( dev, filp );
1595
1596         DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t *)data,
1597                              sizeof(stipple) );
1598
1599         if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
1600                 return DRM_ERR(EFAULT);
1601
1602         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1603
1604         radeon_cp_dispatch_stipple( dev, mask );
1605
1606         COMMIT_RING();
1607         return 0;
1608 }
1609
1610 int radeon_cp_indirect( DRM_IOCTL_ARGS )
1611 {
1612         DRM_DEVICE;
1613         drm_radeon_private_t *dev_priv = dev->dev_private;
1614         drm_device_dma_t *dma = dev->dma;
1615         drm_buf_t *buf;
1616         drm_radeon_indirect_t indirect;
1617         RING_LOCALS;
1618
1619         LOCK_TEST_WITH_RETURN( dev, filp );
1620
1621         if ( !dev_priv ) {
1622                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1623                 return DRM_ERR(EINVAL);
1624         }
1625
1626         DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t *)data,
1627                              sizeof(indirect) );
1628
1629         DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1630                    indirect.idx, indirect.start,
1631                    indirect.end, indirect.discard );
1632
1633         if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1634                 DRM_ERROR( "buffer index %d (of %d max)\n",
1635                            indirect.idx, dma->buf_count - 1 );
1636                 return DRM_ERR(EINVAL);
1637         }
1638
1639         buf = dma->buflist[indirect.idx];
1640
1641         if ( buf->filp != filp ) {
1642                 DRM_ERROR( "process %d using buffer owned by %p\n",
1643                            DRM_CURRENTPID, buf->filp );
1644                 return DRM_ERR(EINVAL);
1645         }
1646         if ( buf->pending ) {
1647                 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1648                 return DRM_ERR(EINVAL);
1649         }
1650
1651         if ( indirect.start < buf->used ) {
1652                 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1653                            indirect.start, buf->used );
1654                 return DRM_ERR(EINVAL);
1655         }
1656
1657         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1658         VB_AGE_TEST_WITH_RETURN( dev_priv );
1659
1660         buf->used = indirect.end;
1661
1662         /* Wait for the 3D stream to idle before the indirect buffer
1663          * containing 2D acceleration commands is processed.
1664          */
1665         BEGIN_RING( 2 );
1666
1667         RADEON_WAIT_UNTIL_3D_IDLE();
1668
1669         ADVANCE_RING();
1670
1671         /* Dispatch the indirect buffer full of commands from the
1672          * X server.  This is insecure and is thus only available to
1673          * privileged clients.
1674          */
1675         radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
1676         if (indirect.discard) {
1677                 radeon_cp_discard_buffer( dev, buf );
1678         }
1679
1680
1681         COMMIT_RING();
1682         return 0;
1683 }
1684
1685 int radeon_cp_vertex2( DRM_IOCTL_ARGS )
1686 {
1687         DRM_DEVICE;
1688         drm_radeon_private_t *dev_priv = dev->dev_private;
1689         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1690         drm_device_dma_t *dma = dev->dma;
1691         drm_buf_t *buf;
1692         drm_radeon_vertex2_t vertex;
1693         int i;
1694         unsigned char laststate;
1695
1696         LOCK_TEST_WITH_RETURN( dev, filp );
1697
1698         if ( !dev_priv ) {
1699                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1700                 return DRM_ERR(EINVAL);
1701         }
1702
1703         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t *)data,
1704                              sizeof(vertex) );
1705
1706         DRM_DEBUG( "pid=%d index=%d discard=%d\n",
1707                    DRM_CURRENTPID,
1708                    vertex.idx, vertex.discard );
1709
1710         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1711                 DRM_ERROR( "buffer index %d (of %d max)\n",
1712                            vertex.idx, dma->buf_count - 1 );
1713                 return DRM_ERR(EINVAL);
1714         }
1715
1716         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1717         VB_AGE_TEST_WITH_RETURN( dev_priv );
1718
1719         buf = dma->buflist[vertex.idx];
1720
1721         if ( buf->filp != filp ) {
1722                 DRM_ERROR( "process %d using buffer owned by %p\n",
1723                            DRM_CURRENTPID, buf->filp );
1724                 return DRM_ERR(EINVAL);
1725         }
1726
1727         if ( buf->pending ) {
1728                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1729                 return DRM_ERR(EINVAL);
1730         }
1731
1732         if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
1733                 return DRM_ERR(EINVAL);
1734
1735         for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
1736                 drm_radeon_prim_t prim;
1737                 drm_radeon_tcl_prim_t tclprim;
1738
1739                 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
1740                         return DRM_ERR(EFAULT);
1741
1742                 if ( prim.stateidx != laststate ) {
1743                         drm_radeon_state_t state;
1744
1745                         if ( DRM_COPY_FROM_USER( &state,
1746                                              &vertex.state[prim.stateidx],
1747                                              sizeof(state) ) )
1748                                 return DRM_ERR(EFAULT);
1749
1750                         radeon_emit_state2( dev_priv, &state );
1751
1752                         laststate = prim.stateidx;
1753                 }
1754
1755                 tclprim.start = prim.start;
1756                 tclprim.finish = prim.finish;
1757                 tclprim.prim = prim.prim;
1758                 tclprim.vc_format = prim.vc_format;
1759
1760                 if ( prim.prim & RADEON_PRIM_WALK_IND ) {
1761                         tclprim.offset = prim.numverts * 64;
1762                         tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1763
1764                         radeon_cp_dispatch_indices( dev, buf, &tclprim );
1765                 } else {
1766                         tclprim.numverts = prim.numverts;
1767                         tclprim.offset = 0; /* not used */
1768
1769                         radeon_cp_dispatch_vertex( dev, buf, &tclprim );
1770                 }
1771
1772                 if (sarea_priv->nbox == 1)
1773                         sarea_priv->nbox = 0;
1774         }
1775
1776         if ( vertex.discard ) {
1777                 radeon_cp_discard_buffer( dev, buf );
1778         }
1779
1780         COMMIT_RING();
1781         return 0;
1782 }
1783
1784
1785 static int radeon_emit_packets(
1786         drm_radeon_private_t *dev_priv,
1787         drm_radeon_cmd_header_t header,
1788         drm_radeon_cmd_buffer_t *cmdbuf )
1789 {
1790         int id = (int)header.packet.packet_id;
1791         int sz, reg;
1792         int *data = (int *)cmdbuf->buf;
1793         RING_LOCALS;
1794
1795         if (id >= RADEON_MAX_STATE_PACKETS)
1796                 return DRM_ERR(EINVAL);
1797
1798         sz = packet[id].len;
1799         reg = packet[id].start;
1800
1801         if (sz * sizeof(int) > cmdbuf->bufsz)
1802                 return DRM_ERR(EINVAL);
1803
1804         BEGIN_RING(sz+1);
1805         OUT_RING( CP_PACKET0( reg, (sz-1) ) );
1806         OUT_RING_USER_TABLE( data, sz );
1807         ADVANCE_RING();
1808
1809         cmdbuf->buf += sz * sizeof(int);
1810         cmdbuf->bufsz -= sz * sizeof(int);
1811         return 0;
1812 }
1813
1814 static __inline__ int radeon_emit_scalars(
1815         drm_radeon_private_t *dev_priv,
1816         drm_radeon_cmd_header_t header,
1817         drm_radeon_cmd_buffer_t *cmdbuf )
1818 {
1819         int sz = header.scalars.count;
1820         int *data = (int *)cmdbuf->buf;
1821         int start = header.scalars.offset;
1822         int stride = header.scalars.stride;
1823         RING_LOCALS;
1824
1825         BEGIN_RING( 3+sz );
1826         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
1827         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
1828         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
1829         OUT_RING_USER_TABLE( data, sz );
1830         ADVANCE_RING();
1831         cmdbuf->buf += sz * sizeof(int);
1832         cmdbuf->bufsz -= sz * sizeof(int);
1833         return 0;
1834 }
1835
1836 /* God this is ugly
1837  */
1838 static __inline__ int radeon_emit_scalars2(
1839         drm_radeon_private_t *dev_priv,
1840         drm_radeon_cmd_header_t header,
1841         drm_radeon_cmd_buffer_t *cmdbuf )
1842 {
1843         int sz = header.scalars.count;
1844         int *data = (int *)cmdbuf->buf;
1845         int start = ((unsigned int)header.scalars.offset) + 0x100;
1846         int stride = header.scalars.stride;
1847         RING_LOCALS;
1848
1849         BEGIN_RING( 3+sz );
1850         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
1851         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
1852         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
1853         OUT_RING_USER_TABLE( data, sz );
1854         ADVANCE_RING();
1855         cmdbuf->buf += sz * sizeof(int);
1856         cmdbuf->bufsz -= sz * sizeof(int);
1857         return 0;
1858 }
1859
1860 static __inline__ int radeon_emit_vectors(
1861         drm_radeon_private_t *dev_priv,
1862         drm_radeon_cmd_header_t header,
1863         drm_radeon_cmd_buffer_t *cmdbuf )
1864 {
1865         int sz = header.vectors.count;
1866         int *data = (int *)cmdbuf->buf;
1867         int start = header.vectors.offset;
1868         int stride = header.vectors.stride;
1869         RING_LOCALS;
1870
1871         BEGIN_RING( 3+sz );
1872         OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
1873         OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
1874         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
1875         OUT_RING_USER_TABLE( data, sz );
1876         ADVANCE_RING();
1877
1878         cmdbuf->buf += sz * sizeof(int);
1879         cmdbuf->bufsz -= sz * sizeof(int);
1880         return 0;
1881 }
1882
1883
1884 static int radeon_emit_packet3( drm_device_t *dev,
1885                                 drm_radeon_cmd_buffer_t *cmdbuf )
1886 {
1887         drm_radeon_private_t *dev_priv = dev->dev_private;
1888         int cmdsz, tmp;
1889         int *cmd = (int *)cmdbuf->buf;
1890         RING_LOCALS;
1891
1892
1893         DRM_DEBUG("\n");
1894
1895         if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
1896                 return DRM_ERR(EFAULT);
1897
1898         cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1899
1900         if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
1901             cmdsz * 4 > cmdbuf->bufsz)
1902                 return DRM_ERR(EINVAL);
1903
1904         BEGIN_RING( cmdsz );
1905         OUT_RING_USER_TABLE( cmd, cmdsz );
1906         ADVANCE_RING();
1907
1908         cmdbuf->buf += cmdsz * 4;
1909         cmdbuf->bufsz -= cmdsz * 4;
1910         return 0;
1911 }
1912
1913
1914 static int radeon_emit_packet3_cliprect( drm_device_t *dev,
1915                                          drm_radeon_cmd_buffer_t *cmdbuf,
1916                                          int orig_nbox )
1917 {
1918         drm_radeon_private_t *dev_priv = dev->dev_private;
1919         drm_clip_rect_t box;
1920         int cmdsz, tmp;
1921         int *cmd = (int *)cmdbuf->buf;
1922         drm_clip_rect_t *boxes = cmdbuf->boxes;
1923         int i = 0;
1924         RING_LOCALS;
1925
1926         DRM_DEBUG("\n");
1927
1928         if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
1929                 return DRM_ERR(EFAULT);
1930
1931         cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1932
1933         if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
1934             cmdsz * 4 > cmdbuf->bufsz)
1935                 return DRM_ERR(EINVAL);
1936
1937         if (!orig_nbox)
1938                 goto out;
1939
1940         do {
1941                 if ( i < cmdbuf->nbox ) {
1942                         if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
1943                                 return DRM_ERR(EFAULT);
1944                         /* FIXME The second and subsequent times round
1945                          * this loop, send a WAIT_UNTIL_3D_IDLE before
1946                          * calling emit_clip_rect(). This fixes a
1947                          * lockup on fast machines when sending
1948                          * several cliprects with a cmdbuf, as when
1949                          * waving a 2D window over a 3D
1950                          * window. Something in the commands from user
1951                          * space seems to hang the card when they're
1952                          * sent several times in a row. That would be
1953                          * the correct place to fix it but this works
1954                          * around it until I can figure that out - Tim
1955                          * Smith */
1956                         if ( i ) {
1957                                 BEGIN_RING( 2 );
1958                                 RADEON_WAIT_UNTIL_3D_IDLE();
1959                                 ADVANCE_RING();
1960                         }
1961                         radeon_emit_clip_rect( dev_priv, &box );
1962                 }
1963
1964                 BEGIN_RING( cmdsz );
1965                 OUT_RING_USER_TABLE( cmd, cmdsz );
1966                 ADVANCE_RING();
1967
1968         } while ( ++i < cmdbuf->nbox );
1969         if (cmdbuf->nbox == 1)
1970                 cmdbuf->nbox = 0;
1971
1972  out:
1973         cmdbuf->buf += cmdsz * 4;
1974         cmdbuf->bufsz -= cmdsz * 4;
1975         return 0;
1976 }
1977
1978
1979 static int radeon_emit_wait( drm_device_t *dev, int flags )
1980 {
1981         drm_radeon_private_t *dev_priv = dev->dev_private;
1982         RING_LOCALS;
1983
1984         DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
1985         switch (flags) {
1986         case RADEON_WAIT_2D:
1987                 BEGIN_RING( 2 );
1988                 RADEON_WAIT_UNTIL_2D_IDLE();
1989                 ADVANCE_RING();
1990                 break;
1991         case RADEON_WAIT_3D:
1992                 BEGIN_RING( 2 );
1993                 RADEON_WAIT_UNTIL_3D_IDLE();
1994                 ADVANCE_RING();
1995                 break;
1996         case RADEON_WAIT_2D|RADEON_WAIT_3D:
1997                 BEGIN_RING( 2 );
1998                 RADEON_WAIT_UNTIL_IDLE();
1999                 ADVANCE_RING();
2000                 break;
2001         default:
2002                 return DRM_ERR(EINVAL);
2003         }
2004
2005         return 0;
2006 }
2007
2008 int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2009 {
2010         DRM_DEVICE;
2011         drm_radeon_private_t *dev_priv = dev->dev_private;
2012         drm_device_dma_t *dma = dev->dma;
2013         drm_buf_t *buf = 0;
2014         int idx;
2015         drm_radeon_cmd_buffer_t cmdbuf;
2016         drm_radeon_cmd_header_t header;
2017         int orig_nbox;
2018
2019         LOCK_TEST_WITH_RETURN( dev, filp );
2020
2021         if ( !dev_priv ) {
2022                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2023                 return DRM_ERR(EINVAL);
2024         }
2025
2026         DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t *)data,
2027                              sizeof(cmdbuf) );
2028
2029         RING_SPACE_TEST_WITH_RETURN( dev_priv );
2030         VB_AGE_TEST_WITH_RETURN( dev_priv );
2031
2032
2033         if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
2034                 return DRM_ERR(EFAULT);
2035
2036         if (cmdbuf.nbox &&
2037             DRM_VERIFYAREA_READ(cmdbuf.boxes,
2038                          cmdbuf.nbox * sizeof(drm_clip_rect_t)))
2039                 return DRM_ERR(EFAULT);
2040
2041         orig_nbox = cmdbuf.nbox;
2042
2043         while ( cmdbuf.bufsz >= sizeof(header) ) {
2044
2045                 if (DRM_GET_USER_UNCHECKED( header.i, (int *)cmdbuf.buf )) {
2046                         DRM_ERROR("__get_user %p\n", cmdbuf.buf);
2047                         return DRM_ERR(EFAULT);
2048                 }
2049
2050                 cmdbuf.buf += sizeof(header);
2051                 cmdbuf.bufsz -= sizeof(header);
2052
2053                 switch (header.header.cmd_type) {
2054                 case RADEON_CMD_PACKET:
2055                         DRM_DEBUG("RADEON_CMD_PACKET\n");
2056                         if (radeon_emit_packets( dev_priv, header, &cmdbuf )) {
2057                                 DRM_ERROR("radeon_emit_packets failed\n");
2058                                 return DRM_ERR(EINVAL);
2059                         }
2060                         break;
2061
2062                 case RADEON_CMD_SCALARS:
2063                         DRM_DEBUG("RADEON_CMD_SCALARS\n");
2064                         if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
2065                                 DRM_ERROR("radeon_emit_scalars failed\n");
2066                                 return DRM_ERR(EINVAL);
2067                         }
2068                         break;
2069
2070                 case RADEON_CMD_VECTORS:
2071                         DRM_DEBUG("RADEON_CMD_VECTORS\n");
2072                         if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
2073                                 DRM_ERROR("radeon_emit_vectors failed\n");
2074                                 return DRM_ERR(EINVAL);
2075                         }
2076                         break;
2077
2078                 case RADEON_CMD_DMA_DISCARD:
2079                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2080                         idx = header.dma.buf_idx;
2081                         if ( idx < 0 || idx >= dma->buf_count ) {
2082                                 DRM_ERROR( "buffer index %d (of %d max)\n",
2083                                            idx, dma->buf_count - 1 );
2084                                 return DRM_ERR(EINVAL);
2085                         }
2086
2087                         buf = dma->buflist[idx];
2088                         if ( buf->filp != filp || buf->pending ) {
2089                                 DRM_ERROR( "bad buffer %p %p %d\n",
2090                                            buf->filp, filp, buf->pending);
2091                                 return DRM_ERR(EINVAL);
2092                         }
2093
2094                         radeon_cp_discard_buffer( dev, buf );
2095                         break;
2096
2097                 case RADEON_CMD_PACKET3:
2098                         DRM_DEBUG("RADEON_CMD_PACKET3\n");
2099                         if (radeon_emit_packet3( dev, &cmdbuf )) {
2100                                 DRM_ERROR("radeon_emit_packet3 failed\n");
2101                                 return DRM_ERR(EINVAL);
2102                         }
2103                         break;
2104
2105                 case RADEON_CMD_PACKET3_CLIP:
2106                         DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2107                         if (radeon_emit_packet3_cliprect( dev, &cmdbuf, orig_nbox )) {
2108                                 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2109                                 return DRM_ERR(EINVAL);
2110                         }
2111                         break;
2112
2113                 case RADEON_CMD_SCALARS2:
2114                         DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2115                         if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
2116                                 DRM_ERROR("radeon_emit_scalars2 failed\n");
2117                                 return DRM_ERR(EINVAL);
2118                         }
2119                         break;
2120
2121                 case RADEON_CMD_WAIT:
2122                         DRM_DEBUG("RADEON_CMD_WAIT\n");
2123                         if (radeon_emit_wait( dev, header.wait.flags )) {
2124                                 DRM_ERROR("radeon_emit_wait failed\n");
2125                                 return DRM_ERR(EINVAL);
2126                         }
2127                         break;
2128                 default:
2129                         DRM_ERROR("bad cmd_type %d at %p\n",
2130                                   header.header.cmd_type,
2131                                   cmdbuf.buf - sizeof(header));
2132                         return DRM_ERR(EINVAL);
2133                 }
2134         }
2135
2136
2137         DRM_DEBUG("DONE\n");
2138         COMMIT_RING();
2139         return 0;
2140 }
2141
2142
2143
2144 int radeon_cp_getparam( DRM_IOCTL_ARGS )
2145 {
2146         DRM_DEVICE;
2147         drm_radeon_private_t *dev_priv = dev->dev_private;
2148         drm_radeon_getparam_t param;
2149         int value;
2150
2151         if ( !dev_priv ) {
2152                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2153                 return DRM_ERR(EINVAL);
2154         }
2155
2156         DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t *)data,
2157                              sizeof(param) );
2158
2159         DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
2160
2161         switch( param.param ) {
2162         case RADEON_PARAM_GART_BUFFER_OFFSET:
2163                 value = dev_priv->gart_buffers_offset;
2164                 break;
2165         case RADEON_PARAM_LAST_FRAME:
2166                 dev_priv->stats.last_frame_reads++;
2167                 value = GET_SCRATCH( 0 );
2168                 break;
2169         case RADEON_PARAM_LAST_DISPATCH:
2170                 value = GET_SCRATCH( 1 );
2171                 break;
2172         case RADEON_PARAM_LAST_CLEAR:
2173                 dev_priv->stats.last_clear_reads++;
2174                 value = GET_SCRATCH( 2 );
2175                 break;
2176         case RADEON_PARAM_IRQ_NR:
2177                 value = dev->irq;
2178                 break;
2179         case RADEON_PARAM_GART_BASE:
2180                 value = dev_priv->gart_vm_start;
2181                 break;
2182         case RADEON_PARAM_REGISTER_HANDLE:
2183                 value = dev_priv->mmio_offset;
2184                 break;
2185         case RADEON_PARAM_STATUS_HANDLE:
2186                 value = dev_priv->ring_rptr_offset;
2187                 break;
2188 #if BITS_PER_LONG == 32
2189         /*
2190          * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2191          * pointer which can't fit into an int-sized variable.  According to
2192          * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2193          * not supporting it shouldn't be a problem.  If the same functionality
2194          * is needed on 64-bit platforms, a new ioctl() would have to be added,
2195          * so backwards-compatibility for the embedded platforms can be
2196          * maintained.  --davidm 4-Feb-2004.
2197          */
2198         case RADEON_PARAM_SAREA_HANDLE:
2199                 /* The lock is the first dword in the sarea. */
2200                 value = (long)dev->lock.hw_lock;
2201                 break;
2202 #endif
2203         case RADEON_PARAM_GART_TEX_HANDLE:
2204                 value = dev_priv->gart_textures_offset;
2205                 break;
2206         default:
2207                 return DRM_ERR(EINVAL);
2208         }
2209
2210         if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
2211                 DRM_ERROR( "copy_to_user\n" );
2212                 return DRM_ERR(EFAULT);
2213         }
2214
2215         return 0;
2216 }