drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.29 2004/08/27 20:06:41 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <asm/serial.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <asm/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70 #include <linux/hdlc.h>
  71
  72 #ifdef CONFIG_HDLC_MODULE
  73 #define CONFIG_HDLC 1
  74 #endif
  75
  76 #define GET_USER(error,value,addr) error = get_user(value,addr)
  77 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  78 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  79 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  80
  81 #include <asm/uaccess.h>
  82
  83 #include "linux/synclink.h"
  84
  85 static MGSL_PARAMS default_params = {
  86         MGSL_MODE_HDLC,                 /* unsigned long mode */
  87         0,                              /* unsigned char loopback; */
  88         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  89         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  90         0,                              /* unsigned long clock_speed; */
  91         0xff,                           /* unsigned char addr_filter; */
  92         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  93         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  94         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  95         9600,                           /* unsigned long data_rate; */
  96         8,                              /* unsigned char data_bits; */
  97         1,                              /* unsigned char stop_bits; */
  98         ASYNC_PARITY_NONE               /* unsigned char parity; */
  99 };
 100
 101 /* size in bytes of DMA data buffers */
 102 #define SCABUFSIZE      1024
 103 #define SCA_MEM_SIZE    0x40000
 104 #define SCA_BASE_SIZE   512
 105 #define SCA_REG_SIZE    16
 106 #define SCA_MAX_PORTS   4
 107 #define SCAMAXDESC      128
 108
 109 #define BUFFERLISTSIZE  4096
 110
 111 /* SCA-I style DMA buffer descriptor */
 112 typedef struct _SCADESC
 113 {
 114         u16     next;           /* lower l6 bits of next descriptor addr */
 115         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 116         u8      buf_base;       /* upper 8 bits of buffer addr */
 117         u8      pad1;
 118         u16     length;         /* length of buffer */
 119         u8      status;         /* status of buffer */
 120         u8      pad2;
 121 } SCADESC, *PSCADESC;
 122
 123 typedef struct _SCADESC_EX
 124 {
 125         /* device driver bookkeeping section */
 126         char    *virt_addr;     /* virtual address of data buffer */
 127         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 128 } SCADESC_EX, *PSCADESC_EX;
 129
 130 /* The queue of BH actions to be performed */
 131
 132 #define BH_RECEIVE  1
 133 #define BH_TRANSMIT 2
 134 #define BH_STATUS   4
 135
 136 #define IO_PIN_SHUTDOWN_LIMIT 100
 137
 138 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 139
 140 struct  _input_signal_events {
 141         int     ri_up;
 142         int     ri_down;
 143         int     dsr_up;
 144         int     dsr_down;
 145         int     dcd_up;
 146         int     dcd_down;
 147         int     cts_up;
 148         int     cts_down;
 149 };
 150
 151 /*
 152  * Device instance data structure
 153  */
 154 typedef struct _synclinkmp_info {
 155         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 156         int                     magic;
 157         int                     flags;
 158         int                     count;          /* count of opens */
 159         int                     line;
 160         unsigned short          close_delay;
 161         unsigned short          closing_wait;   /* time to wait before closing */
 162
 163         struct mgsl_icount      icount;
 164
 165         struct tty_struct       *tty;
 166         int                     timeout;
 167         int                     x_char;         /* xon/xoff character */
 168         int                     blocked_open;   /* # of blocked opens */
 169         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 170         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 171         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 172         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 173         unsigned char           *tx_buf;
 174         int                     tx_put;
 175         int                     tx_get;
 176         int                     tx_count;
 177
 178         wait_queue_head_t       open_wait;
 179         wait_queue_head_t       close_wait;
 180
 181         wait_queue_head_t       status_event_wait_q;
 182         wait_queue_head_t       event_wait_q;
 183         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 184         struct _synclinkmp_info *next_device;   /* device list link */
 185         struct timer_list       status_timer;   /* input signal status check timer */
 186
 187         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 188         struct work_struct task;                        /* task structure for scheduling bh */
 189
 190         u32 max_frame_size;                     /* as set by device config */
 191
 192         u32 pending_bh;
 193
 194         int bh_running;                         /* Protection from multiple */
 195         int isr_overflow;
 196         int bh_requested;
 197
 198         int dcd_chkcount;                       /* check counts to prevent */
 199         int cts_chkcount;                       /* too many IRQs if a signal */
 200         int dsr_chkcount;                       /* is floating */
 201         int ri_chkcount;
 202
 203         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 204         unsigned long buffer_list_phys;
 205
 206         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 207         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 208         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 209         unsigned int current_rx_buf;
 210
 211         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 212         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 213         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 214         unsigned int last_tx_buf;
 215
 216         unsigned char *tmp_rx_buf;
 217         unsigned int tmp_rx_buf_count;
 218
 219         int rx_enabled;
 220         int rx_overflow;
 221
 222         int tx_enabled;
 223         int tx_active;
 224         u32 idle_mode;
 225
 226         unsigned char ie0_value;
 227         unsigned char ie1_value;
 228         unsigned char ie2_value;
 229         unsigned char ctrlreg_value;
 230         unsigned char old_signals;
 231
 232         char device_name[25];                   /* device instance name */
 233
 234         int port_count;
 235         int adapter_num;
 236         int port_num;
 237
 238         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 239
 240         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 241
 242         unsigned int irq_level;                 /* interrupt level */
 243         unsigned long irq_flags;
 244         int irq_requested;                      /* nonzero if IRQ requested */
 245
 246         MGSL_PARAMS params;                     /* communications parameters */
 247
 248         unsigned char serial_signals;           /* current serial signal states */
 249
 250         int irq_occurred;                       /* for diagnostics use */
 251         unsigned int init_error;                /* Initialization startup error */
 252
 253         u32 last_mem_alloc;
 254         unsigned char* memory_base;             /* shared memory address (PCI only) */
 255         u32 phys_memory_base;
 256         int shared_mem_requested;
 257
 258         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 259         u32 phys_sca_base;
 260         u32 sca_offset;
 261         int sca_base_requested;
 262
 263         unsigned char* lcr_base;                /* local config registers (PCI only) */
 264         u32 phys_lcr_base;
 265         u32 lcr_offset;
 266         int lcr_mem_requested;
 267
 268         unsigned char* statctrl_base;           /* status/control register memory */
 269         u32 phys_statctrl_base;
 270         u32 statctrl_offset;
 271         int sca_statctrl_requested;
 272
 273         u32 misc_ctrl_value;
 274         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 275         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 276         BOOLEAN drop_rts_on_tx_done;
 277
 278         struct  _input_signal_events    input_signal_events;
 279
 280         /* SPPP/Cisco HDLC device parts */
 281         int netcount;
 282         int dosyncppp;
 283         spinlock_t netlock;
 284
 285 #ifdef CONFIG_HDLC
 286         struct net_device *netdev;
 287 #endif
 288
 289 } SLMP_INFO;
 290
 291 #define MGSL_MAGIC 0x5401
 292
 293 /*
 294  * define serial signal status change macros
 295  */
 296 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 297 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 298 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 299 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 300
 301 /* Common Register macros */
 302 #define LPR     0x00
 303 #define PABR0   0x02
 304 #define PABR1   0x03
 305 #define WCRL    0x04
 306 #define WCRM    0x05
 307 #define WCRH    0x06
 308 #define DPCR    0x08
 309 #define DMER    0x09
 310 #define ISR0    0x10
 311 #define ISR1    0x11
 312 #define ISR2    0x12
 313 #define IER0    0x14
 314 #define IER1    0x15
 315 #define IER2    0x16
 316 #define ITCR    0x18
 317 #define INTVR   0x1a
 318 #define IMVR    0x1c
 319
 320 /* MSCI Register macros */
 321 #define TRB     0x20
 322 #define TRBL    0x20
 323 #define TRBH    0x21
 324 #define SR0     0x22
 325 #define SR1     0x23
 326 #define SR2     0x24
 327 #define SR3     0x25
 328 #define FST     0x26
 329 #define IE0     0x28
 330 #define IE1     0x29
 331 #define IE2     0x2a
 332 #define FIE     0x2b
 333 #define CMD     0x2c
 334 #define MD0     0x2e
 335 #define MD1     0x2f
 336 #define MD2     0x30
 337 #define CTL     0x31
 338 #define SA0     0x32
 339 #define SA1     0x33
 340 #define IDL     0x34
 341 #define TMC     0x35
 342 #define RXS     0x36
 343 #define TXS     0x37
 344 #define TRC0    0x38
 345 #define TRC1    0x39
 346 #define RRC     0x3a
 347 #define CST0    0x3c
 348 #define CST1    0x3d
 349
 350 /* Timer Register Macros */
 351 #define TCNT    0x60
 352 #define TCNTL   0x60
 353 #define TCNTH   0x61
 354 #define TCONR   0x62
 355 #define TCONRL  0x62
 356 #define TCONRH  0x63
 357 #define TMCS    0x64
 358 #define TEPR    0x65
 359
 360 /* DMA Controller Register macros */
 361 #define DARL    0x80
 362 #define DARH    0x81
 363 #define DARB    0x82
 364 #define BAR     0x80
 365 #define BARL    0x80
 366 #define BARH    0x81
 367 #define BARB    0x82
 368 #define SAR     0x84
 369 #define SARL    0x84
 370 #define SARH    0x85
 371 #define SARB    0x86
 372 #define CPB     0x86
 373 #define CDA     0x88
 374 #define CDAL    0x88
 375 #define CDAH    0x89
 376 #define EDA     0x8a
 377 #define EDAL    0x8a
 378 #define EDAH    0x8b
 379 #define BFL     0x8c
 380 #define BFLL    0x8c
 381 #define BFLH    0x8d
 382 #define BCR     0x8e
 383 #define BCRL    0x8e
 384 #define BCRH    0x8f
 385 #define DSR     0x90
 386 #define DMR     0x91
 387 #define FCT     0x93
 388 #define DIR     0x94
 389 #define DCMD    0x95
 390
 391 /* combine with timer or DMA register address */
 392 #define TIMER0  0x00
 393 #define TIMER1  0x08
 394 #define TIMER2  0x10
 395 #define TIMER3  0x18
 396 #define RXDMA   0x00
 397 #define TXDMA   0x20
 398
 399 /* SCA Command Codes */
 400 #define NOOP            0x00
 401 #define TXRESET         0x01
 402 #define TXENABLE        0x02
 403 #define TXDISABLE       0x03
 404 #define TXCRCINIT       0x04
 405 #define TXCRCEXCL       0x05
 406 #define TXEOM           0x06
 407 #define TXABORT         0x07
 408 #define MPON            0x08
 409 #define TXBUFCLR        0x09
 410 #define RXRESET         0x11
 411 #define RXENABLE        0x12
 412 #define RXDISABLE       0x13
 413 #define RXCRCINIT       0x14
 414 #define RXREJECT        0x15
 415 #define SEARCHMP        0x16
 416 #define RXCRCEXCL       0x17
 417 #define RXCRCCALC       0x18
 418 #define CHRESET         0x21
 419 #define HUNT            0x31
 420
 421 /* DMA command codes */
 422 #define SWABORT         0x01
 423 #define FEICLEAR        0x02
 424
 425 /* IE0 */
 426 #define TXINTE          BIT7
 427 #define RXINTE          BIT6
 428 #define TXRDYE          BIT1
 429 #define RXRDYE          BIT0
 430
 431 /* IE1 & SR1 */
 432 #define UDRN    BIT7
 433 #define IDLE    BIT6
 434 #define SYNCD   BIT4
 435 #define FLGD    BIT4
 436 #define CCTS    BIT3
 437 #define CDCD    BIT2
 438 #define BRKD    BIT1
 439 #define ABTD    BIT1
 440 #define GAPD    BIT1
 441 #define BRKE    BIT0
 442 #define IDLD    BIT0
 443
 444 /* IE2 & SR2 */
 445 #define EOM     BIT7
 446 #define PMP     BIT6
 447 #define SHRT    BIT6
 448 #define PE      BIT5
 449 #define ABT     BIT5
 450 #define FRME    BIT4
 451 #define RBIT    BIT4
 452 #define OVRN    BIT3
 453 #define CRCE    BIT2
 454
 455
 456 /*
 457  * Global linked list of SyncLink devices
 458  */
 459 static SLMP_INFO *synclinkmp_device_list = NULL;
 460 static int synclinkmp_adapter_count = -1;
 461 static int synclinkmp_device_count = 0;
 462
 463 /*
 464  * Set this param to non-zero to load eax with the
 465  * .text section address and breakpoint on module load.
 466  * This is useful for use with gdb and add-symbol-file command.
 467  */
 468 static int break_on_load=0;
 469
 470 /*
 471  * Driver major number, defaults to zero to get auto
 472  * assigned major number. May be forced as module parameter.
 473  */
 474 static int ttymajor=0;
 475
 476 /*
 477  * Array of user specified options for ISA adapters.
 478  */
 479 static int debug_level = 0;
 480 static int maxframe[MAX_DEVICES] = {0,};
 481 static int dosyncppp[MAX_DEVICES] = {0,};
 482
 483 MODULE_PARM(break_on_load,"i");
 484 MODULE_PARM(ttymajor,"i");
 485 MODULE_PARM(debug_level,"i");
 486 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 487 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 488
 489 static char *driver_name = "SyncLink MultiPort driver";
 490 static char *driver_version = "$Revision: 4.29 $";
 491
 492 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 493 static void synclinkmp_remove_one(struct pci_dev *dev);
 494
 495 static struct pci_device_id synclinkmp_pci_tbl[] = {
 496         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 497         { 0, }, /* terminate list */
 498 };
 499 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 500
 501 MODULE_LICENSE("GPL");
 502
 503 static struct pci_driver synclinkmp_pci_driver = {
 504         .name           = "synclinkmp",
 505         .id_table       = synclinkmp_pci_tbl,
 506         .probe          = synclinkmp_init_one,
 507         .remove         = __devexit_p(synclinkmp_remove_one),
 508 };
 509
 510
 511 static struct tty_driver *serial_driver;
 512
 513 /* number of characters left in xmit buffer before we ask for more */
 514 #define WAKEUP_CHARS 256
 515
 516
 517 /* tty callbacks */
 518
 519 static int  open(struct tty_struct *tty, struct file * filp);
 520 static void close(struct tty_struct *tty, struct file * filp);
 521 static void hangup(struct tty_struct *tty);
 522 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 523
 524 static int  write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
 525 static void put_char(struct tty_struct *tty, unsigned char ch);
 526 static void send_xchar(struct tty_struct *tty, char ch);
 527 static void wait_until_sent(struct tty_struct *tty, int timeout);
 528 static int  write_room(struct tty_struct *tty);
 529 static void flush_chars(struct tty_struct *tty);
 530 static void flush_buffer(struct tty_struct *tty);
 531 static void tx_hold(struct tty_struct *tty);
 532 static void tx_release(struct tty_struct *tty);
 533
 534 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 535 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 536 static int  chars_in_buffer(struct tty_struct *tty);
 537 static void throttle(struct tty_struct * tty);
 538 static void unthrottle(struct tty_struct * tty);
 539 static void set_break(struct tty_struct *tty, int break_state);
 540
 541 #ifdef CONFIG_HDLC
 542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 543 static void hdlcdev_tx_done(SLMP_INFO *info);
 544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 545 static int  hdlcdev_init(SLMP_INFO *info);
 546 static void hdlcdev_exit(SLMP_INFO *info);
 547 #endif
 548
 549 /* ioctl handlers */
 550
 551 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 552 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 554 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 555 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 556 static int  tx_enable(SLMP_INFO *info, int enable);
 557 static int  tx_abort(SLMP_INFO *info);
 558 static int  rx_enable(SLMP_INFO *info, int enable);
 559 static int  map_status(int signals);
 560 static int  modem_input_wait(SLMP_INFO *info,int arg);
 561 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 562 static int  tiocmget(struct tty_struct *tty, struct file *file);
 563 static int  tiocmset(struct tty_struct *tty, struct file *file,
 564                      unsigned int set, unsigned int clear);
 565 static void set_break(struct tty_struct *tty, int break_state);
 566
 567 static void add_device(SLMP_INFO *info);
 568 static void device_init(int adapter_num, struct pci_dev *pdev);
 569 static int  claim_resources(SLMP_INFO *info);
 570 static void release_resources(SLMP_INFO *info);
 571
 572 static int  startup(SLMP_INFO *info);
 573 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 574 static void shutdown(SLMP_INFO *info);
 575 static void program_hw(SLMP_INFO *info);
 576 static void change_params(SLMP_INFO *info);
 577
 578 static int  init_adapter(SLMP_INFO *info);
 579 static int  register_test(SLMP_INFO *info);
 580 static int  irq_test(SLMP_INFO *info);
 581 static int  loopback_test(SLMP_INFO *info);
 582 static int  adapter_test(SLMP_INFO *info);
 583 static int  memory_test(SLMP_INFO *info);
 584
 585 static void reset_adapter(SLMP_INFO *info);
 586 static void reset_port(SLMP_INFO *info);
 587 static void async_mode(SLMP_INFO *info);
 588 static void hdlc_mode(SLMP_INFO *info);
 589
 590 static void rx_stop(SLMP_INFO *info);
 591 static void rx_start(SLMP_INFO *info);
 592 static void rx_reset_buffers(SLMP_INFO *info);
 593 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 594 static int  rx_get_frame(SLMP_INFO *info);
 595
 596 static void tx_start(SLMP_INFO *info);
 597 static void tx_stop(SLMP_INFO *info);
 598 static void tx_load_fifo(SLMP_INFO *info);
 599 static void tx_set_idle(SLMP_INFO *info);
 600 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 601
 602 static void get_signals(SLMP_INFO *info);
 603 static void set_signals(SLMP_INFO *info);
 604 static void enable_loopback(SLMP_INFO *info, int enable);
 605 static void set_rate(SLMP_INFO *info, u32 data_rate);
 606
 607 static int  bh_action(SLMP_INFO *info);
 608 static void bh_handler(void* Context);
 609 static void bh_receive(SLMP_INFO *info);
 610 static void bh_transmit(SLMP_INFO *info);
 611 static void bh_status(SLMP_INFO *info);
 612 static void isr_timer(SLMP_INFO *info);
 613 static void isr_rxint(SLMP_INFO *info);
 614 static void isr_rxrdy(SLMP_INFO *info);
 615 static void isr_txint(SLMP_INFO *info);
 616 static void isr_txrdy(SLMP_INFO *info);
 617 static void isr_rxdmaok(SLMP_INFO *info);
 618 static void isr_rxdmaerror(SLMP_INFO *info);
 619 static void isr_txdmaok(SLMP_INFO *info);
 620 static void isr_txdmaerror(SLMP_INFO *info);
 621 static void isr_io_pin(SLMP_INFO *info, u16 status);
 622
 623 static int  alloc_dma_bufs(SLMP_INFO *info);
 624 static void free_dma_bufs(SLMP_INFO *info);
 625 static int  alloc_buf_list(SLMP_INFO *info);
 626 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 627 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 628 static void free_tmp_rx_buf(SLMP_INFO *info);
 629
 630 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 631 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 632 static void tx_timeout(unsigned long context);
 633 static void status_timeout(unsigned long context);
 634
 635 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 636 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 637 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 638 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 639 static unsigned char read_status_reg(SLMP_INFO * info);
 640 static void write_control_reg(SLMP_INFO * info);
 641
 642
 643 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 644 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 645 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 646
 647 static u32 misc_ctrl_value = 0x007e4040;
 648 static u32 lcr1_brdr_value = 0x00800029;
 649
 650 static u32 read_ahead_count = 8;
 651
 652 /* DPCR, DMA Priority Control
 653  *
 654  * 07..05  Not used, must be 0
 655  * 04      BRC, bus release condition: 0=all transfers complete
 656  *              1=release after 1 xfer on all channels
 657  * 03      CCC, channel change condition: 0=every cycle
 658  *              1=after each channel completes all xfers
 659  * 02..00  PR<2..0>, priority 100=round robin
 660  *
 661  * 00000100 = 0x00
 662  */
 663 static unsigned char dma_priority = 0x04;
 664
 665 // Number of bytes that can be written to shared RAM
 666 // in a single write operation
 667 static u32 sca_pci_load_interval = 64;
 668
 669 /*
 670  * 1st function defined in .text section. Calling this function in
 671  * init_module() followed by a breakpoint allows a remote debugger
 672  * (gdb) to get the .text address for the add-symbol-file command.
 673  * This allows remote debugging of dynamically loadable modules.
 674  */
 675 static void* synclinkmp_get_text_ptr(void);
 676 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 677
 678 static inline int sanity_check(SLMP_INFO *info,
 679                                char *name, const char *routine)
 680 {
 681 #ifdef SANITY_CHECK
 682         static const char *badmagic =
 683                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 684         static const char *badinfo =
 685                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 686
 687         if (!info) {
 688                 printk(badinfo, name, routine);
 689                 return 1;
 690         }
 691         if (info->magic != MGSL_MAGIC) {
 692                 printk(badmagic, name, routine);
 693                 return 1;
 694         }
 695 #else
 696         if (!info)
 697                 return 1;
 698 #endif
 699         return 0;
 700 }
 701
 702 /**
 703  * line discipline callback wrappers
 704  *
 705  * The wrappers maintain line discipline references
 706  * while calling into the line discipline.
 707  *
 708  * ldisc_receive_buf  - pass receive data to line discipline
 709  */
 710
 711 static void ldisc_receive_buf(struct tty_struct *tty,
 712                               const __u8 *data, char *flags, int count)
 713 {
 714         struct tty_ldisc *ld;
 715         if (!tty)
 716                 return;
 717         ld = tty_ldisc_ref(tty);
 718         if (ld) {
 719                 if (ld->receive_buf)
 720                         ld->receive_buf(tty, data, flags, count);
 721                 tty_ldisc_deref(ld);
 722         }
 723 }
 724
 725 /* tty callbacks */
 726
 727 /* Called when a port is opened.  Init and enable port.
 728  */
 729 static int open(struct tty_struct *tty, struct file *filp)
 730 {
 731         SLMP_INFO *info;
 732         int retval, line;
 733         unsigned long flags;
 734
 735         line = tty->index;
 736         if ((line < 0) || (line >= synclinkmp_device_count)) {
 737                 printk("%s(%d): open with invalid line #%d.\n",
 738                         __FILE__,__LINE__,line);
 739                 return -ENODEV;
 740         }
 741
 742         info = synclinkmp_device_list;
 743         while(info && info->line != line)
 744                 info = info->next_device;
 745         if (sanity_check(info, tty->name, "open"))
 746                 return -ENODEV;
 747         if ( info->init_error ) {
 748                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 749                         __FILE__,__LINE__,info->device_name,info->init_error);
 750                 return -ENODEV;
 751         }
 752
 753         tty->driver_data = info;
 754         info->tty = tty;
 755
 756         if (debug_level >= DEBUG_LEVEL_INFO)
 757                 printk("%s(%d):%s open(), old ref count = %d\n",
 758                          __FILE__,__LINE__,tty->driver->name, info->count);
 759
 760         /* If port is closing, signal caller to try again */
 761         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 762                 if (info->flags & ASYNC_CLOSING)
 763                         interruptible_sleep_on(&info->close_wait);
 764                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 765                         -EAGAIN : -ERESTARTSYS);
 766                 goto cleanup;
 767         }
 768
 769         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 770
 771         spin_lock_irqsave(&info->netlock, flags);
 772         if (info->netcount) {
 773                 retval = -EBUSY;
 774                 spin_unlock_irqrestore(&info->netlock, flags);
 775                 goto cleanup;
 776         }
 777         info->count++;
 778         spin_unlock_irqrestore(&info->netlock, flags);
 779
 780         if (info->count == 1) {
 781                 /* 1st open on this device, init hardware */
 782                 retval = startup(info);
 783                 if (retval < 0)
 784                         goto cleanup;
 785         }
 786
 787         retval = block_til_ready(tty, filp, info);
 788         if (retval) {
 789                 if (debug_level >= DEBUG_LEVEL_INFO)
 790                         printk("%s(%d):%s block_til_ready() returned %d\n",
 791                                  __FILE__,__LINE__, info->device_name, retval);
 792                 goto cleanup;
 793         }
 794
 795         if (debug_level >= DEBUG_LEVEL_INFO)
 796                 printk("%s(%d):%s open() success\n",
 797                          __FILE__,__LINE__, info->device_name);
 798         retval = 0;
 799
 800 cleanup:
 801         if (retval) {
 802                 if (tty->count == 1)
 803                         info->tty = NULL; /* tty layer will release tty struct */
 804                 if(info->count)
 805                         info->count--;
 806         }
 807
 808         return retval;
 809 }
 810
 811 /* Called when port is closed. Wait for remaining data to be
 812  * sent. Disable port and free resources.
 813  */
 814 static void close(struct tty_struct *tty, struct file *filp)
 815 {
 816         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 817
 818         if (sanity_check(info, tty->name, "close"))
 819                 return;
 820
 821         if (debug_level >= DEBUG_LEVEL_INFO)
 822                 printk("%s(%d):%s close() entry, count=%d\n",
 823                          __FILE__,__LINE__, info->device_name, info->count);
 824
 825         if (!info->count)
 826                 return;
 827
 828         if (tty_hung_up_p(filp))
 829                 goto cleanup;
 830
 831         if ((tty->count == 1) && (info->count != 1)) {
 832                 /*
 833                  * tty->count is 1 and the tty structure will be freed.
 834                  * info->count should be one in this case.
 835                  * if it's not, correct it so that the port is shutdown.
 836                  */
 837                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 838                        "info->count is %d\n",
 839                          __FILE__,__LINE__, info->device_name, info->count);
 840                 info->count = 1;
 841         }
 842
 843         info->count--;
 844
 845         /* if at least one open remaining, leave hardware active */
 846         if (info->count)
 847                 goto cleanup;
 848
 849         info->flags |= ASYNC_CLOSING;
 850
 851         /* set tty->closing to notify line discipline to
 852          * only process XON/XOFF characters. Only the N_TTY
 853          * discipline appears to use this (ppp does not).
 854          */
 855         tty->closing = 1;
 856
 857         /* wait for transmit data to clear all layers */
 858
 859         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 860                 if (debug_level >= DEBUG_LEVEL_INFO)
 861                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 862                                  __FILE__,__LINE__, info->device_name );
 863                 tty_wait_until_sent(tty, info->closing_wait);
 864         }
 865
 866         if (info->flags & ASYNC_INITIALIZED)
 867                 wait_until_sent(tty, info->timeout);
 868
 869         if (tty->driver->flush_buffer)
 870                 tty->driver->flush_buffer(tty);
 871
 872         tty_ldisc_flush(tty);
 873
 874         shutdown(info);
 875
 876         tty->closing = 0;
 877         info->tty = NULL;
 878
 879         if (info->blocked_open) {
 880                 if (info->close_delay) {
 881                         set_current_state(TASK_INTERRUPTIBLE);
 882                         schedule_timeout(info->close_delay);
 883                 }
 884                 wake_up_interruptible(&info->open_wait);
 885         }
 886
 887         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 888
 889         wake_up_interruptible(&info->close_wait);
 890
 891 cleanup:
 892         if (debug_level >= DEBUG_LEVEL_INFO)
 893                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 894                         tty->driver->name, info->count);
 895 }
 896
 897 /* Called by tty_hangup() when a hangup is signaled.
 898  * This is the same as closing all open descriptors for the port.
 899  */
 900 static void hangup(struct tty_struct *tty)
 901 {
 902         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 903
 904         if (debug_level >= DEBUG_LEVEL_INFO)
 905                 printk("%s(%d):%s hangup()\n",
 906                          __FILE__,__LINE__, info->device_name );
 907
 908         if (sanity_check(info, tty->name, "hangup"))
 909                 return;
 910
 911         flush_buffer(tty);
 912         shutdown(info);
 913
 914         info->count = 0;
 915         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 916         info->tty = NULL;
 917
 918         wake_up_interruptible(&info->open_wait);
 919 }
 920
 921 /* Set new termios settings
 922  */
 923 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 924 {
 925         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 926         unsigned long flags;
 927
 928         if (debug_level >= DEBUG_LEVEL_INFO)
 929                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 930                         tty->driver->name );
 931
 932         /* just return if nothing has changed */
 933         if ((tty->termios->c_cflag == old_termios->c_cflag)
 934             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 935                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 936           return;
 937
 938         change_params(info);
 939
 940         /* Handle transition to B0 status */
 941         if (old_termios->c_cflag & CBAUD &&
 942             !(tty->termios->c_cflag & CBAUD)) {
 943                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 944                 spin_lock_irqsave(&info->lock,flags);
 945                 set_signals(info);
 946                 spin_unlock_irqrestore(&info->lock,flags);
 947         }
 948
 949         /* Handle transition away from B0 status */
 950         if (!(old_termios->c_cflag & CBAUD) &&
 951             tty->termios->c_cflag & CBAUD) {
 952                 info->serial_signals |= SerialSignal_DTR;
 953                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 954                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 955                         info->serial_signals |= SerialSignal_RTS;
 956                 }
 957                 spin_lock_irqsave(&info->lock,flags);
 958                 set_signals(info);
 959                 spin_unlock_irqrestore(&info->lock,flags);
 960         }
 961
 962         /* Handle turning off CRTSCTS */
 963         if (old_termios->c_cflag & CRTSCTS &&
 964             !(tty->termios->c_cflag & CRTSCTS)) {
 965                 tty->hw_stopped = 0;
 966                 tx_release(tty);
 967         }
 968 }
 969
 970 /* Send a block of data
 971  *
 972  * Arguments:
 973  *
 974  *      tty             pointer to tty information structure
 975  *      from_user       flag: 1 = from user process
 976  *      buf             pointer to buffer containing send data
 977  *      count           size of send data in bytes
 978  *
 979  * Return Value:        number of characters written
 980  */
 981 static int write(struct tty_struct *tty, int from_user,
 982                  const unsigned char *buf, int count)
 983 {
 984         int     c, ret = 0, err;
 985         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 986         unsigned long flags;
 987
 988         if (debug_level >= DEBUG_LEVEL_INFO)
 989                 printk("%s(%d):%s write() count=%d\n",
 990                        __FILE__,__LINE__,info->device_name,count);
 991
 992         if (sanity_check(info, tty->name, "write"))
 993                 goto cleanup;
 994
 995         if (!tty || !info->tx_buf)
 996                 goto cleanup;
 997
 998         if (info->params.mode == MGSL_MODE_HDLC) {
 999                 if (count > info->max_frame_size) {
1000                         ret = -EIO;
1001                         goto cleanup;
1002                 }
1003                 if (info->tx_active)
1004                         goto cleanup;
1005                 if (info->tx_count) {
1006                         /* send accumulated data from send_char() calls */
1007                         /* as frame and wait before accepting more data. */
1008                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1009                         goto start;
1010                 }
1011                 if (!from_user) {
1012                         ret = info->tx_count = count;
1013                         tx_load_dma_buffer(info, buf, count);
1014                         goto start;
1015                 }
1016         }
1017
1018         for (;;) {
1019                 c = min_t(int, count,
1020                         min(info->max_frame_size - info->tx_count - 1,
1021                             info->max_frame_size - info->tx_put));
1022                 if (c <= 0)
1023                         break;
1024
1025                 if (from_user) {
1026                         COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1027                         if (err) {
1028                                 if (!ret)
1029                                         ret = -EFAULT;
1030                                 break;
1031                         }
1032                 } else
1033                         memcpy(info->tx_buf + info->tx_put, buf, c);
1034
1035                 spin_lock_irqsave(&info->lock,flags);
1036                 info->tx_put += c;
1037                 if (info->tx_put >= info->max_frame_size)
1038                         info->tx_put -= info->max_frame_size;
1039                 info->tx_count += c;
1040                 spin_unlock_irqrestore(&info->lock,flags);
1041
1042                 buf += c;
1043                 count -= c;
1044                 ret += c;
1045         }
1046
1047         if (info->params.mode == MGSL_MODE_HDLC) {
1048                 if (count) {
1049                         ret = info->tx_count = 0;
1050                         goto cleanup;
1051                 }
1052                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1053         }
1054 start:
1055         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1056                 spin_lock_irqsave(&info->lock,flags);
1057                 if (!info->tx_active)
1058                         tx_start(info);
1059                 spin_unlock_irqrestore(&info->lock,flags);
1060         }
1061
1062 cleanup:
1063         if (debug_level >= DEBUG_LEVEL_INFO)
1064                 printk( "%s(%d):%s write() returning=%d\n",
1065                         __FILE__,__LINE__,info->device_name,ret);
1066         return ret;
1067 }
1068
1069 /* Add a character to the transmit buffer.
1070  */
1071 static void put_char(struct tty_struct *tty, unsigned char ch)
1072 {
1073         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1074         unsigned long flags;
1075
1076         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1077                 printk( "%s(%d):%s put_char(%d)\n",
1078                         __FILE__,__LINE__,info->device_name,ch);
1079         }
1080
1081         if (sanity_check(info, tty->name, "put_char"))
1082                 return;
1083
1084         if (!tty || !info->tx_buf)
1085                 return;
1086
1087         spin_lock_irqsave(&info->lock,flags);
1088
1089         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1090              !info->tx_active ) {
1091
1092                 if (info->tx_count < info->max_frame_size - 1) {
1093                         info->tx_buf[info->tx_put++] = ch;
1094                         if (info->tx_put >= info->max_frame_size)
1095                                 info->tx_put -= info->max_frame_size;
1096                         info->tx_count++;
1097                 }
1098         }
1099
1100         spin_unlock_irqrestore(&info->lock,flags);
1101 }
1102
1103 /* Send a high-priority XON/XOFF character
1104  */
1105 static void send_xchar(struct tty_struct *tty, char ch)
1106 {
1107         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1108         unsigned long flags;
1109
1110         if (debug_level >= DEBUG_LEVEL_INFO)
1111                 printk("%s(%d):%s send_xchar(%d)\n",
1112                          __FILE__,__LINE__, info->device_name, ch );
1113
1114         if (sanity_check(info, tty->name, "send_xchar"))
1115                 return;
1116
1117         info->x_char = ch;
1118         if (ch) {
1119                 /* Make sure transmit interrupts are on */
1120                 spin_lock_irqsave(&info->lock,flags);
1121                 if (!info->tx_enabled)
1122                         tx_start(info);
1123                 spin_unlock_irqrestore(&info->lock,flags);
1124         }
1125 }
1126
1127 /* Wait until the transmitter is empty.
1128  */
1129 static void wait_until_sent(struct tty_struct *tty, int timeout)
1130 {
1131         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1132         unsigned long orig_jiffies, char_time;
1133
1134         if (!info )
1135                 return;
1136
1137         if (debug_level >= DEBUG_LEVEL_INFO)
1138                 printk("%s(%d):%s wait_until_sent() entry\n",
1139                          __FILE__,__LINE__, info->device_name );
1140
1141         if (sanity_check(info, tty->name, "wait_until_sent"))
1142                 return;
1143
1144         if (!(info->flags & ASYNC_INITIALIZED))
1145                 goto exit;
1146
1147         orig_jiffies = jiffies;
1148
1149         /* Set check interval to 1/5 of estimated time to
1150          * send a character, and make it at least 1. The check
1151          * interval should also be less than the timeout.
1152          * Note: use tight timings here to satisfy the NIST-PCTS.
1153          */
1154
1155         if ( info->params.data_rate ) {
1156                 char_time = info->timeout/(32 * 5);
1157                 if (!char_time)
1158                         char_time++;
1159         } else
1160                 char_time = 1;
1161
1162         if (timeout)
1163                 char_time = min_t(unsigned long, char_time, timeout);
1164
1165         if ( info->params.mode == MGSL_MODE_HDLC ) {
1166                 while (info->tx_active) {
1167                         set_current_state(TASK_INTERRUPTIBLE);
1168                         schedule_timeout(char_time);
1169                         if (signal_pending(current))
1170                                 break;
1171                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1172                                 break;
1173                 }
1174         } else {
1175                 //TODO: determine if there is something similar to USC16C32
1176                 //      TXSTATUS_ALL_SENT status
1177                 while ( info->tx_active && info->tx_enabled) {
1178                         set_current_state(TASK_INTERRUPTIBLE);
1179                         schedule_timeout(char_time);
1180                         if (signal_pending(current))
1181                                 break;
1182                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1183                                 break;
1184                 }
1185         }
1186
1187 exit:
1188         if (debug_level >= DEBUG_LEVEL_INFO)
1189                 printk("%s(%d):%s wait_until_sent() exit\n",
1190                          __FILE__,__LINE__, info->device_name );
1191 }
1192
1193 /* Return the count of free bytes in transmit buffer
1194  */
1195 static int write_room(struct tty_struct *tty)
1196 {
1197         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1198         int ret;
1199
1200         if (sanity_check(info, tty->name, "write_room"))
1201                 return 0;
1202
1203         if (info->params.mode == MGSL_MODE_HDLC) {
1204                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1205         } else {
1206                 ret = info->max_frame_size - info->tx_count - 1;
1207                 if (ret < 0)
1208                         ret = 0;
1209         }
1210
1211         if (debug_level >= DEBUG_LEVEL_INFO)
1212                 printk("%s(%d):%s write_room()=%d\n",
1213                        __FILE__, __LINE__, info->device_name, ret);
1214
1215         return ret;
1216 }
1217
1218 /* enable transmitter and send remaining buffered characters
1219  */
1220 static void flush_chars(struct tty_struct *tty)
1221 {
1222         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1223         unsigned long flags;
1224
1225         if ( debug_level >= DEBUG_LEVEL_INFO )
1226                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1227                         __FILE__,__LINE__,info->device_name,info->tx_count);
1228
1229         if (sanity_check(info, tty->name, "flush_chars"))
1230                 return;
1231
1232         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1233             !info->tx_buf)
1234                 return;
1235
1236         if ( debug_level >= DEBUG_LEVEL_INFO )
1237                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1238                         __FILE__,__LINE__,info->device_name );
1239
1240         spin_lock_irqsave(&info->lock,flags);
1241
1242         if (!info->tx_active) {
1243                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1244                         info->tx_count ) {
1245                         /* operating in synchronous (frame oriented) mode */
1246                         /* copy data from circular tx_buf to */
1247                         /* transmit DMA buffer. */
1248                         tx_load_dma_buffer(info,
1249                                  info->tx_buf,info->tx_count);
1250                 }
1251                 tx_start(info);
1252         }
1253
1254         spin_unlock_irqrestore(&info->lock,flags);
1255 }
1256
1257 /* Discard all data in the send buffer
1258  */
1259 static void flush_buffer(struct tty_struct *tty)
1260 {
1261         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1262         unsigned long flags;
1263
1264         if (debug_level >= DEBUG_LEVEL_INFO)
1265                 printk("%s(%d):%s flush_buffer() entry\n",
1266                          __FILE__,__LINE__, info->device_name );
1267
1268         if (sanity_check(info, tty->name, "flush_buffer"))
1269                 return;
1270
1271         spin_lock_irqsave(&info->lock,flags);
1272         info->tx_count = info->tx_put = info->tx_get = 0;
1273         del_timer(&info->tx_timer);
1274         spin_unlock_irqrestore(&info->lock,flags);
1275
1276         wake_up_interruptible(&tty->write_wait);
1277         tty_wakeup(tty);
1278 }
1279
1280 /* throttle (stop) transmitter
1281  */
1282 static void tx_hold(struct tty_struct *tty)
1283 {
1284         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1285         unsigned long flags;
1286
1287         if (sanity_check(info, tty->name, "tx_hold"))
1288                 return;
1289
1290         if ( debug_level >= DEBUG_LEVEL_INFO )
1291                 printk("%s(%d):%s tx_hold()\n",
1292                         __FILE__,__LINE__,info->device_name);
1293
1294         spin_lock_irqsave(&info->lock,flags);
1295         if (info->tx_enabled)
1296                 tx_stop(info);
1297         spin_unlock_irqrestore(&info->lock,flags);
1298 }
1299
1300 /* release (start) transmitter
1301  */
1302 static void tx_release(struct tty_struct *tty)
1303 {
1304         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1305         unsigned long flags;
1306
1307         if (sanity_check(info, tty->name, "tx_release"))
1308                 return;
1309
1310         if ( debug_level >= DEBUG_LEVEL_INFO )
1311                 printk("%s(%d):%s tx_release()\n",
1312                         __FILE__,__LINE__,info->device_name);
1313
1314         spin_lock_irqsave(&info->lock,flags);
1315         if (!info->tx_enabled)
1316                 tx_start(info);
1317         spin_unlock_irqrestore(&info->lock,flags);
1318 }
1319
1320 /* Service an IOCTL request
1321  *
1322  * Arguments:
1323  *
1324  *      tty     pointer to tty instance data
1325  *      file    pointer to associated file object for device
1326  *      cmd     IOCTL command code
1327  *      arg     command argument/context
1328  *
1329  * Return Value:        0 if success, otherwise error code
1330  */
1331 static int ioctl(struct tty_struct *tty, struct file *file,
1332                  unsigned int cmd, unsigned long arg)
1333 {
1334         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1335         int error;
1336         struct mgsl_icount cnow;        /* kernel counter temps */
1337         struct serial_icounter_struct __user *p_cuser;  /* user space */
1338         unsigned long flags;
1339         void __user *argp = (void __user *)arg;
1340
1341         if (debug_level >= DEBUG_LEVEL_INFO)
1342                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1343                         info->device_name, cmd );
1344
1345         if (sanity_check(info, tty->name, "ioctl"))
1346                 return -ENODEV;
1347
1348         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1349             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1350                 if (tty->flags & (1 << TTY_IO_ERROR))
1351                     return -EIO;
1352         }
1353
1354         switch (cmd) {
1355         case MGSL_IOCGPARAMS:
1356                 return get_params(info, argp);
1357         case MGSL_IOCSPARAMS:
1358                 return set_params(info, argp);
1359         case MGSL_IOCGTXIDLE:
1360                 return get_txidle(info, argp);
1361         case MGSL_IOCSTXIDLE:
1362                 return set_txidle(info, (int)arg);
1363         case MGSL_IOCTXENABLE:
1364                 return tx_enable(info, (int)arg);
1365         case MGSL_IOCRXENABLE:
1366                 return rx_enable(info, (int)arg);
1367         case MGSL_IOCTXABORT:
1368                 return tx_abort(info);
1369         case MGSL_IOCGSTATS:
1370                 return get_stats(info, argp);
1371         case MGSL_IOCWAITEVENT:
1372                 return wait_mgsl_event(info, argp);
1373         case MGSL_IOCLOOPTXDONE:
1374                 return 0; // TODO: Not supported, need to document
1375                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1376                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1377                  */
1378         case TIOCMIWAIT:
1379                 return modem_input_wait(info,(int)arg);
1380
1381                 /*
1382                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1383                  * Return: write counters to the user passed counter struct
1384                  * NB: both 1->0 and 0->1 transitions are counted except for
1385                  *     RI where only 0->1 is counted.
1386                  */
1387         case TIOCGICOUNT:
1388                 spin_lock_irqsave(&info->lock,flags);
1389                 cnow = info->icount;
1390                 spin_unlock_irqrestore(&info->lock,flags);
1391                 p_cuser = argp;
1392                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1397                 if (error) return error;
1398                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1399                 if (error) return error;
1400                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1401                 if (error) return error;
1402                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1403                 if (error) return error;
1404                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1405                 if (error) return error;
1406                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1407                 if (error) return error;
1408                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1409                 if (error) return error;
1410                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1411                 if (error) return error;
1412                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1413                 if (error) return error;
1414                 return 0;
1415         default:
1416                 return -ENOIOCTLCMD;
1417         }
1418         return 0;
1419 }
1420
1421 /*
1422  * /proc fs routines....
1423  */
1424
1425 static inline int line_info(char *buf, SLMP_INFO *info)
1426 {
1427         char    stat_buf[30];
1428         int     ret;
1429         unsigned long flags;
1430
1431         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1432                        "\tIRQ=%d MaxFrameSize=%u\n",
1433                 info->device_name,
1434                 info->phys_sca_base,
1435                 info->phys_memory_base,
1436                 info->phys_statctrl_base,
1437                 info->phys_lcr_base,
1438                 info->irq_level,
1439                 info->max_frame_size );
1440
1441         /* output current serial signal states */
1442         spin_lock_irqsave(&info->lock,flags);
1443         get_signals(info);
1444         spin_unlock_irqrestore(&info->lock,flags);
1445
1446         stat_buf[0] = 0;
1447         stat_buf[1] = 0;
1448         if (info->serial_signals & SerialSignal_RTS)
1449                 strcat(stat_buf, "|RTS");
1450         if (info->serial_signals & SerialSignal_CTS)
1451                 strcat(stat_buf, "|CTS");
1452         if (info->serial_signals & SerialSignal_DTR)
1453                 strcat(stat_buf, "|DTR");
1454         if (info->serial_signals & SerialSignal_DSR)
1455                 strcat(stat_buf, "|DSR");
1456         if (info->serial_signals & SerialSignal_DCD)
1457                 strcat(stat_buf, "|CD");
1458         if (info->serial_signals & SerialSignal_RI)
1459                 strcat(stat_buf, "|RI");
1460
1461         if (info->params.mode == MGSL_MODE_HDLC) {
1462                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1463                               info->icount.txok, info->icount.rxok);
1464                 if (info->icount.txunder)
1465                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1466                 if (info->icount.txabort)
1467                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1468                 if (info->icount.rxshort)
1469                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1470                 if (info->icount.rxlong)
1471                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1472                 if (info->icount.rxover)
1473                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1474                 if (info->icount.rxcrc)
1475                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1476         } else {
1477                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1478                               info->icount.tx, info->icount.rx);
1479                 if (info->icount.frame)
1480                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1481                 if (info->icount.parity)
1482                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1483                 if (info->icount.brk)
1484                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1485                 if (info->icount.overrun)
1486                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1487         }
1488
1489         /* Append serial signal status to end */
1490         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1491
1492         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1493          info->tx_active,info->bh_requested,info->bh_running,
1494          info->pending_bh);
1495
1496         return ret;
1497 }
1498
1499 /* Called to print information about devices
1500  */
1501 int read_proc(char *page, char **start, off_t off, int count,
1502               int *eof, void *data)
1503 {
1504         int len = 0, l;
1505         off_t   begin = 0;
1506         SLMP_INFO *info;
1507
1508         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1509
1510         info = synclinkmp_device_list;
1511         while( info ) {
1512                 l = line_info(page + len, info);
1513                 len += l;
1514                 if (len+begin > off+count)
1515                         goto done;
1516                 if (len+begin < off) {
1517                         begin += len;
1518                         len = 0;
1519                 }
1520                 info = info->next_device;
1521         }
1522
1523         *eof = 1;
1524 done:
1525         if (off >= len+begin)
1526                 return 0;
1527         *start = page + (off-begin);
1528         return ((count < begin+len-off) ? count : begin+len-off);
1529 }
1530
1531 /* Return the count of bytes in transmit buffer
1532  */
1533 static int chars_in_buffer(struct tty_struct *tty)
1534 {
1535         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536
1537         if (sanity_check(info, tty->name, "chars_in_buffer"))
1538                 return 0;
1539
1540         if (debug_level >= DEBUG_LEVEL_INFO)
1541                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1542                        __FILE__, __LINE__, info->device_name, info->tx_count);
1543
1544         return info->tx_count;
1545 }
1546
1547 /* Signal remote device to throttle send data (our receive data)
1548  */
1549 static void throttle(struct tty_struct * tty)
1550 {
1551         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1552         unsigned long flags;
1553
1554         if (debug_level >= DEBUG_LEVEL_INFO)
1555                 printk("%s(%d):%s throttle() entry\n",
1556                          __FILE__,__LINE__, info->device_name );
1557
1558         if (sanity_check(info, tty->name, "throttle"))
1559                 return;
1560
1561         if (I_IXOFF(tty))
1562                 send_xchar(tty, STOP_CHAR(tty));
1563
1564         if (tty->termios->c_cflag & CRTSCTS) {
1565                 spin_lock_irqsave(&info->lock,flags);
1566                 info->serial_signals &= ~SerialSignal_RTS;
1567                 set_signals(info);
1568                 spin_unlock_irqrestore(&info->lock,flags);
1569         }
1570 }
1571
1572 /* Signal remote device to stop throttling send data (our receive data)
1573  */
1574 static void unthrottle(struct tty_struct * tty)
1575 {
1576         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1577         unsigned long flags;
1578
1579         if (debug_level >= DEBUG_LEVEL_INFO)
1580                 printk("%s(%d):%s unthrottle() entry\n",
1581                          __FILE__,__LINE__, info->device_name );
1582
1583         if (sanity_check(info, tty->name, "unthrottle"))
1584                 return;
1585
1586         if (I_IXOFF(tty)) {
1587                 if (info->x_char)
1588                         info->x_char = 0;
1589                 else
1590                         send_xchar(tty, START_CHAR(tty));
1591         }
1592
1593         if (tty->termios->c_cflag & CRTSCTS) {
1594                 spin_lock_irqsave(&info->lock,flags);
1595                 info->serial_signals |= SerialSignal_RTS;
1596                 set_signals(info);
1597                 spin_unlock_irqrestore(&info->lock,flags);
1598         }
1599 }
1600
1601 /* set or clear transmit break condition
1602  * break_state  -1=set break condition, 0=clear
1603  */
1604 static void set_break(struct tty_struct *tty, int break_state)
1605 {
1606         unsigned char RegValue;
1607         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1608         unsigned long flags;
1609
1610         if (debug_level >= DEBUG_LEVEL_INFO)
1611                 printk("%s(%d):%s set_break(%d)\n",
1612                          __FILE__,__LINE__, info->device_name, break_state);
1613
1614         if (sanity_check(info, tty->name, "set_break"))
1615                 return;
1616
1617         spin_lock_irqsave(&info->lock,flags);
1618         RegValue = read_reg(info, CTL);
1619         if (break_state == -1)
1620                 RegValue |= BIT3;
1621         else
1622                 RegValue &= ~BIT3;
1623         write_reg(info, CTL, RegValue);
1624         spin_unlock_irqrestore(&info->lock,flags);
1625 }
1626
1627 #ifdef CONFIG_HDLC
1628
1629 /**
1630  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1631  * set encoding and frame check sequence (FCS) options
1632  *
1633  * dev       pointer to network device structure
1634  * encoding  serial encoding setting
1635  * parity    FCS setting
1636  *
1637  * returns 0 if success, otherwise error code
1638  */
1639 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1640                           unsigned short parity)
1641 {
1642         SLMP_INFO *info = dev_to_port(dev);
1643         unsigned char  new_encoding;
1644         unsigned short new_crctype;
1645
1646         /* return error if TTY interface open */
1647         if (info->count)
1648                 return -EBUSY;
1649
1650         switch (encoding)
1651         {
1652         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1653         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1654         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1655         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1656         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1657         default: return -EINVAL;
1658         }
1659
1660         switch (parity)
1661         {
1662         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1663         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1664         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1665         default: return -EINVAL;
1666         }
1667
1668         info->params.encoding = new_encoding;
1669         info->params.crc_type = new_crctype;;
1670
1671         /* if network interface up, reprogram hardware */
1672         if (info->netcount)
1673                 program_hw(info);
1674
1675         return 0;
1676 }
1677
1678 /**
1679  * called by generic HDLC layer to send frame
1680  *
1681  * skb  socket buffer containing HDLC frame
1682  * dev  pointer to network device structure
1683  *
1684  * returns 0 if success, otherwise error code
1685  */
1686 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1687 {
1688         SLMP_INFO *info = dev_to_port(dev);
1689         struct net_device_stats *stats = hdlc_stats(dev);
1690         unsigned long flags;
1691
1692         if (debug_level >= DEBUG_LEVEL_INFO)
1693                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1694
1695         /* stop sending until this frame completes */
1696         netif_stop_queue(dev);
1697
1698         /* copy data to device buffers */
1699         info->tx_count = skb->len;
1700         tx_load_dma_buffer(info, skb->data, skb->len);
1701
1702         /* update network statistics */
1703         stats->tx_packets++;
1704         stats->tx_bytes += skb->len;
1705
1706         /* done with socket buffer, so free it */
1707         dev_kfree_skb(skb);
1708
1709         /* save start time for transmit timeout detection */
1710         dev->trans_start = jiffies;
1711
1712         /* start hardware transmitter if necessary */
1713         spin_lock_irqsave(&info->lock,flags);
1714         if (!info->tx_active)
1715                 tx_start(info);
1716         spin_unlock_irqrestore(&info->lock,flags);
1717
1718         return 0;
1719 }
1720
1721 /**
1722  * called by network layer when interface enabled
1723  * claim resources and initialize hardware
1724  *
1725  * dev  pointer to network device structure
1726  *
1727  * returns 0 if success, otherwise error code
1728  */
1729 static int hdlcdev_open(struct net_device *dev)
1730 {
1731         SLMP_INFO *info = dev_to_port(dev);
1732         int rc;
1733         unsigned long flags;
1734
1735         if (debug_level >= DEBUG_LEVEL_INFO)
1736                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1737
1738         /* generic HDLC layer open processing */
1739         if ((rc = hdlc_open(dev)))
1740                 return rc;
1741
1742         /* arbitrate between network and tty opens */
1743         spin_lock_irqsave(&info->netlock, flags);
1744         if (info->count != 0 || info->netcount != 0) {
1745                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1746                 spin_unlock_irqrestore(&info->netlock, flags);
1747                 return -EBUSY;
1748         }
1749         info->netcount=1;
1750         spin_unlock_irqrestore(&info->netlock, flags);
1751
1752         /* claim resources and init adapter */
1753         if ((rc = startup(info)) != 0) {
1754                 spin_lock_irqsave(&info->netlock, flags);
1755                 info->netcount=0;
1756                 spin_unlock_irqrestore(&info->netlock, flags);
1757                 return rc;
1758         }
1759
1760         /* assert DTR and RTS, apply hardware settings */
1761         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1762         program_hw(info);
1763
1764         /* enable network layer transmit */
1765         dev->trans_start = jiffies;
1766         netif_start_queue(dev);
1767
1768         /* inform generic HDLC layer of current DCD status */
1769         spin_lock_irqsave(&info->lock, flags);
1770         get_signals(info);
1771         spin_unlock_irqrestore(&info->lock, flags);
1772         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1773
1774         return 0;
1775 }
1776
1777 /**
1778  * called by network layer when interface is disabled
1779  * shutdown hardware and release resources
1780  *
1781  * dev  pointer to network device structure
1782  *
1783  * returns 0 if success, otherwise error code
1784  */
1785 static int hdlcdev_close(struct net_device *dev)
1786 {
1787         SLMP_INFO *info = dev_to_port(dev);
1788         unsigned long flags;
1789
1790         if (debug_level >= DEBUG_LEVEL_INFO)
1791                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1792
1793         netif_stop_queue(dev);
1794
1795         /* shutdown adapter and release resources */
1796         shutdown(info);
1797
1798         hdlc_close(dev);
1799
1800         spin_lock_irqsave(&info->netlock, flags);
1801         info->netcount=0;
1802         spin_unlock_irqrestore(&info->netlock, flags);
1803
1804         return 0;
1805 }
1806
1807 /**
1808  * called by network layer to process IOCTL call to network device
1809  *
1810  * dev  pointer to network device structure
1811  * ifr  pointer to network interface request structure
1812  * cmd  IOCTL command code
1813  *
1814  * returns 0 if success, otherwise error code
1815  */
1816 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1817 {
1818         const size_t size = sizeof(sync_serial_settings);
1819         sync_serial_settings new_line;
1820         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1821         SLMP_INFO *info = dev_to_port(dev);
1822         unsigned int flags;
1823
1824         if (debug_level >= DEBUG_LEVEL_INFO)
1825                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1826
1827         /* return error if TTY interface open */
1828         if (info->count)
1829                 return -EBUSY;
1830
1831         if (cmd != SIOCWANDEV)
1832                 return hdlc_ioctl(dev, ifr, cmd);
1833
1834         switch(ifr->ifr_settings.type) {
1835         case IF_GET_IFACE: /* return current sync_serial_settings */
1836
1837                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1838                 if (ifr->ifr_settings.size < size) {
1839                         ifr->ifr_settings.size = size; /* data size wanted */
1840                         return -ENOBUFS;
1841                 }
1842
1843                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1844                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1845                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1846                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1847
1848                 switch (flags){
1849                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1850                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1851                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1852                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1853                 default: new_line.clock_type = CLOCK_DEFAULT;
1854                 }
1855
1856                 new_line.clock_rate = info->params.clock_speed;
1857                 new_line.loopback   = info->params.loopback ? 1:0;
1858
1859                 if (copy_to_user(line, &new_line, size))
1860                         return -EFAULT;
1861                 return 0;
1862
1863         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1864
1865                 if(!capable(CAP_NET_ADMIN))
1866                         return -EPERM;
1867                 if (copy_from_user(&new_line, line, size))
1868                         return -EFAULT;
1869
1870                 switch (new_line.clock_type)
1871                 {
1872                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1873                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1874                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1875                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1876                 case CLOCK_DEFAULT:  flags = info->params.flags &
1877                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1878                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1879                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1880                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1881                 default: return -EINVAL;
1882                 }
1883
1884                 if (new_line.loopback != 0 && new_line.loopback != 1)
1885                         return -EINVAL;
1886
1887                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1888                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1889                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1890                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1891                 info->params.flags |= flags;
1892
1893                 info->params.loopback = new_line.loopback;
1894
1895                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1896                         info->params.clock_speed = new_line.clock_rate;
1897                 else
1898                         info->params.clock_speed = 0;
1899
1900                 /* if network interface up, reprogram hardware */
1901                 if (info->netcount)
1902                         program_hw(info);
1903                 return 0;
1904
1905         default:
1906                 return hdlc_ioctl(dev, ifr, cmd);
1907         }
1908 }
1909
1910 /**
1911  * called by network layer when transmit timeout is detected
1912  *
1913  * dev  pointer to network device structure
1914  */
1915 static void hdlcdev_tx_timeout(struct net_device *dev)
1916 {
1917         SLMP_INFO *info = dev_to_port(dev);
1918         struct net_device_stats *stats = hdlc_stats(dev);
1919         unsigned long flags;
1920
1921         if (debug_level >= DEBUG_LEVEL_INFO)
1922                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1923
1924         stats->tx_errors++;
1925         stats->tx_aborted_errors++;
1926
1927         spin_lock_irqsave(&info->lock,flags);
1928         tx_stop(info);
1929         spin_unlock_irqrestore(&info->lock,flags);
1930
1931         netif_wake_queue(dev);
1932 }
1933
1934 /**
1935  * called by device driver when transmit completes
1936  * reenable network layer transmit if stopped
1937  *
1938  * info  pointer to device instance information
1939  */
1940 static void hdlcdev_tx_done(SLMP_INFO *info)
1941 {
1942         if (netif_queue_stopped(info->netdev))
1943                 netif_wake_queue(info->netdev);
1944 }
1945
1946 /**
1947  * called by device driver when frame received
1948  * pass frame to network layer
1949  *
1950  * info  pointer to device instance information
1951  * buf   pointer to buffer contianing frame data
1952  * size  count of data bytes in buf
1953  */
1954 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1955 {
1956         struct sk_buff *skb = dev_alloc_skb(size);
1957         struct net_device *dev = info->netdev;
1958         struct net_device_stats *stats = hdlc_stats(dev);
1959
1960         if (debug_level >= DEBUG_LEVEL_INFO)
1961                 printk("hdlcdev_rx(%s)\n",dev->name);
1962
1963         if (skb == NULL) {
1964                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1965                 stats->rx_dropped++;
1966                 return;
1967         }
1968
1969         memcpy(skb_put(skb, size),buf,size);
1970
1971         skb->dev      = info->netdev;
1972         skb->mac.raw  = skb->data;
1973         skb->protocol = hdlc_type_trans(skb, skb->dev);
1974
1975         stats->rx_packets++;
1976         stats->rx_bytes += size;
1977
1978         netif_rx(skb);
1979
1980         info->netdev->last_rx = jiffies;
1981 }
1982
1983 /**
1984  * called by device driver when adding device instance
1985  * do generic HDLC initialization
1986  *
1987  * info  pointer to device instance information
1988  *
1989  * returns 0 if success, otherwise error code
1990  */
1991 static int hdlcdev_init(SLMP_INFO *info)
1992 {
1993         int rc;
1994         struct net_device *dev;
1995         hdlc_device *hdlc;
1996
1997         /* allocate and initialize network and HDLC layer objects */
1998
1999         if (!(dev = alloc_hdlcdev(info))) {
2000                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
2001                 return -ENOMEM;
2002         }
2003
2004         /* for network layer reporting purposes only */
2005         dev->mem_start = info->phys_sca_base;
2006         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
2007         dev->irq       = info->irq_level;
2008
2009         /* network layer callbacks and settings */
2010         dev->do_ioctl       = hdlcdev_ioctl;
2011         dev->open           = hdlcdev_open;
2012         dev->stop           = hdlcdev_close;
2013         dev->tx_timeout     = hdlcdev_tx_timeout;
2014         dev->watchdog_timeo = 10*HZ;
2015         dev->tx_queue_len   = 50;
2016
2017         /* generic HDLC layer callbacks and settings */
2018         hdlc         = dev_to_hdlc(dev);
2019         hdlc->attach = hdlcdev_attach;
2020         hdlc->xmit   = hdlcdev_xmit;
2021
2022         /* register objects with HDLC layer */
2023         if ((rc = register_hdlc_device(dev))) {
2024                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2025                 free_netdev(dev);
2026                 return rc;
2027         }
2028
2029         info->netdev = dev;
2030         return 0;
2031 }
2032
2033 /**
2034  * called by device driver when removing device instance
2035  * do generic HDLC cleanup
2036  *
2037  * info  pointer to device instance information
2038  */
2039 static void hdlcdev_exit(SLMP_INFO *info)
2040 {
2041         unregister_hdlc_device(info->netdev);
2042         free_netdev(info->netdev);
2043         info->netdev = NULL;
2044 }
2045
2046 #endif /* CONFIG_HDLC */
2047
2048
2049 /* Return next bottom half action to perform.
2050  * Return Value:        BH action code or 0 if nothing to do.
2051  */
2052 int bh_action(SLMP_INFO *info)
2053 {
2054         unsigned long flags;
2055         int rc = 0;
2056
2057         spin_lock_irqsave(&info->lock,flags);
2058
2059         if (info->pending_bh & BH_RECEIVE) {
2060                 info->pending_bh &= ~BH_RECEIVE;
2061                 rc = BH_RECEIVE;
2062         } else if (info->pending_bh & BH_TRANSMIT) {
2063                 info->pending_bh &= ~BH_TRANSMIT;
2064                 rc = BH_TRANSMIT;
2065         } else if (info->pending_bh & BH_STATUS) {
2066                 info->pending_bh &= ~BH_STATUS;
2067                 rc = BH_STATUS;
2068         }
2069
2070         if (!rc) {
2071                 /* Mark BH routine as complete */
2072                 info->bh_running   = 0;
2073                 info->bh_requested = 0;
2074         }
2075
2076         spin_unlock_irqrestore(&info->lock,flags);
2077
2078         return rc;
2079 }
2080
2081 /* Perform bottom half processing of work items queued by ISR.
2082  */
2083 void bh_handler(void* Context)
2084 {
2085         SLMP_INFO *info = (SLMP_INFO*)Context;
2086         int action;
2087
2088         if (!info)
2089                 return;
2090
2091         if ( debug_level >= DEBUG_LEVEL_BH )
2092                 printk( "%s(%d):%s bh_handler() entry\n",
2093                         __FILE__,__LINE__,info->device_name);
2094
2095         info->bh_running = 1;
2096
2097         while((action = bh_action(info)) != 0) {
2098
2099                 /* Process work item */
2100                 if ( debug_level >= DEBUG_LEVEL_BH )
2101                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2102                                 __FILE__,__LINE__,info->device_name, action);
2103
2104                 switch (action) {
2105
2106                 case BH_RECEIVE:
2107                         bh_receive(info);
2108                         break;
2109                 case BH_TRANSMIT:
2110                         bh_transmit(info);
2111                         break;
2112                 case BH_STATUS:
2113                         bh_status(info);
2114                         break;
2115                 default:
2116                         /* unknown work item ID */
2117                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2118                                 __FILE__,__LINE__,info->device_name,action);
2119                         break;
2120                 }
2121         }
2122
2123         if ( debug_level >= DEBUG_LEVEL_BH )
2124                 printk( "%s(%d):%s bh_handler() exit\n",
2125                         __FILE__,__LINE__,info->device_name);
2126 }
2127
2128 void bh_receive(SLMP_INFO *info)
2129 {
2130         if ( debug_level >= DEBUG_LEVEL_BH )
2131                 printk( "%s(%d):%s bh_receive()\n",
2132                         __FILE__,__LINE__,info->device_name);
2133
2134         while( rx_get_frame(info) );
2135 }
2136
2137 void bh_transmit(SLMP_INFO *info)
2138 {
2139         struct tty_struct *tty = info->tty;
2140
2141         if ( debug_level >= DEBUG_LEVEL_BH )
2142                 printk( "%s(%d):%s bh_transmit() entry\n",
2143                         __FILE__,__LINE__,info->device_name);
2144
2145         if (tty) {
2146                 tty_wakeup(tty);
2147                 wake_up_interruptible(&tty->write_wait);
2148         }
2149 }
2150
2151 void bh_status(SLMP_INFO *info)
2152 {
2153         if ( debug_level >= DEBUG_LEVEL_BH )
2154                 printk( "%s(%d):%s bh_status() entry\n",
2155                         __FILE__,__LINE__,info->device_name);
2156
2157         info->ri_chkcount = 0;
2158         info->dsr_chkcount = 0;
2159         info->dcd_chkcount = 0;
2160         info->cts_chkcount = 0;
2161 }
2162
2163 void isr_timer(SLMP_INFO * info)
2164 {
2165         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2166
2167         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2168         write_reg(info, IER2, 0);
2169
2170         /* TMCS, Timer Control/Status Register
2171          *
2172          * 07      CMF, Compare match flag (read only) 1=match
2173          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2174          * 05      Reserved, must be 0
2175          * 04      TME, Timer Enable
2176          * 03..00  Reserved, must be 0
2177          *
2178          * 0000 0000
2179          */
2180         write_reg(info, (unsigned char)(timer + TMCS), 0);
2181
2182         info->irq_occurred = TRUE;
2183
2184         if ( debug_level >= DEBUG_LEVEL_ISR )
2185                 printk("%s(%d):%s isr_timer()\n",
2186                         __FILE__,__LINE__,info->device_name);
2187 }
2188
2189 void isr_rxint(SLMP_INFO * info)
2190 {
2191         struct tty_struct *tty = info->tty;
2192         struct  mgsl_icount *icount = &info->icount;
2193         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2194         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2195
2196         /* clear status bits */
2197         if (status)
2198                 write_reg(info, SR1, status);
2199
2200         if (status2)
2201                 write_reg(info, SR2, status2);
2202
2203         if ( debug_level >= DEBUG_LEVEL_ISR )
2204                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2205                         __FILE__,__LINE__,info->device_name,status,status2);
2206
2207         if (info->params.mode == MGSL_MODE_ASYNC) {
2208                 if (status & BRKD) {
2209                         icount->brk++;
2210
2211                         /* process break detection if tty control
2212                          * is not set to ignore it
2213                          */
2214                         if ( tty ) {
2215                                 if (!(status & info->ignore_status_mask1)) {
2216                                         if (info->read_status_mask1 & BRKD) {
2217                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2218                                                 if (info->flags & ASYNC_SAK)
2219                                                         do_SAK(tty);
2220                                         }
2221                                 }
2222                         }
2223                 }
2224         }
2225         else {
2226                 if (status & (FLGD|IDLD)) {
2227                         if (status & FLGD)
2228                                 info->icount.exithunt++;
2229                         else if (status & IDLD)
2230                                 info->icount.rxidle++;
2231                         wake_up_interruptible(&info->event_wait_q);
2232                 }
2233         }
2234
2235         if (status & CDCD) {
2236                 /* simulate a common modem status change interrupt
2237                  * for our handler
2238                  */
2239                 get_signals( info );
2240                 isr_io_pin(info,
2241                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2242         }
2243 }
2244
2245 /*
2246  * handle async rx data interrupts
2247  */
2248 void isr_rxrdy(SLMP_INFO * info)
2249 {
2250         u16 status;
2251         unsigned char DataByte;
2252         struct tty_struct *tty = info->tty;
2253         struct  mgsl_icount *icount = &info->icount;
2254
2255         if ( debug_level >= DEBUG_LEVEL_ISR )
2256                 printk("%s(%d):%s isr_rxrdy\n",
2257                         __FILE__,__LINE__,info->device_name);
2258
2259         while((status = read_reg(info,CST0)) & BIT0)
2260         {
2261                 DataByte = read_reg(info,TRB);
2262
2263                 if ( tty ) {
2264                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2265                                 continue;
2266
2267                         *tty->flip.char_buf_ptr = DataByte;
2268                         *tty->flip.flag_buf_ptr = 0;
2269                 }
2270
2271                 icount->rx++;
2272
2273                 if ( status & (PE + FRME + OVRN) ) {
2274                         printk("%s(%d):%s rxerr=%04X\n",
2275                                 __FILE__,__LINE__,info->device_name,status);
2276
2277                         /* update error statistics */
2278                         if (status & PE)
2279                                 icount->parity++;
2280                         else if (status & FRME)
2281                                 icount->frame++;
2282                         else if (status & OVRN)
2283                                 icount->overrun++;
2284
2285                         /* discard char if tty control flags say so */
2286                         if (status & info->ignore_status_mask2)
2287                                 continue;
2288
2289                         status &= info->read_status_mask2;
2290
2291                         if ( tty ) {
2292                                 if (status & PE)
2293                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2294                                 else if (status & FRME)
2295                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2296                                 if (status & OVRN) {
2297                                         /* Overrun is special, since it's
2298                                          * reported immediately, and doesn't
2299                                          * affect the current character
2300                                          */
2301                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2302                                                 tty->flip.count++;
2303                                                 tty->flip.flag_buf_ptr++;
2304                                                 tty->flip.char_buf_ptr++;
2305                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2306                                         }
2307                                 }
2308                         }
2309                 }       /* end of if (error) */
2310
2311                 if ( tty ) {
2312                         tty->flip.flag_buf_ptr++;
2313                         tty->flip.char_buf_ptr++;
2314                         tty->flip.count++;
2315                 }
2316         }
2317
2318         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2319                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2320                         __FILE__,__LINE__,info->device_name,
2321                         tty ? tty->flip.count : 0);
2322                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2323                         __FILE__,__LINE__,info->device_name,
2324                         icount->rx,icount->brk,icount->parity,
2325                         icount->frame,icount->overrun);
2326         }
2327
2328         if ( tty && tty->flip.count )
2329                 tty_flip_buffer_push(tty);
2330 }
2331
2332 void isr_txeom(SLMP_INFO * info, unsigned char status)
2333 {
2334         if ( debug_level >= DEBUG_LEVEL_ISR )
2335                 printk("%s(%d):%s isr_txeom status=%02x\n",
2336                         __FILE__,__LINE__,info->device_name,status);
2337
2338         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2339         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2340         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2341
2342         if (status & UDRN) {
2343                 write_reg(info, CMD, TXRESET);
2344                 write_reg(info, CMD, TXENABLE);
2345         } else
2346                 write_reg(info, CMD, TXBUFCLR);
2347
2348         /* disable and clear tx interrupts */
2349         info->ie0_value &= ~TXRDYE;
2350         info->ie1_value &= ~(IDLE + UDRN);
2351         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2352         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2353
2354         if ( info->tx_active ) {
2355                 if (info->params.mode != MGSL_MODE_ASYNC) {
2356                         if (status & UDRN)
2357                                 info->icount.txunder++;
2358                         else if (status & IDLE)
2359                                 info->icount.txok++;
2360                 }
2361
2362                 info->tx_active = 0;
2363                 info->tx_count = info->tx_put = info->tx_get = 0;
2364
2365                 del_timer(&info->tx_timer);
2366
2367                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2368                         info->serial_signals &= ~SerialSignal_RTS;
2369                         info->drop_rts_on_tx_done = 0;
2370                         set_signals(info);
2371                 }
2372
2373 #ifdef CONFIG_HDLC
2374                 if (info->netcount)
2375                         hdlcdev_tx_done(info);
2376                 else
2377 #endif
2378                 {
2379                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2380                                 tx_stop(info);
2381                                 return;
2382                         }
2383                         info->pending_bh |= BH_TRANSMIT;
2384                 }
2385         }
2386 }
2387
2388
2389 /*
2390  * handle tx status interrupts
2391  */
2392 void isr_txint(SLMP_INFO * info)
2393 {
2394         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2395
2396         /* clear status bits */
2397         write_reg(info, SR1, status);
2398
2399         if ( debug_level >= DEBUG_LEVEL_ISR )
2400                 printk("%s(%d):%s isr_txint status=%02x\n",
2401                         __FILE__,__LINE__,info->device_name,status);
2402
2403         if (status & (UDRN + IDLE))
2404                 isr_txeom(info, status);
2405
2406         if (status & CCTS) {
2407                 /* simulate a common modem status change interrupt
2408                  * for our handler
2409                  */
2410                 get_signals( info );
2411                 isr_io_pin(info,
2412                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2413
2414         }
2415 }
2416
2417 /*
2418  * handle async tx data interrupts
2419  */
2420 void isr_txrdy(SLMP_INFO * info)
2421 {
2422         if ( debug_level >= DEBUG_LEVEL_ISR )
2423                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2424                         __FILE__,__LINE__,info->device_name,info->tx_count);
2425
2426         if (info->params.mode != MGSL_MODE_ASYNC) {
2427                 /* disable TXRDY IRQ, enable IDLE IRQ */
2428                 info->ie0_value &= ~TXRDYE;
2429                 info->ie1_value |= IDLE;
2430                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2431                 return;
2432         }
2433
2434         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2435                 tx_stop(info);
2436                 return;
2437         }
2438
2439         if ( info->tx_count )
2440                 tx_load_fifo( info );
2441         else {
2442                 info->tx_active = 0;
2443                 info->ie0_value &= ~TXRDYE;
2444                 write_reg(info, IE0, info->ie0_value);
2445         }
2446
2447         if (info->tx_count < WAKEUP_CHARS)
2448                 info->pending_bh |= BH_TRANSMIT;
2449 }
2450
2451 void isr_rxdmaok(SLMP_INFO * info)
2452 {
2453         /* BIT7 = EOT (end of transfer)
2454          * BIT6 = EOM (end of message/frame)
2455          */
2456         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2457
2458         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2459         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2460
2461         if ( debug_level >= DEBUG_LEVEL_ISR )
2462                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2463                         __FILE__,__LINE__,info->device_name,status);
2464
2465         info->pending_bh |= BH_RECEIVE;
2466 }
2467
2468 void isr_rxdmaerror(SLMP_INFO * info)
2469 {
2470         /* BIT5 = BOF (buffer overflow)
2471          * BIT4 = COF (counter overflow)
2472          */
2473         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2474
2475         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2476         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2477
2478         if ( debug_level >= DEBUG_LEVEL_ISR )
2479                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2480                         __FILE__,__LINE__,info->device_name,status);
2481
2482         info->rx_overflow = TRUE;
2483         info->pending_bh |= BH_RECEIVE;
2484 }
2485
2486 void isr_txdmaok(SLMP_INFO * info)
2487 {
2488         unsigned char status_reg1 = read_reg(info, SR1);
2489
2490         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2491         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2492         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2493
2494         if ( debug_level >= DEBUG_LEVEL_ISR )
2495                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2496                         __FILE__,__LINE__,info->device_name,status_reg1);
2497
2498         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2499         write_reg16(info, TRC0, 0);
2500         info->ie0_value |= TXRDYE;
2501         write_reg(info, IE0, info->ie0_value);
2502 }
2503
2504 void isr_txdmaerror(SLMP_INFO * info)
2505 {
2506         /* BIT5 = BOF (buffer overflow)
2507          * BIT4 = COF (counter overflow)
2508          */
2509         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2510
2511         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2512         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2513
2514         if ( debug_level >= DEBUG_LEVEL_ISR )
2515                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2516                         __FILE__,__LINE__,info->device_name,status);
2517 }
2518
2519 /* handle input serial signal changes
2520  */
2521 void isr_io_pin( SLMP_INFO *info, u16 status )
2522 {
2523         struct  mgsl_icount *icount;
2524
2525         if ( debug_level >= DEBUG_LEVEL_ISR )
2526                 printk("%s(%d):isr_io_pin status=%04X\n",
2527                         __FILE__,__LINE__,status);
2528
2529         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2530                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2531                 icount = &info->icount;
2532                 /* update input line counters */
2533                 if (status & MISCSTATUS_RI_LATCHED) {
2534                         icount->rng++;
2535                         if ( status & SerialSignal_RI )
2536                                 info->input_signal_events.ri_up++;
2537                         else
2538                                 info->input_signal_events.ri_down++;
2539                 }
2540                 if (status & MISCSTATUS_DSR_LATCHED) {
2541                         icount->dsr++;
2542                         if ( status & SerialSignal_DSR )
2543                                 info->input_signal_events.dsr_up++;
2544                         else
2545                                 info->input_signal_events.dsr_down++;
2546                 }
2547                 if (status & MISCSTATUS_DCD_LATCHED) {
2548                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2549                                 info->ie1_value &= ~CDCD;
2550                                 write_reg(info, IE1, info->ie1_value);
2551                         }
2552                         icount->dcd++;
2553                         if (status & SerialSignal_DCD) {
2554                                 info->input_signal_events.dcd_up++;
2555                         } else
2556                                 info->input_signal_events.dcd_down++;
2557 #ifdef CONFIG_HDLC
2558                         if (info->netcount)
2559                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2560 #endif
2561                 }
2562                 if (status & MISCSTATUS_CTS_LATCHED)
2563                 {
2564                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2565                                 info->ie1_value &= ~CCTS;
2566                                 write_reg(info, IE1, info->ie1_value);
2567                         }
2568                         icount->cts++;
2569                         if ( status & SerialSignal_CTS )
2570                                 info->input_signal_events.cts_up++;
2571                         else
2572                                 info->input_signal_events.cts_down++;
2573                 }
2574                 wake_up_interruptible(&info->status_event_wait_q);
2575                 wake_up_interruptible(&info->event_wait_q);
2576
2577                 if ( (info->flags & ASYNC_CHECK_CD) &&
2578                      (status & MISCSTATUS_DCD_LATCHED) ) {
2579                         if ( debug_level >= DEBUG_LEVEL_ISR )
2580                                 printk("%s CD now %s...", info->device_name,
2581                                        (status & SerialSignal_DCD) ? "on" : "off");
2582                         if (status & SerialSignal_DCD)
2583                                 wake_up_interruptible(&info->open_wait);
2584                         else {
2585                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2586                                         printk("doing serial hangup...");
2587                                 if (info->tty)
2588                                         tty_hangup(info->tty);
2589                         }
2590                 }
2591
2592                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2593                      (status & MISCSTATUS_CTS_LATCHED) ) {
2594                         if ( info->tty ) {
2595                                 if (info->tty->hw_stopped) {
2596                                         if (status & SerialSignal_CTS) {
2597                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2598                                                         printk("CTS tx start...");
2599                                                 info->tty->hw_stopped = 0;
2600                                                 tx_start(info);
2601                                                 info->pending_bh |= BH_TRANSMIT;
2602                                                 return;
2603                                         }
2604                                 } else {
2605                                         if (!(status & SerialSignal_CTS)) {
2606                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2607                                                         printk("CTS tx stop...");
2608                                                 info->tty->hw_stopped = 1;
2609                                                 tx_stop(info);
2610                                         }
2611                                 }
2612                         }
2613                 }
2614         }
2615
2616         info->pending_bh |= BH_STATUS;
2617 }
2618
2619 /* Interrupt service routine entry point.
2620  *
2621  * Arguments:
2622  *      irq             interrupt number that caused interrupt
2623  *      dev_id          device ID supplied during interrupt registration
2624  *      regs            interrupted processor context
2625  */
2626 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2627                                         struct pt_regs *regs)
2628 {
2629         SLMP_INFO * info;
2630         unsigned char status, status0, status1=0;
2631         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2632         unsigned char timerstatus0, timerstatus1=0;
2633         unsigned char shift;
2634         unsigned int i;
2635         unsigned short tmp;
2636
2637         if ( debug_level >= DEBUG_LEVEL_ISR )
2638                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2639                         __FILE__,__LINE__,irq);
2640
2641         info = (SLMP_INFO *)dev_id;
2642         if (!info)
2643                 return IRQ_NONE;
2644
2645         spin_lock(&info->lock);
2646
2647         for(;;) {
2648
2649                 /* get status for SCA0 (ports 0-1) */
2650                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2651                 status0 = (unsigned char)tmp;
2652                 dmastatus0 = (unsigned char)(tmp>>8);
2653                 timerstatus0 = read_reg(info, ISR2);
2654
2655                 if ( debug_level >= DEBUG_LEVEL_ISR )
2656                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2657                                 __FILE__,__LINE__,info->device_name,
2658                                 status0,dmastatus0,timerstatus0);
2659
2660                 if (info->port_count == 4) {
2661                         /* get status for SCA1 (ports 2-3) */
2662                         tmp = read_reg16(info->port_array[2], ISR0);
2663                         status1 = (unsigned char)tmp;
2664                         dmastatus1 = (unsigned char)(tmp>>8);
2665                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2666
2667                         if ( debug_level >= DEBUG_LEVEL_ISR )
2668                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2669                                         __FILE__,__LINE__,info->device_name,
2670                                         status1,dmastatus1,timerstatus1);
2671                 }
2672
2673                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2674                          !status1 && !dmastatus1 && !timerstatus1)
2675                         break;
2676
2677                 for(i=0; i < info->port_count ; i++) {
2678                         if (info->port_array[i] == NULL)
2679                                 continue;
2680                         if (i < 2) {
2681                                 status = status0;
2682                                 dmastatus = dmastatus0;
2683                         } else {
2684                                 status = status1;
2685                                 dmastatus = dmastatus1;
2686                         }
2687
2688                         shift = i & 1 ? 4 :0;
2689
2690                         if (status & BIT0 << shift)
2691                                 isr_rxrdy(info->port_array[i]);
2692                         if (status & BIT1 << shift)
2693                                 isr_txrdy(info->port_array[i]);
2694                         if (status & BIT2 << shift)
2695                                 isr_rxint(info->port_array[i]);
2696                         if (status & BIT3 << shift)
2697                                 isr_txint(info->port_array[i]);
2698
2699                         if (dmastatus & BIT0 << shift)
2700                                 isr_rxdmaerror(info->port_array[i]);
2701                         if (dmastatus & BIT1 << shift)
2702                                 isr_rxdmaok(info->port_array[i]);
2703                         if (dmastatus & BIT2 << shift)
2704                                 isr_txdmaerror(info->port_array[i]);
2705                         if (dmastatus & BIT3 << shift)
2706                                 isr_txdmaok(info->port_array[i]);
2707                 }
2708
2709                 if (timerstatus0 & (BIT5 | BIT4))
2710                         isr_timer(info->port_array[0]);
2711                 if (timerstatus0 & (BIT7 | BIT6))
2712                         isr_timer(info->port_array[1]);
2713                 if (timerstatus1 & (BIT5 | BIT4))
2714                         isr_timer(info->port_array[2]);
2715                 if (timerstatus1 & (BIT7 | BIT6))
2716                         isr_timer(info->port_array[3]);
2717         }
2718
2719         for(i=0; i < info->port_count ; i++) {
2720                 SLMP_INFO * port = info->port_array[i];
2721
2722                 /* Request bottom half processing if there's something
2723                  * for it to do and the bh is not already running.
2724                  *
2725                  * Note: startup adapter diags require interrupts.
2726                  * do not request bottom half processing if the
2727                  * device is not open in a normal mode.
2728                  */
2729                 if ( port && (port->count || port->netcount) &&
2730                      port->pending_bh && !port->bh_running &&
2731                      !port->bh_requested ) {
2732                         if ( debug_level >= DEBUG_LEVEL_ISR )
2733                                 printk("%s(%d):%s queueing bh task.\n",
2734                                         __FILE__,__LINE__,port->device_name);
2735                         schedule_work(&port->task);
2736                         port->bh_requested = 1;
2737                 }
2738         }
2739
2740         spin_unlock(&info->lock);
2741
2742         if ( debug_level >= DEBUG_LEVEL_ISR )
2743                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2744                         __FILE__,__LINE__,irq);
2745         return IRQ_HANDLED;
2746 }
2747
2748 /* Initialize and start device.
2749  */
2750 static int startup(SLMP_INFO * info)
2751 {
2752         if ( debug_level >= DEBUG_LEVEL_INFO )
2753                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2754
2755         if (info->flags & ASYNC_INITIALIZED)
2756                 return 0;
2757
2758         if (!info->tx_buf) {
2759                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2760                 if (!info->tx_buf) {
2761                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2762                                 __FILE__,__LINE__,info->device_name);
2763                         return -ENOMEM;
2764                 }
2765         }
2766
2767         info->pending_bh = 0;
2768
2769         /* program hardware for current parameters */
2770         reset_port(info);
2771
2772         change_params(info);
2773
2774         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2775         add_timer(&info->status_timer);
2776
2777         if (info->tty)
2778                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2779
2780         info->flags |= ASYNC_INITIALIZED;
2781
2782         return 0;
2783 }
2784
2785 /* Called by close() and hangup() to shutdown hardware
2786  */
2787 static void shutdown(SLMP_INFO * info)
2788 {
2789         unsigned long flags;
2790
2791         if (!(info->flags & ASYNC_INITIALIZED))
2792                 return;
2793
2794         if (debug_level >= DEBUG_LEVEL_INFO)
2795                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2796                          __FILE__,__LINE__, info->device_name );
2797
2798         /* clear status wait queue because status changes */
2799         /* can't happen after shutting down the hardware */
2800         wake_up_interruptible(&info->status_event_wait_q);
2801         wake_up_interruptible(&info->event_wait_q);
2802
2803         del_timer(&info->tx_timer);
2804         del_timer(&info->status_timer);
2805
2806         if (info->tx_buf) {
2807                 kfree(info->tx_buf);
2808                 info->tx_buf = NULL;
2809         }
2810
2811         spin_lock_irqsave(&info->lock,flags);
2812
2813         reset_port(info);
2814
2815         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2816                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2817                 set_signals(info);
2818         }
2819
2820         spin_unlock_irqrestore(&info->lock,flags);
2821
2822         if (info->tty)
2823                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2824
2825         info->flags &= ~ASYNC_INITIALIZED;
2826 }
2827
2828 static void program_hw(SLMP_INFO *info)
2829 {
2830         unsigned long flags;
2831
2832         spin_lock_irqsave(&info->lock,flags);
2833
2834         rx_stop(info);
2835         tx_stop(info);
2836
2837         info->tx_count = info->tx_put = info->tx_get = 0;
2838
2839         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2840                 hdlc_mode(info);
2841         else
2842                 async_mode(info);
2843
2844         set_signals(info);
2845
2846         info->dcd_chkcount = 0;
2847         info->cts_chkcount = 0;
2848         info->ri_chkcount = 0;
2849         info->dsr_chkcount = 0;
2850
2851         info->ie1_value |= (CDCD|CCTS);
2852         write_reg(info, IE1, info->ie1_value);
2853
2854         get_signals(info);
2855
2856         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2857                 rx_start(info);
2858
2859         spin_unlock_irqrestore(&info->lock,flags);
2860 }
2861
2862 /* Reconfigure adapter based on new parameters
2863  */
2864 static void change_params(SLMP_INFO *info)
2865 {
2866         unsigned cflag;
2867         int bits_per_char;
2868
2869         if (!info->tty || !info->tty->termios)
2870                 return;
2871
2872         if (debug_level >= DEBUG_LEVEL_INFO)
2873                 printk("%s(%d):%s change_params()\n",
2874                          __FILE__,__LINE__, info->device_name );
2875
2876         cflag = info->tty->termios->c_cflag;
2877
2878         /* if B0 rate (hangup) specified then negate DTR and RTS */
2879         /* otherwise assert DTR and RTS */
2880         if (cflag & CBAUD)
2881                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2882         else
2883                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2884
2885         /* byte size and parity */
2886
2887         switch (cflag & CSIZE) {
2888               case CS5: info->params.data_bits = 5; break;
2889               case CS6: info->params.data_bits = 6; break;
2890               case CS7: info->params.data_bits = 7; break;
2891               case CS8: info->params.data_bits = 8; break;
2892               /* Never happens, but GCC is too dumb to figure it out */
2893               default:  info->params.data_bits = 7; break;
2894               }
2895
2896         if (cflag & CSTOPB)
2897                 info->params.stop_bits = 2;
2898         else
2899                 info->params.stop_bits = 1;
2900
2901         info->params.parity = ASYNC_PARITY_NONE;
2902         if (cflag & PARENB) {
2903                 if (cflag & PARODD)
2904                         info->params.parity = ASYNC_PARITY_ODD;
2905                 else
2906                         info->params.parity = ASYNC_PARITY_EVEN;
2907 #ifdef CMSPAR
2908                 if (cflag & CMSPAR)
2909                         info->params.parity = ASYNC_PARITY_SPACE;
2910 #endif
2911         }
2912
2913         /* calculate number of jiffies to transmit a full
2914          * FIFO (32 bytes) at specified data rate
2915          */
2916         bits_per_char = info->params.data_bits +
2917                         info->params.stop_bits + 1;
2918
2919         /* if port data rate is set to 460800 or less then
2920          * allow tty settings to override, otherwise keep the
2921          * current data rate.
2922          */
2923         if (info->params.data_rate <= 460800) {
2924                 info->params.data_rate = tty_get_baud_rate(info->tty);
2925         }
2926
2927         if ( info->params.data_rate ) {
2928                 info->timeout = (32*HZ*bits_per_char) /
2929                                 info->params.data_rate;
2930         }
2931         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2932
2933         if (cflag & CRTSCTS)
2934                 info->flags |= ASYNC_CTS_FLOW;
2935         else
2936                 info->flags &= ~ASYNC_CTS_FLOW;
2937
2938         if (cflag & CLOCAL)
2939                 info->flags &= ~ASYNC_CHECK_CD;
2940         else
2941                 info->flags |= ASYNC_CHECK_CD;
2942
2943         /* process tty input control flags */
2944
2945         info->read_status_mask2 = OVRN;
2946         if (I_INPCK(info->tty))
2947                 info->read_status_mask2 |= PE | FRME;
2948         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2949                 info->read_status_mask1 |= BRKD;
2950         if (I_IGNPAR(info->tty))
2951                 info->ignore_status_mask2 |= PE | FRME;
2952         if (I_IGNBRK(info->tty)) {
2953                 info->ignore_status_mask1 |= BRKD;
2954                 /* If ignoring parity and break indicators, ignore
2955                  * overruns too.  (For real raw support).
2956                  */
2957                 if (I_IGNPAR(info->tty))
2958                         info->ignore_status_mask2 |= OVRN;
2959         }
2960
2961         program_hw(info);
2962 }
2963
2964 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2965 {
2966         int err;
2967
2968         if (debug_level >= DEBUG_LEVEL_INFO)
2969                 printk("%s(%d):%s get_params()\n",
2970                          __FILE__,__LINE__, info->device_name);
2971
2972         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2973         if (err) {
2974                 if ( debug_level >= DEBUG_LEVEL_INFO )
2975                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2976                                 __FILE__,__LINE__,info->device_name);
2977                 return -EFAULT;
2978         }
2979
2980         return 0;
2981 }
2982
2983 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2984 {
2985         int err;
2986         if (debug_level >= DEBUG_LEVEL_INFO)
2987                 printk("%s(%d):%s get_params()\n",
2988                          __FILE__,__LINE__, info->device_name);
2989
2990         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2991         if (err) {
2992                 if ( debug_level >= DEBUG_LEVEL_INFO )
2993                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2994                                 __FILE__,__LINE__,info->device_name);
2995                 return -EFAULT;
2996         }
2997
2998         return 0;
2999 }
3000
3001 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
3002 {
3003         unsigned long flags;
3004         MGSL_PARAMS tmp_params;
3005         int err;
3006
3007         if (debug_level >= DEBUG_LEVEL_INFO)
3008                 printk("%s(%d):%s set_params\n",
3009                         __FILE__,__LINE__,info->device_name );
3010         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
3011         if (err) {
3012                 if ( debug_level >= DEBUG_LEVEL_INFO )
3013                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
3014                                 __FILE__,__LINE__,info->device_name);
3015                 return -EFAULT;
3016         }
3017
3018         spin_lock_irqsave(&info->lock,flags);
3019         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3020         spin_unlock_irqrestore(&info->lock,flags);
3021
3022         change_params(info);
3023
3024         return 0;
3025 }
3026
3027 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3028 {
3029         int err;
3030
3031         if (debug_level >= DEBUG_LEVEL_INFO)
3032                 printk("%s(%d):%s get_txidle()=%d\n",
3033                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3034
3035         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3036         if (err) {
3037                 if ( debug_level >= DEBUG_LEVEL_INFO )
3038                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3039                                 __FILE__,__LINE__,info->device_name);
3040                 return -EFAULT;
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int set_txidle(SLMP_INFO * info, int idle_mode)
3047 {
3048         unsigned long flags;
3049
3050         if (debug_level >= DEBUG_LEVEL_INFO)
3051                 printk("%s(%d):%s set_txidle(%d)\n",
3052                         __FILE__,__LINE__,info->device_name, idle_mode );
3053
3054         spin_lock_irqsave(&info->lock,flags);
3055         info->idle_mode = idle_mode;
3056         tx_set_idle( info );
3057         spin_unlock_irqrestore(&info->lock,flags);
3058         return 0;
3059 }
3060
3061 static int tx_enable(SLMP_INFO * info, int enable)
3062 {
3063         unsigned long flags;
3064
3065         if (debug_level >= DEBUG_LEVEL_INFO)
3066                 printk("%s(%d):%s tx_enable(%d)\n",
3067                         __FILE__,__LINE__,info->device_name, enable);
3068
3069         spin_lock_irqsave(&info->lock,flags);
3070         if ( enable ) {
3071                 if ( !info->tx_enabled ) {
3072                         tx_start(info);
3073                 }
3074         } else {
3075                 if ( info->tx_enabled )
3076                         tx_stop(info);
3077         }
3078         spin_unlock_irqrestore(&info->lock,flags);
3079         return 0;
3080 }
3081
3082 /* abort send HDLC frame
3083  */
3084 static int tx_abort(SLMP_INFO * info)
3085 {
3086         unsigned long flags;
3087
3088         if (debug_level >= DEBUG_LEVEL_INFO)
3089                 printk("%s(%d):%s tx_abort()\n",
3090                         __FILE__,__LINE__,info->device_name);
3091
3092         spin_lock_irqsave(&info->lock,flags);
3093         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3094                 info->ie1_value &= ~UDRN;
3095                 info->ie1_value |= IDLE;
3096                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3097                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3098
3099                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3100                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3101
3102                 write_reg(info, CMD, TXABORT);
3103         }
3104         spin_unlock_irqrestore(&info->lock,flags);
3105         return 0;
3106 }
3107
3108 static int rx_enable(SLMP_INFO * info, int enable)
3109 {
3110         unsigned long flags;
3111
3112         if (debug_level >= DEBUG_LEVEL_INFO)
3113                 printk("%s(%d):%s rx_enable(%d)\n",
3114                         __FILE__,__LINE__,info->device_name,enable);
3115
3116         spin_lock_irqsave(&info->lock,flags);
3117         if ( enable ) {
3118                 if ( !info->rx_enabled )
3119                         rx_start(info);
3120         } else {
3121                 if ( info->rx_enabled )
3122                         rx_stop(info);
3123         }
3124         spin_unlock_irqrestore(&info->lock,flags);
3125         return 0;
3126 }
3127
3128 static int map_status(int signals)
3129 {
3130         /* Map status bits to API event bits */
3131
3132         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
3133                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
3134                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
3135                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
3136 }
3137
3138 /* wait for specified event to occur
3139  */
3140 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3141 {
3142         unsigned long flags;
3143         int s;
3144         int rc=0;
3145         struct mgsl_icount cprev, cnow;
3146         int events;
3147         int mask;
3148         struct  _input_signal_events oldsigs, newsigs;
3149         DECLARE_WAITQUEUE(wait, current);
3150
3151         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3152         if (rc) {
3153                 return  -EFAULT;
3154         }
3155
3156         if (debug_level >= DEBUG_LEVEL_INFO)
3157                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3158                         __FILE__,__LINE__,info->device_name,mask);
3159
3160         spin_lock_irqsave(&info->lock,flags);
3161
3162         /* return immediately if state matches requested events */
3163         get_signals(info);
3164         s = map_status(info->serial_signals);
3165
3166         events = mask &
3167                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3168                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3169                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3170                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3171         if (events) {
3172                 spin_unlock_irqrestore(&info->lock,flags);
3173                 goto exit;
3174         }
3175
3176         /* save current irq counts */
3177         cprev = info->icount;
3178         oldsigs = info->input_signal_events;
3179
3180         /* enable hunt and idle irqs if needed */
3181         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3182                 unsigned char oldval = info->ie1_value;
3183                 unsigned char newval = oldval +
3184                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3185                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3186                 if ( oldval != newval ) {
3187                         info->ie1_value = newval;
3188                         write_reg(info, IE1, info->ie1_value);
3189                 }
3190         }
3191
3192         set_current_state(TASK_INTERRUPTIBLE);
3193         add_wait_queue(&info->event_wait_q, &wait);
3194
3195         spin_unlock_irqrestore(&info->lock,flags);
3196
3197         for(;;) {
3198                 schedule();
3199                 if (signal_pending(current)) {
3200                         rc = -ERESTARTSYS;
3201                         break;
3202                 }
3203
3204                 /* get current irq counts */
3205                 spin_lock_irqsave(&info->lock,flags);
3206                 cnow = info->icount;
3207                 newsigs = info->input_signal_events;
3208                 set_current_state(TASK_INTERRUPTIBLE);
3209                 spin_unlock_irqrestore(&info->lock,flags);
3210
3211                 /* if no change, wait aborted for some reason */
3212                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3213                     newsigs.dsr_down == oldsigs.dsr_down &&
3214                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3215                     newsigs.dcd_down == oldsigs.dcd_down &&
3216                     newsigs.cts_up   == oldsigs.cts_up   &&
3217                     newsigs.cts_down == oldsigs.cts_down &&
3218                     newsigs.ri_up    == oldsigs.ri_up    &&
3219                     newsigs.ri_down  == oldsigs.ri_down  &&
3220                     cnow.exithunt    == cprev.exithunt   &&
3221                     cnow.rxidle      == cprev.rxidle) {
3222                         rc = -EIO;
3223                         break;
3224                 }
3225
3226                 events = mask &
3227                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3228                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3229                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3230                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3231                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3232                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3233                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3234                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3235                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3236                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3237                 if (events)
3238                         break;
3239
3240                 cprev = cnow;
3241                 oldsigs = newsigs;
3242         }
3243
3244         remove_wait_queue(&info->event_wait_q, &wait);
3245         set_current_state(TASK_RUNNING);
3246
3247
3248         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3249                 spin_lock_irqsave(&info->lock,flags);
3250                 if (!waitqueue_active(&info->event_wait_q)) {
3251                         /* disable enable exit hunt mode/idle rcvd IRQs */
3252                         info->ie1_value &= ~(FLGD|IDLD);
3253                         write_reg(info, IE1, info->ie1_value);
3254                 }
3255                 spin_unlock_irqrestore(&info->lock,flags);
3256         }
3257 exit:
3258         if ( rc == 0 )
3259                 PUT_USER(rc, events, mask_ptr);
3260
3261         return rc;
3262 }
3263
3264 static int modem_input_wait(SLMP_INFO *info,int arg)
3265 {
3266         unsigned long flags;
3267         int rc;
3268         struct mgsl_icount cprev, cnow;
3269         DECLARE_WAITQUEUE(wait, current);
3270
3271         /* save current irq counts */
3272         spin_lock_irqsave(&info->lock,flags);
3273         cprev = info->icount;
3274         add_wait_queue(&info->status_event_wait_q, &wait);
3275         set_current_state(TASK_INTERRUPTIBLE);
3276         spin_unlock_irqrestore(&info->lock,flags);
3277
3278         for(;;) {
3279                 schedule();
3280                 if (signal_pending(current)) {
3281                         rc = -ERESTARTSYS;
3282                         break;
3283                 }
3284
3285                 /* get new irq counts */
3286                 spin_lock_irqsave(&info->lock,flags);
3287                 cnow = info->icount;
3288                 set_current_state(TASK_INTERRUPTIBLE);
3289                 spin_unlock_irqrestore(&info->lock,flags);
3290
3291                 /* if no change, wait aborted for some reason */
3292                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3293                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3294                         rc = -EIO;
3295                         break;
3296                 }
3297
3298                 /* check for change in caller specified modem input */
3299                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3300                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3301                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3302                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3303                         rc = 0;
3304                         break;
3305                 }
3306
3307                 cprev = cnow;
3308         }
3309         remove_wait_queue(&info->status_event_wait_q, &wait);
3310         set_current_state(TASK_RUNNING);
3311         return rc;
3312 }
3313
3314 /* return the state of the serial control and status signals
3315  */
3316 static int tiocmget(struct tty_struct *tty, struct file *file)
3317 {
3318         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3319         unsigned int result;
3320         unsigned long flags;
3321
3322         spin_lock_irqsave(&info->lock,flags);
3323         get_signals(info);
3324         spin_unlock_irqrestore(&info->lock,flags);
3325
3326         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3327                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3328                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3329                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3330                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3331                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3332
3333         if (debug_level >= DEBUG_LEVEL_INFO)
3334                 printk("%s(%d):%s tiocmget() value=%08X\n",
3335                          __FILE__,__LINE__, info->device_name, result );
3336         return result;
3337 }
3338
3339 /* set modem control signals (DTR/RTS)
3340  */
3341 static int tiocmset(struct tty_struct *tty, struct file *file,
3342                     unsigned int set, unsigned int clear)
3343 {
3344         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3345         unsigned long flags;
3346
3347         if (debug_level >= DEBUG_LEVEL_INFO)
3348                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3349                         __FILE__,__LINE__,info->device_name, set, clear);
3350
3351         if (set & TIOCM_RTS)
3352                 info->serial_signals |= SerialSignal_RTS;
3353         if (set & TIOCM_DTR)
3354                 info->serial_signals |= SerialSignal_DTR;
3355         if (clear & TIOCM_RTS)
3356                 info->serial_signals &= ~SerialSignal_RTS;
3357         if (clear & TIOCM_DTR)
3358                 info->serial_signals &= ~SerialSignal_DTR;
3359
3360         spin_lock_irqsave(&info->lock,flags);
3361         set_signals(info);
3362         spin_unlock_irqrestore(&info->lock,flags);
3363
3364         return 0;
3365 }
3366
3367
3368
3369 /* Block the current process until the specified port is ready to open.
3370  */
3371 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3372                            SLMP_INFO *info)
3373 {
3374         DECLARE_WAITQUEUE(wait, current);
3375         int             retval;
3376         int             do_clocal = 0, extra_count = 0;
3377         unsigned long   flags;
3378
3379         if (debug_level >= DEBUG_LEVEL_INFO)
3380                 printk("%s(%d):%s block_til_ready()\n",
3381                          __FILE__,__LINE__, tty->driver->name );
3382
3383         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3384                 /* nonblock mode is set or port is not enabled */
3385                 /* just verify that callout device is not active */
3386                 info->flags |= ASYNC_NORMAL_ACTIVE;
3387                 return 0;
3388         }
3389
3390         if (tty->termios->c_cflag & CLOCAL)
3391                 do_clocal = 1;
3392
3393         /* Wait for carrier detect and the line to become
3394          * free (i.e., not in use by the callout).  While we are in
3395          * this loop, info->count is dropped by one, so that
3396          * close() knows when to free things.  We restore it upon
3397          * exit, either normal or abnormal.
3398          */
3399
3400         retval = 0;
3401         add_wait_queue(&info->open_wait, &wait);
3402
3403         if (debug_level >= DEBUG_LEVEL_INFO)
3404                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3405                          __FILE__,__LINE__, tty->driver->name, info->count );
3406
3407         spin_lock_irqsave(&info->lock, flags);
3408         if (!tty_hung_up_p(filp)) {
3409                 extra_count = 1;
3410                 info->count--;
3411         }
3412         spin_unlock_irqrestore(&info->lock, flags);
3413         info->blocked_open++;
3414
3415         while (1) {
3416                 if ((tty->termios->c_cflag & CBAUD)) {
3417                         spin_lock_irqsave(&info->lock,flags);
3418                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3419                         set_signals(info);
3420                         spin_unlock_irqrestore(&info->lock,flags);
3421                 }
3422
3423                 set_current_state(TASK_INTERRUPTIBLE);
3424
3425                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3426                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3427                                         -EAGAIN : -ERESTARTSYS;
3428                         break;
3429                 }
3430
3431                 spin_lock_irqsave(&info->lock,flags);
3432                 get_signals(info);
3433                 spin_unlock_irqrestore(&info->lock,flags);
3434
3435                 if (!(info->flags & ASYNC_CLOSING) &&
3436                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3437                         break;
3438                 }
3439
3440                 if (signal_pending(current)) {
3441                         retval = -ERESTARTSYS;
3442                         break;
3443                 }
3444
3445                 if (debug_level >= DEBUG_LEVEL_INFO)
3446                         printk("%s(%d):%s block_til_ready() count=%d\n",
3447                                  __FILE__,__LINE__, tty->driver->name, info->count );
3448
3449                 schedule();
3450         }
3451
3452         set_current_state(TASK_RUNNING);
3453         remove_wait_queue(&info->open_wait, &wait);
3454
3455         if (extra_count)
3456                 info->count++;
3457         info->blocked_open--;
3458
3459         if (debug_level >= DEBUG_LEVEL_INFO)
3460                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3461                          __FILE__,__LINE__, tty->driver->name, info->count );
3462
3463         if (!retval)
3464                 info->flags |= ASYNC_NORMAL_ACTIVE;
3465
3466         return retval;
3467 }
3468
3469 int alloc_dma_bufs(SLMP_INFO *info)
3470 {
3471         unsigned short BuffersPerFrame;
3472         unsigned short BufferCount;
3473
3474         // Force allocation to start at 64K boundary for each port.
3475         // This is necessary because *all* buffer descriptors for a port
3476         // *must* be in the same 64K block. All descriptors on a port
3477         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3478         // into the CBP register.
3479         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3480
3481         /* Calculate the number of DMA buffers necessary to hold the */
3482         /* largest allowable frame size. Note: If the max frame size is */
3483         /* not an even multiple of the DMA buffer size then we need to */
3484         /* round the buffer count per frame up one. */
3485
3486         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3487         if ( info->max_frame_size % SCABUFSIZE )
3488                 BuffersPerFrame++;
3489
3490         /* calculate total number of data buffers (SCABUFSIZE) possible
3491          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3492          * for the descriptor list (BUFFERLISTSIZE).
3493          */
3494         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3495
3496         /* limit number of buffers to maximum amount of descriptors */
3497         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3498                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3499
3500         /* use enough buffers to transmit one max size frame */
3501         info->tx_buf_count = BuffersPerFrame + 1;
3502
3503         /* never use more than half the available buffers for transmit */
3504         if (info->tx_buf_count > (BufferCount/2))
3505                 info->tx_buf_count = BufferCount/2;
3506
3507         if (info->tx_buf_count > SCAMAXDESC)
3508                 info->tx_buf_count = SCAMAXDESC;
3509
3510         /* use remaining buffers for receive */
3511         info->rx_buf_count = BufferCount - info->tx_buf_count;
3512
3513         if (info->rx_buf_count > SCAMAXDESC)
3514                 info->rx_buf_count = SCAMAXDESC;
3515
3516         if ( debug_level >= DEBUG_LEVEL_INFO )
3517                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3518                         __FILE__,__LINE__, info->device_name,
3519                         info->tx_buf_count,info->rx_buf_count);
3520
3521         if ( alloc_buf_list( info ) < 0 ||
3522                 alloc_frame_bufs(info,
3523                                         info->rx_buf_list,
3524                                         info->rx_buf_list_ex,
3525                                         info->rx_buf_count) < 0 ||
3526                 alloc_frame_bufs(info,
3527                                         info->tx_buf_list,
3528                                         info->tx_buf_list_ex,
3529                                         info->tx_buf_count) < 0 ||
3530                 alloc_tmp_rx_buf(info) < 0 ) {
3531                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3532                         __FILE__,__LINE__, info->device_name);
3533                 return -ENOMEM;
3534         }
3535
3536         rx_reset_buffers( info );
3537
3538         return 0;
3539 }
3540
3541 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3542  */
3543 int alloc_buf_list(SLMP_INFO *info)
3544 {
3545         unsigned int i;
3546
3547         /* build list in adapter shared memory */
3548         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3549         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3550         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3551
3552         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3553
3554         /* Save virtual address pointers to the receive and */
3555         /* transmit buffer lists. (Receive 1st). These pointers will */
3556         /* be used by the processor to access the lists. */
3557         info->rx_buf_list = (SCADESC *)info->buffer_list;
3558
3559         info->tx_buf_list = (SCADESC *)info->buffer_list;
3560         info->tx_buf_list += info->rx_buf_count;
3561
3562         /* Build links for circular buffer entry lists (tx and rx)
3563          *
3564          * Note: links are physical addresses read by the SCA device
3565          * to determine the next buffer entry to use.
3566          */
3567
3568         for ( i = 0; i < info->rx_buf_count; i++ ) {
3569                 /* calculate and store physical address of this buffer entry */
3570                 info->rx_buf_list_ex[i].phys_entry =
3571                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3572
3573                 /* calculate and store physical address of */
3574                 /* next entry in cirular list of entries */
3575                 info->rx_buf_list[i].next = info->buffer_list_phys;
3576                 if ( i < info->rx_buf_count - 1 )
3577                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3578
3579                 info->rx_buf_list[i].length = SCABUFSIZE;
3580         }
3581
3582         for ( i = 0; i < info->tx_buf_count; i++ ) {
3583                 /* calculate and store physical address of this buffer entry */
3584                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3585                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3586
3587                 /* calculate and store physical address of */
3588                 /* next entry in cirular list of entries */
3589
3590                 info->tx_buf_list[i].next = info->buffer_list_phys +
3591                         info->rx_buf_count * sizeof(SCADESC);
3592
3593                 if ( i < info->tx_buf_count - 1 )
3594                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3595         }
3596
3597         return 0;
3598 }
3599
3600 /* Allocate the frame DMA buffers used by the specified buffer list.
3601  */
3602 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3603 {
3604         int i;
3605         unsigned long phys_addr;
3606
3607         for ( i = 0; i < count; i++ ) {
3608                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3609                 phys_addr = info->port_array[0]->last_mem_alloc;
3610                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3611
3612                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3613                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3614         }
3615
3616         return 0;
3617 }
3618
3619 void free_dma_bufs(SLMP_INFO *info)
3620 {
3621         info->buffer_list = NULL;
3622         info->rx_buf_list = NULL;
3623         info->tx_buf_list = NULL;
3624 }
3625
3626 /* allocate buffer large enough to hold max_frame_size.
3627  * This buffer is used to pass an assembled frame to the line discipline.
3628  */
3629 int alloc_tmp_rx_buf(SLMP_INFO *info)
3630 {
3631         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3632         if (info->tmp_rx_buf == NULL)
3633                 return -ENOMEM;
3634         return 0;
3635 }
3636
3637 void free_tmp_rx_buf(SLMP_INFO *info)
3638 {
3639         if (info->tmp_rx_buf)
3640                 kfree(info->tmp_rx_buf);
3641         info->tmp_rx_buf = NULL;
3642 }
3643
3644 int claim_resources(SLMP_INFO *info)
3645 {
3646         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3647                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3648                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3649                 info->init_error = DiagStatus_AddressConflict;
3650                 goto errout;
3651         }
3652         else
3653                 info->shared_mem_requested = 1;
3654
3655         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3656                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3657                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3658                 info->init_error = DiagStatus_AddressConflict;
3659                 goto errout;
3660         }
3661         else
3662                 info->lcr_mem_requested = 1;
3663
3664         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3665                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3666                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3667                 info->init_error = DiagStatus_AddressConflict;
3668                 goto errout;
3669         }
3670         else
3671                 info->sca_base_requested = 1;
3672
3673         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3674                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3675                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3676                 info->init_error = DiagStatus_AddressConflict;
3677                 goto errout;
3678         }
3679         else
3680                 info->sca_statctrl_requested = 1;
3681
3682         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3683         if (!info->memory_base) {
3684                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3685                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3686                 info->init_error = DiagStatus_CantAssignPciResources;
3687                 goto errout;
3688         }
3689
3690         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3691         if (!info->lcr_base) {
3692                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3693                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3694                 info->init_error = DiagStatus_CantAssignPciResources;
3695                 goto errout;
3696         }
3697         info->lcr_base += info->lcr_offset;
3698
3699         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3700         if (!info->sca_base) {
3701                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3702                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3703                 info->init_error = DiagStatus_CantAssignPciResources;
3704                 goto errout;
3705         }
3706         info->sca_base += info->sca_offset;
3707
3708         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3709         if (!info->statctrl_base) {
3710                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3711                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3712                 info->init_error = DiagStatus_CantAssignPciResources;
3713                 goto errout;
3714         }
3715         info->statctrl_base += info->statctrl_offset;
3716
3717         if ( !memory_test(info) ) {
3718                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3719                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3720                 info->init_error = DiagStatus_MemoryError;
3721                 goto errout;
3722         }
3723
3724         return 0;
3725
3726 errout:
3727         release_resources( info );
3728         return -ENODEV;
3729 }
3730
3731 void release_resources(SLMP_INFO *info)
3732 {
3733         if ( debug_level >= DEBUG_LEVEL_INFO )
3734                 printk( "%s(%d):%s release_resources() entry\n",
3735                         __FILE__,__LINE__,info->device_name );
3736
3737         if ( info->irq_requested ) {
3738                 free_irq(info->irq_level, info);
3739                 info->irq_requested = 0;
3740         }
3741
3742         if ( info->shared_mem_requested ) {
3743                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3744                 info->shared_mem_requested = 0;
3745         }
3746         if ( info->lcr_mem_requested ) {
3747                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3748                 info->lcr_mem_requested = 0;
3749         }
3750         if ( info->sca_base_requested ) {
3751                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3752                 info->sca_base_requested = 0;
3753         }
3754         if ( info->sca_statctrl_requested ) {
3755                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3756                 info->sca_statctrl_requested = 0;
3757         }
3758
3759         if (info->memory_base){
3760                 iounmap(info->memory_base);
3761                 info->memory_base = NULL;
3762         }
3763
3764         if (info->sca_base) {
3765                 iounmap(info->sca_base - info->sca_offset);
3766                 info->sca_base=NULL;
3767         }
3768
3769         if (info->statctrl_base) {
3770                 iounmap(info->statctrl_base - info->statctrl_offset);
3771                 info->statctrl_base=NULL;
3772         }
3773
3774         if (info->lcr_base){
3775                 iounmap(info->lcr_base - info->lcr_offset);
3776                 info->lcr_base = NULL;
3777         }
3778
3779         if ( debug_level >= DEBUG_LEVEL_INFO )
3780                 printk( "%s(%d):%s release_resources() exit\n",
3781                         __FILE__,__LINE__,info->device_name );
3782 }
3783
3784 /* Add the specified device instance data structure to the
3785  * global linked list of devices and increment the device count.
3786  */
3787 void add_device(SLMP_INFO *info)
3788 {
3789         info->next_device = NULL;
3790         info->line = synclinkmp_device_count;
3791         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3792
3793         if (info->line < MAX_DEVICES) {
3794                 if (maxframe[info->line])
3795                         info->max_frame_size = maxframe[info->line];
3796                 info->dosyncppp = dosyncppp[info->line];
3797         }
3798
3799         synclinkmp_device_count++;
3800
3801         if ( !synclinkmp_device_list )
3802                 synclinkmp_device_list = info;
3803         else {
3804                 SLMP_INFO *current_dev = synclinkmp_device_list;
3805                 while( current_dev->next_device )
3806                         current_dev = current_dev->next_device;
3807                 current_dev->next_device = info;
3808         }
3809
3810         if ( info->max_frame_size < 4096 )
3811                 info->max_frame_size = 4096;
3812         else if ( info->max_frame_size > 65535 )
3813                 info->max_frame_size = 65535;
3814
3815         printk( "SyncLink MultiPort %s: "
3816                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3817                 info->device_name,
3818                 info->phys_sca_base,
3819                 info->phys_memory_base,
3820                 info->phys_statctrl_base,
3821                 info->phys_lcr_base,
3822                 info->irq_level,
3823                 info->max_frame_size );
3824
3825 #ifdef CONFIG_HDLC
3826         hdlcdev_init(info);
3827 #endif
3828 }
3829
3830 /* Allocate and initialize a device instance structure
3831  *
3832  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3833  */
3834 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3835 {
3836         SLMP_INFO *info;
3837
3838         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3839                  GFP_KERNEL);
3840
3841         if (!info) {
3842                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3843                         __FILE__,__LINE__, adapter_num, port_num);
3844         } else {
3845                 memset(info, 0, sizeof(SLMP_INFO));
3846                 info->magic = MGSL_MAGIC;
3847                 INIT_WORK(&info->task, bh_handler, info);
3848                 info->max_frame_size = 4096;
3849                 info->close_delay = 5*HZ/10;
3850                 info->closing_wait = 30*HZ;
3851                 init_waitqueue_head(&info->open_wait);
3852                 init_waitqueue_head(&info->close_wait);
3853                 init_waitqueue_head(&info->status_event_wait_q);
3854                 init_waitqueue_head(&info->event_wait_q);
3855                 spin_lock_init(&info->netlock);
3856                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3857                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3858                 info->adapter_num = adapter_num;
3859                 info->port_num = port_num;
3860
3861                 /* Copy configuration info to device instance data */
3862                 info->irq_level = pdev->irq;
3863                 info->phys_lcr_base = pci_resource_start(pdev,0);
3864                 info->phys_sca_base = pci_resource_start(pdev,2);
3865                 info->phys_memory_base = pci_resource_start(pdev,3);
3866                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3867
3868                 /* Because veremap only works on page boundaries we must map
3869                  * a larger area than is actually implemented for the LCR
3870                  * memory range. We map a full page starting at the page boundary.
3871                  */
3872                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3873                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3874
3875                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3876                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3877
3878                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3879                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3880
3881                 info->bus_type = MGSL_BUS_TYPE_PCI;
3882                 info->irq_flags = SA_SHIRQ;
3883
3884                 init_timer(&info->tx_timer);
3885                 info->tx_timer.data = (unsigned long)info;
3886                 info->tx_timer.function = tx_timeout;
3887
3888                 init_timer(&info->status_timer);
3889                 info->status_timer.data = (unsigned long)info;
3890                 info->status_timer.function = status_timeout;
3891
3892                 /* Store the PCI9050 misc control register value because a flaw
3893                  * in the PCI9050 prevents LCR registers from being read if
3894                  * BIOS assigns an LCR base address with bit 7 set.
3895                  *
3896                  * Only the misc control register is accessed for which only
3897                  * write access is needed, so set an initial value and change
3898                  * bits to the device instance data as we write the value
3899                  * to the actual misc control register.
3900                  */
3901                 info->misc_ctrl_value = 0x087e4546;
3902
3903                 /* initial port state is unknown - if startup errors
3904                  * occur, init_error will be set to indicate the
3905                  * problem. Once the port is fully initialized,
3906                  * this value will be set to 0 to indicate the
3907                  * port is available.
3908                  */
3909                 info->init_error = -1;
3910         }
3911
3912         return info;
3913 }
3914
3915 void device_init(int adapter_num, struct pci_dev *pdev)
3916 {
3917         SLMP_INFO *port_array[SCA_MAX_PORTS];
3918         int port;
3919
3920         /* allocate device instances for up to SCA_MAX_PORTS devices */
3921         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3922                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3923                 if( port_array[port] == NULL ) {
3924                         for ( --port; port >= 0; --port )
3925                                 kfree(port_array[port]);
3926                         return;
3927                 }
3928         }
3929
3930         /* give copy of port_array to all ports and add to device list  */
3931         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3932                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3933                 add_device( port_array[port] );
3934                 spin_lock_init(&port_array[port]->lock);
3935         }
3936
3937         /* Allocate and claim adapter resources */
3938         if ( !claim_resources(port_array[0]) ) {
3939
3940                 alloc_dma_bufs(port_array[0]);
3941
3942                 /* copy resource information from first port to others */
3943                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3944                         port_array[port]->lock  = port_array[0]->lock;
3945                         port_array[port]->irq_level     = port_array[0]->irq_level;
3946                         port_array[port]->memory_base   = port_array[0]->memory_base;
3947                         port_array[port]->sca_base      = port_array[0]->sca_base;
3948                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3949                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3950                         alloc_dma_bufs(port_array[port]);
3951                 }
3952
3953                 if ( request_irq(port_array[0]->irq_level,
3954                                         synclinkmp_interrupt,
3955                                         port_array[0]->irq_flags,
3956                                         port_array[0]->device_name,
3957                                         port_array[0]) < 0 ) {
3958                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3959                                 __FILE__,__LINE__,
3960                                 port_array[0]->device_name,
3961                                 port_array[0]->irq_level );
3962                 }
3963                 else {
3964                         port_array[0]->irq_requested = 1;
3965                         adapter_test(port_array[0]);
3966                 }
3967         }
3968 }
3969
3970 static struct tty_operations ops = {
3971         .open = open,
3972         .close = close,
3973         .write = write,
3974         .put_char = put_char,
3975         .flush_chars = flush_chars,
3976         .write_room = write_room,
3977         .chars_in_buffer = chars_in_buffer,
3978         .flush_buffer = flush_buffer,
3979         .ioctl = ioctl,
3980         .throttle = throttle,
3981         .unthrottle = unthrottle,
3982         .send_xchar = send_xchar,
3983         .break_ctl = set_break,
3984         .wait_until_sent = wait_until_sent,
3985         .read_proc = read_proc,
3986         .set_termios = set_termios,
3987         .stop = tx_hold,
3988         .start = tx_release,
3989         .hangup = hangup,
3990         .tiocmget = tiocmget,
3991         .tiocmset = tiocmset,
3992 };
3993
3994 static void synclinkmp_cleanup(void)
3995 {
3996         int rc;
3997         SLMP_INFO *info;
3998         SLMP_INFO *tmp;
3999
4000         printk("Unloading %s %s\n", driver_name, driver_version);
4001
4002         if (serial_driver) {
4003                 if ((rc = tty_unregister_driver(serial_driver)))
4004                         printk("%s(%d) failed to unregister tty driver err=%d\n",
4005                                __FILE__,__LINE__,rc);
4006                 put_tty_driver(serial_driver);
4007         }
4008
4009         /* reset devices */
4010         info = synclinkmp_device_list;
4011         while(info) {
4012                 reset_port(info);
4013                 info = info->next_device;
4014         }
4015
4016         /* release devices */
4017         info = synclinkmp_device_list;
4018         while(info) {
4019 #ifdef CONFIG_HDLC
4020                 hdlcdev_exit(info);
4021 #endif
4022                 free_dma_bufs(info);
4023                 free_tmp_rx_buf(info);
4024                 if ( info->port_num == 0 ) {
4025                         if (info->sca_base)
4026                                 write_reg(info, LPR, 1); /* set low power mode */
4027                         release_resources(info);
4028                 }
4029                 tmp = info;
4030                 info = info->next_device;
4031                 kfree(tmp);
4032         }
4033
4034         pci_unregister_driver(&synclinkmp_pci_driver);
4035 }
4036
4037 /* Driver initialization entry point.
4038  */
4039
4040 static int __init synclinkmp_init(void)
4041 {
4042         int rc;
4043
4044         if (break_on_load) {
4045                 synclinkmp_get_text_ptr();
4046                 BREAKPOINT();
4047         }
4048
4049         printk("%s %s\n", driver_name, driver_version);
4050
4051         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4052                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4053                 return rc;
4054         }
4055
4056         serial_driver = alloc_tty_driver(128);
4057         if (!serial_driver) {
4058                 rc = -ENOMEM;
4059                 goto error;
4060         }
4061
4062         /* Initialize the tty_driver structure */
4063
4064         serial_driver->owner = THIS_MODULE;
4065         serial_driver->driver_name = "synclinkmp";
4066         serial_driver->name = "ttySLM";
4067         serial_driver->major = ttymajor;
4068         serial_driver->minor_start = 64;
4069         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4070         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4071         serial_driver->init_termios = tty_std_termios;
4072         serial_driver->init_termios.c_cflag =
4073                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4074         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4075         tty_set_operations(serial_driver, &ops);
4076         if ((rc = tty_register_driver(serial_driver)) < 0) {
4077                 printk("%s(%d):Couldn't register serial driver\n",
4078                         __FILE__,__LINE__);
4079                 put_tty_driver(serial_driver);
4080                 serial_driver = NULL;
4081                 goto error;
4082         }
4083
4084         printk("%s %s, tty major#%d\n",
4085                 driver_name, driver_version,
4086                 serial_driver->major);
4087
4088         return 0;
4089
4090 error:
4091         synclinkmp_cleanup();
4092         return rc;
4093 }
4094
4095 static void __exit synclinkmp_exit(void)
4096 {
4097         synclinkmp_cleanup();
4098 }
4099
4100 module_init(synclinkmp_init);
4101 module_exit(synclinkmp_exit);
4102
4103 /* Set the port for internal loopback mode.
4104  * The TxCLK and RxCLK signals are generated from the BRG and
4105  * the TxD is looped back to the RxD internally.
4106  */
4107 void enable_loopback(SLMP_INFO *info, int enable)
4108 {
4109         if (enable) {
4110                 /* MD2 (Mode Register 2)
4111                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4112                  */
4113                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4114
4115                 /* degate external TxC clock source */
4116                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4117                 write_control_reg(info);
4118
4119                 /* RXS/TXS (Rx/Tx clock source)
4120                  * 07      Reserved, must be 0
4121                  * 06..04  Clock Source, 100=BRG
4122                  * 03..00  Clock Divisor, 0000=1
4123                  */
4124                 write_reg(info, RXS, 0x40);
4125                 write_reg(info, TXS, 0x40);
4126
4127         } else {
4128                 /* MD2 (Mode Register 2)
4129                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4130                  */
4131                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4132
4133                 /* RXS/TXS (Rx/Tx clock source)
4134                  * 07      Reserved, must be 0
4135                  * 06..04  Clock Source, 000=RxC/TxC Pin
4136                  * 03..00  Clock Divisor, 0000=1
4137                  */
4138                 write_reg(info, RXS, 0x00);
4139                 write_reg(info, TXS, 0x00);
4140         }
4141
4142         /* set LinkSpeed if available, otherwise default to 2Mbps */
4143         if (info->params.clock_speed)
4144                 set_rate(info, info->params.clock_speed);
4145         else
4146                 set_rate(info, 3686400);
4147 }
4148
4149 /* Set the baud rate register to the desired speed
4150  *
4151  *      data_rate       data rate of clock in bits per second
4152  *                      A data rate of 0 disables the AUX clock.
4153  */
4154 void set_rate( SLMP_INFO *info, u32 data_rate )
4155 {
4156         u32 TMCValue;
4157         unsigned char BRValue;
4158         u32 Divisor=0;
4159
4160         /* fBRG = fCLK/(TMC * 2^BR)
4161          */
4162         if (data_rate != 0) {
4163                 Divisor = 14745600/data_rate;
4164                 if (!Divisor)
4165                         Divisor = 1;
4166
4167                 TMCValue = Divisor;
4168
4169                 BRValue = 0;
4170                 if (TMCValue != 1 && TMCValue != 2) {
4171                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4172                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4173                          * 50/50 duty cycle.
4174                          */
4175                         BRValue = 1;
4176                         TMCValue >>= 1;
4177                 }
4178
4179                 /* while TMCValue is too big for TMC register, divide
4180                  * by 2 and increment BR exponent.
4181                  */
4182                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4183                         TMCValue >>= 1;
4184
4185                 write_reg(info, TXS,
4186                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4187                 write_reg(info, RXS,
4188                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4189                 write_reg(info, TMC, (unsigned char)TMCValue);
4190         }
4191         else {
4192                 write_reg(info, TXS,0);
4193                 write_reg(info, RXS,0);
4194                 write_reg(info, TMC, 0);
4195         }
4196 }
4197
4198 /* Disable receiver
4199  */
4200 void rx_stop(SLMP_INFO *info)
4201 {
4202         if (debug_level >= DEBUG_LEVEL_ISR)
4203                 printk("%s(%d):%s rx_stop()\n",
4204                          __FILE__,__LINE__, info->device_name );
4205
4206         write_reg(info, CMD, RXRESET);
4207
4208         info->ie0_value &= ~RXRDYE;
4209         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4210
4211         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4212         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4213         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4214
4215         info->rx_enabled = 0;
4216         info->rx_overflow = 0;
4217 }
4218
4219 /* enable the receiver
4220  */
4221 void rx_start(SLMP_INFO *info)
4222 {
4223         int i;
4224
4225         if (debug_level >= DEBUG_LEVEL_ISR)
4226                 printk("%s(%d):%s rx_start()\n",
4227                          __FILE__,__LINE__, info->device_name );
4228
4229         write_reg(info, CMD, RXRESET);
4230
4231         if ( info->params.mode == MGSL_MODE_HDLC ) {
4232                 /* HDLC, disabe IRQ on rxdata */
4233                 info->ie0_value &= ~RXRDYE;
4234                 write_reg(info, IE0, info->ie0_value);
4235
4236                 /* Reset all Rx DMA buffers and program rx dma */
4237                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4238                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4239
4240                 for (i = 0; i < info->rx_buf_count; i++) {
4241                         info->rx_buf_list[i].status = 0xff;
4242
4243                         // throttle to 4 shared memory writes at a time to prevent
4244                         // hogging local bus (keep latency time for DMA requests low).
4245                         if (!(i % 4))
4246                                 read_status_reg(info);
4247                 }
4248                 info->current_rx_buf = 0;
4249
4250                 /* set current/1st descriptor address */
4251                 write_reg16(info, RXDMA + CDA,
4252                         info->rx_buf_list_ex[0].phys_entry);
4253
4254                 /* set new last rx descriptor address */
4255                 write_reg16(info, RXDMA + EDA,
4256                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4257
4258                 /* set buffer length (shared by all rx dma data buffers) */
4259                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4260
4261                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4262                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4263         } else {
4264                 /* async, enable IRQ on rxdata */
4265                 info->ie0_value |= RXRDYE;
4266                 write_reg(info, IE0, info->ie0_value);
4267         }
4268
4269         write_reg(info, CMD, RXENABLE);
4270
4271         info->rx_overflow = FALSE;
4272         info->rx_enabled = 1;
4273 }
4274
4275 /* Enable the transmitter and send a transmit frame if
4276  * one is loaded in the DMA buffers.
4277  */
4278 void tx_start(SLMP_INFO *info)
4279 {
4280         if (debug_level >= DEBUG_LEVEL_ISR)
4281                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4282                          __FILE__,__LINE__, info->device_name,info->tx_count );
4283
4284         if (!info->tx_enabled ) {
4285                 write_reg(info, CMD, TXRESET);
4286                 write_reg(info, CMD, TXENABLE);
4287                 info->tx_enabled = TRUE;
4288         }
4289
4290         if ( info->tx_count ) {
4291
4292                 /* If auto RTS enabled and RTS is inactive, then assert */
4293                 /* RTS and set a flag indicating that the driver should */
4294                 /* negate RTS when the transmission completes. */
4295
4296                 info->drop_rts_on_tx_done = 0;
4297
4298                 if (info->params.mode != MGSL_MODE_ASYNC) {
4299
4300                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4301                                 get_signals( info );
4302                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4303                                         info->serial_signals |= SerialSignal_RTS;
4304                                         set_signals( info );
4305                                         info->drop_rts_on_tx_done = 1;
4306                                 }
4307                         }
4308
4309                         write_reg16(info, TRC0,
4310                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4311
4312                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4313                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4314
4315                         /* set TX CDA (current descriptor address) */
4316                         write_reg16(info, TXDMA + CDA,
4317                                 info->tx_buf_list_ex[0].phys_entry);
4318
4319                         /* set TX EDA (last descriptor address) */
4320                         write_reg16(info, TXDMA + EDA,
4321                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4322
4323                         /* enable underrun IRQ */
4324                         info->ie1_value &= ~IDLE;
4325                         info->ie1_value |= UDRN;
4326                         write_reg(info, IE1, info->ie1_value);
4327                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4328
4329                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4330                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4331
4332                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4333                         add_timer(&info->tx_timer);
4334                 }
4335                 else {
4336                         tx_load_fifo(info);
4337                         /* async, enable IRQ on txdata */
4338                         info->ie0_value |= TXRDYE;
4339                         write_reg(info, IE0, info->ie0_value);
4340                 }
4341
4342                 info->tx_active = 1;
4343         }
4344 }
4345
4346 /* stop the transmitter and DMA
4347  */
4348 void tx_stop( SLMP_INFO *info )
4349 {
4350         if (debug_level >= DEBUG_LEVEL_ISR)
4351                 printk("%s(%d):%s tx_stop()\n",
4352                          __FILE__,__LINE__, info->device_name );
4353
4354         del_timer(&info->tx_timer);
4355
4356         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4357         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4358
4359         write_reg(info, CMD, TXRESET);
4360
4361         info->ie1_value &= ~(UDRN + IDLE);
4362         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4363         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4364
4365         info->ie0_value &= ~TXRDYE;
4366         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4367
4368         info->tx_enabled = 0;
4369         info->tx_active  = 0;
4370 }
4371
4372 /* Fill the transmit FIFO until the FIFO is full or
4373  * there is no more data to load.
4374  */
4375 void tx_load_fifo(SLMP_INFO *info)
4376 {
4377         u8 TwoBytes[2];
4378
4379         /* do nothing is now tx data available and no XON/XOFF pending */
4380
4381         if ( !info->tx_count && !info->x_char )
4382                 return;
4383
4384         /* load the Transmit FIFO until FIFOs full or all data sent */
4385
4386         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4387
4388                 /* there is more space in the transmit FIFO and */
4389                 /* there is more data in transmit buffer */
4390
4391                 if ( (info->tx_count > 1) && !info->x_char ) {
4392                         /* write 16-bits */
4393                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4394                         if (info->tx_get >= info->max_frame_size)
4395                                 info->tx_get -= info->max_frame_size;
4396                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4397                         if (info->tx_get >= info->max_frame_size)
4398                                 info->tx_get -= info->max_frame_size;
4399
4400                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4401
4402                         info->tx_count -= 2;
4403                         info->icount.tx += 2;
4404                 } else {
4405                         /* only 1 byte left to transmit or 1 FIFO slot left */
4406
4407                         if (info->x_char) {
4408                                 /* transmit pending high priority char */
4409                                 write_reg(info, TRB, info->x_char);
4410                                 info->x_char = 0;
4411                         } else {
4412                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4413                                 if (info->tx_get >= info->max_frame_size)
4414                                         info->tx_get -= info->max_frame_size;
4415                                 info->tx_count--;
4416                         }
4417                         info->icount.tx++;
4418                 }
4419         }
4420 }
4421
4422 /* Reset a port to a known state
4423  */
4424 void reset_port(SLMP_INFO *info)
4425 {
4426         if (info->sca_base) {
4427
4428                 tx_stop(info);
4429                 rx_stop(info);
4430
4431                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4432                 set_signals(info);
4433
4434                 /* disable all port interrupts */
4435                 info->ie0_value = 0;
4436                 info->ie1_value = 0;
4437                 info->ie2_value = 0;
4438                 write_reg(info, IE0, info->ie0_value);
4439                 write_reg(info, IE1, info->ie1_value);
4440                 write_reg(info, IE2, info->ie2_value);
4441
4442                 write_reg(info, CMD, CHRESET);
4443         }
4444 }
4445
4446 /* Reset all the ports to a known state.
4447  */
4448 void reset_adapter(SLMP_INFO *info)
4449 {
4450         int i;
4451
4452         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4453                 if (info->port_array[i])
4454                         reset_port(info->port_array[i]);
4455         }
4456 }
4457
4458 /* Program port for asynchronous communications.
4459  */
4460 void async_mode(SLMP_INFO *info)
4461 {
4462
4463         unsigned char RegValue;
4464
4465         tx_stop(info);
4466         rx_stop(info);
4467
4468         /* MD0, Mode Register 0
4469          *
4470          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4471          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4472          * 03      Reserved, must be 0
4473          * 02      CRCCC, CRC Calculation, 0=disabled
4474          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4475          *
4476          * 0000 0000
4477          */
4478         RegValue = 0x00;
4479         if (info->params.stop_bits != 1)
4480                 RegValue |= BIT1;
4481         write_reg(info, MD0, RegValue);
4482
4483         /* MD1, Mode Register 1
4484          *
4485          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4486          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4487          * 03..02  RXCHR<1..0>, rx char size
4488          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4489          *
4490          * 0100 0000
4491          */
4492         RegValue = 0x40;
4493         switch (info->params.data_bits) {
4494         case 7: RegValue |= BIT4 + BIT2; break;
4495         case 6: RegValue |= BIT5 + BIT3; break;
4496         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4497         }
4498         if (info->params.parity != ASYNC_PARITY_NONE) {
4499                 RegValue |= BIT1;
4500                 if (info->params.parity == ASYNC_PARITY_ODD)
4501                         RegValue |= BIT0;
4502         }
4503         write_reg(info, MD1, RegValue);
4504
4505         /* MD2, Mode Register 2
4506          *
4507          * 07..02  Reserved, must be 0
4508          * 01..00  CNCT<1..0> Channel connection, 0=normal
4509          *
4510          * 0000 0000
4511          */
4512         RegValue = 0x00;
4513         write_reg(info, MD2, RegValue);
4514
4515         /* RXS, Receive clock source
4516          *
4517          * 07      Reserved, must be 0
4518          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4519          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4520          */
4521         RegValue=BIT6;
4522         write_reg(info, RXS, RegValue);
4523
4524         /* TXS, Transmit clock source
4525          *
4526          * 07      Reserved, must be 0
4527          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4528          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4529          */
4530         RegValue=BIT6;
4531         write_reg(info, TXS, RegValue);
4532
4533         /* Control Register
4534          *
4535          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4536          */
4537         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4538         write_control_reg(info);
4539
4540         tx_set_idle(info);
4541
4542         /* RRC Receive Ready Control 0
4543          *
4544          * 07..05  Reserved, must be 0
4545          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4546          */
4547         write_reg(info, TRC0, 0x00);
4548
4549         /* TRC0 Transmit Ready Control 0
4550          *
4551          * 07..05  Reserved, must be 0
4552          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4553          */
4554         write_reg(info, TRC0, 0x10);
4555
4556         /* TRC1 Transmit Ready Control 1
4557          *
4558          * 07..05  Reserved, must be 0
4559          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4560          */
4561         write_reg(info, TRC1, 0x1e);
4562
4563         /* CTL, MSCI control register
4564          *
4565          * 07..06  Reserved, set to 0
4566          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4567          * 04      IDLC, idle control, 0=mark 1=idle register
4568          * 03      BRK, break, 0=off 1 =on (async)
4569          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4570          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4571          * 00      RTS, RTS output control, 0=active 1=inactive
4572          *
4573          * 0001 0001
4574          */
4575         RegValue = 0x10;
4576         if (!(info->serial_signals & SerialSignal_RTS))
4577                 RegValue |= 0x01;
4578         write_reg(info, CTL, RegValue);
4579
4580         /* enable status interrupts */
4581         info->ie0_value |= TXINTE + RXINTE;
4582         write_reg(info, IE0, info->ie0_value);
4583
4584         /* enable break detect interrupt */
4585         info->ie1_value = BRKD;
4586         write_reg(info, IE1, info->ie1_value);
4587
4588         /* enable rx overrun interrupt */
4589         info->ie2_value = OVRN;
4590         write_reg(info, IE2, info->ie2_value);
4591
4592         set_rate( info, info->params.data_rate * 16 );
4593
4594         if (info->params.loopback)
4595                 enable_loopback(info,1);
4596 }
4597
4598 /* Program the SCA for HDLC communications.
4599  */
4600 void hdlc_mode(SLMP_INFO *info)
4601 {
4602         unsigned char RegValue;
4603         u32 DpllDivisor;
4604
4605         // Can't use DPLL because SCA outputs recovered clock on RxC when
4606         // DPLL mode selected. This causes output contention with RxC receiver.
4607         // Use of DPLL would require external hardware to disable RxC receiver
4608         // when DPLL mode selected.
4609         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4610
4611         /* disable DMA interrupts */
4612         write_reg(info, TXDMA + DIR, 0);
4613         write_reg(info, RXDMA + DIR, 0);
4614
4615         /* MD0, Mode Register 0
4616          *
4617          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4618          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4619          * 03      Reserved, must be 0
4620          * 02      CRCCC, CRC Calculation, 1=enabled
4621          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4622          * 00      CRC0, CRC initial value, 1 = all 1s
4623          *
4624          * 1000 0001
4625          */
4626         RegValue = 0x81;
4627         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4628                 RegValue |= BIT4;
4629         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4630                 RegValue |= BIT4;
4631         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4632                 RegValue |= BIT2 + BIT1;
4633         write_reg(info, MD0, RegValue);
4634
4635         /* MD1, Mode Register 1
4636          *
4637          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4638          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4639          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4640          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4641          *
4642          * 0000 0000
4643          */
4644         RegValue = 0x00;
4645         write_reg(info, MD1, RegValue);
4646
4647         /* MD2, Mode Register 2
4648          *
4649          * 07      NRZFM, 0=NRZ, 1=FM
4650          * 06..05  CODE<1..0> Encoding, 00=NRZ
4651          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4652          * 02      Reserved, must be 0
4653          * 01..00  CNCT<1..0> Channel connection, 0=normal
4654          *
4655          * 0000 0000
4656          */
4657         RegValue = 0x00;
4658         switch(info->params.encoding) {
4659         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4660         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4661         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4662         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4663 #if 0
4664         case HDLC_ENCODING_NRZB:                                        /* not supported */
4665         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4666         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4667 #endif
4668         }
4669         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4670                 DpllDivisor = 16;
4671                 RegValue |= BIT3;
4672         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4673                 DpllDivisor = 8;
4674         } else {
4675                 DpllDivisor = 32;
4676                 RegValue |= BIT4;
4677         }
4678         write_reg(info, MD2, RegValue);
4679
4680
4681         /* RXS, Receive clock source
4682          *
4683          * 07      Reserved, must be 0
4684          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4685          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4686          */
4687         RegValue=0;
4688         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4689                 RegValue |= BIT6;
4690         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4691                 RegValue |= BIT6 + BIT5;
4692         write_reg(info, RXS, RegValue);
4693
4694         /* TXS, Transmit clock source
4695          *
4696          * 07      Reserved, must be 0
4697          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4698          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4699          */
4700         RegValue=0;
4701         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4702                 RegValue |= BIT6;
4703         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4704                 RegValue |= BIT6 + BIT5;
4705         write_reg(info, TXS, RegValue);
4706
4707         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4708                 set_rate(info, info->params.clock_speed * DpllDivisor);
4709         else
4710                 set_rate(info, info->params.clock_speed);
4711
4712         /* GPDATA (General Purpose I/O Data Register)
4713          *
4714          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4715          */
4716         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4717                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4718         else
4719                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4720         write_control_reg(info);
4721
4722         /* RRC Receive Ready Control 0
4723          *
4724          * 07..05  Reserved, must be 0
4725          * 04..00  RRC<4..0> Rx FIFO trigger active
4726          */
4727         write_reg(info, RRC, rx_active_fifo_level);
4728
4729         /* TRC0 Transmit Ready Control 0
4730          *
4731          * 07..05  Reserved, must be 0
4732          * 04..00  TRC<4..0> Tx FIFO trigger active
4733          */
4734         write_reg(info, TRC0, tx_active_fifo_level);
4735
4736         /* TRC1 Transmit Ready Control 1
4737          *
4738          * 07..05  Reserved, must be 0
4739          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4740          */
4741         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4742
4743         /* DMR, DMA Mode Register
4744          *
4745          * 07..05  Reserved, must be 0
4746          * 04      TMOD, Transfer Mode: 1=chained-block
4747          * 03      Reserved, must be 0
4748          * 02      NF, Number of Frames: 1=multi-frame
4749          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4750          * 00      Reserved, must be 0
4751          *
4752          * 0001 0100
4753          */
4754         write_reg(info, TXDMA + DMR, 0x14);
4755         write_reg(info, RXDMA + DMR, 0x14);
4756
4757         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4758         write_reg(info, RXDMA + CPB,
4759                 (unsigned char)(info->buffer_list_phys >> 16));
4760
4761         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4762         write_reg(info, TXDMA + CPB,
4763                 (unsigned char)(info->buffer_list_phys >> 16));
4764
4765         /* enable status interrupts. other code enables/disables
4766          * the individual sources for these two interrupt classes.
4767          */
4768         info->ie0_value |= TXINTE + RXINTE;
4769         write_reg(info, IE0, info->ie0_value);
4770
4771         /* CTL, MSCI control register
4772          *
4773          * 07..06  Reserved, set to 0
4774          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4775          * 04      IDLC, idle control, 0=mark 1=idle register
4776          * 03      BRK, break, 0=off 1 =on (async)
4777          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4778          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4779          * 00      RTS, RTS output control, 0=active 1=inactive
4780          *
4781          * 0001 0001
4782          */
4783         RegValue = 0x10;
4784         if (!(info->serial_signals & SerialSignal_RTS))
4785                 RegValue |= 0x01;
4786         write_reg(info, CTL, RegValue);
4787
4788         /* preamble not supported ! */
4789
4790         tx_set_idle(info);
4791         tx_stop(info);
4792         rx_stop(info);
4793
4794         set_rate(info, info->params.clock_speed);
4795
4796         if (info->params.loopback)
4797                 enable_loopback(info,1);
4798 }
4799
4800 /* Set the transmit HDLC idle mode
4801  */
4802 void tx_set_idle(SLMP_INFO *info)
4803 {
4804         unsigned char RegValue = 0xff;
4805
4806         /* Map API idle mode to SCA register bits */
4807         switch(info->idle_mode) {
4808         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4809         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4810         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4811         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4812         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4813         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4814         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4815         }
4816
4817         write_reg(info, IDL, RegValue);
4818 }
4819
4820 /* Query the adapter for the state of the V24 status (input) signals.
4821  */
4822 void get_signals(SLMP_INFO *info)
4823 {
4824         u16 status = read_reg(info, SR3);
4825         u16 gpstatus = read_status_reg(info);
4826         u16 testbit;
4827
4828         /* clear all serial signals except DTR and RTS */
4829         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4830
4831         /* set serial signal bits to reflect MISR */
4832
4833         if (!(status & BIT3))
4834                 info->serial_signals |= SerialSignal_CTS;
4835
4836         if ( !(status & BIT2))
4837                 info->serial_signals |= SerialSignal_DCD;
4838
4839         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4840         if (!(gpstatus & testbit))
4841                 info->serial_signals |= SerialSignal_RI;
4842
4843         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4844         if (!(gpstatus & testbit))
4845                 info->serial_signals |= SerialSignal_DSR;
4846 }
4847
4848 /* Set the state of DTR and RTS based on contents of
4849  * serial_signals member of device context.
4850  */
4851 void set_signals(SLMP_INFO *info)
4852 {
4853         unsigned char RegValue;
4854         u16 EnableBit;
4855
4856         RegValue = read_reg(info, CTL);
4857         if (info->serial_signals & SerialSignal_RTS)
4858                 RegValue &= ~BIT0;
4859         else
4860                 RegValue |= BIT0;
4861         write_reg(info, CTL, RegValue);
4862
4863         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4864         EnableBit = BIT1 << (info->port_num*2);
4865         if (info->serial_signals & SerialSignal_DTR)
4866                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4867         else
4868                 info->port_array[0]->ctrlreg_value |= EnableBit;
4869         write_control_reg(info);
4870 }
4871
4872 /*******************/
4873 /* DMA Buffer Code */
4874 /*******************/
4875
4876 /* Set the count for all receive buffers to SCABUFSIZE
4877  * and set the current buffer to the first buffer. This effectively
4878  * makes all buffers free and discards any data in buffers.
4879  */
4880 void rx_reset_buffers(SLMP_INFO *info)
4881 {
4882         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4883 }
4884
4885 /* Free the buffers used by a received frame
4886  *
4887  * info   pointer to device instance data
4888  * first  index of 1st receive buffer of frame
4889  * last   index of last receive buffer of frame
4890  */
4891 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4892 {
4893         int done = 0;
4894
4895         while(!done) {
4896                 /* reset current buffer for reuse */
4897                 info->rx_buf_list[first].status = 0xff;
4898
4899                 if (first == last) {
4900                         done = 1;
4901                         /* set new last rx descriptor address */
4902                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4903                 }
4904
4905                 first++;
4906                 if (first == info->rx_buf_count)
4907                         first = 0;
4908         }
4909
4910         /* set current buffer to next buffer after last buffer of frame */
4911         info->current_rx_buf = first;
4912 }
4913
4914 /* Return a received frame from the receive DMA buffers.
4915  * Only frames received without errors are returned.
4916  *
4917  * Return Value:        1 if frame returned, otherwise 0
4918  */
4919 int rx_get_frame(SLMP_INFO *info)
4920 {
4921         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4922         unsigned short status;
4923         unsigned int framesize = 0;
4924         int ReturnCode = 0;
4925         unsigned long flags;
4926         struct tty_struct *tty = info->tty;
4927         unsigned char addr_field = 0xff;
4928         SCADESC *desc;
4929         SCADESC_EX *desc_ex;
4930
4931 CheckAgain:
4932         /* assume no frame returned, set zero length */
4933         framesize = 0;
4934         addr_field = 0xff;
4935
4936         /*
4937          * current_rx_buf points to the 1st buffer of the next available
4938          * receive frame. To find the last buffer of the frame look for
4939          * a non-zero status field in the buffer entries. (The status
4940          * field is set by the 16C32 after completing a receive frame.
4941          */
4942         StartIndex = EndIndex = info->current_rx_buf;
4943
4944         for ( ;; ) {
4945                 desc = &info->rx_buf_list[EndIndex];
4946                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4947
4948                 if (desc->status == 0xff)
4949                         goto Cleanup;   /* current desc still in use, no frames available */
4950
4951                 if (framesize == 0 && info->params.addr_filter != 0xff)
4952                         addr_field = desc_ex->virt_addr[0];
4953
4954                 framesize += desc->length;
4955
4956                 /* Status != 0 means last buffer of frame */
4957                 if (desc->status)
4958                         break;
4959
4960                 EndIndex++;
4961                 if (EndIndex == info->rx_buf_count)
4962                         EndIndex = 0;
4963
4964                 if (EndIndex == info->current_rx_buf) {
4965                         /* all buffers have been 'used' but none mark      */
4966                         /* the end of a frame. Reset buffers and receiver. */
4967                         if ( info->rx_enabled ){
4968                                 spin_lock_irqsave(&info->lock,flags);
4969                                 rx_start(info);
4970                                 spin_unlock_irqrestore(&info->lock,flags);
4971                         }
4972                         goto Cleanup;
4973                 }
4974
4975         }
4976
4977         /* check status of receive frame */
4978
4979         /* frame status is byte stored after frame data
4980          *
4981          * 7 EOM (end of msg), 1 = last buffer of frame
4982          * 6 Short Frame, 1 = short frame
4983          * 5 Abort, 1 = frame aborted
4984          * 4 Residue, 1 = last byte is partial
4985          * 3 Overrun, 1 = overrun occurred during frame reception
4986          * 2 CRC,     1 = CRC error detected
4987          *
4988          */
4989         status = desc->status;
4990
4991         /* ignore CRC bit if not using CRC (bit is undefined) */
4992         /* Note:CRC is not save to data buffer */
4993         if (info->params.crc_type == HDLC_CRC_NONE)
4994                 status &= ~BIT2;
4995
4996         if (framesize == 0 ||
4997                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4998                 /* discard 0 byte frames, this seems to occur sometime
4999                  * when remote is idling flags.
5000                  */
5001                 rx_free_frame_buffers(info, StartIndex, EndIndex);
5002                 goto CheckAgain;
5003         }
5004
5005         if (framesize < 2)
5006                 status |= BIT6;
5007
5008         if (status & (BIT6+BIT5+BIT3+BIT2)) {
5009                 /* received frame has errors,
5010                  * update counts and mark frame size as 0
5011                  */
5012                 if (status & BIT6)
5013                         info->icount.rxshort++;
5014                 else if (status & BIT5)
5015                         info->icount.rxabort++;
5016                 else if (status & BIT3)
5017                         info->icount.rxover++;
5018                 else
5019                         info->icount.rxcrc++;
5020
5021                 framesize = 0;
5022 #ifdef CONFIG_HDLC
5023                 {
5024                         struct net_device_stats *stats = hdlc_stats(info->netdev);
5025                         stats->rx_errors++;
5026                         stats->rx_frame_errors++;
5027                 }
5028 #endif
5029         }
5030
5031         if ( debug_level >= DEBUG_LEVEL_BH )
5032                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5033                         __FILE__,__LINE__,info->device_name,status,framesize);
5034
5035         if ( debug_level >= DEBUG_LEVEL_DATA )
5036                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5037                         min_t(int, framesize,SCABUFSIZE),0);
5038
5039         if (framesize) {
5040                 if (framesize > info->max_frame_size)
5041                         info->icount.rxlong++;
5042                 else {
5043                         /* copy dma buffer(s) to contiguous intermediate buffer */
5044                         int copy_count = framesize;
5045                         int index = StartIndex;
5046                         unsigned char *ptmp = info->tmp_rx_buf;
5047                         info->tmp_rx_buf_count = framesize;
5048
5049                         info->icount.rxok++;
5050
5051                         while(copy_count) {
5052                                 int partial_count = min(copy_count,SCABUFSIZE);
5053                                 memcpy( ptmp,
5054                                         info->rx_buf_list_ex[index].virt_addr,
5055                                         partial_count );
5056                                 ptmp += partial_count;
5057                                 copy_count -= partial_count;
5058
5059                                 if ( ++index == info->rx_buf_count )
5060                                         index = 0;
5061                         }
5062
5063 #ifdef CONFIG_HDLC
5064                         if (info->netcount)
5065                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5066                         else
5067 #endif
5068                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5069                                                   info->flag_buf, framesize);
5070                 }
5071         }
5072         /* Free the buffers used by this frame. */
5073         rx_free_frame_buffers( info, StartIndex, EndIndex );
5074
5075         ReturnCode = 1;
5076
5077 Cleanup:
5078         if ( info->rx_enabled && info->rx_overflow ) {
5079                 /* Receiver is enabled, but needs to restarted due to
5080                  * rx buffer overflow. If buffers are empty, restart receiver.
5081                  */
5082                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5083                         spin_lock_irqsave(&info->lock,flags);
5084                         rx_start(info);
5085                         spin_unlock_irqrestore(&info->lock,flags);
5086                 }
5087         }
5088
5089         return ReturnCode;
5090 }
5091
5092 /* load the transmit DMA buffer with data
5093  */
5094 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5095 {
5096         unsigned short copy_count;
5097         unsigned int i = 0;
5098         SCADESC *desc;
5099         SCADESC_EX *desc_ex;
5100
5101         if ( debug_level >= DEBUG_LEVEL_DATA )
5102                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5103
5104         /* Copy source buffer to one or more DMA buffers, starting with
5105          * the first transmit dma buffer.
5106          */
5107         for(i=0;;)
5108         {
5109                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5110
5111                 desc = &info->tx_buf_list[i];
5112                 desc_ex = &info->tx_buf_list_ex[i];
5113
5114                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5115
5116                 desc->length = copy_count;
5117                 desc->status = 0;
5118
5119                 buf += copy_count;
5120                 count -= copy_count;
5121
5122                 if (!count)
5123                         break;
5124
5125                 i++;
5126                 if (i >= info->tx_buf_count)
5127                         i = 0;
5128         }
5129
5130         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5131         info->last_tx_buf = ++i;
5132 }
5133
5134 int register_test(SLMP_INFO *info)
5135 {
5136         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5137         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5138         unsigned int i;
5139         int rc = TRUE;
5140         unsigned long flags;
5141
5142         spin_lock_irqsave(&info->lock,flags);
5143         reset_port(info);
5144
5145         /* assume failure */
5146         info->init_error = DiagStatus_AddressFailure;
5147
5148         /* Write bit patterns to various registers but do it out of */
5149         /* sync, then read back and verify values. */
5150
5151         for (i = 0 ; i < count ; i++) {
5152                 write_reg(info, TMC, testval[i]);
5153                 write_reg(info, IDL, testval[(i+1)%count]);
5154                 write_reg(info, SA0, testval[(i+2)%count]);
5155                 write_reg(info, SA1, testval[(i+3)%count]);
5156
5157                 if ( (read_reg(info, TMC) != testval[i]) ||
5158                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5159                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5160                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5161                 {
5162                         rc = FALSE;
5163                         break;
5164                 }
5165         }
5166
5167         reset_port(info);
5168         spin_unlock_irqrestore(&info->lock,flags);
5169
5170         return rc;
5171 }
5172
5173 int irq_test(SLMP_INFO *info)
5174 {
5175         unsigned long timeout;
5176         unsigned long flags;
5177
5178         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5179
5180         spin_lock_irqsave(&info->lock,flags);
5181         reset_port(info);
5182
5183         /* assume failure */
5184         info->init_error = DiagStatus_IrqFailure;
5185         info->irq_occurred = FALSE;
5186
5187         /* setup timer0 on SCA0 to interrupt */
5188
5189         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5190         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5191
5192         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5193         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5194
5195
5196         /* TMCS, Timer Control/Status Register
5197          *
5198          * 07      CMF, Compare match flag (read only) 1=match
5199          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5200          * 05      Reserved, must be 0
5201          * 04      TME, Timer Enable
5202          * 03..00  Reserved, must be 0
5203          *
5204          * 0101 0000
5205          */
5206         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5207
5208         spin_unlock_irqrestore(&info->lock,flags);
5209
5210         timeout=100;
5211         while( timeout-- && !info->irq_occurred ) {
5212                 set_current_state(TASK_INTERRUPTIBLE);
5213                 schedule_timeout(msecs_to_jiffies(10));
5214         }
5215
5216         spin_lock_irqsave(&info->lock,flags);
5217         reset_port(info);
5218         spin_unlock_irqrestore(&info->lock,flags);
5219
5220         return info->irq_occurred;
5221 }
5222
5223 /* initialize individual SCA device (2 ports)
5224  */
5225 int sca_init(SLMP_INFO *info)
5226 {
5227         /* set wait controller to single mem partition (low), no wait states */
5228         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5229         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5230         write_reg(info, WCRL, 0);       /* wait controller low range */
5231         write_reg(info, WCRM, 0);       /* wait controller mid range */
5232         write_reg(info, WCRH, 0);       /* wait controller high range */
5233
5234         /* DPCR, DMA Priority Control
5235          *
5236          * 07..05  Not used, must be 0
5237          * 04      BRC, bus release condition: 0=all transfers complete
5238          * 03      CCC, channel change condition: 0=every cycle
5239          * 02..00  PR<2..0>, priority 100=round robin
5240          *
5241          * 00000100 = 0x04
5242          */
5243         write_reg(info, DPCR, dma_priority);
5244
5245         /* DMA Master Enable, BIT7: 1=enable all channels */
5246         write_reg(info, DMER, 0x80);
5247
5248         /* enable all interrupt classes */
5249         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5250         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5251         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5252
5253         /* ITCR, interrupt control register
5254          * 07      IPC, interrupt priority, 0=MSCI->DMA
5255          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5256          * 04      VOS, Vector Output, 0=unmodified vector
5257          * 03..00  Reserved, must be 0
5258          */
5259         write_reg(info, ITCR, 0);
5260
5261         return TRUE;
5262 }
5263
5264 /* initialize adapter hardware
5265  */
5266 int init_adapter(SLMP_INFO *info)
5267 {
5268         int i;
5269
5270         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5271         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5272         u32 readval;
5273
5274         info->misc_ctrl_value |= BIT30;
5275         *MiscCtrl = info->misc_ctrl_value;
5276
5277         /*
5278          * Force at least 170ns delay before clearing
5279          * reset bit. Each read from LCR takes at least
5280          * 30ns so 10 times for 300ns to be safe.
5281          */
5282         for(i=0;i<10;i++)
5283                 readval = *MiscCtrl;
5284
5285         info->misc_ctrl_value &= ~BIT30;
5286         *MiscCtrl = info->misc_ctrl_value;
5287
5288         /* init control reg (all DTRs off, all clksel=input) */
5289         info->ctrlreg_value = 0xaa;
5290         write_control_reg(info);
5291
5292         {
5293                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5294                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5295
5296                 switch(read_ahead_count)
5297                 {
5298                 case 16:
5299                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5300                         break;
5301                 case 8:
5302                         lcr1_brdr_value |= BIT5 + BIT4;
5303                         break;
5304                 case 4:
5305                         lcr1_brdr_value |= BIT5 + BIT3;
5306                         break;
5307                 case 0:
5308                         lcr1_brdr_value |= BIT5;
5309                         break;
5310                 }
5311
5312                 *LCR1BRDR = lcr1_brdr_value;
5313                 *MiscCtrl = misc_ctrl_value;
5314         }
5315
5316         sca_init(info->port_array[0]);
5317         sca_init(info->port_array[2]);
5318
5319         return TRUE;
5320 }
5321
5322 /* Loopback an HDLC frame to test the hardware
5323  * interrupt and DMA functions.
5324  */
5325 int loopback_test(SLMP_INFO *info)
5326 {
5327 #define TESTFRAMESIZE 20
5328
5329         unsigned long timeout;
5330         u16 count = TESTFRAMESIZE;
5331         unsigned char buf[TESTFRAMESIZE];
5332         int rc = FALSE;
5333         unsigned long flags;
5334
5335         struct tty_struct *oldtty = info->tty;
5336         u32 speed = info->params.clock_speed;
5337
5338         info->params.clock_speed = 3686400;
5339         info->tty = NULL;
5340
5341         /* assume failure */
5342         info->init_error = DiagStatus_DmaFailure;
5343
5344         /* build and send transmit frame */
5345         for (count = 0; count < TESTFRAMESIZE;++count)
5346                 buf[count] = (unsigned char)count;
5347
5348         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5349
5350         /* program hardware for HDLC and enabled receiver */
5351         spin_lock_irqsave(&info->lock,flags);
5352         hdlc_mode(info);
5353         enable_loopback(info,1);
5354         rx_start(info);
5355         info->tx_count = count;
5356         tx_load_dma_buffer(info,buf,count);
5357         tx_start(info);
5358         spin_unlock_irqrestore(&info->lock,flags);
5359
5360         /* wait for receive complete */
5361         /* Set a timeout for waiting for interrupt. */
5362         for ( timeout = 100; timeout; --timeout ) {
5363                 set_current_state(TASK_INTERRUPTIBLE);
5364                 schedule_timeout(msecs_to_jiffies(10));
5365
5366                 if (rx_get_frame(info)) {
5367                         rc = TRUE;
5368                         break;
5369                 }
5370         }
5371
5372         /* verify received frame length and contents */
5373         if (rc == TRUE &&
5374                 ( info->tmp_rx_buf_count != count ||
5375                   memcmp(buf, info->tmp_rx_buf,count))) {
5376                 rc = FALSE;
5377         }
5378
5379         spin_lock_irqsave(&info->lock,flags);
5380         reset_adapter(info);
5381         spin_unlock_irqrestore(&info->lock,flags);
5382
5383         info->params.clock_speed = speed;
5384         info->tty = oldtty;
5385
5386         return rc;
5387 }
5388
5389 /* Perform diagnostics on hardware
5390  */
5391 int adapter_test( SLMP_INFO *info )
5392 {
5393         unsigned long flags;
5394         if ( debug_level >= DEBUG_LEVEL_INFO )
5395                 printk( "%s(%d):Testing device %s\n",
5396                         __FILE__,__LINE__,info->device_name );
5397
5398         spin_lock_irqsave(&info->lock,flags);
5399         init_adapter(info);
5400         spin_unlock_irqrestore(&info->lock,flags);
5401
5402         info->port_array[0]->port_count = 0;
5403
5404         if ( register_test(info->port_array[0]) &&
5405                 register_test(info->port_array[1])) {
5406
5407                 info->port_array[0]->port_count = 2;
5408
5409                 if ( register_test(info->port_array[2]) &&
5410                         register_test(info->port_array[3]) )
5411                         info->port_array[0]->port_count += 2;
5412         }
5413         else {
5414                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5415                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5416                 return -ENODEV;
5417         }
5418
5419         if ( !irq_test(info->port_array[0]) ||
5420                 !irq_test(info->port_array[1]) ||
5421                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5422                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5423                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5424                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5425                 return -ENODEV;
5426         }
5427
5428         if (!loopback_test(info->port_array[0]) ||
5429                 !loopback_test(info->port_array[1]) ||
5430                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5431                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5432                 printk( "%s(%d):DMA test failure for device %s\n",
5433                         __FILE__,__LINE__,info->device_name);
5434                 return -ENODEV;
5435         }
5436
5437         if ( debug_level >= DEBUG_LEVEL_INFO )
5438                 printk( "%s(%d):device %s passed diagnostics\n",
5439                         __FILE__,__LINE__,info->device_name );
5440
5441         info->port_array[0]->init_error = 0;
5442         info->port_array[1]->init_error = 0;
5443         if ( info->port_count > 2 ) {
5444                 info->port_array[2]->init_error = 0;
5445                 info->port_array[3]->init_error = 0;
5446         }
5447
5448         return 0;
5449 }
5450
5451 /* Test the shared memory on a PCI adapter.
5452  */
5453 int memory_test(SLMP_INFO *info)
5454 {
5455         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5456                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5457         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5458         unsigned long i;
5459         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5460         unsigned long * addr = (unsigned long *)info->memory_base;
5461
5462         /* Test data lines with test pattern at one location. */
5463
5464         for ( i = 0 ; i < count ; i++ ) {
5465                 *addr = testval[i];
5466                 if ( *addr != testval[i] )
5467                         return FALSE;
5468         }
5469
5470         /* Test address lines with incrementing pattern over */
5471         /* entire address range. */
5472
5473         for ( i = 0 ; i < limit ; i++ ) {
5474                 *addr = i * 4;
5475                 addr++;
5476         }
5477
5478         addr = (unsigned long *)info->memory_base;
5479
5480         for ( i = 0 ; i < limit ; i++ ) {
5481                 if ( *addr != i * 4 )
5482                         return FALSE;
5483                 addr++;
5484         }
5485
5486         memset( info->memory_base, 0, SCA_MEM_SIZE );
5487         return TRUE;
5488 }
5489
5490 /* Load data into PCI adapter shared memory.
5491  *
5492  * The PCI9050 releases control of the local bus
5493  * after completing the current read or write operation.
5494  *
5495  * While the PCI9050 write FIFO not empty, the
5496  * PCI9050 treats all of the writes as a single transaction
5497  * and does not release the bus. This causes DMA latency problems
5498  * at high speeds when copying large data blocks to the shared memory.
5499  *
5500  * This function breaks a write into multiple transations by
5501  * interleaving a read which flushes the write FIFO and 'completes'
5502  * the write transation. This allows any pending DMA request to gain control
5503  * of the local bus in a timely fasion.
5504  */
5505 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5506 {
5507         /* A load interval of 16 allows for 4 32-bit writes at */
5508         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5509
5510         unsigned short interval = count / sca_pci_load_interval;
5511         unsigned short i;
5512
5513         for ( i = 0 ; i < interval ; i++ )
5514         {
5515                 memcpy(dest, src, sca_pci_load_interval);
5516                 read_status_reg(info);
5517                 dest += sca_pci_load_interval;
5518                 src += sca_pci_load_interval;
5519         }
5520
5521         memcpy(dest, src, count % sca_pci_load_interval);
5522 }
5523
5524 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5525 {
5526         int i;
5527         int linecount;
5528         if (xmit)
5529                 printk("%s tx data:\n",info->device_name);
5530         else
5531                 printk("%s rx data:\n",info->device_name);
5532
5533         while(count) {
5534                 if (count > 16)
5535                         linecount = 16;
5536                 else
5537                         linecount = count;
5538
5539                 for(i=0;i<linecount;i++)
5540                         printk("%02X ",(unsigned char)data[i]);
5541                 for(;i<17;i++)
5542                         printk("   ");
5543                 for(i=0;i<linecount;i++) {
5544                         if (data[i]>=040 && data[i]<=0176)
5545                                 printk("%c",data[i]);
5546                         else
5547                                 printk(".");
5548                 }
5549                 printk("\n");
5550
5551                 data  += linecount;
5552                 count -= linecount;
5553         }
5554 }       /* end of trace_block() */
5555
5556 /* called when HDLC frame times out
5557  * update stats and do tx completion processing
5558  */
5559 void tx_timeout(unsigned long context)
5560 {
5561         SLMP_INFO *info = (SLMP_INFO*)context;
5562         unsigned long flags;
5563
5564         if ( debug_level >= DEBUG_LEVEL_INFO )
5565                 printk( "%s(%d):%s tx_timeout()\n",
5566                         __FILE__,__LINE__,info->device_name);
5567         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5568                 info->icount.txtimeout++;
5569         }
5570         spin_lock_irqsave(&info->lock,flags);
5571         info->tx_active = 0;
5572         info->tx_count = info->tx_put = info->tx_get = 0;
5573
5574         spin_unlock_irqrestore(&info->lock,flags);
5575
5576 #ifdef CONFIG_HDLC
5577         if (info->netcount)
5578                 hdlcdev_tx_done(info);
5579         else
5580 #endif
5581                 bh_transmit(info);
5582 }
5583
5584 /* called to periodically check the DSR/RI modem signal input status
5585  */
5586 void status_timeout(unsigned long context)
5587 {
5588         u16 status = 0;
5589         SLMP_INFO *info = (SLMP_INFO*)context;
5590         unsigned long flags;
5591         unsigned char delta;
5592
5593
5594         spin_lock_irqsave(&info->lock,flags);
5595         get_signals(info);
5596         spin_unlock_irqrestore(&info->lock,flags);
5597
5598         /* check for DSR/RI state change */
5599
5600         delta = info->old_signals ^ info->serial_signals;
5601         info->old_signals = info->serial_signals;
5602
5603         if (delta & SerialSignal_DSR)
5604                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5605
5606         if (delta & SerialSignal_RI)
5607                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5608
5609         if (delta & SerialSignal_DCD)
5610                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5611
5612         if (delta & SerialSignal_CTS)
5613                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5614
5615         if (status)
5616                 isr_io_pin(info,status);
5617
5618         info->status_timer.data = (unsigned long)info;
5619         info->status_timer.function = status_timeout;
5620         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5621         add_timer(&info->status_timer);
5622 }
5623
5624
5625 /* Register Access Routines -
5626  * All registers are memory mapped
5627  */
5628 #define CALC_REGADDR() \
5629         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5630         if (info->port_num > 1) \
5631                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5632         if ( info->port_num & 1) { \
5633                 if (Addr > 0x7f) \
5634                         RegAddr += 0x40;        /* DMA access */ \
5635                 else if (Addr > 0x1f && Addr < 0x60) \
5636                         RegAddr += 0x20;        /* MSCI access */ \
5637         }
5638
5639
5640 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5641 {
5642         CALC_REGADDR();
5643         return *RegAddr;
5644 }
5645 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5646 {
5647         CALC_REGADDR();
5648         *RegAddr = Value;
5649 }
5650
5651 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5652 {
5653         CALC_REGADDR();
5654         return *((u16 *)RegAddr);
5655 }
5656
5657 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5658 {
5659         CALC_REGADDR();
5660         *((u16 *)RegAddr) = Value;
5661 }
5662
5663 unsigned char read_status_reg(SLMP_INFO * info)
5664 {
5665         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5666         return *RegAddr;
5667 }
5668
5669 void write_control_reg(SLMP_INFO * info)
5670 {
5671         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5672         *RegAddr = info->port_array[0]->ctrlreg_value;
5673 }
5674
5675
5676 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5677                                           const struct pci_device_id *ent)
5678 {
5679         if (pci_enable_device(dev)) {
5680                 printk("error enabling pci device %p\n", dev);
5681                 return -EIO;
5682         }
5683         device_init( ++synclinkmp_adapter_count, dev );
5684         return 0;
5685 }
5686
5687 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5688 {
5689 }