drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.22 2004/06/03 14:50:10 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <asm/serial.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <asm/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70
  71 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
  72 #define CONFIG_SYNCLINK_SYNCPPP 1
  73 #endif
  74
  75 #ifdef CONFIG_SYNCLINK_SYNCPPP
  76 #include <net/syncppp.h>
  77 #endif
  78
  79 #define GET_USER(error,value,addr) error = get_user(value,addr)
  80 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  81 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  82 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  83
  84 #include <asm/uaccess.h>
  85
  86 #include "linux/synclink.h"
  87
  88 static MGSL_PARAMS default_params = {
  89         MGSL_MODE_HDLC,                 /* unsigned long mode */
  90         0,                              /* unsigned char loopback; */
  91         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  92         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  93         0,                              /* unsigned long clock_speed; */
  94         0xff,                           /* unsigned char addr_filter; */
  95         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  96         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  97         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  98         9600,                           /* unsigned long data_rate; */
  99         8,                              /* unsigned char data_bits; */
 100         1,                              /* unsigned char stop_bits; */
 101         ASYNC_PARITY_NONE               /* unsigned char parity; */
 102 };
 103
 104 /* size in bytes of DMA data buffers */
 105 #define SCABUFSIZE      1024
 106 #define SCA_MEM_SIZE    0x40000
 107 #define SCA_BASE_SIZE   512
 108 #define SCA_REG_SIZE    16
 109 #define SCA_MAX_PORTS   4
 110 #define SCAMAXDESC      128
 111
 112 #define BUFFERLISTSIZE  4096
 113
 114 /* SCA-I style DMA buffer descriptor */
 115 typedef struct _SCADESC
 116 {
 117         u16     next;           /* lower l6 bits of next descriptor addr */
 118         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 119         u8      buf_base;       /* upper 8 bits of buffer addr */
 120         u8      pad1;
 121         u16     length;         /* length of buffer */
 122         u8      status;         /* status of buffer */
 123         u8      pad2;
 124 } SCADESC, *PSCADESC;
 125
 126 typedef struct _SCADESC_EX
 127 {
 128         /* device driver bookkeeping section */
 129         char    *virt_addr;     /* virtual address of data buffer */
 130         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 131 } SCADESC_EX, *PSCADESC_EX;
 132
 133 /* The queue of BH actions to be performed */
 134
 135 #define BH_RECEIVE  1
 136 #define BH_TRANSMIT 2
 137 #define BH_STATUS   4
 138
 139 #define IO_PIN_SHUTDOWN_LIMIT 100
 140
 141 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 142
 143 struct  _input_signal_events {
 144         int     ri_up;
 145         int     ri_down;
 146         int     dsr_up;
 147         int     dsr_down;
 148         int     dcd_up;
 149         int     dcd_down;
 150         int     cts_up;
 151         int     cts_down;
 152 };
 153
 154 /*
 155  * Device instance data structure
 156  */
 157 typedef struct _synclinkmp_info {
 158         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 159         int                     magic;
 160         int                     flags;
 161         int                     count;          /* count of opens */
 162         int                     line;
 163         unsigned short          close_delay;
 164         unsigned short          closing_wait;   /* time to wait before closing */
 165
 166         struct mgsl_icount      icount;
 167
 168         struct tty_struct       *tty;
 169         int                     timeout;
 170         int                     x_char;         /* xon/xoff character */
 171         int                     blocked_open;   /* # of blocked opens */
 172         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 173         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 174         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 175         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 176         unsigned char           *tx_buf;
 177         int                     tx_put;
 178         int                     tx_get;
 179         int                     tx_count;
 180
 181         wait_queue_head_t       open_wait;
 182         wait_queue_head_t       close_wait;
 183
 184         wait_queue_head_t       status_event_wait_q;
 185         wait_queue_head_t       event_wait_q;
 186         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 187         struct _synclinkmp_info *next_device;   /* device list link */
 188         struct timer_list       status_timer;   /* input signal status check timer */
 189
 190         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 191         struct work_struct task;                        /* task structure for scheduling bh */
 192
 193         u32 max_frame_size;                     /* as set by device config */
 194
 195         u32 pending_bh;
 196
 197         int bh_running;                         /* Protection from multiple */
 198         int isr_overflow;
 199         int bh_requested;
 200
 201         int dcd_chkcount;                       /* check counts to prevent */
 202         int cts_chkcount;                       /* too many IRQs if a signal */
 203         int dsr_chkcount;                       /* is floating */
 204         int ri_chkcount;
 205
 206         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 207         unsigned long buffer_list_phys;
 208
 209         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 210         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 211         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 212         unsigned int current_rx_buf;
 213
 214         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 215         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 216         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 217         unsigned int last_tx_buf;
 218
 219         unsigned char *tmp_rx_buf;
 220         unsigned int tmp_rx_buf_count;
 221
 222         int rx_enabled;
 223         int rx_overflow;
 224
 225         int tx_enabled;
 226         int tx_active;
 227         u32 idle_mode;
 228
 229         unsigned char ie0_value;
 230         unsigned char ie1_value;
 231         unsigned char ie2_value;
 232         unsigned char ctrlreg_value;
 233         unsigned char old_signals;
 234
 235         char device_name[25];                   /* device instance name */
 236
 237         int port_count;
 238         int adapter_num;
 239         int port_num;
 240
 241         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 242
 243         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 244
 245         unsigned int irq_level;                 /* interrupt level */
 246         unsigned long irq_flags;
 247         int irq_requested;                      /* nonzero if IRQ requested */
 248
 249         MGSL_PARAMS params;                     /* communications parameters */
 250
 251         unsigned char serial_signals;           /* current serial signal states */
 252
 253         int irq_occurred;                       /* for diagnostics use */
 254         unsigned int init_error;                /* Initialization startup error */
 255
 256         u32 last_mem_alloc;
 257         unsigned char* memory_base;             /* shared memory address (PCI only) */
 258         u32 phys_memory_base;
 259         int shared_mem_requested;
 260
 261         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 262         u32 phys_sca_base;
 263         u32 sca_offset;
 264         int sca_base_requested;
 265
 266         unsigned char* lcr_base;                /* local config registers (PCI only) */
 267         u32 phys_lcr_base;
 268         u32 lcr_offset;
 269         int lcr_mem_requested;
 270
 271         unsigned char* statctrl_base;           /* status/control register memory */
 272         u32 phys_statctrl_base;
 273         u32 statctrl_offset;
 274         int sca_statctrl_requested;
 275
 276         u32 misc_ctrl_value;
 277         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 278         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 279         BOOLEAN drop_rts_on_tx_done;
 280
 281         struct  _input_signal_events    input_signal_events;
 282
 283         /* SPPP/Cisco HDLC device parts */
 284         int netcount;
 285         int dosyncppp;
 286         spinlock_t netlock;
 287 #ifdef CONFIG_SYNCLINK_SYNCPPP
 288         struct ppp_device pppdev;
 289         char netname[10];
 290         struct net_device *netdev;
 291         struct net_device_stats netstats;
 292 #endif
 293 } SLMP_INFO;
 294
 295 #define MGSL_MAGIC 0x5401
 296
 297 /*
 298  * define serial signal status change macros
 299  */
 300 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 301 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 302 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 303 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 304
 305 /* Common Register macros */
 306 #define LPR     0x00
 307 #define PABR0   0x02
 308 #define PABR1   0x03
 309 #define WCRL    0x04
 310 #define WCRM    0x05
 311 #define WCRH    0x06
 312 #define DPCR    0x08
 313 #define DMER    0x09
 314 #define ISR0    0x10
 315 #define ISR1    0x11
 316 #define ISR2    0x12
 317 #define IER0    0x14
 318 #define IER1    0x15
 319 #define IER2    0x16
 320 #define ITCR    0x18
 321 #define INTVR   0x1a
 322 #define IMVR    0x1c
 323
 324 /* MSCI Register macros */
 325 #define TRB     0x20
 326 #define TRBL    0x20
 327 #define TRBH    0x21
 328 #define SR0     0x22
 329 #define SR1     0x23
 330 #define SR2     0x24
 331 #define SR3     0x25
 332 #define FST     0x26
 333 #define IE0     0x28
 334 #define IE1     0x29
 335 #define IE2     0x2a
 336 #define FIE     0x2b
 337 #define CMD     0x2c
 338 #define MD0     0x2e
 339 #define MD1     0x2f
 340 #define MD2     0x30
 341 #define CTL     0x31
 342 #define SA0     0x32
 343 #define SA1     0x33
 344 #define IDL     0x34
 345 #define TMC     0x35
 346 #define RXS     0x36
 347 #define TXS     0x37
 348 #define TRC0    0x38
 349 #define TRC1    0x39
 350 #define RRC     0x3a
 351 #define CST0    0x3c
 352 #define CST1    0x3d
 353
 354 /* Timer Register Macros */
 355 #define TCNT    0x60
 356 #define TCNTL   0x60
 357 #define TCNTH   0x61
 358 #define TCONR   0x62
 359 #define TCONRL  0x62
 360 #define TCONRH  0x63
 361 #define TMCS    0x64
 362 #define TEPR    0x65
 363
 364 /* DMA Controller Register macros */
 365 #define DAR     0x80
 366 #define DARL    0x80
 367 #define DARH    0x81
 368 #define DARB    0x82
 369 #define BAR     0x80
 370 #define BARL    0x80
 371 #define BARH    0x81
 372 #define BARB    0x82
 373 #define SAR     0x84
 374 #define SARL    0x84
 375 #define SARH    0x85
 376 #define SARB    0x86
 377 #define CPB     0x86
 378 #define CDA     0x88
 379 #define CDAL    0x88
 380 #define CDAH    0x89
 381 #define EDA     0x8a
 382 #define EDAL    0x8a
 383 #define EDAH    0x8b
 384 #define BFL     0x8c
 385 #define BFLL    0x8c
 386 #define BFLH    0x8d
 387 #define BCR     0x8e
 388 #define BCRL    0x8e
 389 #define BCRH    0x8f
 390 #define DSR     0x90
 391 #define DMR     0x91
 392 #define FCT     0x93
 393 #define DIR     0x94
 394 #define DCMD    0x95
 395
 396 /* combine with timer or DMA register address */
 397 #define TIMER0  0x00
 398 #define TIMER1  0x08
 399 #define TIMER2  0x10
 400 #define TIMER3  0x18
 401 #define RXDMA   0x00
 402 #define TXDMA   0x20
 403
 404 /* SCA Command Codes */
 405 #define NOOP            0x00
 406 #define TXRESET         0x01
 407 #define TXENABLE        0x02
 408 #define TXDISABLE       0x03
 409 #define TXCRCINIT       0x04
 410 #define TXCRCEXCL       0x05
 411 #define TXEOM           0x06
 412 #define TXABORT         0x07
 413 #define MPON            0x08
 414 #define TXBUFCLR        0x09
 415 #define RXRESET         0x11
 416 #define RXENABLE        0x12
 417 #define RXDISABLE       0x13
 418 #define RXCRCINIT       0x14
 419 #define RXREJECT        0x15
 420 #define SEARCHMP        0x16
 421 #define RXCRCEXCL       0x17
 422 #define RXCRCCALC       0x18
 423 #define CHRESET         0x21
 424 #define HUNT            0x31
 425
 426 /* DMA command codes */
 427 #define SWABORT         0x01
 428 #define FEICLEAR        0x02
 429
 430 /* IE0 */
 431 #define TXINTE          BIT7
 432 #define RXINTE          BIT6
 433 #define TXRDYE          BIT1
 434 #define RXRDYE          BIT0
 435
 436 /* IE1 & SR1 */
 437 #define UDRN    BIT7
 438 #define IDLE    BIT6
 439 #define SYNCD   BIT4
 440 #define FLGD    BIT4
 441 #define CCTS    BIT3
 442 #define CDCD    BIT2
 443 #define BRKD    BIT1
 444 #define ABTD    BIT1
 445 #define GAPD    BIT1
 446 #define BRKE    BIT0
 447 #define IDLD    BIT0
 448
 449 /* IE2 & SR2 */
 450 #define EOM     BIT7
 451 #define PMP     BIT6
 452 #define SHRT    BIT6
 453 #define PE      BIT5
 454 #define ABT     BIT5
 455 #define FRME    BIT4
 456 #define RBIT    BIT4
 457 #define OVRN    BIT3
 458 #define CRCE    BIT2
 459
 460
 461 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
 462
 463 /*
 464  * Global linked list of SyncLink devices
 465  */
 466 static SLMP_INFO *synclinkmp_device_list = NULL;
 467 static int synclinkmp_adapter_count = -1;
 468 static int synclinkmp_device_count = 0;
 469
 470 /*
 471  * Set this param to non-zero to load eax with the
 472  * .text section address and breakpoint on module load.
 473  * This is useful for use with gdb and add-symbol-file command.
 474  */
 475 static int break_on_load=0;
 476
 477 /*
 478  * Driver major number, defaults to zero to get auto
 479  * assigned major number. May be forced as module parameter.
 480  */
 481 static int ttymajor=0;
 482
 483 /*
 484  * Array of user specified options for ISA adapters.
 485  */
 486 static int debug_level = 0;
 487 static int maxframe[MAX_DEVICES] = {0,};
 488 static int dosyncppp[MAX_DEVICES] = {0,};
 489
 490 MODULE_PARM(break_on_load,"i");
 491 MODULE_PARM(ttymajor,"i");
 492 MODULE_PARM(debug_level,"i");
 493 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 494 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 495
 496 static char *driver_name = "SyncLink MultiPort driver";
 497 static char *driver_version = "$Revision: 4.22 $";
 498
 499 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 500 static void synclinkmp_remove_one(struct pci_dev *dev);
 501
 502 static struct pci_device_id synclinkmp_pci_tbl[] = {
 503         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 504         { 0, }, /* terminate list */
 505 };
 506 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 507
 508 MODULE_LICENSE("GPL");
 509
 510 static struct pci_driver synclinkmp_pci_driver = {
 511         .name           = "synclinkmp",
 512         .id_table       = synclinkmp_pci_tbl,
 513         .probe          = synclinkmp_init_one,
 514         .remove         = __devexit_p(synclinkmp_remove_one),
 515 };
 516
 517
 518 static struct tty_driver *serial_driver;
 519
 520 /* number of characters left in xmit buffer before we ask for more */
 521 #define WAKEUP_CHARS 256
 522
 523 #ifndef MIN
 524 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 525 #endif
 526
 527
 528 /* tty callbacks */
 529
 530 static int  open(struct tty_struct *tty, struct file * filp);
 531 static void close(struct tty_struct *tty, struct file * filp);
 532 static void hangup(struct tty_struct *tty);
 533 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 534
 535 static int  write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
 536 static void put_char(struct tty_struct *tty, unsigned char ch);
 537 static void send_xchar(struct tty_struct *tty, char ch);
 538 static void wait_until_sent(struct tty_struct *tty, int timeout);
 539 static int  write_room(struct tty_struct *tty);
 540 static void flush_chars(struct tty_struct *tty);
 541 static void flush_buffer(struct tty_struct *tty);
 542 static void tx_hold(struct tty_struct *tty);
 543 static void tx_release(struct tty_struct *tty);
 544
 545 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 546 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 547 static int  chars_in_buffer(struct tty_struct *tty);
 548 static void throttle(struct tty_struct * tty);
 549 static void unthrottle(struct tty_struct * tty);
 550 static void set_break(struct tty_struct *tty, int break_state);
 551
 552 /* sppp support and callbacks */
 553
 554 #ifdef CONFIG_SYNCLINK_SYNCPPP
 555 static void sppp_init(SLMP_INFO *info);
 556 static void sppp_delete(SLMP_INFO *info);
 557 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size);
 558 static void sppp_tx_done(SLMP_INFO *info);
 559
 560 static int  sppp_cb_open(struct net_device *d);
 561 static int  sppp_cb_close(struct net_device *d);
 562 static int  sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 563 static int  sppp_cb_tx(struct sk_buff *skb, struct net_device *dev);
 564 static void sppp_cb_tx_timeout(struct net_device *dev);
 565 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev);
 566 #endif
 567
 568 /* ioctl handlers */
 569
 570 static int  get_stats(SLMP_INFO *info, struct mgsl_icount *user_icount);
 571 static int  get_params(SLMP_INFO *info, MGSL_PARAMS *params);
 572 static int  set_params(SLMP_INFO *info, MGSL_PARAMS *params);
 573 static int  get_txidle(SLMP_INFO *info, int*idle_mode);
 574 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 575 static int  tx_enable(SLMP_INFO *info, int enable);
 576 static int  tx_abort(SLMP_INFO *info);
 577 static int  rx_enable(SLMP_INFO *info, int enable);
 578 static int  map_status(int signals);
 579 static int  modem_input_wait(SLMP_INFO *info,int arg);
 580 static int  wait_mgsl_event(SLMP_INFO *info, int *mask_ptr);
 581 static int  tiocmget(struct tty_struct *tty, struct file *file);
 582 static int  tiocmset(struct tty_struct *tty, struct file *file,
 583                      unsigned int set, unsigned int clear);
 584 static void set_break(struct tty_struct *tty, int break_state);
 585
 586 static void add_device(SLMP_INFO *info);
 587 static void device_init(int adapter_num, struct pci_dev *pdev);
 588 static int  claim_resources(SLMP_INFO *info);
 589 static void release_resources(SLMP_INFO *info);
 590
 591 static int  startup(SLMP_INFO *info);
 592 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 593 static void shutdown(SLMP_INFO *info);
 594 static void program_hw(SLMP_INFO *info);
 595 static void change_params(SLMP_INFO *info);
 596
 597 static int  init_adapter(SLMP_INFO *info);
 598 static int  register_test(SLMP_INFO *info);
 599 static int  irq_test(SLMP_INFO *info);
 600 static int  loopback_test(SLMP_INFO *info);
 601 static int  adapter_test(SLMP_INFO *info);
 602 static int  memory_test(SLMP_INFO *info);
 603
 604 static void reset_adapter(SLMP_INFO *info);
 605 static void reset_port(SLMP_INFO *info);
 606 static void async_mode(SLMP_INFO *info);
 607 static void hdlc_mode(SLMP_INFO *info);
 608
 609 static void rx_stop(SLMP_INFO *info);
 610 static void rx_start(SLMP_INFO *info);
 611 static void rx_reset_buffers(SLMP_INFO *info);
 612 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 613 static int  rx_get_frame(SLMP_INFO *info);
 614
 615 static void tx_start(SLMP_INFO *info);
 616 static void tx_stop(SLMP_INFO *info);
 617 static void tx_load_fifo(SLMP_INFO *info);
 618 static void tx_set_idle(SLMP_INFO *info);
 619 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 620
 621 static void get_signals(SLMP_INFO *info);
 622 static void set_signals(SLMP_INFO *info);
 623 static void enable_loopback(SLMP_INFO *info, int enable);
 624 static void set_rate(SLMP_INFO *info, u32 data_rate);
 625
 626 static int  bh_action(SLMP_INFO *info);
 627 static void bh_handler(void* Context);
 628 static void bh_receive(SLMP_INFO *info);
 629 static void bh_transmit(SLMP_INFO *info);
 630 static void bh_status(SLMP_INFO *info);
 631 static void isr_timer(SLMP_INFO *info);
 632 static void isr_rxint(SLMP_INFO *info);
 633 static void isr_rxrdy(SLMP_INFO *info);
 634 static void isr_txint(SLMP_INFO *info);
 635 static void isr_txrdy(SLMP_INFO *info);
 636 static void isr_rxdmaok(SLMP_INFO *info);
 637 static void isr_rxdmaerror(SLMP_INFO *info);
 638 static void isr_txdmaok(SLMP_INFO *info);
 639 static void isr_txdmaerror(SLMP_INFO *info);
 640 static void isr_io_pin(SLMP_INFO *info, u16 status);
 641
 642 static int  alloc_dma_bufs(SLMP_INFO *info);
 643 static void free_dma_bufs(SLMP_INFO *info);
 644 static int  alloc_buf_list(SLMP_INFO *info);
 645 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 646 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 647 static void free_tmp_rx_buf(SLMP_INFO *info);
 648
 649 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 650 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 651 static void tx_timeout(unsigned long context);
 652 static void status_timeout(unsigned long context);
 653
 654 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 655 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 656 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 657 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 658 static unsigned char read_status_reg(SLMP_INFO * info);
 659 static void write_control_reg(SLMP_INFO * info);
 660
 661
 662 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 663 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 664 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 665
 666 static u32 misc_ctrl_value = 0x007e4040;
 667 static u32 lcr1_brdr_value = 0x0080002d;
 668
 669 static u32 read_ahead_count = 8;
 670
 671 /* DPCR, DMA Priority Control
 672  *
 673  * 07..05  Not used, must be 0
 674  * 04      BRC, bus release condition: 0=all transfers complete
 675  *              1=release after 1 xfer on all channels
 676  * 03      CCC, channel change condition: 0=every cycle
 677  *              1=after each channel completes all xfers
 678  * 02..00  PR<2..0>, priority 100=round robin
 679  *
 680  * 00000100 = 0x00
 681  */
 682 static unsigned char dma_priority = 0x04;
 683
 684 // Number of bytes that can be written to shared RAM
 685 // in a single write operation
 686 static u32 sca_pci_load_interval = 64;
 687
 688 /*
 689  * 1st function defined in .text section. Calling this function in
 690  * init_module() followed by a breakpoint allows a remote debugger
 691  * (gdb) to get the .text address for the add-symbol-file command.
 692  * This allows remote debugging of dynamically loadable modules.
 693  */
 694 static void* synclinkmp_get_text_ptr(void);
 695 static void* synclinkmp_get_text_ptr() {return synclinkmp_get_text_ptr;}
 696
 697 static inline int sanity_check(SLMP_INFO *info,
 698                                char *name, const char *routine)
 699 {
 700 #ifdef SANITY_CHECK
 701         static const char *badmagic =
 702                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 703         static const char *badinfo =
 704                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 705
 706         if (!info) {
 707                 printk(badinfo, name, routine);
 708                 return 1;
 709         }
 710         if (info->magic != MGSL_MAGIC) {
 711                 printk(badmagic, name, routine);
 712                 return 1;
 713         }
 714 #else
 715         if (!info)
 716                 return 1;
 717 #endif
 718         return 0;
 719 }
 720
 721 /* tty callbacks */
 722
 723 /* Called when a port is opened.  Init and enable port.
 724  */
 725 static int open(struct tty_struct *tty, struct file *filp)
 726 {
 727         SLMP_INFO *info;
 728         int retval, line;
 729         unsigned long flags;
 730
 731         line = tty->index;
 732         if ((line < 0) || (line >= synclinkmp_device_count)) {
 733                 printk("%s(%d): open with invalid line #%d.\n",
 734                         __FILE__,__LINE__,line);
 735                 return -ENODEV;
 736         }
 737
 738         info = synclinkmp_device_list;
 739         while(info && info->line != line)
 740                 info = info->next_device;
 741         if (sanity_check(info, tty->name, "open"))
 742                 return -ENODEV;
 743         if ( info->init_error ) {
 744                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 745                         __FILE__,__LINE__,info->device_name,info->init_error);
 746                 return -ENODEV;
 747         }
 748
 749         tty->driver_data = info;
 750         info->tty = tty;
 751
 752         if (debug_level >= DEBUG_LEVEL_INFO)
 753                 printk("%s(%d):%s open(), old ref count = %d\n",
 754                          __FILE__,__LINE__,tty->driver->name, info->count);
 755
 756         /* If port is closing, signal caller to try again */
 757         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 758                 if (info->flags & ASYNC_CLOSING)
 759                         interruptible_sleep_on(&info->close_wait);
 760                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 761                         -EAGAIN : -ERESTARTSYS);
 762                 goto cleanup;
 763         }
 764
 765         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 766
 767         spin_lock_irqsave(&info->netlock, flags);
 768         if (info->netcount) {
 769                 retval = -EBUSY;
 770                 spin_unlock_irqrestore(&info->netlock, flags);
 771                 goto cleanup;
 772         }
 773         info->count++;
 774         spin_unlock_irqrestore(&info->netlock, flags);
 775
 776         if (info->count == 1) {
 777                 /* 1st open on this device, init hardware */
 778                 retval = startup(info);
 779                 if (retval < 0)
 780                         goto cleanup;
 781         }
 782
 783         retval = block_til_ready(tty, filp, info);
 784         if (retval) {
 785                 if (debug_level >= DEBUG_LEVEL_INFO)
 786                         printk("%s(%d):%s block_til_ready() returned %d\n",
 787                                  __FILE__,__LINE__, info->device_name, retval);
 788                 goto cleanup;
 789         }
 790
 791         if (debug_level >= DEBUG_LEVEL_INFO)
 792                 printk("%s(%d):%s open() success\n",
 793                          __FILE__,__LINE__, info->device_name);
 794         retval = 0;
 795
 796 cleanup:
 797         if (retval) {
 798                 if (tty->count == 1)
 799                         info->tty = 0; /* tty layer will release tty struct */
 800                 if(info->count)
 801                         info->count--;
 802         }
 803
 804         return retval;
 805 }
 806
 807 /* Called when port is closed. Wait for remaining data to be
 808  * sent. Disable port and free resources.
 809  */
 810 static void close(struct tty_struct *tty, struct file *filp)
 811 {
 812         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 813
 814         if (sanity_check(info, tty->name, "close"))
 815                 return;
 816
 817         if (debug_level >= DEBUG_LEVEL_INFO)
 818                 printk("%s(%d):%s close() entry, count=%d\n",
 819                          __FILE__,__LINE__, info->device_name, info->count);
 820
 821         if (!info->count)
 822                 return;
 823
 824         if (tty_hung_up_p(filp))
 825                 goto cleanup;
 826
 827         if ((tty->count == 1) && (info->count != 1)) {
 828                 /*
 829                  * tty->count is 1 and the tty structure will be freed.
 830                  * info->count should be one in this case.
 831                  * if it's not, correct it so that the port is shutdown.
 832                  */
 833                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 834                        "info->count is %d\n",
 835                          __FILE__,__LINE__, info->device_name, info->count);
 836                 info->count = 1;
 837         }
 838
 839         info->count--;
 840
 841         /* if at least one open remaining, leave hardware active */
 842         if (info->count)
 843                 goto cleanup;
 844
 845         info->flags |= ASYNC_CLOSING;
 846
 847         /* set tty->closing to notify line discipline to
 848          * only process XON/XOFF characters. Only the N_TTY
 849          * discipline appears to use this (ppp does not).
 850          */
 851         tty->closing = 1;
 852
 853         /* wait for transmit data to clear all layers */
 854
 855         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 856                 if (debug_level >= DEBUG_LEVEL_INFO)
 857                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 858                                  __FILE__,__LINE__, info->device_name );
 859                 tty_wait_until_sent(tty, info->closing_wait);
 860         }
 861
 862         if (info->flags & ASYNC_INITIALIZED)
 863                 wait_until_sent(tty, info->timeout);
 864
 865         if (tty->driver->flush_buffer)
 866                 tty->driver->flush_buffer(tty);
 867
 868         if (tty->ldisc.flush_buffer)
 869                 tty->ldisc.flush_buffer(tty);
 870
 871         shutdown(info);
 872
 873         tty->closing = 0;
 874         info->tty = 0;
 875
 876         if (info->blocked_open) {
 877                 if (info->close_delay) {
 878                         set_current_state(TASK_INTERRUPTIBLE);
 879                         schedule_timeout(info->close_delay);
 880                 }
 881                 wake_up_interruptible(&info->open_wait);
 882         }
 883
 884         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 885
 886         wake_up_interruptible(&info->close_wait);
 887
 888 cleanup:
 889         if (debug_level >= DEBUG_LEVEL_INFO)
 890                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 891                         tty->driver->name, info->count);
 892 }
 893
 894 /* Called by tty_hangup() when a hangup is signaled.
 895  * This is the same as closing all open descriptors for the port.
 896  */
 897 static void hangup(struct tty_struct *tty)
 898 {
 899         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 900
 901         if (debug_level >= DEBUG_LEVEL_INFO)
 902                 printk("%s(%d):%s hangup()\n",
 903                          __FILE__,__LINE__, info->device_name );
 904
 905         if (sanity_check(info, tty->name, "hangup"))
 906                 return;
 907
 908         flush_buffer(tty);
 909         shutdown(info);
 910
 911         info->count = 0;
 912         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 913         info->tty = 0;
 914
 915         wake_up_interruptible(&info->open_wait);
 916 }
 917
 918 /* Set new termios settings
 919  */
 920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 921 {
 922         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 923         unsigned long flags;
 924
 925         if (debug_level >= DEBUG_LEVEL_INFO)
 926                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 927                         tty->driver->name );
 928
 929         /* just return if nothing has changed */
 930         if ((tty->termios->c_cflag == old_termios->c_cflag)
 931             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 932                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 933           return;
 934
 935         change_params(info);
 936
 937         /* Handle transition to B0 status */
 938         if (old_termios->c_cflag & CBAUD &&
 939             !(tty->termios->c_cflag & CBAUD)) {
 940                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 set_signals(info);
 943                 spin_unlock_irqrestore(&info->lock,flags);
 944         }
 945
 946         /* Handle transition away from B0 status */
 947         if (!(old_termios->c_cflag & CBAUD) &&
 948             tty->termios->c_cflag & CBAUD) {
 949                 info->serial_signals |= SerialSignal_DTR;
 950                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 951                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 952                         info->serial_signals |= SerialSignal_RTS;
 953                 }
 954                 spin_lock_irqsave(&info->lock,flags);
 955                 set_signals(info);
 956                 spin_unlock_irqrestore(&info->lock,flags);
 957         }
 958
 959         /* Handle turning off CRTSCTS */
 960         if (old_termios->c_cflag & CRTSCTS &&
 961             !(tty->termios->c_cflag & CRTSCTS)) {
 962                 tty->hw_stopped = 0;
 963                 tx_release(tty);
 964         }
 965 }
 966
 967 /* Send a block of data
 968  *
 969  * Arguments:
 970  *
 971  *      tty             pointer to tty information structure
 972  *      from_user       flag: 1 = from user process
 973  *      buf             pointer to buffer containing send data
 974  *      count           size of send data in bytes
 975  *
 976  * Return Value:        number of characters written
 977  */
 978 static int write(struct tty_struct *tty, int from_user,
 979                  const unsigned char *buf, int count)
 980 {
 981         int     c, ret = 0, err;
 982         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 983         unsigned long flags;
 984
 985         if (debug_level >= DEBUG_LEVEL_INFO)
 986                 printk("%s(%d):%s write() count=%d\n",
 987                        __FILE__,__LINE__,info->device_name,count);
 988
 989         if (sanity_check(info, tty->name, "write"))
 990                 goto cleanup;
 991
 992         if (!tty || !info->tx_buf)
 993                 goto cleanup;
 994
 995         if (info->params.mode == MGSL_MODE_HDLC) {
 996                 if (count > info->max_frame_size) {
 997                         ret = -EIO;
 998                         goto cleanup;
 999                 }
1000                 if (info->tx_active)
1001                         goto cleanup;
1002                 if (info->tx_count) {
1003                         /* send accumulated data from send_char() calls */
1004                         /* as frame and wait before accepting more data. */
1005                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006                         goto start;
1007                 }
1008                 if (!from_user) {
1009                         ret = info->tx_count = count;
1010                         tx_load_dma_buffer(info, buf, count);
1011                         goto start;
1012                 }
1013         }
1014
1015         for (;;) {
1016                 c = MIN(count,
1017                         MIN(info->max_frame_size - info->tx_count - 1,
1018                             info->max_frame_size - info->tx_put));
1019                 if (c <= 0)
1020                         break;
1021
1022                 if (from_user) {
1023                         COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1024                         if (err) {
1025                                 if (!ret)
1026                                         ret = -EFAULT;
1027                                 break;
1028                         }
1029                 } else
1030                         memcpy(info->tx_buf + info->tx_put, buf, c);
1031
1032                 spin_lock_irqsave(&info->lock,flags);
1033                 info->tx_put += c;
1034                 if (info->tx_put >= info->max_frame_size)
1035                         info->tx_put -= info->max_frame_size;
1036                 info->tx_count += c;
1037                 spin_unlock_irqrestore(&info->lock,flags);
1038
1039                 buf += c;
1040                 count -= c;
1041                 ret += c;
1042         }
1043
1044         if (info->params.mode == MGSL_MODE_HDLC) {
1045                 if (count) {
1046                         ret = info->tx_count = 0;
1047                         goto cleanup;
1048                 }
1049                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1050         }
1051 start:
1052         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1053                 spin_lock_irqsave(&info->lock,flags);
1054                 if (!info->tx_active)
1055                         tx_start(info);
1056                 spin_unlock_irqrestore(&info->lock,flags);
1057         }
1058
1059 cleanup:
1060         if (debug_level >= DEBUG_LEVEL_INFO)
1061                 printk( "%s(%d):%s write() returning=%d\n",
1062                         __FILE__,__LINE__,info->device_name,ret);
1063         return ret;
1064 }
1065
1066 /* Add a character to the transmit buffer.
1067  */
1068 static void put_char(struct tty_struct *tty, unsigned char ch)
1069 {
1070         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1071         unsigned long flags;
1072
1073         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1074                 printk( "%s(%d):%s put_char(%d)\n",
1075                         __FILE__,__LINE__,info->device_name,ch);
1076         }
1077
1078         if (sanity_check(info, tty->name, "put_char"))
1079                 return;
1080
1081         if (!tty || !info->tx_buf)
1082                 return;
1083
1084         spin_lock_irqsave(&info->lock,flags);
1085
1086         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1087              !info->tx_active ) {
1088
1089                 if (info->tx_count < info->max_frame_size - 1) {
1090                         info->tx_buf[info->tx_put++] = ch;
1091                         if (info->tx_put >= info->max_frame_size)
1092                                 info->tx_put -= info->max_frame_size;
1093                         info->tx_count++;
1094                 }
1095         }
1096
1097         spin_unlock_irqrestore(&info->lock,flags);
1098 }
1099
1100 /* Send a high-priority XON/XOFF character
1101  */
1102 static void send_xchar(struct tty_struct *tty, char ch)
1103 {
1104         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1105         unsigned long flags;
1106
1107         if (debug_level >= DEBUG_LEVEL_INFO)
1108                 printk("%s(%d):%s send_xchar(%d)\n",
1109                          __FILE__,__LINE__, info->device_name, ch );
1110
1111         if (sanity_check(info, tty->name, "send_xchar"))
1112                 return;
1113
1114         info->x_char = ch;
1115         if (ch) {
1116                 /* Make sure transmit interrupts are on */
1117                 spin_lock_irqsave(&info->lock,flags);
1118                 if (!info->tx_enabled)
1119                         tx_start(info);
1120                 spin_unlock_irqrestore(&info->lock,flags);
1121         }
1122 }
1123
1124 /* Wait until the transmitter is empty.
1125  */
1126 static void wait_until_sent(struct tty_struct *tty, int timeout)
1127 {
1128         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1129         unsigned long orig_jiffies, char_time;
1130
1131         if (!info )
1132                 return;
1133
1134         if (debug_level >= DEBUG_LEVEL_INFO)
1135                 printk("%s(%d):%s wait_until_sent() entry\n",
1136                          __FILE__,__LINE__, info->device_name );
1137
1138         if (sanity_check(info, tty->name, "wait_until_sent"))
1139                 return;
1140
1141         if (!(info->flags & ASYNC_INITIALIZED))
1142                 goto exit;
1143
1144         orig_jiffies = jiffies;
1145
1146         /* Set check interval to 1/5 of estimated time to
1147          * send a character, and make it at least 1. The check
1148          * interval should also be less than the timeout.
1149          * Note: use tight timings here to satisfy the NIST-PCTS.
1150          */
1151
1152         if ( info->params.data_rate ) {
1153                 char_time = info->timeout/(32 * 5);
1154                 if (!char_time)
1155                         char_time++;
1156         } else
1157                 char_time = 1;
1158
1159         if (timeout)
1160                 char_time = MIN(char_time, timeout);
1161
1162         if ( info->params.mode == MGSL_MODE_HDLC ) {
1163                 while (info->tx_active) {
1164                         set_current_state(TASK_INTERRUPTIBLE);
1165                         schedule_timeout(char_time);
1166                         if (signal_pending(current))
1167                                 break;
1168                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1169                                 break;
1170                 }
1171         } else {
1172                 //TODO: determine if there is something similar to USC16C32
1173                 //      TXSTATUS_ALL_SENT status
1174                 while ( info->tx_active && info->tx_enabled) {
1175                         set_current_state(TASK_INTERRUPTIBLE);
1176                         schedule_timeout(char_time);
1177                         if (signal_pending(current))
1178                                 break;
1179                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1180                                 break;
1181                 }
1182         }
1183
1184 exit:
1185         if (debug_level >= DEBUG_LEVEL_INFO)
1186                 printk("%s(%d):%s wait_until_sent() exit\n",
1187                          __FILE__,__LINE__, info->device_name );
1188 }
1189
1190 /* Return the count of free bytes in transmit buffer
1191  */
1192 static int write_room(struct tty_struct *tty)
1193 {
1194         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1195         int ret;
1196
1197         if (sanity_check(info, tty->name, "write_room"))
1198                 return 0;
1199
1200         if (info->params.mode == MGSL_MODE_HDLC) {
1201                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1202         } else {
1203                 ret = info->max_frame_size - info->tx_count - 1;
1204                 if (ret < 0)
1205                         ret = 0;
1206         }
1207
1208         if (debug_level >= DEBUG_LEVEL_INFO)
1209                 printk("%s(%d):%s write_room()=%d\n",
1210                        __FILE__, __LINE__, info->device_name, ret);
1211
1212         return ret;
1213 }
1214
1215 /* enable transmitter and send remaining buffered characters
1216  */
1217 static void flush_chars(struct tty_struct *tty)
1218 {
1219         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1220         unsigned long flags;
1221
1222         if ( debug_level >= DEBUG_LEVEL_INFO )
1223                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1224                         __FILE__,__LINE__,info->device_name,info->tx_count);
1225
1226         if (sanity_check(info, tty->name, "flush_chars"))
1227                 return;
1228
1229         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1230             !info->tx_buf)
1231                 return;
1232
1233         if ( debug_level >= DEBUG_LEVEL_INFO )
1234                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1235                         __FILE__,__LINE__,info->device_name );
1236
1237         spin_lock_irqsave(&info->lock,flags);
1238
1239         if (!info->tx_active) {
1240                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1241                         info->tx_count ) {
1242                         /* operating in synchronous (frame oriented) mode */
1243                         /* copy data from circular tx_buf to */
1244                         /* transmit DMA buffer. */
1245                         tx_load_dma_buffer(info,
1246                                  info->tx_buf,info->tx_count);
1247                 }
1248                 tx_start(info);
1249         }
1250
1251         spin_unlock_irqrestore(&info->lock,flags);
1252 }
1253
1254 /* Discard all data in the send buffer
1255  */
1256 static void flush_buffer(struct tty_struct *tty)
1257 {
1258         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1259         unsigned long flags;
1260
1261         if (debug_level >= DEBUG_LEVEL_INFO)
1262                 printk("%s(%d):%s flush_buffer() entry\n",
1263                          __FILE__,__LINE__, info->device_name );
1264
1265         if (sanity_check(info, tty->name, "flush_buffer"))
1266                 return;
1267
1268         spin_lock_irqsave(&info->lock,flags);
1269         info->tx_count = info->tx_put = info->tx_get = 0;
1270         del_timer(&info->tx_timer);
1271         spin_unlock_irqrestore(&info->lock,flags);
1272
1273         wake_up_interruptible(&tty->write_wait);
1274         if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1275             tty->ldisc.write_wakeup)
1276                 (tty->ldisc.write_wakeup)(tty);
1277 }
1278
1279 /* throttle (stop) transmitter
1280  */
1281 static void tx_hold(struct tty_struct *tty)
1282 {
1283         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1284         unsigned long flags;
1285
1286         if (sanity_check(info, tty->name, "tx_hold"))
1287                 return;
1288
1289         if ( debug_level >= DEBUG_LEVEL_INFO )
1290                 printk("%s(%d):%s tx_hold()\n",
1291                         __FILE__,__LINE__,info->device_name);
1292
1293         spin_lock_irqsave(&info->lock,flags);
1294         if (info->tx_enabled)
1295                 tx_stop(info);
1296         spin_unlock_irqrestore(&info->lock,flags);
1297 }
1298
1299 /* release (start) transmitter
1300  */
1301 static void tx_release(struct tty_struct *tty)
1302 {
1303         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1304         unsigned long flags;
1305
1306         if (sanity_check(info, tty->name, "tx_release"))
1307                 return;
1308
1309         if ( debug_level >= DEBUG_LEVEL_INFO )
1310                 printk("%s(%d):%s tx_release()\n",
1311                         __FILE__,__LINE__,info->device_name);
1312
1313         spin_lock_irqsave(&info->lock,flags);
1314         if (!info->tx_enabled)
1315                 tx_start(info);
1316         spin_unlock_irqrestore(&info->lock,flags);
1317 }
1318
1319 /* Service an IOCTL request
1320  *
1321  * Arguments:
1322  *
1323  *      tty     pointer to tty instance data
1324  *      file    pointer to associated file object for device
1325  *      cmd     IOCTL command code
1326  *      arg     command argument/context
1327  *
1328  * Return Value:        0 if success, otherwise error code
1329  */
1330 static int ioctl(struct tty_struct *tty, struct file *file,
1331                  unsigned int cmd, unsigned long arg)
1332 {
1333         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1334         int error;
1335         struct mgsl_icount cnow;        /* kernel counter temps */
1336         struct serial_icounter_struct *p_cuser; /* user space */
1337         unsigned long flags;
1338
1339         if (debug_level >= DEBUG_LEVEL_INFO)
1340                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1341                         info->device_name, cmd );
1342
1343         if (sanity_check(info, tty->name, "ioctl"))
1344                 return -ENODEV;
1345
1346         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1347             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1348                 if (tty->flags & (1 << TTY_IO_ERROR))
1349                     return -EIO;
1350         }
1351
1352         switch (cmd) {
1353         case MGSL_IOCGPARAMS:
1354                 return get_params(info,(MGSL_PARAMS *)arg);
1355         case MGSL_IOCSPARAMS:
1356                 return set_params(info,(MGSL_PARAMS *)arg);
1357         case MGSL_IOCGTXIDLE:
1358                 return get_txidle(info,(int*)arg);
1359         case MGSL_IOCSTXIDLE:
1360                 return set_txidle(info,(int)arg);
1361         case MGSL_IOCTXENABLE:
1362                 return tx_enable(info,(int)arg);
1363         case MGSL_IOCRXENABLE:
1364                 return rx_enable(info,(int)arg);
1365         case MGSL_IOCTXABORT:
1366                 return tx_abort(info);
1367         case MGSL_IOCGSTATS:
1368                 return get_stats(info,(struct mgsl_icount*)arg);
1369         case MGSL_IOCWAITEVENT:
1370                 return wait_mgsl_event(info,(int*)arg);
1371         case MGSL_IOCLOOPTXDONE:
1372                 return 0; // TODO: Not supported, need to document
1373                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1374                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1375                  */
1376         case TIOCMIWAIT:
1377                 return modem_input_wait(info,(int)arg);
1378
1379                 /*
1380                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1381                  * Return: write counters to the user passed counter struct
1382                  * NB: both 1->0 and 0->1 transitions are counted except for
1383                  *     RI where only 0->1 is counted.
1384                  */
1385         case TIOCGICOUNT:
1386                 spin_lock_irqsave(&info->lock,flags);
1387                 cnow = info->icount;
1388                 spin_unlock_irqrestore(&info->lock,flags);
1389                 p_cuser = (struct serial_icounter_struct *) arg;
1390                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1397                 if (error) return error;
1398                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1399                 if (error) return error;
1400                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1401                 if (error) return error;
1402                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1403                 if (error) return error;
1404                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1405                 if (error) return error;
1406                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1407                 if (error) return error;
1408                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1409                 if (error) return error;
1410                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1411                 if (error) return error;
1412                 return 0;
1413         default:
1414                 return -ENOIOCTLCMD;
1415         }
1416         return 0;
1417 }
1418
1419 /*
1420  * /proc fs routines....
1421  */
1422
1423 static inline int line_info(char *buf, SLMP_INFO *info)
1424 {
1425         char    stat_buf[30];
1426         int     ret;
1427         unsigned long flags;
1428
1429         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1430                        "\tIRQ=%d MaxFrameSize=%u\n",
1431                 info->device_name,
1432                 info->phys_sca_base,
1433                 info->phys_memory_base,
1434                 info->phys_statctrl_base,
1435                 info->phys_lcr_base,
1436                 info->irq_level,
1437                 info->max_frame_size );
1438
1439         /* output current serial signal states */
1440         spin_lock_irqsave(&info->lock,flags);
1441         get_signals(info);
1442         spin_unlock_irqrestore(&info->lock,flags);
1443
1444         stat_buf[0] = 0;
1445         stat_buf[1] = 0;
1446         if (info->serial_signals & SerialSignal_RTS)
1447                 strcat(stat_buf, "|RTS");
1448         if (info->serial_signals & SerialSignal_CTS)
1449                 strcat(stat_buf, "|CTS");
1450         if (info->serial_signals & SerialSignal_DTR)
1451                 strcat(stat_buf, "|DTR");
1452         if (info->serial_signals & SerialSignal_DSR)
1453                 strcat(stat_buf, "|DSR");
1454         if (info->serial_signals & SerialSignal_DCD)
1455                 strcat(stat_buf, "|CD");
1456         if (info->serial_signals & SerialSignal_RI)
1457                 strcat(stat_buf, "|RI");
1458
1459         if (info->params.mode == MGSL_MODE_HDLC) {
1460                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1461                               info->icount.txok, info->icount.rxok);
1462                 if (info->icount.txunder)
1463                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1464                 if (info->icount.txabort)
1465                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1466                 if (info->icount.rxshort)
1467                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1468                 if (info->icount.rxlong)
1469                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1470                 if (info->icount.rxover)
1471                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1472                 if (info->icount.rxcrc)
1473                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1474         } else {
1475                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1476                               info->icount.tx, info->icount.rx);
1477                 if (info->icount.frame)
1478                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1479                 if (info->icount.parity)
1480                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1481                 if (info->icount.brk)
1482                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1483                 if (info->icount.overrun)
1484                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1485         }
1486
1487         /* Append serial signal status to end */
1488         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1489
1490         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1491          info->tx_active,info->bh_requested,info->bh_running,
1492          info->pending_bh);
1493
1494         return ret;
1495 }
1496
1497 /* Called to print information about devices
1498  */
1499 int read_proc(char *page, char **start, off_t off, int count,
1500               int *eof, void *data)
1501 {
1502         int len = 0, l;
1503         off_t   begin = 0;
1504         SLMP_INFO *info;
1505
1506         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1507
1508         info = synclinkmp_device_list;
1509         while( info ) {
1510                 l = line_info(page + len, info);
1511                 len += l;
1512                 if (len+begin > off+count)
1513                         goto done;
1514                 if (len+begin < off) {
1515                         begin += len;
1516                         len = 0;
1517                 }
1518                 info = info->next_device;
1519         }
1520
1521         *eof = 1;
1522 done:
1523         if (off >= len+begin)
1524                 return 0;
1525         *start = page + (off-begin);
1526         return ((count < begin+len-off) ? count : begin+len-off);
1527 }
1528
1529 /* Return the count of bytes in transmit buffer
1530  */
1531 static int chars_in_buffer(struct tty_struct *tty)
1532 {
1533         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1534
1535         if (sanity_check(info, tty->name, "chars_in_buffer"))
1536                 return 0;
1537
1538         if (debug_level >= DEBUG_LEVEL_INFO)
1539                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1540                        __FILE__, __LINE__, info->device_name, info->tx_count);
1541
1542         return info->tx_count;
1543 }
1544
1545 /* Signal remote device to throttle send data (our receive data)
1546  */
1547 static void throttle(struct tty_struct * tty)
1548 {
1549         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1550         unsigned long flags;
1551
1552         if (debug_level >= DEBUG_LEVEL_INFO)
1553                 printk("%s(%d):%s throttle() entry\n",
1554                          __FILE__,__LINE__, info->device_name );
1555
1556         if (sanity_check(info, tty->name, "throttle"))
1557                 return;
1558
1559         if (I_IXOFF(tty))
1560                 send_xchar(tty, STOP_CHAR(tty));
1561
1562         if (tty->termios->c_cflag & CRTSCTS) {
1563                 spin_lock_irqsave(&info->lock,flags);
1564                 info->serial_signals &= ~SerialSignal_RTS;
1565                 set_signals(info);
1566                 spin_unlock_irqrestore(&info->lock,flags);
1567         }
1568 }
1569
1570 /* Signal remote device to stop throttling send data (our receive data)
1571  */
1572 static void unthrottle(struct tty_struct * tty)
1573 {
1574         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1575         unsigned long flags;
1576
1577         if (debug_level >= DEBUG_LEVEL_INFO)
1578                 printk("%s(%d):%s unthrottle() entry\n",
1579                          __FILE__,__LINE__, info->device_name );
1580
1581         if (sanity_check(info, tty->name, "unthrottle"))
1582                 return;
1583
1584         if (I_IXOFF(tty)) {
1585                 if (info->x_char)
1586                         info->x_char = 0;
1587                 else
1588                         send_xchar(tty, START_CHAR(tty));
1589         }
1590
1591         if (tty->termios->c_cflag & CRTSCTS) {
1592                 spin_lock_irqsave(&info->lock,flags);
1593                 info->serial_signals |= SerialSignal_RTS;
1594                 set_signals(info);
1595                 spin_unlock_irqrestore(&info->lock,flags);
1596         }
1597 }
1598
1599 /* set or clear transmit break condition
1600  * break_state  -1=set break condition, 0=clear
1601  */
1602 static void set_break(struct tty_struct *tty, int break_state)
1603 {
1604         unsigned char RegValue;
1605         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1606         unsigned long flags;
1607
1608         if (debug_level >= DEBUG_LEVEL_INFO)
1609                 printk("%s(%d):%s set_break(%d)\n",
1610                          __FILE__,__LINE__, info->device_name, break_state);
1611
1612         if (sanity_check(info, tty->name, "set_break"))
1613                 return;
1614
1615         spin_lock_irqsave(&info->lock,flags);
1616         RegValue = read_reg(info, CTL);
1617         if (break_state == -1)
1618                 RegValue |= BIT3;
1619         else
1620                 RegValue &= ~BIT3;
1621         write_reg(info, CTL, RegValue);
1622         spin_unlock_irqrestore(&info->lock,flags);
1623 }
1624
1625 #ifdef CONFIG_SYNCLINK_SYNCPPP
1626
1627 /* syncppp support and callbacks */
1628
1629 static void cb_setup(struct net_device *dev)
1630 {
1631         dev->open = sppp_cb_open;
1632         dev->stop = sppp_cb_close;
1633         dev->hard_start_xmit = sppp_cb_tx;
1634         dev->do_ioctl = sppp_cb_ioctl;
1635         dev->get_stats = sppp_cb_net_stats;
1636         dev->tx_timeout = sppp_cb_tx_timeout;
1637         dev->watchdog_timeo = 10*HZ;
1638 }
1639
1640 static void sppp_init(SLMP_INFO *info)
1641 {
1642         struct net_device *d;
1643
1644         sprintf(info->netname,"mgslm%dp%d",info->adapter_num,info->port_num);
1645
1646         d = alloc_netdev(0, info->netname, cb_setup);
1647         if (!d) {
1648                 printk(KERN_WARNING "%s: alloc_netdev failed.\n",
1649                                                 info->netname);
1650                 return;
1651         }
1652
1653         info->if_ptr = &info->pppdev;
1654         info->netdev = info->pppdev.dev = d;
1655
1656         d->irq = info->irq_level;
1657         d->priv = info;
1658
1659         sppp_attach(&info->pppdev);
1660         cb_setup(d);
1661
1662         if (register_netdev(d)) {
1663                 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
1664                 sppp_detach(info->netdev);
1665                 info->netdev = NULL;
1666                 info->pppdev.dev = NULL;
1667                 free_netdev(d);
1668                 return;
1669         }
1670
1671         if (debug_level >= DEBUG_LEVEL_INFO)
1672                 printk("sppp_init(%s)\n",info->netname);
1673 }
1674
1675 static void sppp_delete(SLMP_INFO *info)
1676 {
1677         if (debug_level >= DEBUG_LEVEL_INFO)
1678                 printk("sppp_delete(%s)\n",info->netname);
1679         unregister_netdev(info->netdev);
1680         sppp_detach(info->netdev);
1681         free_netdev(info->netdev);
1682         info->netdev = NULL;
1683         info->pppdev.dev = NULL;
1684 }
1685
1686 static int sppp_cb_open(struct net_device *d)
1687 {
1688         SLMP_INFO *info = d->priv;
1689         int err;
1690         unsigned long flags;
1691
1692         if (debug_level >= DEBUG_LEVEL_INFO)
1693                 printk("sppp_cb_open(%s)\n",info->netname);
1694
1695         spin_lock_irqsave(&info->netlock, flags);
1696         if (info->count != 0 || info->netcount != 0) {
1697                 printk(KERN_WARNING "%s: sppp_cb_open returning busy\n", info->netname);
1698                 spin_unlock_irqrestore(&info->netlock, flags);
1699                 return -EBUSY;
1700         }
1701         info->netcount=1;
1702         spin_unlock_irqrestore(&info->netlock, flags);
1703
1704         /* claim resources and init adapter */
1705         if ((err = startup(info)) != 0)
1706                 goto open_fail;
1707
1708         /* allow syncppp module to do open processing */
1709         if ((err = sppp_open(d)) != 0) {
1710                 shutdown(info);
1711                 goto open_fail;
1712         }
1713
1714         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1715         program_hw(info);
1716
1717         d->trans_start = jiffies;
1718         netif_start_queue(d);
1719         return 0;
1720
1721 open_fail:
1722         spin_lock_irqsave(&info->netlock, flags);
1723         info->netcount=0;
1724         spin_unlock_irqrestore(&info->netlock, flags);
1725         return err;
1726 }
1727
1728 static void sppp_cb_tx_timeout(struct net_device *dev)
1729 {
1730         SLMP_INFO *info = dev->priv;
1731         unsigned long flags;
1732
1733         if (debug_level >= DEBUG_LEVEL_INFO)
1734                 printk("sppp_tx_timeout(%s)\n",info->netname);
1735
1736         info->netstats.tx_errors++;
1737         info->netstats.tx_aborted_errors++;
1738
1739         spin_lock_irqsave(&info->lock,flags);
1740         tx_stop(info);
1741         spin_unlock_irqrestore(&info->lock,flags);
1742
1743         netif_wake_queue(dev);
1744 }
1745
1746 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev)
1747 {
1748         SLMP_INFO *info = dev->priv;
1749         unsigned long flags;
1750
1751         if (debug_level >= DEBUG_LEVEL_INFO)
1752                 printk("sppp_tx(%s)\n",info->netname);
1753
1754         netif_stop_queue(dev);
1755
1756         info->tx_count = skb->len;
1757         tx_load_dma_buffer(info, skb->data, skb->len);
1758         info->netstats.tx_packets++;
1759         info->netstats.tx_bytes += skb->len;
1760         dev_kfree_skb(skb);
1761
1762         dev->trans_start = jiffies;
1763
1764         spin_lock_irqsave(&info->lock,flags);
1765         if (!info->tx_active)
1766                 tx_start(info);
1767         spin_unlock_irqrestore(&info->lock,flags);
1768
1769         return 0;
1770 }
1771
1772 static int sppp_cb_close(struct net_device *d)
1773 {
1774         SLMP_INFO *info = d->priv;
1775         unsigned long flags;
1776
1777         if (debug_level >= DEBUG_LEVEL_INFO)
1778                 printk("sppp_cb_close(%s)\n",info->netname);
1779
1780         /* shutdown adapter and release resources */
1781         shutdown(info);
1782
1783         /* allow syncppp to do close processing */
1784         sppp_close(d);
1785         netif_stop_queue(d);
1786
1787         spin_lock_irqsave(&info->netlock, flags);
1788         info->netcount=0;
1789         spin_unlock_irqrestore(&info->netlock, flags);
1790         return 0;
1791 }
1792
1793 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size)
1794 {
1795         struct sk_buff *skb = dev_alloc_skb(size);
1796         if (debug_level >= DEBUG_LEVEL_INFO)
1797                 printk("sppp_rx_done(%s)\n",info->netname);
1798         if (skb == NULL) {
1799                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1800                         info->netname);
1801                 info->netstats.rx_dropped++;
1802                 return;
1803         }
1804
1805         memcpy(skb_put(skb, size),buf,size);
1806
1807         skb->protocol = htons(ETH_P_WAN_PPP);
1808         skb->dev = info->netdev;
1809         skb->mac.raw = skb->data;
1810         info->netstats.rx_packets++;
1811         info->netstats.rx_bytes += size;
1812         netif_rx(skb);
1813         info->netdev->trans_start = jiffies;
1814 }
1815
1816 static void sppp_tx_done(SLMP_INFO *info)
1817 {
1818         if (netif_queue_stopped(info->netdev))
1819             netif_wake_queue(info->netdev);
1820 }
1821
1822 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev)
1823 {
1824         SLMP_INFO *info = dev->priv;
1825         if (debug_level >= DEBUG_LEVEL_INFO)
1826                 printk("net_stats(%s)\n",info->netname);
1827         return &info->netstats;
1828 }
1829
1830 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1831 {
1832         SLMP_INFO *info = dev->priv;
1833         if (debug_level >= DEBUG_LEVEL_INFO)
1834                 printk("%s(%d):ioctl %s cmd=%08X\n", __FILE__,__LINE__,
1835                         info->netname, cmd );
1836         return sppp_do_ioctl(dev, ifr, cmd);
1837 }
1838
1839 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
1840
1841
1842 /* Return next bottom half action to perform.
1843  * Return Value:        BH action code or 0 if nothing to do.
1844  */
1845 int bh_action(SLMP_INFO *info)
1846 {
1847         unsigned long flags;
1848         int rc = 0;
1849
1850         spin_lock_irqsave(&info->lock,flags);
1851
1852         if (info->pending_bh & BH_RECEIVE) {
1853                 info->pending_bh &= ~BH_RECEIVE;
1854                 rc = BH_RECEIVE;
1855         } else if (info->pending_bh & BH_TRANSMIT) {
1856                 info->pending_bh &= ~BH_TRANSMIT;
1857                 rc = BH_TRANSMIT;
1858         } else if (info->pending_bh & BH_STATUS) {
1859                 info->pending_bh &= ~BH_STATUS;
1860                 rc = BH_STATUS;
1861         }
1862
1863         if (!rc) {
1864                 /* Mark BH routine as complete */
1865                 info->bh_running   = 0;
1866                 info->bh_requested = 0;
1867         }
1868
1869         spin_unlock_irqrestore(&info->lock,flags);
1870
1871         return rc;
1872 }
1873
1874 /* Perform bottom half processing of work items queued by ISR.
1875  */
1876 void bh_handler(void* Context)
1877 {
1878         SLMP_INFO *info = (SLMP_INFO*)Context;
1879         int action;
1880
1881         if (!info)
1882                 return;
1883
1884         if ( debug_level >= DEBUG_LEVEL_BH )
1885                 printk( "%s(%d):%s bh_handler() entry\n",
1886                         __FILE__,__LINE__,info->device_name);
1887
1888         info->bh_running = 1;
1889
1890         while((action = bh_action(info)) != 0) {
1891
1892                 /* Process work item */
1893                 if ( debug_level >= DEBUG_LEVEL_BH )
1894                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
1895                                 __FILE__,__LINE__,info->device_name, action);
1896
1897                 switch (action) {
1898
1899                 case BH_RECEIVE:
1900                         bh_receive(info);
1901                         break;
1902                 case BH_TRANSMIT:
1903                         bh_transmit(info);
1904                         break;
1905                 case BH_STATUS:
1906                         bh_status(info);
1907                         break;
1908                 default:
1909                         /* unknown work item ID */
1910                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
1911                                 __FILE__,__LINE__,info->device_name,action);
1912                         break;
1913                 }
1914         }
1915
1916         if ( debug_level >= DEBUG_LEVEL_BH )
1917                 printk( "%s(%d):%s bh_handler() exit\n",
1918                         __FILE__,__LINE__,info->device_name);
1919 }
1920
1921 void bh_receive(SLMP_INFO *info)
1922 {
1923         if ( debug_level >= DEBUG_LEVEL_BH )
1924                 printk( "%s(%d):%s bh_receive()\n",
1925                         __FILE__,__LINE__,info->device_name);
1926
1927         while( rx_get_frame(info) );
1928 }
1929
1930 void bh_transmit(SLMP_INFO *info)
1931 {
1932         struct tty_struct *tty = info->tty;
1933
1934         if ( debug_level >= DEBUG_LEVEL_BH )
1935                 printk( "%s(%d):%s bh_transmit() entry\n",
1936                         __FILE__,__LINE__,info->device_name);
1937
1938         if (tty) {
1939                 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1940                     tty->ldisc.write_wakeup) {
1941                         if ( debug_level >= DEBUG_LEVEL_BH )
1942                                 printk( "%s(%d):%s calling ldisc.write_wakeup\n",
1943                                         __FILE__,__LINE__,info->device_name);
1944                         (tty->ldisc.write_wakeup)(tty);
1945                 }
1946                 wake_up_interruptible(&tty->write_wait);
1947         }
1948 }
1949
1950 void bh_status(SLMP_INFO *info)
1951 {
1952         if ( debug_level >= DEBUG_LEVEL_BH )
1953                 printk( "%s(%d):%s bh_status() entry\n",
1954                         __FILE__,__LINE__,info->device_name);
1955
1956         info->ri_chkcount = 0;
1957         info->dsr_chkcount = 0;
1958         info->dcd_chkcount = 0;
1959         info->cts_chkcount = 0;
1960 }
1961
1962 void isr_timer(SLMP_INFO * info)
1963 {
1964         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
1965
1966         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
1967         write_reg(info, IER2, 0);
1968
1969         /* TMCS, Timer Control/Status Register
1970          *
1971          * 07      CMF, Compare match flag (read only) 1=match
1972          * 06      ECMI, CMF Interrupt Enable: 0=disabled
1973          * 05      Reserved, must be 0
1974          * 04      TME, Timer Enable
1975          * 03..00  Reserved, must be 0
1976          *
1977          * 0000 0000
1978          */
1979         write_reg(info, (unsigned char)(timer + TMCS), 0);
1980
1981         info->irq_occurred = TRUE;
1982
1983         if ( debug_level >= DEBUG_LEVEL_ISR )
1984                 printk("%s(%d):%s isr_timer()\n",
1985                         __FILE__,__LINE__,info->device_name);
1986 }
1987
1988 void isr_rxint(SLMP_INFO * info)
1989 {
1990         struct tty_struct *tty = info->tty;
1991         struct  mgsl_icount *icount = &info->icount;
1992         unsigned char status = read_reg(info, SR1);
1993         unsigned char status2 = read_reg(info, SR2);
1994
1995         /* clear status bits */
1996         if ( status & (FLGD + IDLD + CDCD + BRKD) )
1997                 write_reg(info, SR1,
1998                                 (unsigned char)(status & (FLGD + IDLD + CDCD + BRKD)));
1999
2000         if ( status2 & OVRN )
2001                 write_reg(info, SR2, (unsigned char)(status2 & OVRN));
2002
2003         if ( debug_level >= DEBUG_LEVEL_ISR )
2004                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2005                         __FILE__,__LINE__,info->device_name,status,status2);
2006
2007         if (info->params.mode == MGSL_MODE_ASYNC) {
2008                 if (status & BRKD) {
2009                         icount->brk++;
2010
2011                         /* process break detection if tty control
2012                          * is not set to ignore it
2013                          */
2014                         if ( tty ) {
2015                                 if (!(status & info->ignore_status_mask1)) {
2016                                         if (info->read_status_mask1 & BRKD) {
2017                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2018                                                 if (info->flags & ASYNC_SAK)
2019                                                         do_SAK(tty);
2020                                         }
2021                                 }
2022                         }
2023                 }
2024         }
2025         else {
2026                 if (status & (FLGD|IDLD)) {
2027                         if (status & FLGD)
2028                                 info->icount.exithunt++;
2029                         else if (status & IDLD)
2030                                 info->icount.rxidle++;
2031                         wake_up_interruptible(&info->event_wait_q);
2032                 }
2033         }
2034
2035         if (status & CDCD) {
2036                 /* simulate a common modem status change interrupt
2037                  * for our handler
2038                  */
2039                 get_signals( info );
2040                 isr_io_pin(info,
2041                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2042         }
2043 }
2044
2045 /*
2046  * handle async rx data interrupts
2047  */
2048 void isr_rxrdy(SLMP_INFO * info)
2049 {
2050         u16 status;
2051         unsigned char DataByte;
2052         struct tty_struct *tty = info->tty;
2053         struct  mgsl_icount *icount = &info->icount;
2054
2055         if ( debug_level >= DEBUG_LEVEL_ISR )
2056                 printk("%s(%d):%s isr_rxrdy\n",
2057                         __FILE__,__LINE__,info->device_name);
2058
2059         while((status = read_reg(info,CST0)) & BIT0)
2060         {
2061                 DataByte = read_reg(info,TRB);
2062
2063                 if ( tty ) {
2064                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2065                                 continue;
2066
2067                         *tty->flip.char_buf_ptr = DataByte;
2068                         *tty->flip.flag_buf_ptr = 0;
2069                 }
2070
2071                 icount->rx++;
2072
2073                 if ( status & (PE + FRME + OVRN) ) {
2074                         printk("%s(%d):%s rxerr=%04X\n",
2075                                 __FILE__,__LINE__,info->device_name,status);
2076
2077                         /* update error statistics */
2078                         if (status & PE)
2079                                 icount->parity++;
2080                         else if (status & FRME)
2081                                 icount->frame++;
2082                         else if (status & OVRN)
2083                                 icount->overrun++;
2084
2085                         /* discard char if tty control flags say so */
2086                         if (status & info->ignore_status_mask2)
2087                                 continue;
2088
2089                         status &= info->read_status_mask2;
2090
2091                         if ( tty ) {
2092                                 if (status & PE)
2093                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2094                                 else if (status & FRME)
2095                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2096                                 if (status & OVRN) {
2097                                         /* Overrun is special, since it's
2098                                          * reported immediately, and doesn't
2099                                          * affect the current character
2100                                          */
2101                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2102                                                 tty->flip.count++;
2103                                                 tty->flip.flag_buf_ptr++;
2104                                                 tty->flip.char_buf_ptr++;
2105                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2106                                         }
2107                                 }
2108                         }
2109                 }       /* end of if (error) */
2110
2111                 if ( tty ) {
2112                         tty->flip.flag_buf_ptr++;
2113                         tty->flip.char_buf_ptr++;
2114                         tty->flip.count++;
2115                 }
2116         }
2117
2118         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2119                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2120                         __FILE__,__LINE__,info->device_name,
2121                         tty ? tty->flip.count : 0);
2122                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2123                         __FILE__,__LINE__,info->device_name,
2124                         icount->rx,icount->brk,icount->parity,
2125                         icount->frame,icount->overrun);
2126         }
2127
2128         if ( tty && tty->flip.count )
2129                 tty_flip_buffer_push(tty);
2130 }
2131
2132 void isr_txeom(SLMP_INFO * info, unsigned char status)
2133 {
2134         if ( debug_level >= DEBUG_LEVEL_ISR )
2135                 printk("%s(%d):%s isr_txeom status=%02x\n",
2136                         __FILE__,__LINE__,info->device_name,status);
2137
2138         /* disable and clear MSCI interrupts */
2139         info->ie1_value &= ~(IDLE + UDRN);
2140         write_reg(info, IE1, info->ie1_value);
2141         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2142
2143         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2144         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2145         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2146
2147         if ( info->tx_active ) {
2148                 if (info->params.mode != MGSL_MODE_ASYNC) {
2149                         if (status & UDRN)
2150                                 info->icount.txunder++;
2151                         else if (status & IDLE)
2152                                 info->icount.txok++;
2153                 }
2154
2155                 info->tx_active = 0;
2156                 info->tx_count = info->tx_put = info->tx_get = 0;
2157
2158                 del_timer(&info->tx_timer);
2159
2160                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2161                         info->serial_signals &= ~SerialSignal_RTS;
2162                         info->drop_rts_on_tx_done = 0;
2163                         set_signals(info);
2164                 }
2165
2166 #ifdef CONFIG_SYNCLINK_SYNCPPP
2167                 if (info->netcount)
2168                         sppp_tx_done(info);
2169                 else
2170 #endif
2171                 {
2172                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2173                                 tx_stop(info);
2174                                 return;
2175                         }
2176                         info->pending_bh |= BH_TRANSMIT;
2177                 }
2178         }
2179 }
2180
2181
2182 /*
2183  * handle tx status interrupts
2184  */
2185 void isr_txint(SLMP_INFO * info)
2186 {
2187         unsigned char status = read_reg(info, SR1);
2188
2189         /* clear status bits */
2190         write_reg(info, SR1, (unsigned char)(status & (UDRN + IDLE + CCTS)));
2191
2192         if ( debug_level >= DEBUG_LEVEL_ISR )
2193                 printk("%s(%d):%s isr_txint status=%02x\n",
2194                         __FILE__,__LINE__,info->device_name,status);
2195
2196         if (status & (UDRN + IDLE))
2197                 isr_txeom(info, status);
2198
2199         if (status & CCTS) {
2200                 /* simulate a common modem status change interrupt
2201                  * for our handler
2202                  */
2203                 get_signals( info );
2204                 isr_io_pin(info,
2205                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2206
2207         }
2208 }
2209
2210 /*
2211  * handle async tx data interrupts
2212  */
2213 void isr_txrdy(SLMP_INFO * info)
2214 {
2215         if ( debug_level >= DEBUG_LEVEL_ISR )
2216                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2217                         __FILE__,__LINE__,info->device_name,info->tx_count);
2218
2219         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2220                 tx_stop(info);
2221                 return;
2222         }
2223
2224         if ( info->tx_count )
2225                 tx_load_fifo( info );
2226         else {
2227                 info->tx_active = 0;
2228                 info->ie0_value &= ~TXRDYE;
2229                 write_reg(info, IE0, info->ie0_value);
2230         }
2231
2232         if (info->tx_count < WAKEUP_CHARS)
2233                 info->pending_bh |= BH_TRANSMIT;
2234 }
2235
2236 void isr_rxdmaok(SLMP_INFO * info)
2237 {
2238         /* BIT7 = EOT (end of transfer)
2239          * BIT6 = EOM (end of message/frame)
2240          */
2241         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2242
2243         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2244         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2245
2246         if ( debug_level >= DEBUG_LEVEL_ISR )
2247                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2248                         __FILE__,__LINE__,info->device_name,status);
2249
2250         info->pending_bh |= BH_RECEIVE;
2251 }
2252
2253 void isr_rxdmaerror(SLMP_INFO * info)
2254 {
2255         /* BIT5 = BOF (buffer overflow)
2256          * BIT4 = COF (counter overflow)
2257          */
2258         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2259
2260         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2261         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2262
2263         if ( debug_level >= DEBUG_LEVEL_ISR )
2264                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2265                         __FILE__,__LINE__,info->device_name,status);
2266
2267         info->rx_overflow = TRUE;
2268         info->pending_bh |= BH_RECEIVE;
2269 }
2270
2271 void isr_txdmaok(SLMP_INFO * info)
2272 {
2273         /* BIT7 = EOT (end of transfer, used for async mode)
2274          * BIT6 = EOM (end of message/frame, used for sync mode)
2275          *
2276          * We don't look at DMA status because only EOT is enabled
2277          * and we always clear and disable all tx DMA IRQs.
2278          */
2279 //      unsigned char dma_status = read_reg(info,TXDMA + DSR) & 0xc0;
2280         unsigned char status_reg1 = read_reg(info, SR1);
2281
2282         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2283         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2284         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2285
2286         if ( debug_level >= DEBUG_LEVEL_ISR )
2287                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2288                         __FILE__,__LINE__,info->device_name,status_reg1);
2289
2290         /* If transmitter already idle, do end of frame processing,
2291          * otherwise enable interrupt for tx IDLE.
2292          */
2293         if (status_reg1 & IDLE)
2294                 isr_txeom(info, IDLE);
2295         else {
2296                 /* disable and clear underrun IRQ, enable IDLE interrupt */
2297                 info->ie1_value |= IDLE;
2298                 info->ie1_value &= ~UDRN;
2299                 write_reg(info, IE1, info->ie1_value);
2300
2301                 write_reg(info, SR1, UDRN);
2302         }
2303 }
2304
2305 void isr_txdmaerror(SLMP_INFO * info)
2306 {
2307         /* BIT5 = BOF (buffer overflow)
2308          * BIT4 = COF (counter overflow)
2309          */
2310         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2311
2312         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2313         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2314
2315         if ( debug_level >= DEBUG_LEVEL_ISR )
2316                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2317                         __FILE__,__LINE__,info->device_name,status);
2318 }
2319
2320 /* handle input serial signal changes
2321  */
2322 void isr_io_pin( SLMP_INFO *info, u16 status )
2323 {
2324         struct  mgsl_icount *icount;
2325
2326         if ( debug_level >= DEBUG_LEVEL_ISR )
2327                 printk("%s(%d):isr_io_pin status=%04X\n",
2328                         __FILE__,__LINE__,status);
2329
2330         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2331                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2332                 icount = &info->icount;
2333                 /* update input line counters */
2334                 if (status & MISCSTATUS_RI_LATCHED) {
2335                         icount->rng++;
2336                         if ( status & SerialSignal_RI )
2337                                 info->input_signal_events.ri_up++;
2338                         else
2339                                 info->input_signal_events.ri_down++;
2340                 }
2341                 if (status & MISCSTATUS_DSR_LATCHED) {
2342                         icount->dsr++;
2343                         if ( status & SerialSignal_DSR )
2344                                 info->input_signal_events.dsr_up++;
2345                         else
2346                                 info->input_signal_events.dsr_down++;
2347                 }
2348                 if (status & MISCSTATUS_DCD_LATCHED) {
2349                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2350                                 info->ie1_value &= ~CDCD;
2351                                 write_reg(info, IE1, info->ie1_value);
2352                         }
2353                         icount->dcd++;
2354                         if (status & SerialSignal_DCD) {
2355                                 info->input_signal_events.dcd_up++;
2356 #ifdef CONFIG_SYNCLINK_SYNCPPP
2357                                 if (info->netcount)
2358                                         sppp_reopen(info->netdev);
2359 #endif
2360                         } else
2361                                 info->input_signal_events.dcd_down++;
2362                 }
2363                 if (status & MISCSTATUS_CTS_LATCHED)
2364                 {
2365                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2366                                 info->ie1_value &= ~CCTS;
2367                                 write_reg(info, IE1, info->ie1_value);
2368                         }
2369                         icount->cts++;
2370                         if ( status & SerialSignal_CTS )
2371                                 info->input_signal_events.cts_up++;
2372                         else
2373                                 info->input_signal_events.cts_down++;
2374                 }
2375                 wake_up_interruptible(&info->status_event_wait_q);
2376                 wake_up_interruptible(&info->event_wait_q);
2377
2378                 if ( (info->flags & ASYNC_CHECK_CD) &&
2379                      (status & MISCSTATUS_DCD_LATCHED) ) {
2380                         if ( debug_level >= DEBUG_LEVEL_ISR )
2381                                 printk("%s CD now %s...", info->device_name,
2382                                        (status & SerialSignal_DCD) ? "on" : "off");
2383                         if (status & SerialSignal_DCD)
2384                                 wake_up_interruptible(&info->open_wait);
2385                         else {
2386                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2387                                         printk("doing serial hangup...");
2388                                 if (info->tty)
2389                                         tty_hangup(info->tty);
2390                         }
2391                 }
2392
2393                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2394                      (status & MISCSTATUS_CTS_LATCHED) ) {
2395                         if ( info->tty ) {
2396                                 if (info->tty->hw_stopped) {
2397                                         if (status & SerialSignal_CTS) {
2398                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2399                                                         printk("CTS tx start...");
2400                                                 info->tty->hw_stopped = 0;
2401                                                 tx_start(info);
2402                                                 info->pending_bh |= BH_TRANSMIT;
2403                                                 return;
2404                                         }
2405                                 } else {
2406                                         if (!(status & SerialSignal_CTS)) {
2407                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2408                                                         printk("CTS tx stop...");
2409                                                 info->tty->hw_stopped = 1;
2410                                                 tx_stop(info);
2411                                         }
2412                                 }
2413                         }
2414                 }
2415         }
2416
2417         info->pending_bh |= BH_STATUS;
2418 }
2419
2420 /* Interrupt service routine entry point.
2421  *
2422  * Arguments:
2423  *      irq             interrupt number that caused interrupt
2424  *      dev_id          device ID supplied during interrupt registration
2425  *      regs            interrupted processor context
2426  */
2427 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2428                                         struct pt_regs *regs)
2429 {
2430         SLMP_INFO * info;
2431         unsigned char status, status0, status1=0;
2432         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2433         unsigned char timerstatus0, timerstatus1=0;
2434         unsigned char shift;
2435         unsigned int i;
2436         unsigned short tmp;
2437
2438         if ( debug_level >= DEBUG_LEVEL_ISR )
2439                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2440                         __FILE__,__LINE__,irq);
2441
2442         info = (SLMP_INFO *)dev_id;
2443         if (!info)
2444                 return IRQ_NONE;
2445
2446         spin_lock(&info->lock);
2447
2448         for(;;) {
2449
2450                 /* get status for SCA0 (ports 0-1) */
2451                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2452                 status0 = (unsigned char)tmp;
2453                 dmastatus0 = (unsigned char)(tmp>>8);
2454                 timerstatus0 = read_reg(info, ISR2);
2455
2456                 if ( debug_level >= DEBUG_LEVEL_ISR )
2457                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2458                                 __FILE__,__LINE__,info->device_name,
2459                                 status0,dmastatus0,timerstatus0);
2460
2461                 if (info->port_count == 4) {
2462                         /* get status for SCA1 (ports 2-3) */
2463                         tmp = read_reg16(info->port_array[2], ISR0);
2464                         status1 = (unsigned char)tmp;
2465                         dmastatus1 = (unsigned char)(tmp>>8);
2466                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2467
2468                         if ( debug_level >= DEBUG_LEVEL_ISR )
2469                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2470                                         __FILE__,__LINE__,info->device_name,
2471                                         status1,dmastatus1,timerstatus1);
2472                 }
2473
2474                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2475                          !status1 && !dmastatus1 && !timerstatus1)
2476                         break;
2477
2478                 for(i=0; i < info->port_count ; i++) {
2479                         if (info->port_array[i] == NULL)
2480                                 continue;
2481                         if (i < 2) {
2482                                 status = status0;
2483                                 dmastatus = dmastatus0;
2484                         } else {
2485                                 status = status1;
2486                                 dmastatus = dmastatus1;
2487                         }
2488
2489                         shift = i & 1 ? 4 :0;
2490
2491                         if (status & BIT0 << shift)
2492                                 isr_rxrdy(info->port_array[i]);
2493                         if (status & BIT1 << shift)
2494                                 isr_txrdy(info->port_array[i]);
2495                         if (status & BIT2 << shift)
2496                                 isr_rxint(info->port_array[i]);
2497                         if (status & BIT3 << shift)
2498                                 isr_txint(info->port_array[i]);
2499
2500                         if (dmastatus & BIT0 << shift)
2501                                 isr_rxdmaerror(info->port_array[i]);
2502                         if (dmastatus & BIT1 << shift)
2503                                 isr_rxdmaok(info->port_array[i]);
2504                         if (dmastatus & BIT2 << shift)
2505                                 isr_txdmaerror(info->port_array[i]);
2506                         if (dmastatus & BIT3 << shift)
2507                                 isr_txdmaok(info->port_array[i]);
2508                 }
2509
2510                 if (timerstatus0 & (BIT5 | BIT4))
2511                         isr_timer(info->port_array[0]);
2512                 if (timerstatus0 & (BIT7 | BIT6))
2513                         isr_timer(info->port_array[1]);
2514                 if (timerstatus1 & (BIT5 | BIT4))
2515                         isr_timer(info->port_array[2]);
2516                 if (timerstatus1 & (BIT7 | BIT6))
2517                         isr_timer(info->port_array[3]);
2518         }
2519
2520         for(i=0; i < info->port_count ; i++) {
2521                 SLMP_INFO * port = info->port_array[i];
2522
2523                 /* Request bottom half processing if there's something
2524                  * for it to do and the bh is not already running.
2525                  *
2526                  * Note: startup adapter diags require interrupts.
2527                  * do not request bottom half processing if the
2528                  * device is not open in a normal mode.
2529                  */
2530                 if ( port && (port->count || port->netcount) &&
2531                      port->pending_bh && !port->bh_running &&
2532                      !port->bh_requested ) {
2533                         if ( debug_level >= DEBUG_LEVEL_ISR )
2534                                 printk("%s(%d):%s queueing bh task.\n",
2535                                         __FILE__,__LINE__,port->device_name);
2536                         schedule_work(&port->task);
2537                         port->bh_requested = 1;
2538                 }
2539         }
2540
2541         spin_unlock(&info->lock);
2542
2543         if ( debug_level >= DEBUG_LEVEL_ISR )
2544                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2545                         __FILE__,__LINE__,irq);
2546         return IRQ_HANDLED;
2547 }
2548
2549 /* Initialize and start device.
2550  */
2551 static int startup(SLMP_INFO * info)
2552 {
2553         if ( debug_level >= DEBUG_LEVEL_INFO )
2554                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2555
2556         if (info->flags & ASYNC_INITIALIZED)
2557                 return 0;
2558
2559         if (!info->tx_buf) {
2560                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2561                 if (!info->tx_buf) {
2562                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2563                                 __FILE__,__LINE__,info->device_name);
2564                         return -ENOMEM;
2565                 }
2566         }
2567
2568         info->pending_bh = 0;
2569
2570         /* program hardware for current parameters */
2571         reset_port(info);
2572
2573         change_params(info);
2574
2575         info->status_timer.expires = jiffies + jiffies_from_ms(10);
2576         add_timer(&info->status_timer);
2577
2578         if (info->tty)
2579                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2580
2581         info->flags |= ASYNC_INITIALIZED;
2582
2583         return 0;
2584 }
2585
2586 /* Called by close() and hangup() to shutdown hardware
2587  */
2588 static void shutdown(SLMP_INFO * info)
2589 {
2590         unsigned long flags;
2591
2592         if (!(info->flags & ASYNC_INITIALIZED))
2593                 return;
2594
2595         if (debug_level >= DEBUG_LEVEL_INFO)
2596                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2597                          __FILE__,__LINE__, info->device_name );
2598
2599         /* clear status wait queue because status changes */
2600         /* can't happen after shutting down the hardware */
2601         wake_up_interruptible(&info->status_event_wait_q);
2602         wake_up_interruptible(&info->event_wait_q);
2603
2604         del_timer(&info->tx_timer);
2605         del_timer(&info->status_timer);
2606
2607         if (info->tx_buf) {
2608                 kfree(info->tx_buf);
2609                 info->tx_buf = 0;
2610         }
2611
2612         spin_lock_irqsave(&info->lock,flags);
2613
2614         reset_port(info);
2615
2616         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2617                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2618                 set_signals(info);
2619         }
2620
2621         spin_unlock_irqrestore(&info->lock,flags);
2622
2623         if (info->tty)
2624                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2625
2626         info->flags &= ~ASYNC_INITIALIZED;
2627 }
2628
2629 static void program_hw(SLMP_INFO *info)
2630 {
2631         unsigned long flags;
2632
2633         spin_lock_irqsave(&info->lock,flags);
2634
2635         rx_stop(info);
2636         tx_stop(info);
2637
2638         info->tx_count = info->tx_put = info->tx_get = 0;
2639
2640         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2641                 hdlc_mode(info);
2642         else
2643                 async_mode(info);
2644
2645         set_signals(info);
2646
2647         info->dcd_chkcount = 0;
2648         info->cts_chkcount = 0;
2649         info->ri_chkcount = 0;
2650         info->dsr_chkcount = 0;
2651
2652         info->ie1_value |= (CDCD|CCTS);
2653         write_reg(info, IE1, info->ie1_value);
2654
2655         get_signals(info);
2656
2657         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2658                 rx_start(info);
2659
2660         spin_unlock_irqrestore(&info->lock,flags);
2661 }
2662
2663 /* Reconfigure adapter based on new parameters
2664  */
2665 static void change_params(SLMP_INFO *info)
2666 {
2667         unsigned cflag;
2668         int bits_per_char;
2669
2670         if (!info->tty || !info->tty->termios)
2671                 return;
2672
2673         if (debug_level >= DEBUG_LEVEL_INFO)
2674                 printk("%s(%d):%s change_params()\n",
2675                          __FILE__,__LINE__, info->device_name );
2676
2677         cflag = info->tty->termios->c_cflag;
2678
2679         /* if B0 rate (hangup) specified then negate DTR and RTS */
2680         /* otherwise assert DTR and RTS */
2681         if (cflag & CBAUD)
2682                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2683         else
2684                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2685
2686         /* byte size and parity */
2687
2688         switch (cflag & CSIZE) {
2689               case CS5: info->params.data_bits = 5; break;
2690               case CS6: info->params.data_bits = 6; break;
2691               case CS7: info->params.data_bits = 7; break;
2692               case CS8: info->params.data_bits = 8; break;
2693               /* Never happens, but GCC is too dumb to figure it out */
2694               default:  info->params.data_bits = 7; break;
2695               }
2696
2697         if (cflag & CSTOPB)
2698                 info->params.stop_bits = 2;
2699         else
2700                 info->params.stop_bits = 1;
2701
2702         info->params.parity = ASYNC_PARITY_NONE;
2703         if (cflag & PARENB) {
2704                 if (cflag & PARODD)
2705                         info->params.parity = ASYNC_PARITY_ODD;
2706                 else
2707                         info->params.parity = ASYNC_PARITY_EVEN;
2708 #ifdef CMSPAR
2709                 if (cflag & CMSPAR)
2710                         info->params.parity = ASYNC_PARITY_SPACE;
2711 #endif
2712         }
2713
2714         /* calculate number of jiffies to transmit a full
2715          * FIFO (32 bytes) at specified data rate
2716          */
2717         bits_per_char = info->params.data_bits +
2718                         info->params.stop_bits + 1;
2719
2720         /* if port data rate is set to 460800 or less then
2721          * allow tty settings to override, otherwise keep the
2722          * current data rate.
2723          */
2724         if (info->params.data_rate <= 460800) {
2725                 info->params.data_rate = tty_get_baud_rate(info->tty);
2726         }
2727
2728         if ( info->params.data_rate ) {
2729                 info->timeout = (32*HZ*bits_per_char) /
2730                                 info->params.data_rate;
2731         }
2732         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2733
2734         if (cflag & CRTSCTS)
2735                 info->flags |= ASYNC_CTS_FLOW;
2736         else
2737                 info->flags &= ~ASYNC_CTS_FLOW;
2738
2739         if (cflag & CLOCAL)
2740                 info->flags &= ~ASYNC_CHECK_CD;
2741         else
2742                 info->flags |= ASYNC_CHECK_CD;
2743
2744         /* process tty input control flags */
2745
2746         info->read_status_mask2 = OVRN;
2747         if (I_INPCK(info->tty))
2748                 info->read_status_mask2 |= PE | FRME;
2749         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2750                 info->read_status_mask1 |= BRKD;
2751         if (I_IGNPAR(info->tty))
2752                 info->ignore_status_mask2 |= PE | FRME;
2753         if (I_IGNBRK(info->tty)) {
2754                 info->ignore_status_mask1 |= BRKD;
2755                 /* If ignoring parity and break indicators, ignore
2756                  * overruns too.  (For real raw support).
2757                  */
2758                 if (I_IGNPAR(info->tty))
2759                         info->ignore_status_mask2 |= OVRN;
2760         }
2761
2762         program_hw(info);
2763 }
2764
2765 static int get_stats(SLMP_INFO * info, struct mgsl_icount *user_icount)
2766 {
2767         int err;
2768
2769         if (debug_level >= DEBUG_LEVEL_INFO)
2770                 printk("%s(%d):%s get_params()\n",
2771                          __FILE__,__LINE__, info->device_name);
2772
2773         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2774         if (err) {
2775                 if ( debug_level >= DEBUG_LEVEL_INFO )
2776                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2777                                 __FILE__,__LINE__,info->device_name);
2778                 return -EFAULT;
2779         }
2780
2781         return 0;
2782 }
2783
2784 static int get_params(SLMP_INFO * info, MGSL_PARAMS *user_params)
2785 {
2786         int err;
2787         if (debug_level >= DEBUG_LEVEL_INFO)
2788                 printk("%s(%d):%s get_params()\n",
2789                          __FILE__,__LINE__, info->device_name);
2790
2791         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2792         if (err) {
2793                 if ( debug_level >= DEBUG_LEVEL_INFO )
2794                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2795                                 __FILE__,__LINE__,info->device_name);
2796                 return -EFAULT;
2797         }
2798
2799         return 0;
2800 }
2801
2802 static int set_params(SLMP_INFO * info, MGSL_PARAMS *new_params)
2803 {
2804         unsigned long flags;
2805         MGSL_PARAMS tmp_params;
2806         int err;
2807
2808         if (debug_level >= DEBUG_LEVEL_INFO)
2809                 printk("%s(%d):%s set_params\n",
2810                         __FILE__,__LINE__,info->device_name );
2811         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2812         if (err) {
2813                 if ( debug_level >= DEBUG_LEVEL_INFO )
2814                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2815                                 __FILE__,__LINE__,info->device_name);
2816                 return -EFAULT;
2817         }
2818
2819         spin_lock_irqsave(&info->lock,flags);
2820         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2821         spin_unlock_irqrestore(&info->lock,flags);
2822
2823         change_params(info);
2824
2825         return 0;
2826 }
2827
2828 static int get_txidle(SLMP_INFO * info, int*idle_mode)
2829 {
2830         int err;
2831
2832         if (debug_level >= DEBUG_LEVEL_INFO)
2833                 printk("%s(%d):%s get_txidle()=%d\n",
2834                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2835
2836         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2837         if (err) {
2838                 if ( debug_level >= DEBUG_LEVEL_INFO )
2839                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2840                                 __FILE__,__LINE__,info->device_name);
2841                 return -EFAULT;
2842         }
2843
2844         return 0;
2845 }
2846
2847 static int set_txidle(SLMP_INFO * info, int idle_mode)
2848 {
2849         unsigned long flags;
2850
2851         if (debug_level >= DEBUG_LEVEL_INFO)
2852                 printk("%s(%d):%s set_txidle(%d)\n",
2853                         __FILE__,__LINE__,info->device_name, idle_mode );
2854
2855         spin_lock_irqsave(&info->lock,flags);
2856         info->idle_mode = idle_mode;
2857         tx_set_idle( info );
2858         spin_unlock_irqrestore(&info->lock,flags);
2859         return 0;
2860 }
2861
2862 static int tx_enable(SLMP_INFO * info, int enable)
2863 {
2864         unsigned long flags;
2865
2866         if (debug_level >= DEBUG_LEVEL_INFO)
2867                 printk("%s(%d):%s tx_enable(%d)\n",
2868                         __FILE__,__LINE__,info->device_name, enable);
2869
2870         spin_lock_irqsave(&info->lock,flags);
2871         if ( enable ) {
2872                 if ( !info->tx_enabled ) {
2873                         tx_start(info);
2874                 }
2875         } else {
2876                 if ( info->tx_enabled )
2877                         tx_stop(info);
2878         }
2879         spin_unlock_irqrestore(&info->lock,flags);
2880         return 0;
2881 }
2882
2883 /* abort send HDLC frame
2884  */
2885 static int tx_abort(SLMP_INFO * info)
2886 {
2887         unsigned long flags;
2888
2889         if (debug_level >= DEBUG_LEVEL_INFO)
2890                 printk("%s(%d):%s tx_abort()\n",
2891                         __FILE__,__LINE__,info->device_name);
2892
2893         spin_lock_irqsave(&info->lock,flags);
2894         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2895                 info->ie1_value &= ~UDRN;
2896                 info->ie1_value |= IDLE;
2897                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2898                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
2899
2900                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
2901                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2902
2903                 write_reg(info, CMD, TXABORT);
2904         }
2905         spin_unlock_irqrestore(&info->lock,flags);
2906         return 0;
2907 }
2908
2909 static int rx_enable(SLMP_INFO * info, int enable)
2910 {
2911         unsigned long flags;
2912
2913         if (debug_level >= DEBUG_LEVEL_INFO)
2914                 printk("%s(%d):%s rx_enable(%d)\n",
2915                         __FILE__,__LINE__,info->device_name,enable);
2916
2917         spin_lock_irqsave(&info->lock,flags);
2918         if ( enable ) {
2919                 if ( !info->rx_enabled )
2920                         rx_start(info);
2921         } else {
2922                 if ( info->rx_enabled )
2923                         rx_stop(info);
2924         }
2925         spin_unlock_irqrestore(&info->lock,flags);
2926         return 0;
2927 }
2928
2929 static int map_status(int signals)
2930 {
2931         /* Map status bits to API event bits */
2932
2933         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
2934                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
2935                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
2936                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
2937 }
2938
2939 /* wait for specified event to occur
2940  */
2941 static int wait_mgsl_event(SLMP_INFO * info, int * mask_ptr)
2942 {
2943         unsigned long flags;
2944         int s;
2945         int rc=0;
2946         struct mgsl_icount cprev, cnow;
2947         int events;
2948         int mask;
2949         struct  _input_signal_events oldsigs, newsigs;
2950         DECLARE_WAITQUEUE(wait, current);
2951
2952         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2953         if (rc) {
2954                 return  -EFAULT;
2955         }
2956
2957         if (debug_level >= DEBUG_LEVEL_INFO)
2958                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
2959                         __FILE__,__LINE__,info->device_name,mask);
2960
2961         spin_lock_irqsave(&info->lock,flags);
2962
2963         /* return immediately if state matches requested events */
2964         get_signals(info);
2965         s = map_status(info->serial_signals);
2966
2967         events = mask &
2968                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2969                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2970                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2971                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2972         if (events) {
2973                 spin_unlock_irqrestore(&info->lock,flags);
2974                 goto exit;
2975         }
2976
2977         /* save current irq counts */
2978         cprev = info->icount;
2979         oldsigs = info->input_signal_events;
2980
2981         /* enable hunt and idle irqs if needed */
2982         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2983                 unsigned char oldval = info->ie1_value;
2984                 unsigned char newval = oldval +
2985                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
2986                          (mask & MgslEvent_IdleReceived ? IDLE:0);
2987                 if ( oldval != newval ) {
2988                         info->ie1_value = newval;
2989                         write_reg(info, IE1, info->ie1_value);
2990                 }
2991         }
2992
2993         set_current_state(TASK_INTERRUPTIBLE);
2994         add_wait_queue(&info->event_wait_q, &wait);
2995
2996         spin_unlock_irqrestore(&info->lock,flags);
2997
2998         for(;;) {
2999                 schedule();
3000                 if (signal_pending(current)) {
3001                         rc = -ERESTARTSYS;
3002                         break;
3003                 }
3004
3005                 /* get current irq counts */
3006                 spin_lock_irqsave(&info->lock,flags);
3007                 cnow = info->icount;
3008                 newsigs = info->input_signal_events;
3009                 set_current_state(TASK_INTERRUPTIBLE);
3010                 spin_unlock_irqrestore(&info->lock,flags);
3011
3012                 /* if no change, wait aborted for some reason */
3013                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3014                     newsigs.dsr_down == oldsigs.dsr_down &&
3015                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3016                     newsigs.dcd_down == oldsigs.dcd_down &&
3017                     newsigs.cts_up   == oldsigs.cts_up   &&
3018                     newsigs.cts_down == oldsigs.cts_down &&
3019                     newsigs.ri_up    == oldsigs.ri_up    &&
3020                     newsigs.ri_down  == oldsigs.ri_down  &&
3021                     cnow.exithunt    == cprev.exithunt   &&
3022                     cnow.rxidle      == cprev.rxidle) {
3023                         rc = -EIO;
3024                         break;
3025                 }
3026
3027                 events = mask &
3028                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3029                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3030                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3031                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3032                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3033                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3034                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3035                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3036                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3037                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3038                 if (events)
3039                         break;
3040
3041                 cprev = cnow;
3042                 oldsigs = newsigs;
3043         }
3044
3045         remove_wait_queue(&info->event_wait_q, &wait);
3046         set_current_state(TASK_RUNNING);
3047
3048
3049         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3050                 spin_lock_irqsave(&info->lock,flags);
3051                 if (!waitqueue_active(&info->event_wait_q)) {
3052                         /* disable enable exit hunt mode/idle rcvd IRQs */
3053                         info->ie1_value &= ~(FLGD|IDLE);
3054                         write_reg(info, IE1, info->ie1_value);
3055                 }
3056                 spin_unlock_irqrestore(&info->lock,flags);
3057         }
3058 exit:
3059         if ( rc == 0 )
3060                 PUT_USER(rc, events, mask_ptr);
3061
3062         return rc;
3063 }
3064
3065 static int modem_input_wait(SLMP_INFO *info,int arg)
3066 {
3067         unsigned long flags;
3068         int rc;
3069         struct mgsl_icount cprev, cnow;
3070         DECLARE_WAITQUEUE(wait, current);
3071
3072         /* save current irq counts */
3073         spin_lock_irqsave(&info->lock,flags);
3074         cprev = info->icount;
3075         add_wait_queue(&info->status_event_wait_q, &wait);
3076         set_current_state(TASK_INTERRUPTIBLE);
3077         spin_unlock_irqrestore(&info->lock,flags);
3078
3079         for(;;) {
3080                 schedule();
3081                 if (signal_pending(current)) {
3082                         rc = -ERESTARTSYS;
3083                         break;
3084                 }
3085
3086                 /* get new irq counts */
3087                 spin_lock_irqsave(&info->lock,flags);
3088                 cnow = info->icount;
3089                 set_current_state(TASK_INTERRUPTIBLE);
3090                 spin_unlock_irqrestore(&info->lock,flags);
3091
3092                 /* if no change, wait aborted for some reason */
3093                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3094                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3095                         rc = -EIO;
3096                         break;
3097                 }
3098
3099                 /* check for change in caller specified modem input */
3100                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3101                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3102                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3103                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3104                         rc = 0;
3105                         break;
3106                 }
3107
3108                 cprev = cnow;
3109         }
3110         remove_wait_queue(&info->status_event_wait_q, &wait);
3111         set_current_state(TASK_RUNNING);
3112         return rc;
3113 }
3114
3115 /* return the state of the serial control and status signals
3116  */
3117 static int tiocmget(struct tty_struct *tty, struct file *file)
3118 {
3119         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3120         unsigned int result;
3121         unsigned long flags;
3122
3123         spin_lock_irqsave(&info->lock,flags);
3124         get_signals(info);
3125         spin_unlock_irqrestore(&info->lock,flags);
3126
3127         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3128                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3129                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3130                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3131                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3132                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3133
3134         if (debug_level >= DEBUG_LEVEL_INFO)
3135                 printk("%s(%d):%s tiocmget() value=%08X\n",
3136                          __FILE__,__LINE__, info->device_name, result );
3137         return result;
3138 }
3139
3140 /* set modem control signals (DTR/RTS)
3141  */
3142 static int tiocmset(struct tty_struct *tty, struct file *file,
3143                     unsigned int set, unsigned int clear)
3144 {
3145         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3146         unsigned long flags;
3147
3148         if (debug_level >= DEBUG_LEVEL_INFO)
3149                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3150                         __FILE__,__LINE__,info->device_name, set, clear);
3151
3152         if (set & TIOCM_RTS)
3153                 info->serial_signals |= SerialSignal_RTS;
3154         if (set & TIOCM_DTR)
3155                 info->serial_signals |= SerialSignal_DTR;
3156         if (clear & TIOCM_RTS)
3157                 info->serial_signals &= ~SerialSignal_RTS;
3158         if (clear & TIOCM_DTR)
3159                 info->serial_signals &= ~SerialSignal_DTR;
3160
3161         spin_lock_irqsave(&info->lock,flags);
3162         set_signals(info);
3163         spin_unlock_irqrestore(&info->lock,flags);
3164
3165         return 0;
3166 }
3167
3168
3169
3170 /* Block the current process until the specified port is ready to open.
3171  */
3172 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3173                            SLMP_INFO *info)
3174 {
3175         DECLARE_WAITQUEUE(wait, current);
3176         int             retval;
3177         int             do_clocal = 0, extra_count = 0;
3178         unsigned long   flags;
3179
3180         if (debug_level >= DEBUG_LEVEL_INFO)
3181                 printk("%s(%d):%s block_til_ready()\n",
3182                          __FILE__,__LINE__, tty->driver->name );
3183
3184         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3185                 /* nonblock mode is set or port is not enabled */
3186                 /* just verify that callout device is not active */
3187                 info->flags |= ASYNC_NORMAL_ACTIVE;
3188                 return 0;
3189         }
3190
3191         if (tty->termios->c_cflag & CLOCAL)
3192                 do_clocal = 1;
3193
3194         /* Wait for carrier detect and the line to become
3195          * free (i.e., not in use by the callout).  While we are in
3196          * this loop, info->count is dropped by one, so that
3197          * close() knows when to free things.  We restore it upon
3198          * exit, either normal or abnormal.
3199          */
3200
3201         retval = 0;
3202         add_wait_queue(&info->open_wait, &wait);
3203
3204         if (debug_level >= DEBUG_LEVEL_INFO)
3205                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3206                          __FILE__,__LINE__, tty->driver->name, info->count );
3207
3208         spin_lock_irqsave(&info->lock, flags);
3209         if (!tty_hung_up_p(filp)) {
3210                 extra_count = 1;
3211                 info->count--;
3212         }
3213         spin_unlock_irqrestore(&info->lock, flags);
3214         info->blocked_open++;
3215
3216         while (1) {
3217                 if ((tty->termios->c_cflag & CBAUD)) {
3218                         spin_lock_irqsave(&info->lock,flags);
3219                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3220                         set_signals(info);
3221                         spin_unlock_irqrestore(&info->lock,flags);
3222                 }
3223
3224                 set_current_state(TASK_INTERRUPTIBLE);
3225
3226                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3227                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3228                                         -EAGAIN : -ERESTARTSYS;
3229                         break;
3230                 }
3231
3232                 spin_lock_irqsave(&info->lock,flags);
3233                 get_signals(info);
3234                 spin_unlock_irqrestore(&info->lock,flags);
3235
3236                 if (!(info->flags & ASYNC_CLOSING) &&
3237                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3238                         break;
3239                 }
3240
3241                 if (signal_pending(current)) {
3242                         retval = -ERESTARTSYS;
3243                         break;
3244                 }
3245
3246                 if (debug_level >= DEBUG_LEVEL_INFO)
3247                         printk("%s(%d):%s block_til_ready() count=%d\n",
3248                                  __FILE__,__LINE__, tty->driver->name, info->count );
3249
3250                 schedule();
3251         }
3252
3253         set_current_state(TASK_RUNNING);
3254         remove_wait_queue(&info->open_wait, &wait);
3255
3256         if (extra_count)
3257                 info->count++;
3258         info->blocked_open--;
3259
3260         if (debug_level >= DEBUG_LEVEL_INFO)
3261                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3262                          __FILE__,__LINE__, tty->driver->name, info->count );
3263
3264         if (!retval)
3265                 info->flags |= ASYNC_NORMAL_ACTIVE;
3266
3267         return retval;
3268 }
3269
3270 int alloc_dma_bufs(SLMP_INFO *info)
3271 {
3272         unsigned short BuffersPerFrame;
3273         unsigned short BufferCount;
3274
3275         // Force allocation to start at 64K boundary for each port.
3276         // This is necessary because *all* buffer descriptors for a port
3277         // *must* be in the same 64K block. All descriptors on a port
3278         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3279         // into the CBP register.
3280         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3281
3282         /* Calculate the number of DMA buffers necessary to hold the */
3283         /* largest allowable frame size. Note: If the max frame size is */
3284         /* not an even multiple of the DMA buffer size then we need to */
3285         /* round the buffer count per frame up one. */
3286
3287         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3288         if ( info->max_frame_size % SCABUFSIZE )
3289                 BuffersPerFrame++;
3290
3291         /* calculate total number of data buffers (SCABUFSIZE) possible
3292          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3293          * for the descriptor list (BUFFERLISTSIZE).
3294          */
3295         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3296
3297         /* limit number of buffers to maximum amount of descriptors */
3298         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3299                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3300
3301         /* use enough buffers to transmit one max size frame */
3302         info->tx_buf_count = BuffersPerFrame + 1;
3303
3304         /* never use more than half the available buffers for transmit */
3305         if (info->tx_buf_count > (BufferCount/2))
3306                 info->tx_buf_count = BufferCount/2;
3307
3308         if (info->tx_buf_count > SCAMAXDESC)
3309                 info->tx_buf_count = SCAMAXDESC;
3310
3311         /* use remaining buffers for receive */
3312         info->rx_buf_count = BufferCount - info->tx_buf_count;
3313
3314         if (info->rx_buf_count > SCAMAXDESC)
3315                 info->rx_buf_count = SCAMAXDESC;
3316
3317         if ( debug_level >= DEBUG_LEVEL_INFO )
3318                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3319                         __FILE__,__LINE__, info->device_name,
3320                         info->tx_buf_count,info->rx_buf_count);
3321
3322         if ( alloc_buf_list( info ) < 0 ||
3323                 alloc_frame_bufs(info,
3324                                         info->rx_buf_list,
3325                                         info->rx_buf_list_ex,
3326                                         info->rx_buf_count) < 0 ||
3327                 alloc_frame_bufs(info,
3328                                         info->tx_buf_list,
3329                                         info->tx_buf_list_ex,
3330                                         info->tx_buf_count) < 0 ||
3331                 alloc_tmp_rx_buf(info) < 0 ) {
3332                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3333                         __FILE__,__LINE__, info->device_name);
3334                 return -ENOMEM;
3335         }
3336
3337         rx_reset_buffers( info );
3338
3339         return 0;
3340 }
3341
3342 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3343  */
3344 int alloc_buf_list(SLMP_INFO *info)
3345 {
3346         unsigned int i;
3347
3348         /* build list in adapter shared memory */
3349         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3350         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3351         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3352
3353         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3354
3355         /* Save virtual address pointers to the receive and */
3356         /* transmit buffer lists. (Receive 1st). These pointers will */
3357         /* be used by the processor to access the lists. */
3358         info->rx_buf_list = (SCADESC *)info->buffer_list;
3359
3360         info->tx_buf_list = (SCADESC *)info->buffer_list;
3361         info->tx_buf_list += info->rx_buf_count;
3362
3363         /* Build links for circular buffer entry lists (tx and rx)
3364          *
3365          * Note: links are physical addresses read by the SCA device
3366          * to determine the next buffer entry to use.
3367          */
3368
3369         for ( i = 0; i < info->rx_buf_count; i++ ) {
3370                 /* calculate and store physical address of this buffer entry */
3371                 info->rx_buf_list_ex[i].phys_entry =
3372                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3373
3374                 /* calculate and store physical address of */
3375                 /* next entry in cirular list of entries */
3376                 info->rx_buf_list[i].next = info->buffer_list_phys;
3377                 if ( i < info->rx_buf_count - 1 )
3378                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3379
3380                 info->rx_buf_list[i].length = SCABUFSIZE;
3381         }
3382
3383         for ( i = 0; i < info->tx_buf_count; i++ ) {
3384                 /* calculate and store physical address of this buffer entry */
3385                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3386                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3387
3388                 /* calculate and store physical address of */
3389                 /* next entry in cirular list of entries */
3390
3391                 info->tx_buf_list[i].next = info->buffer_list_phys +
3392                         info->rx_buf_count * sizeof(SCADESC);
3393
3394                 if ( i < info->tx_buf_count - 1 )
3395                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3396         }
3397
3398         return 0;
3399 }
3400
3401 /* Allocate the frame DMA buffers used by the specified buffer list.
3402  */
3403 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3404 {
3405         int i;
3406         unsigned long phys_addr;
3407
3408         for ( i = 0; i < count; i++ ) {
3409                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3410                 phys_addr = info->port_array[0]->last_mem_alloc;
3411                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3412
3413                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3414                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3415         }
3416
3417         return 0;
3418 }
3419
3420 void free_dma_bufs(SLMP_INFO *info)
3421 {
3422         info->buffer_list = NULL;
3423         info->rx_buf_list = NULL;
3424         info->tx_buf_list = NULL;
3425 }
3426
3427 /* allocate buffer large enough to hold max_frame_size.
3428  * This buffer is used to pass an assembled frame to the line discipline.
3429  */
3430 int alloc_tmp_rx_buf(SLMP_INFO *info)
3431 {
3432         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3433         if (info->tmp_rx_buf == NULL)
3434                 return -ENOMEM;
3435         return 0;
3436 }
3437
3438 void free_tmp_rx_buf(SLMP_INFO *info)
3439 {
3440         if (info->tmp_rx_buf)
3441                 kfree(info->tmp_rx_buf);
3442         info->tmp_rx_buf = NULL;
3443 }
3444
3445 int claim_resources(SLMP_INFO *info)
3446 {
3447         if (request_mem_region(info->phys_memory_base,0x40000,"synclinkmp") == NULL) {
3448                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3449                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3450                 goto errout;
3451         }
3452         else
3453                 info->shared_mem_requested = 1;
3454
3455         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3456                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3457                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3458                 goto errout;
3459         }
3460         else
3461                 info->lcr_mem_requested = 1;
3462
3463         if (request_mem_region(info->phys_sca_base + info->sca_offset,512,"synclinkmp") == NULL) {
3464                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3465                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3466                 goto errout;
3467         }
3468         else
3469                 info->sca_base_requested = 1;
3470
3471         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,16,"synclinkmp") == NULL) {
3472                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3473                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3474                 goto errout;
3475         }
3476         else
3477                 info->sca_statctrl_requested = 1;
3478
3479         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3480         if (!info->memory_base) {
3481                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3482                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3483                 goto errout;
3484         }
3485
3486         if ( !memory_test(info) ) {
3487                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3488                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3489                 goto errout;
3490         }
3491
3492         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
3493         if (!info->lcr_base) {
3494                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3495                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3496                 goto errout;
3497         }
3498
3499         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE) + info->sca_offset;
3500         if (!info->sca_base) {
3501                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3502                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3503                 goto errout;
3504         }
3505
3506         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE) + info->statctrl_offset;
3507         if (!info->statctrl_base) {
3508                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3509                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3510                 goto errout;
3511         }
3512
3513         return 0;
3514
3515 errout:
3516         release_resources( info );
3517         return -ENODEV;
3518 }
3519
3520 void release_resources(SLMP_INFO *info)
3521 {
3522         if ( debug_level >= DEBUG_LEVEL_INFO )
3523                 printk( "%s(%d):%s release_resources() entry\n",
3524                         __FILE__,__LINE__,info->device_name );
3525
3526         if ( info->irq_requested ) {
3527                 free_irq(info->irq_level, info);
3528                 info->irq_requested = 0;
3529         }
3530
3531         if ( info->shared_mem_requested ) {
3532                 release_mem_region(info->phys_memory_base,0x40000);
3533                 info->shared_mem_requested = 0;
3534         }
3535         if ( info->lcr_mem_requested ) {
3536                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3537                 info->lcr_mem_requested = 0;
3538         }
3539         if ( info->sca_base_requested ) {
3540                 release_mem_region(info->phys_sca_base + info->sca_offset,512);
3541                 info->sca_base_requested = 0;
3542         }
3543         if ( info->sca_statctrl_requested ) {
3544                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,16);
3545                 info->sca_statctrl_requested = 0;
3546         }
3547
3548         if (info->memory_base){
3549                 iounmap(info->memory_base);
3550                 info->memory_base = 0;
3551         }
3552
3553         if (info->sca_base) {
3554                 iounmap(info->sca_base - info->sca_offset);
3555                 info->sca_base=0;
3556         }
3557
3558         if (info->statctrl_base) {
3559                 iounmap(info->statctrl_base - info->statctrl_offset);
3560                 info->statctrl_base=0;
3561         }
3562
3563         if (info->lcr_base){
3564                 iounmap(info->lcr_base - info->lcr_offset);
3565                 info->lcr_base = 0;
3566         }
3567
3568         if ( debug_level >= DEBUG_LEVEL_INFO )
3569                 printk( "%s(%d):%s release_resources() exit\n",
3570                         __FILE__,__LINE__,info->device_name );
3571 }
3572
3573 /* Add the specified device instance data structure to the
3574  * global linked list of devices and increment the device count.
3575  */
3576 void add_device(SLMP_INFO *info)
3577 {
3578         info->next_device = NULL;
3579         info->line = synclinkmp_device_count;
3580         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3581
3582         if (info->line < MAX_DEVICES) {
3583                 if (maxframe[info->line])
3584                         info->max_frame_size = maxframe[info->line];
3585                 info->dosyncppp = dosyncppp[info->line];
3586         }
3587
3588         synclinkmp_device_count++;
3589
3590         if ( !synclinkmp_device_list )
3591                 synclinkmp_device_list = info;
3592         else {
3593                 SLMP_INFO *current_dev = synclinkmp_device_list;
3594                 while( current_dev->next_device )
3595                         current_dev = current_dev->next_device;
3596                 current_dev->next_device = info;
3597         }
3598
3599         if ( info->max_frame_size < 4096 )
3600                 info->max_frame_size = 4096;
3601         else if ( info->max_frame_size > 65535 )
3602                 info->max_frame_size = 65535;
3603
3604         printk( "SyncLink MultiPort %s: "
3605                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3606                 info->device_name,
3607                 info->phys_sca_base,
3608                 info->phys_memory_base,
3609                 info->phys_statctrl_base,
3610                 info->phys_lcr_base,
3611                 info->irq_level,
3612                 info->max_frame_size );
3613
3614 #ifdef CONFIG_SYNCLINK_SYNCPPP
3615         if (info->dosyncppp)
3616                 sppp_init(info);
3617 #endif
3618 }
3619
3620 /* Allocate and initialize a device instance structure
3621  *
3622  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3623  */
3624 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3625 {
3626         SLMP_INFO *info;
3627
3628         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3629                  GFP_KERNEL);
3630
3631         if (!info) {
3632                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3633                         __FILE__,__LINE__, adapter_num, port_num);
3634         } else {
3635                 memset(info, 0, sizeof(SLMP_INFO));
3636                 info->magic = MGSL_MAGIC;
3637                 INIT_WORK(&info->task, bh_handler, info);
3638                 info->max_frame_size = 4096;
3639                 info->close_delay = 5*HZ/10;
3640                 info->closing_wait = 30*HZ;
3641                 init_waitqueue_head(&info->open_wait);
3642                 init_waitqueue_head(&info->close_wait);
3643                 init_waitqueue_head(&info->status_event_wait_q);
3644                 init_waitqueue_head(&info->event_wait_q);
3645                 spin_lock_init(&info->netlock);
3646                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3647                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3648                 info->adapter_num = adapter_num;
3649                 info->port_num = port_num;
3650
3651                 /* Copy configuration info to device instance data */
3652                 info->irq_level = pdev->irq;
3653                 info->phys_lcr_base = pci_resource_start(pdev,0);
3654                 info->phys_sca_base = pci_resource_start(pdev,2);
3655                 info->phys_memory_base = pci_resource_start(pdev,3);
3656                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3657
3658                 /* Because veremap only works on page boundaries we must map
3659                  * a larger area than is actually implemented for the LCR
3660                  * memory range. We map a full page starting at the page boundary.
3661                  */
3662                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3663                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3664
3665                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3666                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3667
3668                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3669                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3670
3671                 info->bus_type = MGSL_BUS_TYPE_PCI;
3672                 info->irq_flags = SA_SHIRQ;
3673
3674                 init_timer(&info->tx_timer);
3675                 info->tx_timer.data = (unsigned long)info;
3676                 info->tx_timer.function = tx_timeout;
3677
3678                 init_timer(&info->status_timer);
3679                 info->status_timer.data = (unsigned long)info;
3680                 info->status_timer.function = status_timeout;
3681
3682                 /* Store the PCI9050 misc control register value because a flaw
3683                  * in the PCI9050 prevents LCR registers from being read if
3684                  * BIOS assigns an LCR base address with bit 7 set.
3685                  *
3686                  * Only the misc control register is accessed for which only
3687                  * write access is needed, so set an initial value and change
3688                  * bits to the device instance data as we write the value
3689                  * to the actual misc control register.
3690                  */
3691                 info->misc_ctrl_value = 0x087e4546;
3692
3693                 /* initial port state is unknown - if startup errors
3694                  * occur, init_error will be set to indicate the
3695                  * problem. Once the port is fully initialized,
3696                  * this value will be set to 0 to indicate the
3697                  * port is available.
3698                  */
3699                 info->init_error = -1;
3700         }
3701
3702         return info;
3703 }
3704
3705 void device_init(int adapter_num, struct pci_dev *pdev)
3706 {
3707         SLMP_INFO *port_array[SCA_MAX_PORTS];
3708         int port;
3709
3710         /* allocate device instances for up to SCA_MAX_PORTS devices */
3711         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3712                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3713                 if( port_array[port] == NULL ) {
3714                         for ( --port; port >= 0; --port )
3715                                 kfree(port_array[port]);
3716                         return;
3717                 }
3718         }
3719
3720         /* give copy of port_array to all ports and add to device list  */
3721         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3722                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3723                 add_device( port_array[port] );
3724                 spin_lock_init(&port_array[port]->lock);
3725         }
3726
3727         /* Allocate and claim adapter resources */
3728         if ( !claim_resources(port_array[0]) ) {
3729
3730                 alloc_dma_bufs(port_array[0]);
3731
3732                 /* copy resource information from first port to others */
3733                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3734                         port_array[port]->lock  = port_array[0]->lock;
3735                         port_array[port]->irq_level     = port_array[0]->irq_level;
3736                         port_array[port]->memory_base   = port_array[0]->memory_base;
3737                         port_array[port]->sca_base      = port_array[0]->sca_base;
3738                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3739                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3740                         alloc_dma_bufs(port_array[port]);
3741                 }
3742
3743                 if ( request_irq(port_array[0]->irq_level,
3744                                         synclinkmp_interrupt,
3745                                         port_array[0]->irq_flags,
3746                                         port_array[0]->device_name,
3747                                         port_array[0]) < 0 ) {
3748                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3749                                 __FILE__,__LINE__,
3750                                 port_array[0]->device_name,
3751                                 port_array[0]->irq_level );
3752                 }
3753                 else {
3754                         port_array[0]->irq_requested = 1;
3755                         adapter_test(port_array[0]);
3756                 }
3757         }
3758 }
3759
3760 static struct tty_operations ops = {
3761         .open = open,
3762         .close = close,
3763         .write = write,
3764         .put_char = put_char,
3765         .flush_chars = flush_chars,
3766         .write_room = write_room,
3767         .chars_in_buffer = chars_in_buffer,
3768         .flush_buffer = flush_buffer,
3769         .ioctl = ioctl,
3770         .throttle = throttle,
3771         .unthrottle = unthrottle,
3772         .send_xchar = send_xchar,
3773         .break_ctl = set_break,
3774         .wait_until_sent = wait_until_sent,
3775         .read_proc = read_proc,
3776         .set_termios = set_termios,
3777         .stop = tx_hold,
3778         .start = tx_release,
3779         .hangup = hangup,
3780         .tiocmget = tiocmget,
3781         .tiocmset = tiocmset,
3782 };
3783
3784 static void synclinkmp_cleanup(void)
3785 {
3786         unsigned long flags;
3787         int rc;
3788         SLMP_INFO *info;
3789         SLMP_INFO *tmp;
3790
3791         printk("Unloading %s %s\n", driver_name, driver_version);
3792
3793         if (serial_driver) {
3794                 if ((rc = tty_unregister_driver(serial_driver)))
3795                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3796                                __FILE__,__LINE__,rc);
3797                 put_tty_driver(serial_driver);
3798         }
3799
3800         info = synclinkmp_device_list;
3801         while(info) {
3802 #ifdef CONFIG_SYNCLINK_SYNCPPP
3803                 if (info->dosyncppp)
3804                         sppp_delete(info);
3805 #endif
3806                 reset_port(info);
3807                 if ( info->port_num == 0 ) {
3808                         if ( info->irq_requested ) {
3809                                 free_irq(info->irq_level, info);
3810                                 info->irq_requested = 0;
3811                         }
3812                 }
3813                 info = info->next_device;
3814         }
3815
3816         /* port 0 of each adapter originally claimed
3817          * all resources, release those now
3818          */
3819         info = synclinkmp_device_list;
3820         while(info) {
3821                 free_dma_bufs(info);
3822                 free_tmp_rx_buf(info);
3823                 if ( info->port_num == 0 ) {
3824                         spin_lock_irqsave(&info->lock,flags);
3825                         reset_adapter(info);
3826                         write_reg(info, LPR, 1);                /* set low power mode */
3827                         spin_unlock_irqrestore(&info->lock,flags);
3828                         release_resources(info);
3829                 }
3830                 tmp = info;
3831                 info = info->next_device;
3832                 kfree(tmp);
3833         }
3834
3835         pci_unregister_driver(&synclinkmp_pci_driver);
3836 }
3837
3838 /* Driver initialization entry point.
3839  */
3840
3841 static int __init synclinkmp_init(void)
3842 {
3843         int rc;
3844
3845         if (break_on_load) {
3846                 synclinkmp_get_text_ptr();
3847                 BREAKPOINT();
3848         }
3849
3850         printk("%s %s\n", driver_name, driver_version);
3851
3852         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3853                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3854                 return rc;
3855         }
3856
3857         serial_driver = alloc_tty_driver(128);
3858         if (!serial_driver) {
3859                 rc = -ENOMEM;
3860                 goto error;
3861         }
3862
3863         /* Initialize the tty_driver structure */
3864
3865         serial_driver->owner = THIS_MODULE;
3866         serial_driver->driver_name = "synclinkmp";
3867         serial_driver->name = "ttySLM";
3868         serial_driver->major = ttymajor;
3869         serial_driver->minor_start = 64;
3870         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3871         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3872         serial_driver->init_termios = tty_std_termios;
3873         serial_driver->init_termios.c_cflag =
3874                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3875         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3876         tty_set_operations(serial_driver, &ops);
3877         if ((rc = tty_register_driver(serial_driver)) < 0) {
3878                 printk("%s(%d):Couldn't register serial driver\n",
3879                         __FILE__,__LINE__);
3880                 put_tty_driver(serial_driver);
3881                 serial_driver = NULL;
3882                 goto error;
3883         }
3884
3885         printk("%s %s, tty major#%d\n",
3886                 driver_name, driver_version,
3887                 serial_driver->major);
3888
3889         return 0;
3890
3891 error:
3892         synclinkmp_cleanup();
3893         return rc;
3894 }
3895
3896 static void __exit synclinkmp_exit(void)
3897 {
3898         synclinkmp_cleanup();
3899 }
3900
3901 module_init(synclinkmp_init);
3902 module_exit(synclinkmp_exit);
3903
3904 /* Set the port for internal loopback mode.
3905  * The TxCLK and RxCLK signals are generated from the BRG and
3906  * the TxD is looped back to the RxD internally.
3907  */
3908 void enable_loopback(SLMP_INFO *info, int enable)
3909 {
3910         if (enable) {
3911                 /* MD2 (Mode Register 2)
3912                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
3913                  */
3914                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
3915
3916                 /* degate external TxC clock source */
3917                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
3918                 write_control_reg(info);
3919
3920                 /* RXS/TXS (Rx/Tx clock source)
3921                  * 07      Reserved, must be 0
3922                  * 06..04  Clock Source, 100=BRG
3923                  * 03..00  Clock Divisor, 0000=1
3924                  */
3925                 write_reg(info, RXS, 0x40);
3926                 write_reg(info, TXS, 0x40);
3927
3928         } else {
3929                 /* MD2 (Mode Register 2)
3930                  * 01..00  CNCT<1..0> Channel connection, 0=normal
3931                  */
3932                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
3933
3934                 /* RXS/TXS (Rx/Tx clock source)
3935                  * 07      Reserved, must be 0
3936                  * 06..04  Clock Source, 000=RxC/TxC Pin
3937                  * 03..00  Clock Divisor, 0000=1
3938                  */
3939                 write_reg(info, RXS, 0x00);
3940                 write_reg(info, TXS, 0x00);
3941         }
3942
3943         /* set LinkSpeed if available, otherwise default to 2Mbps */
3944         if (info->params.clock_speed)
3945                 set_rate(info, info->params.clock_speed);
3946         else
3947                 set_rate(info, 3686400);
3948 }
3949
3950 /* Set the baud rate register to the desired speed
3951  *
3952  *      data_rate       data rate of clock in bits per second
3953  *                      A data rate of 0 disables the AUX clock.
3954  */
3955 void set_rate( SLMP_INFO *info, u32 data_rate )
3956 {
3957         u32 TMCValue;
3958         unsigned char BRValue;
3959         u32 Divisor=0;
3960
3961         /* fBRG = fCLK/(TMC * 2^BR)
3962          */
3963         if (data_rate != 0) {
3964                 Divisor = 14745600/data_rate;
3965                 if (!Divisor)
3966                         Divisor = 1;
3967
3968                 TMCValue = Divisor;
3969
3970                 BRValue = 0;
3971                 if (TMCValue != 1 && TMCValue != 2) {
3972                         /* BRValue of 0 provides 50/50 duty cycle *only* when
3973                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
3974                          * 50/50 duty cycle.
3975                          */
3976                         BRValue = 1;
3977                         TMCValue >>= 1;
3978                 }
3979
3980                 /* while TMCValue is too big for TMC register, divide
3981                  * by 2 and increment BR exponent.
3982                  */
3983                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
3984                         TMCValue >>= 1;
3985
3986                 write_reg(info, TXS,
3987                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
3988                 write_reg(info, RXS,
3989                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
3990                 write_reg(info, TMC, (unsigned char)TMCValue);
3991         }
3992         else {
3993                 write_reg(info, TXS,0);
3994                 write_reg(info, RXS,0);
3995                 write_reg(info, TMC, 0);
3996         }
3997 }
3998
3999 /* Disable receiver
4000  */
4001 void rx_stop(SLMP_INFO *info)
4002 {
4003         if (debug_level >= DEBUG_LEVEL_ISR)
4004                 printk("%s(%d):%s rx_stop()\n",
4005                          __FILE__,__LINE__, info->device_name );
4006
4007         write_reg(info, CMD, RXRESET);
4008
4009         info->ie0_value &= ~RXRDYE;
4010         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4011
4012         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4013         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4014         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4015
4016         info->rx_enabled = 0;
4017         info->rx_overflow = 0;
4018 }
4019
4020 /* enable the receiver
4021  */
4022 void rx_start(SLMP_INFO *info)
4023 {
4024         int i;
4025
4026         if (debug_level >= DEBUG_LEVEL_ISR)
4027                 printk("%s(%d):%s rx_start()\n",
4028                          __FILE__,__LINE__, info->device_name );
4029
4030         write_reg(info, CMD, RXRESET);
4031
4032         if ( info->params.mode == MGSL_MODE_HDLC ) {
4033                 /* HDLC, disabe IRQ on rxdata */
4034                 info->ie0_value &= ~RXRDYE;
4035                 write_reg(info, IE0, info->ie0_value);
4036
4037                 /* Reset all Rx DMA buffers and program rx dma */
4038                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4039                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4040
4041                 for (i = 0; i < info->rx_buf_count; i++) {
4042                         info->rx_buf_list[i].status = 0xff;
4043
4044                         // throttle to 4 shared memory writes at a time to prevent
4045                         // hogging local bus (keep latency time for DMA requests low).
4046                         if (!(i % 4))
4047                                 read_status_reg(info);
4048                 }
4049                 info->current_rx_buf = 0;
4050
4051                 /* set current/1st descriptor address */
4052                 write_reg16(info, RXDMA + CDA,
4053                         info->rx_buf_list_ex[0].phys_entry);
4054
4055                 /* set new last rx descriptor address */
4056                 write_reg16(info, RXDMA + EDA,
4057                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4058
4059                 /* set buffer length (shared by all rx dma data buffers) */
4060                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4061
4062                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4063                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4064         } else {
4065                 /* async, enable IRQ on rxdata */
4066                 info->ie0_value |= RXRDYE;
4067                 write_reg(info, IE0, info->ie0_value);
4068         }
4069
4070         write_reg(info, CMD, RXENABLE);
4071
4072         info->rx_overflow = FALSE;
4073         info->rx_enabled = 1;
4074 }
4075
4076 /* Enable the transmitter and send a transmit frame if
4077  * one is loaded in the DMA buffers.
4078  */
4079 void tx_start(SLMP_INFO *info)
4080 {
4081         if (debug_level >= DEBUG_LEVEL_ISR)
4082                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4083                          __FILE__,__LINE__, info->device_name,info->tx_count );
4084
4085         if (!info->tx_enabled ) {
4086                 write_reg(info, CMD, TXRESET);
4087                 write_reg(info, CMD, TXENABLE);
4088                 info->tx_enabled = TRUE;
4089         }
4090
4091         if ( info->tx_count ) {
4092
4093                 /* If auto RTS enabled and RTS is inactive, then assert */
4094                 /* RTS and set a flag indicating that the driver should */
4095                 /* negate RTS when the transmission completes. */
4096
4097                 info->drop_rts_on_tx_done = 0;
4098
4099                 if (info->params.mode != MGSL_MODE_ASYNC) {
4100
4101                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4102                                 get_signals( info );
4103                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4104                                         info->serial_signals |= SerialSignal_RTS;
4105                                         set_signals( info );
4106                                         info->drop_rts_on_tx_done = 1;
4107                                 }
4108                         }
4109
4110                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4111                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4112
4113                         /* set TX CDA (current descriptor address) */
4114                         write_reg16(info, TXDMA + CDA,
4115                                 info->tx_buf_list_ex[0].phys_entry);
4116
4117                         /* set TX EDA (last descriptor address) */
4118                         write_reg16(info, TXDMA + EDA,
4119                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4120
4121                         /* clear IDLE and UDRN status bit */
4122                         info->ie1_value &= ~(IDLE + UDRN);
4123                         if (info->params.mode != MGSL_MODE_ASYNC)
4124                                 info->ie1_value |= UDRN;                /* HDLC, IRQ on underrun */
4125                         write_reg(info, IE1, info->ie1_value);  /* enable MSCI interrupts */
4126                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4127
4128                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4129                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4130
4131                         info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
4132                         add_timer(&info->tx_timer);
4133                 }
4134                 else {
4135                         tx_load_fifo(info);
4136                         /* async, enable IRQ on txdata */
4137                         info->ie0_value |= TXRDYE;
4138                         write_reg(info, IE0, info->ie0_value);
4139                 }
4140
4141                 info->tx_active = 1;
4142         }
4143 }
4144
4145 /* stop the transmitter and DMA
4146  */
4147 void tx_stop( SLMP_INFO *info )
4148 {
4149         if (debug_level >= DEBUG_LEVEL_ISR)
4150                 printk("%s(%d):%s tx_stop()\n",
4151                          __FILE__,__LINE__, info->device_name );
4152
4153         del_timer(&info->tx_timer);
4154
4155         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4156         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4157
4158         write_reg(info, CMD, TXRESET);
4159
4160         info->ie1_value &= ~(UDRN + IDLE);
4161         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4162         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4163
4164         info->ie0_value &= ~TXRDYE;
4165         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4166
4167         info->tx_enabled = 0;
4168         info->tx_active  = 0;
4169 }
4170
4171 /* Fill the transmit FIFO until the FIFO is full or
4172  * there is no more data to load.
4173  */
4174 void tx_load_fifo(SLMP_INFO *info)
4175 {
4176         u8 TwoBytes[2];
4177
4178         /* do nothing is now tx data available and no XON/XOFF pending */
4179
4180         if ( !info->tx_count && !info->x_char )
4181                 return;
4182
4183         /* load the Transmit FIFO until FIFOs full or all data sent */
4184
4185         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4186
4187                 /* there is more space in the transmit FIFO and */
4188                 /* there is more data in transmit buffer */
4189
4190                 if ( (info->tx_count > 1) && !info->x_char ) {
4191                         /* write 16-bits */
4192                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4193                         if (info->tx_get >= info->max_frame_size)
4194                                 info->tx_get -= info->max_frame_size;
4195                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4196                         if (info->tx_get >= info->max_frame_size)
4197                                 info->tx_get -= info->max_frame_size;
4198
4199                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4200
4201                         info->tx_count -= 2;
4202                         info->icount.tx += 2;
4203                 } else {
4204                         /* only 1 byte left to transmit or 1 FIFO slot left */
4205
4206                         if (info->x_char) {
4207                                 /* transmit pending high priority char */
4208                                 write_reg(info, TRB, info->x_char);
4209                                 info->x_char = 0;
4210                         } else {
4211                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4212                                 if (info->tx_get >= info->max_frame_size)
4213                                         info->tx_get -= info->max_frame_size;
4214                                 info->tx_count--;
4215                         }
4216                         info->icount.tx++;
4217                 }
4218         }
4219 }
4220
4221 /* Reset a port to a known state
4222  */
4223 void reset_port(SLMP_INFO *info)
4224 {
4225         if (info->sca_base) {
4226
4227                 tx_stop(info);
4228                 rx_stop(info);
4229
4230                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4231                 set_signals(info);
4232
4233                 /* disable all port interrupts */
4234                 info->ie0_value = 0;
4235                 info->ie1_value = 0;
4236                 info->ie2_value = 0;
4237                 write_reg(info, IE0, info->ie0_value);
4238                 write_reg(info, IE1, info->ie1_value);
4239                 write_reg(info, IE2, info->ie2_value);
4240
4241                 write_reg(info, CMD, CHRESET);
4242         }
4243 }
4244
4245 /* Reset all the ports to a known state.
4246  */
4247 void reset_adapter(SLMP_INFO *info)
4248 {
4249         int i;
4250
4251         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4252                 if (info->port_array[i])
4253                         reset_port(info->port_array[i]);
4254         }
4255 }
4256
4257 /* Program port for asynchronous communications.
4258  */
4259 void async_mode(SLMP_INFO *info)
4260 {
4261
4262         unsigned char RegValue;
4263
4264         tx_stop(info);
4265         rx_stop(info);
4266
4267         /* MD0, Mode Register 0
4268          *
4269          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4270          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4271          * 03      Reserved, must be 0
4272          * 02      CRCCC, CRC Calculation, 0=disabled
4273          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4274          *
4275          * 0000 0000
4276          */
4277         RegValue = 0x00;
4278         if (info->params.stop_bits != 1)
4279                 RegValue |= BIT1;
4280         write_reg(info, MD0, RegValue);
4281
4282         /* MD1, Mode Register 1
4283          *
4284          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4285          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4286          * 03..02  RXCHR<1..0>, rx char size
4287          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4288          *
4289          * 0100 0000
4290          */
4291         RegValue = 0x40;
4292         switch (info->params.data_bits) {
4293         case 7: RegValue |= BIT4 + BIT2; break;
4294         case 6: RegValue |= BIT5 + BIT3; break;
4295         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4296         }
4297         if (info->params.parity != ASYNC_PARITY_NONE) {
4298                 RegValue |= BIT1;
4299                 if (info->params.parity == ASYNC_PARITY_ODD)
4300                         RegValue |= BIT0;
4301         }
4302         write_reg(info, MD1, RegValue);
4303
4304         /* MD2, Mode Register 2
4305          *
4306          * 07..02  Reserved, must be 0
4307          * 01..00  CNCT<1..0> Channel connection, 0=normal
4308          *
4309          * 0000 0000
4310          */
4311         RegValue = 0x00;
4312         write_reg(info, MD2, RegValue);
4313
4314         /* RXS, Receive clock source
4315          *
4316          * 07      Reserved, must be 0
4317          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4318          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4319          */
4320         RegValue=BIT6;
4321         write_reg(info, RXS, RegValue);
4322
4323         /* TXS, Transmit clock source
4324          *
4325          * 07      Reserved, must be 0
4326          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4327          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4328          */
4329         RegValue=BIT6;
4330         write_reg(info, TXS, RegValue);
4331
4332         /* Control Register
4333          *
4334          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4335          */
4336         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4337         write_control_reg(info);
4338
4339         tx_set_idle(info);
4340
4341         /* RRC Receive Ready Control 0
4342          *
4343          * 07..05  Reserved, must be 0
4344          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4345          */
4346         write_reg(info, TRC0, 0x00);
4347
4348         /* TRC0 Transmit Ready Control 0
4349          *
4350          * 07..05  Reserved, must be 0
4351          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4352          */
4353         write_reg(info, TRC0, 0x10);
4354
4355         /* TRC1 Transmit Ready Control 1
4356          *
4357          * 07..05  Reserved, must be 0
4358          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4359          */
4360         write_reg(info, TRC1, 0x1e);
4361
4362         /* CTL, MSCI control register
4363          *
4364          * 07..06  Reserved, set to 0
4365          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4366          * 04      IDLC, idle control, 0=mark 1=idle register
4367          * 03      BRK, break, 0=off 1 =on (async)
4368          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4369          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4370          * 00      RTS, RTS output control, 0=active 1=inactive
4371          *
4372          * 0001 0001
4373          */
4374         RegValue = 0x10;
4375         if (!(info->serial_signals & SerialSignal_RTS))
4376                 RegValue |= 0x01;
4377         write_reg(info, CTL, RegValue);
4378
4379         /* enable status interrupts */
4380         info->ie0_value |= TXINTE + RXINTE;
4381         write_reg(info, IE0, info->ie0_value);
4382
4383         /* enable break detect interrupt */
4384         info->ie1_value = BRKD;
4385         write_reg(info, IE1, info->ie1_value);
4386
4387         /* enable rx overrun interrupt */
4388         info->ie2_value = OVRN;
4389         write_reg(info, IE2, info->ie2_value);
4390
4391         set_rate( info, info->params.data_rate * 16 );
4392
4393         if (info->params.loopback)
4394                 enable_loopback(info,1);
4395 }
4396
4397 /* Program the SCA for HDLC communications.
4398  */
4399 void hdlc_mode(SLMP_INFO *info)
4400 {
4401         unsigned char RegValue;
4402         u32 DpllDivisor;
4403
4404         // Can't use DPLL because SCA outputs recovered clock on RxC when
4405         // DPLL mode selected. This causes output contention with RxC receiver.
4406         // Use of DPLL would require external hardware to disable RxC receiver
4407         // when DPLL mode selected.
4408         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4409
4410         /* disable DMA interrupts */
4411         write_reg(info, TXDMA + DIR, 0);
4412         write_reg(info, RXDMA + DIR, 0);
4413
4414         /* MD0, Mode Register 0
4415          *
4416          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4417          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4418          * 03      Reserved, must be 0
4419          * 02      CRCCC, CRC Calculation, 1=enabled
4420          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4421          * 00      CRC0, CRC initial value, 1 = all 1s
4422          *
4423          * 1000 0001
4424          */
4425         RegValue = 0x81;
4426         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4427                 RegValue |= BIT4;
4428         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4429                 RegValue |= BIT4;
4430         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4431                 RegValue |= BIT2 + BIT1;
4432         write_reg(info, MD0, RegValue);
4433
4434         /* MD1, Mode Register 1
4435          *
4436          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4437          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4438          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4439          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4440          *
4441          * 0000 0000
4442          */
4443         RegValue = 0x00;
4444         write_reg(info, MD1, RegValue);
4445
4446         /* MD2, Mode Register 2
4447          *
4448          * 07      NRZFM, 0=NRZ, 1=FM
4449          * 06..05  CODE<1..0> Encoding, 00=NRZ
4450          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4451          * 02      Reserved, must be 0
4452          * 01..00  CNCT<1..0> Channel connection, 0=normal
4453          *
4454          * 0000 0000
4455          */
4456         RegValue = 0x00;
4457         switch(info->params.encoding) {
4458         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4459         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4460         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4461         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4462 #if 0
4463         case HDLC_ENCODING_NRZB:                                        /* not supported */
4464         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4465         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4466 #endif
4467         }
4468         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4469                 DpllDivisor = 16;
4470                 RegValue |= BIT3;
4471         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4472                 DpllDivisor = 8;
4473         } else {
4474                 DpllDivisor = 32;
4475                 RegValue |= BIT4;
4476         }
4477         write_reg(info, MD2, RegValue);
4478
4479
4480         /* RXS, Receive clock source
4481          *
4482          * 07      Reserved, must be 0
4483          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4484          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4485          */
4486         RegValue=0;
4487         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4488                 RegValue |= BIT6;
4489         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4490                 RegValue |= BIT6 + BIT5;
4491         write_reg(info, RXS, RegValue);
4492
4493         /* TXS, Transmit clock source
4494          *
4495          * 07      Reserved, must be 0
4496          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4497          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4498          */
4499         RegValue=0;
4500         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4501                 RegValue |= BIT6;
4502         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4503                 RegValue |= BIT6 + BIT5;
4504         write_reg(info, TXS, RegValue);
4505
4506         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4507                 set_rate(info, info->params.clock_speed * DpllDivisor);
4508         else
4509                 set_rate(info, info->params.clock_speed);
4510
4511         /* GPDATA (General Purpose I/O Data Register)
4512          *
4513          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4514          */
4515         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4516                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4517         else
4518                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4519         write_control_reg(info);
4520
4521         /* RRC Receive Ready Control 0
4522          *
4523          * 07..05  Reserved, must be 0
4524          * 04..00  RRC<4..0> Rx FIFO trigger active
4525          */
4526         write_reg(info, RRC, rx_active_fifo_level);
4527
4528         /* TRC0 Transmit Ready Control 0
4529          *
4530          * 07..05  Reserved, must be 0
4531          * 04..00  TRC<4..0> Tx FIFO trigger active
4532          */
4533         write_reg(info, TRC0, tx_active_fifo_level);
4534
4535         /* TRC1 Transmit Ready Control 1
4536          *
4537          * 07..05  Reserved, must be 0
4538          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4539          */
4540         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4541
4542         /* DMR, DMA Mode Register
4543          *
4544          * 07..05  Reserved, must be 0
4545          * 04      TMOD, Transfer Mode: 1=chained-block
4546          * 03      Reserved, must be 0
4547          * 02      NF, Number of Frames: 1=multi-frame
4548          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4549          * 00      Reserved, must be 0
4550          *
4551          * 0001 0100
4552          */
4553         write_reg(info, TXDMA + DMR, 0x14);
4554         write_reg(info, RXDMA + DMR, 0x14);
4555
4556         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4557         write_reg(info, RXDMA + CPB,
4558                 (unsigned char)(info->buffer_list_phys >> 16));
4559
4560         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4561         write_reg(info, TXDMA + CPB,
4562                 (unsigned char)(info->buffer_list_phys >> 16));
4563
4564         /* enable status interrupts. other code enables/disables
4565          * the individual sources for these two interrupt classes.
4566          */
4567         info->ie0_value |= TXINTE + RXINTE;
4568         write_reg(info, IE0, info->ie0_value);
4569
4570         /* CTL, MSCI control register
4571          *
4572          * 07..06  Reserved, set to 0
4573          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4574          * 04      IDLC, idle control, 0=mark 1=idle register
4575          * 03      BRK, break, 0=off 1 =on (async)
4576          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4577          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4578          * 00      RTS, RTS output control, 0=active 1=inactive
4579          *
4580          * 0001 0001
4581          */
4582         RegValue = 0x10;
4583         if (!(info->serial_signals & SerialSignal_RTS))
4584                 RegValue |= 0x01;
4585         write_reg(info, CTL, RegValue);
4586
4587         /* preamble not supported ! */
4588
4589         tx_set_idle(info);
4590         tx_stop(info);
4591         rx_stop(info);
4592
4593         set_rate(info, info->params.clock_speed);
4594
4595         if (info->params.loopback)
4596                 enable_loopback(info,1);
4597 }
4598
4599 /* Set the transmit HDLC idle mode
4600  */
4601 void tx_set_idle(SLMP_INFO *info)
4602 {
4603         unsigned char RegValue = 0xff;
4604
4605         /* Map API idle mode to SCA register bits */
4606         switch(info->idle_mode) {
4607         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4608         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4609         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4610         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4611         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4612         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4613         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4614         }
4615
4616         write_reg(info, IDL, RegValue);
4617 }
4618
4619 /* Query the adapter for the state of the V24 status (input) signals.
4620  */
4621 void get_signals(SLMP_INFO *info)
4622 {
4623         u16 status = read_reg(info, SR3);
4624         u16 gpstatus = read_status_reg(info);
4625         u16 testbit;
4626
4627         /* clear all serial signals except DTR and RTS */
4628         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4629
4630         /* set serial signal bits to reflect MISR */
4631
4632         if (!(status & BIT3))
4633                 info->serial_signals |= SerialSignal_CTS;
4634
4635         if ( !(status & BIT2))
4636                 info->serial_signals |= SerialSignal_DCD;
4637
4638         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4639         if (!(gpstatus & testbit))
4640                 info->serial_signals |= SerialSignal_RI;
4641
4642         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4643         if (!(gpstatus & testbit))
4644                 info->serial_signals |= SerialSignal_DSR;
4645 }
4646
4647 /* Set the state of DTR and RTS based on contents of
4648  * serial_signals member of device context.
4649  */
4650 void set_signals(SLMP_INFO *info)
4651 {
4652         unsigned char RegValue;
4653         u16 EnableBit;
4654
4655         RegValue = read_reg(info, CTL);
4656         if (info->serial_signals & SerialSignal_RTS)
4657                 RegValue &= ~BIT0;
4658         else
4659                 RegValue |= BIT0;
4660         write_reg(info, CTL, RegValue);
4661
4662         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4663         EnableBit = BIT1 << (info->port_num*2);
4664         if (info->serial_signals & SerialSignal_DTR)
4665                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4666         else
4667                 info->port_array[0]->ctrlreg_value |= EnableBit;
4668         write_control_reg(info);
4669 }
4670
4671 /*******************/
4672 /* DMA Buffer Code */
4673 /*******************/
4674
4675 /* Set the count for all receive buffers to SCABUFSIZE
4676  * and set the current buffer to the first buffer. This effectively
4677  * makes all buffers free and discards any data in buffers.
4678  */
4679 void rx_reset_buffers(SLMP_INFO *info)
4680 {
4681         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4682 }
4683
4684 /* Free the buffers used by a received frame
4685  *
4686  * info   pointer to device instance data
4687  * first  index of 1st receive buffer of frame
4688  * last   index of last receive buffer of frame
4689  */
4690 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4691 {
4692         int done = 0;
4693
4694         while(!done) {
4695                 /* reset current buffer for reuse */
4696                 info->rx_buf_list[first].status = 0xff;
4697
4698                 if (first == last) {
4699                         done = 1;
4700                         /* set new last rx descriptor address */
4701                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4702                 }
4703
4704                 first++;
4705                 if (first == info->rx_buf_count)
4706                         first = 0;
4707         }
4708
4709         /* set current buffer to next buffer after last buffer of frame */
4710         info->current_rx_buf = first;
4711 }
4712
4713 /* Return a received frame from the receive DMA buffers.
4714  * Only frames received without errors are returned.
4715  *
4716  * Return Value:        1 if frame returned, otherwise 0
4717  */
4718 int rx_get_frame(SLMP_INFO *info)
4719 {
4720         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4721         unsigned short status;
4722         unsigned int framesize = 0;
4723         int ReturnCode = 0;
4724         unsigned long flags;
4725         struct tty_struct *tty = info->tty;
4726         unsigned char addr_field = 0xff;
4727         SCADESC *desc;
4728         SCADESC_EX *desc_ex;
4729
4730 CheckAgain:
4731         /* assume no frame returned, set zero length */
4732         framesize = 0;
4733         addr_field = 0xff;
4734
4735         /*
4736          * current_rx_buf points to the 1st buffer of the next available
4737          * receive frame. To find the last buffer of the frame look for
4738          * a non-zero status field in the buffer entries. (The status
4739          * field is set by the 16C32 after completing a receive frame.
4740          */
4741         StartIndex = EndIndex = info->current_rx_buf;
4742
4743         for ( ;; ) {
4744                 desc = &info->rx_buf_list[EndIndex];
4745                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4746
4747                 if (desc->status == 0xff)
4748                         goto Cleanup;   /* current desc still in use, no frames available */
4749
4750                 if (framesize == 0 && info->params.addr_filter != 0xff)
4751                         addr_field = desc_ex->virt_addr[0];
4752
4753                 framesize += desc->length;
4754
4755                 /* Status != 0 means last buffer of frame */
4756                 if (desc->status)
4757                         break;
4758
4759                 EndIndex++;
4760                 if (EndIndex == info->rx_buf_count)
4761                         EndIndex = 0;
4762
4763                 if (EndIndex == info->current_rx_buf) {
4764                         /* all buffers have been 'used' but none mark      */
4765                         /* the end of a frame. Reset buffers and receiver. */
4766                         if ( info->rx_enabled ){
4767                                 spin_lock_irqsave(&info->lock,flags);
4768                                 rx_start(info);
4769                                 spin_unlock_irqrestore(&info->lock,flags);
4770                         }
4771                         goto Cleanup;
4772                 }
4773
4774         }
4775
4776         /* check status of receive frame */
4777
4778         /* frame status is byte stored after frame data
4779          *
4780          * 7 EOM (end of msg), 1 = last buffer of frame
4781          * 6 Short Frame, 1 = short frame
4782          * 5 Abort, 1 = frame aborted
4783          * 4 Residue, 1 = last byte is partial
4784          * 3 Overrun, 1 = overrun occurred during frame reception
4785          * 2 CRC,     1 = CRC error detected
4786          *
4787          */
4788         status = desc->status;
4789
4790         /* ignore CRC bit if not using CRC (bit is undefined) */
4791         /* Note:CRC is not save to data buffer */
4792         if (info->params.crc_type == HDLC_CRC_NONE)
4793                 status &= ~BIT2;
4794
4795         if (framesize == 0 ||
4796                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4797                 /* discard 0 byte frames, this seems to occur sometime
4798                  * when remote is idling flags.
4799                  */
4800                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4801                 goto CheckAgain;
4802         }
4803
4804         if (framesize < 2)
4805                 status |= BIT6;
4806
4807         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4808                 /* received frame has errors,
4809                  * update counts and mark frame size as 0
4810                  */
4811                 if (status & BIT6)
4812                         info->icount.rxshort++;
4813                 else if (status & BIT5)
4814                         info->icount.rxabort++;
4815                 else if (status & BIT3)
4816                         info->icount.rxover++;
4817                 else
4818                         info->icount.rxcrc++;
4819
4820                 framesize = 0;
4821
4822 #ifdef CONFIG_SYNCLINK_SYNCPPP
4823                 info->netstats.rx_errors++;
4824                 info->netstats.rx_frame_errors++;
4825 #endif
4826         }
4827
4828         if ( debug_level >= DEBUG_LEVEL_BH )
4829                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4830                         __FILE__,__LINE__,info->device_name,status,framesize);
4831
4832         if ( debug_level >= DEBUG_LEVEL_DATA )
4833                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4834                         MIN(framesize,SCABUFSIZE),0);
4835
4836         if (framesize) {
4837                 if (framesize > info->max_frame_size)
4838                         info->icount.rxlong++;
4839                 else {
4840                         /* copy dma buffer(s) to contiguous intermediate buffer */
4841                         int copy_count = framesize;
4842                         int index = StartIndex;
4843                         unsigned char *ptmp = info->tmp_rx_buf;
4844                         info->tmp_rx_buf_count = framesize;
4845
4846                         info->icount.rxok++;
4847
4848                         while(copy_count) {
4849                                 int partial_count = MIN(copy_count,SCABUFSIZE);
4850                                 memcpy( ptmp,
4851                                         info->rx_buf_list_ex[index].virt_addr,
4852                                         partial_count );
4853                                 ptmp += partial_count;
4854                                 copy_count -= partial_count;
4855
4856                                 if ( ++index == info->rx_buf_count )
4857                                         index = 0;
4858                         }
4859
4860 #ifdef CONFIG_SYNCLINK_SYNCPPP
4861                         if (info->netcount) {
4862                                 /* pass frame to syncppp device */
4863                                 sppp_rx_done(info,info->tmp_rx_buf,framesize);
4864                         }
4865                         else
4866 #endif
4867                         {
4868                                 if ( tty && tty->ldisc.receive_buf ) {
4869                                         /* Call the line discipline receive callback directly. */
4870                                         tty->ldisc.receive_buf(tty,
4871                                                 info->tmp_rx_buf,
4872                                                 info->flag_buf,
4873                                                 framesize);
4874                                 }
4875                         }
4876                 }
4877         }
4878         /* Free the buffers used by this frame. */
4879         rx_free_frame_buffers( info, StartIndex, EndIndex );
4880
4881         ReturnCode = 1;
4882
4883 Cleanup:
4884         if ( info->rx_enabled && info->rx_overflow ) {
4885                 /* Receiver is enabled, but needs to restarted due to
4886                  * rx buffer overflow. If buffers are empty, restart receiver.
4887                  */
4888                 if (info->rx_buf_list[EndIndex].status == 0xff) {
4889                         spin_lock_irqsave(&info->lock,flags);
4890                         rx_start(info);
4891                         spin_unlock_irqrestore(&info->lock,flags);
4892                 }
4893         }
4894
4895         return ReturnCode;
4896 }
4897
4898 /* load the transmit DMA buffer with data
4899  */
4900 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4901 {
4902         unsigned short copy_count;
4903         unsigned int i = 0;
4904         SCADESC *desc;
4905         SCADESC_EX *desc_ex;
4906
4907         if ( debug_level >= DEBUG_LEVEL_DATA )
4908                 trace_block(info,buf, MIN(count,SCABUFSIZE), 1);
4909
4910         /* Copy source buffer to one or more DMA buffers, starting with
4911          * the first transmit dma buffer.
4912          */
4913         for(i=0;;)
4914         {
4915                 copy_count = MIN(count,SCABUFSIZE);
4916
4917                 desc = &info->tx_buf_list[i];
4918                 desc_ex = &info->tx_buf_list_ex[i];
4919
4920                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
4921
4922                 desc->length = copy_count;
4923                 desc->status = 0;
4924
4925                 buf += copy_count;
4926                 count -= copy_count;
4927
4928                 if (!count)
4929                         break;
4930
4931                 i++;
4932                 if (i >= info->tx_buf_count)
4933                         i = 0;
4934         }
4935
4936         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
4937         info->last_tx_buf = ++i;
4938 }
4939
4940 int register_test(SLMP_INFO *info)
4941 {
4942         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
4943         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
4944         unsigned int i;
4945         int rc = TRUE;
4946         unsigned long flags;
4947
4948         spin_lock_irqsave(&info->lock,flags);
4949         reset_port(info);
4950
4951         /* assume failure */
4952         info->init_error = DiagStatus_AddressFailure;
4953
4954         /* Write bit patterns to various registers but do it out of */
4955         /* sync, then read back and verify values. */
4956
4957         for (i = 0 ; i < count ; i++) {
4958                 write_reg(info, TMC, testval[i]);
4959                 write_reg(info, IDL, testval[(i+1)%count]);
4960                 write_reg(info, SA0, testval[(i+2)%count]);
4961                 write_reg(info, SA1, testval[(i+3)%count]);
4962
4963                 if ( (read_reg(info, TMC) != testval[i]) ||
4964                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
4965                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
4966                           (read_reg(info, SA1) != testval[(i+3)%count]) )
4967                 {
4968                         rc = FALSE;
4969                         break;
4970                 }
4971         }
4972
4973         reset_port(info);
4974         spin_unlock_irqrestore(&info->lock,flags);
4975
4976         return rc;
4977 }
4978
4979 int irq_test(SLMP_INFO *info)
4980 {
4981         unsigned long timeout;
4982         unsigned long flags;
4983
4984         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
4985
4986         spin_lock_irqsave(&info->lock,flags);
4987         reset_port(info);
4988
4989         /* assume failure */
4990         info->init_error = DiagStatus_IrqFailure;
4991         info->irq_occurred = FALSE;
4992
4993         /* setup timer0 on SCA0 to interrupt */
4994
4995         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
4996         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
4997
4998         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
4999         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5000
5001
5002         /* TMCS, Timer Control/Status Register
5003          *
5004          * 07      CMF, Compare match flag (read only) 1=match
5005          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5006          * 05      Reserved, must be 0
5007          * 04      TME, Timer Enable
5008          * 03..00  Reserved, must be 0
5009          *
5010          * 0101 0000
5011          */
5012         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5013
5014         spin_unlock_irqrestore(&info->lock,flags);
5015
5016         timeout=100;
5017         while( timeout-- && !info->irq_occurred ) {
5018                 set_current_state(TASK_INTERRUPTIBLE);
5019                 schedule_timeout(jiffies_from_ms(10));
5020         }
5021
5022         spin_lock_irqsave(&info->lock,flags);
5023         reset_port(info);
5024         spin_unlock_irqrestore(&info->lock,flags);
5025
5026         return info->irq_occurred;
5027 }
5028
5029 /* initialize individual SCA device (2 ports)
5030  */
5031 int sca_init(SLMP_INFO *info)
5032 {
5033         /* set wait controller to single mem partition (low), no wait states */
5034         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5035         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5036         write_reg(info, WCRL, 0);       /* wait controller low range */
5037         write_reg(info, WCRM, 0);       /* wait controller mid range */
5038         write_reg(info, WCRH, 0);       /* wait controller high range */
5039
5040         /* DPCR, DMA Priority Control
5041          *
5042          * 07..05  Not used, must be 0
5043          * 04      BRC, bus release condition: 0=all transfers complete
5044          * 03      CCC, channel change condition: 0=every cycle
5045          * 02..00  PR<2..0>, priority 100=round robin
5046          *
5047          * 00000100 = 0x04
5048          */
5049         write_reg(info, DPCR, dma_priority);
5050
5051         /* DMA Master Enable, BIT7: 1=enable all channels */
5052         write_reg(info, DMER, 0x80);
5053
5054         /* enable all interrupt classes */
5055         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5056         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5057         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5058
5059         /* ITCR, interrupt control register
5060          * 07      IPC, interrupt priority, 0=MSCI->DMA
5061          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5062          * 04      VOS, Vector Output, 0=unmodified vector
5063          * 03..00  Reserved, must be 0
5064          */
5065         write_reg(info, ITCR, 0);
5066
5067         return TRUE;
5068 }
5069
5070 /* initialize adapter hardware
5071  */
5072 int init_adapter(SLMP_INFO *info)
5073 {
5074         int i;
5075
5076         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5077         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5078         u32 readval;
5079
5080         info->misc_ctrl_value |= BIT30;
5081         *MiscCtrl = info->misc_ctrl_value;
5082
5083         /*
5084          * Force at least 170ns delay before clearing
5085          * reset bit. Each read from LCR takes at least
5086          * 30ns so 10 times for 300ns to be safe.
5087          */
5088         for(i=0;i<10;i++)
5089                 readval = *MiscCtrl;
5090
5091         info->misc_ctrl_value &= ~BIT30;
5092         *MiscCtrl = info->misc_ctrl_value;
5093
5094         /* init control reg (all DTRs off, all clksel=input) */
5095         info->ctrlreg_value = 0xaa;
5096         write_control_reg(info);
5097
5098         {
5099                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5100                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5101
5102                 switch(read_ahead_count)
5103                 {
5104                 case 16:
5105                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5106                         break;
5107                 case 8:
5108                         lcr1_brdr_value |= BIT5 + BIT4;
5109                         break;
5110                 case 4:
5111                         lcr1_brdr_value |= BIT5 + BIT3;
5112                         break;
5113                 case 0:
5114                         lcr1_brdr_value |= BIT5;
5115                         break;
5116                 }
5117
5118                 *LCR1BRDR = lcr1_brdr_value;
5119                 *MiscCtrl = misc_ctrl_value;
5120         }
5121
5122         sca_init(info->port_array[0]);
5123         sca_init(info->port_array[2]);
5124
5125         return TRUE;
5126 }
5127
5128 /* Loopback an HDLC frame to test the hardware
5129  * interrupt and DMA functions.
5130  */
5131 int loopback_test(SLMP_INFO *info)
5132 {
5133 #define TESTFRAMESIZE 20
5134
5135         unsigned long timeout;
5136         u16 count = TESTFRAMESIZE;
5137         unsigned char buf[TESTFRAMESIZE];
5138         int rc = FALSE;
5139         unsigned long flags;
5140
5141         struct tty_struct *oldtty = info->tty;
5142         u32 speed = info->params.clock_speed;
5143
5144         info->params.clock_speed = 3686400;
5145         info->tty = 0;
5146
5147         /* assume failure */
5148         info->init_error = DiagStatus_DmaFailure;
5149
5150         /* build and send transmit frame */
5151         for (count = 0; count < TESTFRAMESIZE;++count)
5152                 buf[count] = (unsigned char)count;
5153
5154         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5155
5156         /* program hardware for HDLC and enabled receiver */
5157         spin_lock_irqsave(&info->lock,flags);
5158         hdlc_mode(info);
5159         enable_loopback(info,1);
5160         rx_start(info);
5161         info->tx_count = count;
5162         tx_load_dma_buffer(info,buf,count);
5163         tx_start(info);
5164         spin_unlock_irqrestore(&info->lock,flags);
5165
5166         /* wait for receive complete */
5167         /* Set a timeout for waiting for interrupt. */
5168         for ( timeout = 100; timeout; --timeout ) {
5169                 set_current_state(TASK_INTERRUPTIBLE);
5170                 schedule_timeout(jiffies_from_ms(10));
5171
5172                 if (rx_get_frame(info)) {
5173                         rc = TRUE;
5174                         break;
5175                 }
5176         }
5177
5178         /* verify received frame length and contents */
5179         if (rc == TRUE &&
5180                 ( info->tmp_rx_buf_count != count ||
5181                   memcmp(buf, info->tmp_rx_buf,count))) {
5182                 rc = FALSE;
5183         }
5184
5185         spin_lock_irqsave(&info->lock,flags);
5186         reset_adapter(info);
5187         spin_unlock_irqrestore(&info->lock,flags);
5188
5189         info->params.clock_speed = speed;
5190         info->tty = oldtty;
5191
5192         return rc;
5193 }
5194
5195 /* Perform diagnostics on hardware
5196  */
5197 int adapter_test( SLMP_INFO *info )
5198 {
5199         unsigned long flags;
5200         if ( debug_level >= DEBUG_LEVEL_INFO )
5201                 printk( "%s(%d):Testing device %s\n",
5202                         __FILE__,__LINE__,info->device_name );
5203
5204         spin_lock_irqsave(&info->lock,flags);
5205         init_adapter(info);
5206         spin_unlock_irqrestore(&info->lock,flags);
5207
5208         info->port_array[0]->port_count = 0;
5209
5210         if ( register_test(info->port_array[0]) &&
5211                 register_test(info->port_array[1])) {
5212
5213                 info->port_array[0]->port_count = 2;
5214
5215                 if ( register_test(info->port_array[2]) &&
5216                         register_test(info->port_array[3]) )
5217                         info->port_array[0]->port_count += 2;
5218         }
5219         else {
5220                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5221                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5222                 return -ENODEV;
5223         }
5224
5225         if ( !irq_test(info->port_array[0]) ||
5226                 !irq_test(info->port_array[1]) ||
5227                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5228                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5229                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5230                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5231                 return -ENODEV;
5232         }
5233
5234         if (!loopback_test(info->port_array[0]) ||
5235                 !loopback_test(info->port_array[1]) ||
5236                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5237                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5238                 printk( "%s(%d):DMA test failure for device %s\n",
5239                         __FILE__,__LINE__,info->device_name);
5240                 return -ENODEV;
5241         }
5242
5243         if ( debug_level >= DEBUG_LEVEL_INFO )
5244                 printk( "%s(%d):device %s passed diagnostics\n",
5245                         __FILE__,__LINE__,info->device_name );
5246
5247         info->port_array[0]->init_error = 0;
5248         info->port_array[1]->init_error = 0;
5249         if ( info->port_count > 2 ) {
5250                 info->port_array[2]->init_error = 0;
5251                 info->port_array[3]->init_error = 0;
5252         }
5253
5254         return 0;
5255 }
5256
5257 /* Test the shared memory on a PCI adapter.
5258  */
5259 int memory_test(SLMP_INFO *info)
5260 {
5261         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5262                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5263         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5264         unsigned long i;
5265         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5266         unsigned long * addr = (unsigned long *)info->memory_base;
5267
5268         /* Test data lines with test pattern at one location. */
5269
5270         for ( i = 0 ; i < count ; i++ ) {
5271                 *addr = testval[i];
5272                 if ( *addr != testval[i] )
5273                         return FALSE;
5274         }
5275
5276         /* Test address lines with incrementing pattern over */
5277         /* entire address range. */
5278
5279         for ( i = 0 ; i < limit ; i++ ) {
5280                 *addr = i * 4;
5281                 addr++;
5282         }
5283
5284         addr = (unsigned long *)info->memory_base;
5285
5286         for ( i = 0 ; i < limit ; i++ ) {
5287                 if ( *addr != i * 4 )
5288                         return FALSE;
5289                 addr++;
5290         }
5291
5292         memset( info->memory_base, 0, SCA_MEM_SIZE );
5293         return TRUE;
5294 }
5295
5296 /* Load data into PCI adapter shared memory.
5297  *
5298  * The PCI9050 releases control of the local bus
5299  * after completing the current read or write operation.
5300  *
5301  * While the PCI9050 write FIFO not empty, the
5302  * PCI9050 treats all of the writes as a single transaction
5303  * and does not release the bus. This causes DMA latency problems
5304  * at high speeds when copying large data blocks to the shared memory.
5305  *
5306  * This function breaks a write into multiple transations by
5307  * interleaving a read which flushes the write FIFO and 'completes'
5308  * the write transation. This allows any pending DMA request to gain control
5309  * of the local bus in a timely fasion.
5310  */
5311 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5312 {
5313         /* A load interval of 16 allows for 4 32-bit writes at */
5314         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5315
5316         unsigned short interval = count / sca_pci_load_interval;
5317         unsigned short i;
5318
5319         for ( i = 0 ; i < interval ; i++ )
5320         {
5321                 memcpy(dest, src, sca_pci_load_interval);
5322                 read_status_reg(info);
5323                 dest += sca_pci_load_interval;
5324                 src += sca_pci_load_interval;
5325         }
5326
5327         memcpy(dest, src, count % sca_pci_load_interval);
5328 }
5329
5330 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5331 {
5332         int i;
5333         int linecount;
5334         if (xmit)
5335                 printk("%s tx data:\n",info->device_name);
5336         else
5337                 printk("%s rx data:\n",info->device_name);
5338
5339         while(count) {
5340                 if (count > 16)
5341                         linecount = 16;
5342                 else
5343                         linecount = count;
5344
5345                 for(i=0;i<linecount;i++)
5346                         printk("%02X ",(unsigned char)data[i]);
5347                 for(;i<17;i++)
5348                         printk("   ");
5349                 for(i=0;i<linecount;i++) {
5350                         if (data[i]>=040 && data[i]<=0176)
5351                                 printk("%c",data[i]);
5352                         else
5353                                 printk(".");
5354                 }
5355                 printk("\n");
5356
5357                 data  += linecount;
5358                 count -= linecount;
5359         }
5360 }       /* end of trace_block() */
5361
5362 /* called when HDLC frame times out
5363  * update stats and do tx completion processing
5364  */
5365 void tx_timeout(unsigned long context)
5366 {
5367         SLMP_INFO *info = (SLMP_INFO*)context;
5368         unsigned long flags;
5369
5370         if ( debug_level >= DEBUG_LEVEL_INFO )
5371                 printk( "%s(%d):%s tx_timeout()\n",
5372                         __FILE__,__LINE__,info->device_name);
5373         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5374                 info->icount.txtimeout++;
5375         }
5376         spin_lock_irqsave(&info->lock,flags);
5377         info->tx_active = 0;
5378         info->tx_count = info->tx_put = info->tx_get = 0;
5379
5380         spin_unlock_irqrestore(&info->lock,flags);
5381
5382 #ifdef CONFIG_SYNCLINK_SYNCPPP
5383         if (info->netcount)
5384                 sppp_tx_done(info);
5385         else
5386 #endif
5387                 bh_transmit(info);
5388 }
5389
5390 /* called to periodically check the DSR/RI modem signal input status
5391  */
5392 void status_timeout(unsigned long context)
5393 {
5394         u16 status = 0;
5395         SLMP_INFO *info = (SLMP_INFO*)context;
5396         unsigned long flags;
5397         unsigned char delta;
5398
5399
5400         spin_lock_irqsave(&info->lock,flags);
5401         get_signals(info);
5402         spin_unlock_irqrestore(&info->lock,flags);
5403
5404         /* check for DSR/RI state change */
5405
5406         delta = info->old_signals ^ info->serial_signals;
5407         info->old_signals = info->serial_signals;
5408
5409         if (delta & SerialSignal_DSR)
5410                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5411
5412         if (delta & SerialSignal_RI)
5413                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5414
5415         if (delta & SerialSignal_DCD)
5416                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5417
5418         if (delta & SerialSignal_CTS)
5419                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5420
5421         if (status)
5422                 isr_io_pin(info,status);
5423
5424         info->status_timer.data = (unsigned long)info;
5425         info->status_timer.function = status_timeout;
5426         info->status_timer.expires = jiffies + jiffies_from_ms(10);
5427         add_timer(&info->status_timer);
5428 }
5429
5430
5431 /* Register Access Routines -
5432  * All registers are memory mapped
5433  */
5434 #define CALC_REGADDR() \
5435         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5436         if (info->port_num > 1) \
5437                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5438         if ( info->port_num & 1) { \
5439                 if (Addr > 0x7f) \
5440                         RegAddr += 0x40;        /* DMA access */ \
5441                 else if (Addr > 0x1f && Addr < 0x60) \
5442                         RegAddr += 0x20;        /* MSCI access */ \
5443         }
5444
5445
5446 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5447 {
5448         CALC_REGADDR();
5449         return *RegAddr;
5450 }
5451 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5452 {
5453         CALC_REGADDR();
5454         *RegAddr = Value;
5455 }
5456
5457 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5458 {
5459         CALC_REGADDR();
5460         return *((u16 *)RegAddr);
5461 }
5462
5463 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5464 {
5465         CALC_REGADDR();
5466         *((u16 *)RegAddr) = Value;
5467 }
5468
5469 unsigned char read_status_reg(SLMP_INFO * info)
5470 {
5471         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5472         return *RegAddr;
5473 }
5474
5475 void write_control_reg(SLMP_INFO * info)
5476 {
5477         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5478         *RegAddr = info->port_array[0]->ctrlreg_value;
5479 }
5480
5481
5482 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5483                                           const struct pci_device_id *ent)
5484 {
5485         if (pci_enable_device(dev)) {
5486                 printk("error enabling pci device %p\n", dev);
5487                 return -EIO;
5488         }
5489         device_init( ++synclinkmp_adapter_count, dev );
5490         return 0;
5491 }
5492
5493 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5494 {
5495 }