drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.22 2004/06/03 14:50:10 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <asm/serial.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <asm/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70
  71 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
  72 #define CONFIG_SYNCLINK_SYNCPPP 1
  73 #endif
  74
  75 #ifdef CONFIG_SYNCLINK_SYNCPPP
  76 #include <net/syncppp.h>
  77 #endif
  78
  79 #define GET_USER(error,value,addr) error = get_user(value,addr)
  80 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  81 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  82 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  83
  84 #include <asm/uaccess.h>
  85
  86 #include "linux/synclink.h"
  87
  88 static MGSL_PARAMS default_params = {
  89         MGSL_MODE_HDLC,                 /* unsigned long mode */
  90         0,                              /* unsigned char loopback; */
  91         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  92         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  93         0,                              /* unsigned long clock_speed; */
  94         0xff,                           /* unsigned char addr_filter; */
  95         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  96         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  97         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  98         9600,                           /* unsigned long data_rate; */
  99         8,                              /* unsigned char data_bits; */
 100         1,                              /* unsigned char stop_bits; */
 101         ASYNC_PARITY_NONE               /* unsigned char parity; */
 102 };
 103
 104 /* size in bytes of DMA data buffers */
 105 #define SCABUFSIZE      1024
 106 #define SCA_MEM_SIZE    0x40000
 107 #define SCA_BASE_SIZE   512
 108 #define SCA_REG_SIZE    16
 109 #define SCA_MAX_PORTS   4
 110 #define SCAMAXDESC      128
 111
 112 #define BUFFERLISTSIZE  4096
 113
 114 /* SCA-I style DMA buffer descriptor */
 115 typedef struct _SCADESC
 116 {
 117         u16     next;           /* lower l6 bits of next descriptor addr */
 118         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 119         u8      buf_base;       /* upper 8 bits of buffer addr */
 120         u8      pad1;
 121         u16     length;         /* length of buffer */
 122         u8      status;         /* status of buffer */
 123         u8      pad2;
 124 } SCADESC, *PSCADESC;
 125
 126 typedef struct _SCADESC_EX
 127 {
 128         /* device driver bookkeeping section */
 129         char    *virt_addr;     /* virtual address of data buffer */
 130         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 131 } SCADESC_EX, *PSCADESC_EX;
 132
 133 /* The queue of BH actions to be performed */
 134
 135 #define BH_RECEIVE  1
 136 #define BH_TRANSMIT 2
 137 #define BH_STATUS   4
 138
 139 #define IO_PIN_SHUTDOWN_LIMIT 100
 140
 141 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 142
 143 struct  _input_signal_events {
 144         int     ri_up;
 145         int     ri_down;
 146         int     dsr_up;
 147         int     dsr_down;
 148         int     dcd_up;
 149         int     dcd_down;
 150         int     cts_up;
 151         int     cts_down;
 152 };
 153
 154 /*
 155  * Device instance data structure
 156  */
 157 typedef struct _synclinkmp_info {
 158         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 159         int                     magic;
 160         int                     flags;
 161         int                     count;          /* count of opens */
 162         int                     line;
 163         unsigned short          close_delay;
 164         unsigned short          closing_wait;   /* time to wait before closing */
 165
 166         struct mgsl_icount      icount;
 167
 168         struct tty_struct       *tty;
 169         int                     timeout;
 170         int                     x_char;         /* xon/xoff character */
 171         int                     blocked_open;   /* # of blocked opens */
 172         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 173         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 174         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 175         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 176         unsigned char           *tx_buf;
 177         int                     tx_put;
 178         int                     tx_get;
 179         int                     tx_count;
 180
 181         wait_queue_head_t       open_wait;
 182         wait_queue_head_t       close_wait;
 183
 184         wait_queue_head_t       status_event_wait_q;
 185         wait_queue_head_t       event_wait_q;
 186         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 187         struct _synclinkmp_info *next_device;   /* device list link */
 188         struct timer_list       status_timer;   /* input signal status check timer */
 189
 190         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 191         struct work_struct task;                        /* task structure for scheduling bh */
 192
 193         u32 max_frame_size;                     /* as set by device config */
 194
 195         u32 pending_bh;
 196
 197         int bh_running;                         /* Protection from multiple */
 198         int isr_overflow;
 199         int bh_requested;
 200
 201         int dcd_chkcount;                       /* check counts to prevent */
 202         int cts_chkcount;                       /* too many IRQs if a signal */
 203         int dsr_chkcount;                       /* is floating */
 204         int ri_chkcount;
 205
 206         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 207         unsigned long buffer_list_phys;
 208
 209         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 210         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 211         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 212         unsigned int current_rx_buf;
 213
 214         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 215         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 216         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 217         unsigned int last_tx_buf;
 218
 219         unsigned char *tmp_rx_buf;
 220         unsigned int tmp_rx_buf_count;
 221
 222         int rx_enabled;
 223         int rx_overflow;
 224
 225         int tx_enabled;
 226         int tx_active;
 227         u32 idle_mode;
 228
 229         unsigned char ie0_value;
 230         unsigned char ie1_value;
 231         unsigned char ie2_value;
 232         unsigned char ctrlreg_value;
 233         unsigned char old_signals;
 234
 235         char device_name[25];                   /* device instance name */
 236
 237         int port_count;
 238         int adapter_num;
 239         int port_num;
 240
 241         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 242
 243         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 244
 245         unsigned int irq_level;                 /* interrupt level */
 246         unsigned long irq_flags;
 247         int irq_requested;                      /* nonzero if IRQ requested */
 248
 249         MGSL_PARAMS params;                     /* communications parameters */
 250
 251         unsigned char serial_signals;           /* current serial signal states */
 252
 253         int irq_occurred;                       /* for diagnostics use */
 254         unsigned int init_error;                /* Initialization startup error */
 255
 256         u32 last_mem_alloc;
 257         unsigned char* memory_base;             /* shared memory address (PCI only) */
 258         u32 phys_memory_base;
 259         int shared_mem_requested;
 260
 261         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 262         u32 phys_sca_base;
 263         u32 sca_offset;
 264         int sca_base_requested;
 265
 266         unsigned char* lcr_base;                /* local config registers (PCI only) */
 267         u32 phys_lcr_base;
 268         u32 lcr_offset;
 269         int lcr_mem_requested;
 270
 271         unsigned char* statctrl_base;           /* status/control register memory */
 272         u32 phys_statctrl_base;
 273         u32 statctrl_offset;
 274         int sca_statctrl_requested;
 275
 276         u32 misc_ctrl_value;
 277         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 278         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 279         BOOLEAN drop_rts_on_tx_done;
 280
 281         struct  _input_signal_events    input_signal_events;
 282
 283         /* SPPP/Cisco HDLC device parts */
 284         int netcount;
 285         int dosyncppp;
 286         spinlock_t netlock;
 287 #ifdef CONFIG_SYNCLINK_SYNCPPP
 288         struct ppp_device pppdev;
 289         char netname[10];
 290         struct net_device *netdev;
 291         struct net_device_stats netstats;
 292 #endif
 293 } SLMP_INFO;
 294
 295 #define MGSL_MAGIC 0x5401
 296
 297 /*
 298  * define serial signal status change macros
 299  */
 300 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 301 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 302 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 303 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 304
 305 /* Common Register macros */
 306 #define LPR     0x00
 307 #define PABR0   0x02
 308 #define PABR1   0x03
 309 #define WCRL    0x04
 310 #define WCRM    0x05
 311 #define WCRH    0x06
 312 #define DPCR    0x08
 313 #define DMER    0x09
 314 #define ISR0    0x10
 315 #define ISR1    0x11
 316 #define ISR2    0x12
 317 #define IER0    0x14
 318 #define IER1    0x15
 319 #define IER2    0x16
 320 #define ITCR    0x18
 321 #define INTVR   0x1a
 322 #define IMVR    0x1c
 323
 324 /* MSCI Register macros */
 325 #define TRB     0x20
 326 #define TRBL    0x20
 327 #define TRBH    0x21
 328 #define SR0     0x22
 329 #define SR1     0x23
 330 #define SR2     0x24
 331 #define SR3     0x25
 332 #define FST     0x26
 333 #define IE0     0x28
 334 #define IE1     0x29
 335 #define IE2     0x2a
 336 #define FIE     0x2b
 337 #define CMD     0x2c
 338 #define MD0     0x2e
 339 #define MD1     0x2f
 340 #define MD2     0x30
 341 #define CTL     0x31
 342 #define SA0     0x32
 343 #define SA1     0x33
 344 #define IDL     0x34
 345 #define TMC     0x35
 346 #define RXS     0x36
 347 #define TXS     0x37
 348 #define TRC0    0x38
 349 #define TRC1    0x39
 350 #define RRC     0x3a
 351 #define CST0    0x3c
 352 #define CST1    0x3d
 353
 354 /* Timer Register Macros */
 355 #define TCNT    0x60
 356 #define TCNTL   0x60
 357 #define TCNTH   0x61
 358 #define TCONR   0x62
 359 #define TCONRL  0x62
 360 #define TCONRH  0x63
 361 #define TMCS    0x64
 362 #define TEPR    0x65
 363
 364 /* DMA Controller Register macros */
 365 #define DAR     0x80
 366 #define DARL    0x80
 367 #define DARH    0x81
 368 #define DARB    0x82
 369 #define BAR     0x80
 370 #define BARL    0x80
 371 #define BARH    0x81
 372 #define BARB    0x82
 373 #define SAR     0x84
 374 #define SARL    0x84
 375 #define SARH    0x85
 376 #define SARB    0x86
 377 #define CPB     0x86
 378 #define CDA     0x88
 379 #define CDAL    0x88
 380 #define CDAH    0x89
 381 #define EDA     0x8a
 382 #define EDAL    0x8a
 383 #define EDAH    0x8b
 384 #define BFL     0x8c
 385 #define BFLL    0x8c
 386 #define BFLH    0x8d
 387 #define BCR     0x8e
 388 #define BCRL    0x8e
 389 #define BCRH    0x8f
 390 #define DSR     0x90
 391 #define DMR     0x91
 392 #define FCT     0x93
 393 #define DIR     0x94
 394 #define DCMD    0x95
 395
 396 /* combine with timer or DMA register address */
 397 #define TIMER0  0x00
 398 #define TIMER1  0x08
 399 #define TIMER2  0x10
 400 #define TIMER3  0x18
 401 #define RXDMA   0x00
 402 #define TXDMA   0x20
 403
 404 /* SCA Command Codes */
 405 #define NOOP            0x00
 406 #define TXRESET         0x01
 407 #define TXENABLE        0x02
 408 #define TXDISABLE       0x03
 409 #define TXCRCINIT       0x04
 410 #define TXCRCEXCL       0x05
 411 #define TXEOM           0x06
 412 #define TXABORT         0x07
 413 #define MPON            0x08
 414 #define TXBUFCLR        0x09
 415 #define RXRESET         0x11
 416 #define RXENABLE        0x12
 417 #define RXDISABLE       0x13
 418 #define RXCRCINIT       0x14
 419 #define RXREJECT        0x15
 420 #define SEARCHMP        0x16
 421 #define RXCRCEXCL       0x17
 422 #define RXCRCCALC       0x18
 423 #define CHRESET         0x21
 424 #define HUNT            0x31
 425
 426 /* DMA command codes */
 427 #define SWABORT         0x01
 428 #define FEICLEAR        0x02
 429
 430 /* IE0 */
 431 #define TXINTE          BIT7
 432 #define RXINTE          BIT6
 433 #define TXRDYE          BIT1
 434 #define RXRDYE          BIT0
 435
 436 /* IE1 & SR1 */
 437 #define UDRN    BIT7
 438 #define IDLE    BIT6
 439 #define SYNCD   BIT4
 440 #define FLGD    BIT4
 441 #define CCTS    BIT3
 442 #define CDCD    BIT2
 443 #define BRKD    BIT1
 444 #define ABTD    BIT1
 445 #define GAPD    BIT1
 446 #define BRKE    BIT0
 447 #define IDLD    BIT0
 448
 449 /* IE2 & SR2 */
 450 #define EOM     BIT7
 451 #define PMP     BIT6
 452 #define SHRT    BIT6
 453 #define PE      BIT5
 454 #define ABT     BIT5
 455 #define FRME    BIT4
 456 #define RBIT    BIT4
 457 #define OVRN    BIT3
 458 #define CRCE    BIT2
 459
 460
 461 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
 462
 463 /*
 464  * Global linked list of SyncLink devices
 465  */
 466 static SLMP_INFO *synclinkmp_device_list = NULL;
 467 static int synclinkmp_adapter_count = -1;
 468 static int synclinkmp_device_count = 0;
 469
 470 /*
 471  * Set this param to non-zero to load eax with the
 472  * .text section address and breakpoint on module load.
 473  * This is useful for use with gdb and add-symbol-file command.
 474  */
 475 static int break_on_load=0;
 476
 477 /*
 478  * Driver major number, defaults to zero to get auto
 479  * assigned major number. May be forced as module parameter.
 480  */
 481 static int ttymajor=0;
 482
 483 /*
 484  * Array of user specified options for ISA adapters.
 485  */
 486 static int debug_level = 0;
 487 static int maxframe[MAX_DEVICES] = {0,};
 488 static int dosyncppp[MAX_DEVICES] = {0,};
 489
 490 MODULE_PARM(break_on_load,"i");
 491 MODULE_PARM(ttymajor,"i");
 492 MODULE_PARM(debug_level,"i");
 493 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 494 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 495
 496 static char *driver_name = "SyncLink MultiPort driver";
 497 static char *driver_version = "$Revision: 4.22 $";
 498
 499 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 500 static void synclinkmp_remove_one(struct pci_dev *dev);
 501
 502 static struct pci_device_id synclinkmp_pci_tbl[] = {
 503         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 504         { 0, }, /* terminate list */
 505 };
 506 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 507
 508 MODULE_LICENSE("GPL");
 509
 510 static struct pci_driver synclinkmp_pci_driver = {
 511         .name           = "synclinkmp",
 512         .id_table       = synclinkmp_pci_tbl,
 513         .probe          = synclinkmp_init_one,
 514         .remove         = __devexit_p(synclinkmp_remove_one),
 515 };
 516
 517
 518 static struct tty_driver *serial_driver;
 519
 520 /* number of characters left in xmit buffer before we ask for more */
 521 #define WAKEUP_CHARS 256
 522
 523 #ifndef MIN
 524 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 525 #endif
 526
 527
 528 /* tty callbacks */
 529
 530 static int  open(struct tty_struct *tty, struct file * filp);
 531 static void close(struct tty_struct *tty, struct file * filp);
 532 static void hangup(struct tty_struct *tty);
 533 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 534
 535 static int  write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
 536 static void put_char(struct tty_struct *tty, unsigned char ch);
 537 static void send_xchar(struct tty_struct *tty, char ch);
 538 static void wait_until_sent(struct tty_struct *tty, int timeout);
 539 static int  write_room(struct tty_struct *tty);
 540 static void flush_chars(struct tty_struct *tty);
 541 static void flush_buffer(struct tty_struct *tty);
 542 static void tx_hold(struct tty_struct *tty);
 543 static void tx_release(struct tty_struct *tty);
 544
 545 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 546 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 547 static int  chars_in_buffer(struct tty_struct *tty);
 548 static void throttle(struct tty_struct * tty);
 549 static void unthrottle(struct tty_struct * tty);
 550 static void set_break(struct tty_struct *tty, int break_state);
 551
 552 /* sppp support and callbacks */
 553
 554 #ifdef CONFIG_SYNCLINK_SYNCPPP
 555 static void sppp_init(SLMP_INFO *info);
 556 static void sppp_delete(SLMP_INFO *info);
 557 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size);
 558 static void sppp_tx_done(SLMP_INFO *info);
 559
 560 static int  sppp_cb_open(struct net_device *d);
 561 static int  sppp_cb_close(struct net_device *d);
 562 static int  sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 563 static int  sppp_cb_tx(struct sk_buff *skb, struct net_device *dev);
 564 static void sppp_cb_tx_timeout(struct net_device *dev);
 565 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev);
 566 #endif
 567
 568 /* ioctl handlers */
 569
 570 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 571 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 572 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 573 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 574 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 575 static int  tx_enable(SLMP_INFO *info, int enable);
 576 static int  tx_abort(SLMP_INFO *info);
 577 static int  rx_enable(SLMP_INFO *info, int enable);
 578 static int  map_status(int signals);
 579 static int  modem_input_wait(SLMP_INFO *info,int arg);
 580 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 581 static int  tiocmget(struct tty_struct *tty, struct file *file);
 582 static int  tiocmset(struct tty_struct *tty, struct file *file,
 583                      unsigned int set, unsigned int clear);
 584 static void set_break(struct tty_struct *tty, int break_state);
 585
 586 static void add_device(SLMP_INFO *info);
 587 static void device_init(int adapter_num, struct pci_dev *pdev);
 588 static int  claim_resources(SLMP_INFO *info);
 589 static void release_resources(SLMP_INFO *info);
 590
 591 static int  startup(SLMP_INFO *info);
 592 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 593 static void shutdown(SLMP_INFO *info);
 594 static void program_hw(SLMP_INFO *info);
 595 static void change_params(SLMP_INFO *info);
 596
 597 static int  init_adapter(SLMP_INFO *info);
 598 static int  register_test(SLMP_INFO *info);
 599 static int  irq_test(SLMP_INFO *info);
 600 static int  loopback_test(SLMP_INFO *info);
 601 static int  adapter_test(SLMP_INFO *info);
 602 static int  memory_test(SLMP_INFO *info);
 603
 604 static void reset_adapter(SLMP_INFO *info);
 605 static void reset_port(SLMP_INFO *info);
 606 static void async_mode(SLMP_INFO *info);
 607 static void hdlc_mode(SLMP_INFO *info);
 608
 609 static void rx_stop(SLMP_INFO *info);
 610 static void rx_start(SLMP_INFO *info);
 611 static void rx_reset_buffers(SLMP_INFO *info);
 612 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 613 static int  rx_get_frame(SLMP_INFO *info);
 614
 615 static void tx_start(SLMP_INFO *info);
 616 static void tx_stop(SLMP_INFO *info);
 617 static void tx_load_fifo(SLMP_INFO *info);
 618 static void tx_set_idle(SLMP_INFO *info);
 619 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 620
 621 static void get_signals(SLMP_INFO *info);
 622 static void set_signals(SLMP_INFO *info);
 623 static void enable_loopback(SLMP_INFO *info, int enable);
 624 static void set_rate(SLMP_INFO *info, u32 data_rate);
 625
 626 static int  bh_action(SLMP_INFO *info);
 627 static void bh_handler(void* Context);
 628 static void bh_receive(SLMP_INFO *info);
 629 static void bh_transmit(SLMP_INFO *info);
 630 static void bh_status(SLMP_INFO *info);
 631 static void isr_timer(SLMP_INFO *info);
 632 static void isr_rxint(SLMP_INFO *info);
 633 static void isr_rxrdy(SLMP_INFO *info);
 634 static void isr_txint(SLMP_INFO *info);
 635 static void isr_txrdy(SLMP_INFO *info);
 636 static void isr_rxdmaok(SLMP_INFO *info);
 637 static void isr_rxdmaerror(SLMP_INFO *info);
 638 static void isr_txdmaok(SLMP_INFO *info);
 639 static void isr_txdmaerror(SLMP_INFO *info);
 640 static void isr_io_pin(SLMP_INFO *info, u16 status);
 641
 642 static int  alloc_dma_bufs(SLMP_INFO *info);
 643 static void free_dma_bufs(SLMP_INFO *info);
 644 static int  alloc_buf_list(SLMP_INFO *info);
 645 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 646 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 647 static void free_tmp_rx_buf(SLMP_INFO *info);
 648
 649 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 650 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 651 static void tx_timeout(unsigned long context);
 652 static void status_timeout(unsigned long context);
 653
 654 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 655 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 656 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 657 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 658 static unsigned char read_status_reg(SLMP_INFO * info);
 659 static void write_control_reg(SLMP_INFO * info);
 660
 661
 662 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 663 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 664 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 665
 666 static u32 misc_ctrl_value = 0x007e4040;
 667 static u32 lcr1_brdr_value = 0x0080002d;
 668
 669 static u32 read_ahead_count = 8;
 670
 671 /* DPCR, DMA Priority Control
 672  *
 673  * 07..05  Not used, must be 0
 674  * 04      BRC, bus release condition: 0=all transfers complete
 675  *              1=release after 1 xfer on all channels
 676  * 03      CCC, channel change condition: 0=every cycle
 677  *              1=after each channel completes all xfers
 678  * 02..00  PR<2..0>, priority 100=round robin
 679  *
 680  * 00000100 = 0x00
 681  */
 682 static unsigned char dma_priority = 0x04;
 683
 684 // Number of bytes that can be written to shared RAM
 685 // in a single write operation
 686 static u32 sca_pci_load_interval = 64;
 687
 688 /*
 689  * 1st function defined in .text section. Calling this function in
 690  * init_module() followed by a breakpoint allows a remote debugger
 691  * (gdb) to get the .text address for the add-symbol-file command.
 692  * This allows remote debugging of dynamically loadable modules.
 693  */
 694 static void* synclinkmp_get_text_ptr(void);
 695 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 696
 697 static inline int sanity_check(SLMP_INFO *info,
 698                                char *name, const char *routine)
 699 {
 700 #ifdef SANITY_CHECK
 701         static const char *badmagic =
 702                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 703         static const char *badinfo =
 704                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 705
 706         if (!info) {
 707                 printk(badinfo, name, routine);
 708                 return 1;
 709         }
 710         if (info->magic != MGSL_MAGIC) {
 711                 printk(badmagic, name, routine);
 712                 return 1;
 713         }
 714 #else
 715         if (!info)
 716                 return 1;
 717 #endif
 718         return 0;
 719 }
 720
 721 /* tty callbacks */
 722
 723 /* Called when a port is opened.  Init and enable port.
 724  */
 725 static int open(struct tty_struct *tty, struct file *filp)
 726 {
 727         SLMP_INFO *info;
 728         int retval, line;
 729         unsigned long flags;
 730
 731         line = tty->index;
 732         if ((line < 0) || (line >= synclinkmp_device_count)) {
 733                 printk("%s(%d): open with invalid line #%d.\n",
 734                         __FILE__,__LINE__,line);
 735                 return -ENODEV;
 736         }
 737
 738         info = synclinkmp_device_list;
 739         while(info && info->line != line)
 740                 info = info->next_device;
 741         if (sanity_check(info, tty->name, "open"))
 742                 return -ENODEV;
 743         if ( info->init_error ) {
 744                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 745                         __FILE__,__LINE__,info->device_name,info->init_error);
 746                 return -ENODEV;
 747         }
 748
 749         tty->driver_data = info;
 750         info->tty = tty;
 751
 752         if (debug_level >= DEBUG_LEVEL_INFO)
 753                 printk("%s(%d):%s open(), old ref count = %d\n",
 754                          __FILE__,__LINE__,tty->driver->name, info->count);
 755
 756         /* If port is closing, signal caller to try again */
 757         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 758                 if (info->flags & ASYNC_CLOSING)
 759                         interruptible_sleep_on(&info->close_wait);
 760                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 761                         -EAGAIN : -ERESTARTSYS);
 762                 goto cleanup;
 763         }
 764
 765         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 766
 767         spin_lock_irqsave(&info->netlock, flags);
 768         if (info->netcount) {
 769                 retval = -EBUSY;
 770                 spin_unlock_irqrestore(&info->netlock, flags);
 771                 goto cleanup;
 772         }
 773         info->count++;
 774         spin_unlock_irqrestore(&info->netlock, flags);
 775
 776         if (info->count == 1) {
 777                 /* 1st open on this device, init hardware */
 778                 retval = startup(info);
 779                 if (retval < 0)
 780                         goto cleanup;
 781         }
 782
 783         retval = block_til_ready(tty, filp, info);
 784         if (retval) {
 785                 if (debug_level >= DEBUG_LEVEL_INFO)
 786                         printk("%s(%d):%s block_til_ready() returned %d\n",
 787                                  __FILE__,__LINE__, info->device_name, retval);
 788                 goto cleanup;
 789         }
 790
 791         if (debug_level >= DEBUG_LEVEL_INFO)
 792                 printk("%s(%d):%s open() success\n",
 793                          __FILE__,__LINE__, info->device_name);
 794         retval = 0;
 795
 796 cleanup:
 797         if (retval) {
 798                 if (tty->count == 1)
 799                         info->tty = 0; /* tty layer will release tty struct */
 800                 if(info->count)
 801                         info->count--;
 802         }
 803
 804         return retval;
 805 }
 806
 807 /* Called when port is closed. Wait for remaining data to be
 808  * sent. Disable port and free resources.
 809  */
 810 static void close(struct tty_struct *tty, struct file *filp)
 811 {
 812         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 813
 814         if (sanity_check(info, tty->name, "close"))
 815                 return;
 816
 817         if (debug_level >= DEBUG_LEVEL_INFO)
 818                 printk("%s(%d):%s close() entry, count=%d\n",
 819                          __FILE__,__LINE__, info->device_name, info->count);
 820
 821         if (!info->count)
 822                 return;
 823
 824         if (tty_hung_up_p(filp))
 825                 goto cleanup;
 826
 827         if ((tty->count == 1) && (info->count != 1)) {
 828                 /*
 829                  * tty->count is 1 and the tty structure will be freed.
 830                  * info->count should be one in this case.
 831                  * if it's not, correct it so that the port is shutdown.
 832                  */
 833                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 834                        "info->count is %d\n",
 835                          __FILE__,__LINE__, info->device_name, info->count);
 836                 info->count = 1;
 837         }
 838
 839         info->count--;
 840
 841         /* if at least one open remaining, leave hardware active */
 842         if (info->count)
 843                 goto cleanup;
 844
 845         info->flags |= ASYNC_CLOSING;
 846
 847         /* set tty->closing to notify line discipline to
 848          * only process XON/XOFF characters. Only the N_TTY
 849          * discipline appears to use this (ppp does not).
 850          */
 851         tty->closing = 1;
 852
 853         /* wait for transmit data to clear all layers */
 854
 855         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 856                 if (debug_level >= DEBUG_LEVEL_INFO)
 857                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 858                                  __FILE__,__LINE__, info->device_name );
 859                 tty_wait_until_sent(tty, info->closing_wait);
 860         }
 861
 862         if (info->flags & ASYNC_INITIALIZED)
 863                 wait_until_sent(tty, info->timeout);
 864
 865         if (tty->driver->flush_buffer)
 866                 tty->driver->flush_buffer(tty);
 867
 868         if (tty->ldisc.flush_buffer)
 869                 tty->ldisc.flush_buffer(tty);
 870
 871         shutdown(info);
 872
 873         tty->closing = 0;
 874         info->tty = 0;
 875
 876         if (info->blocked_open) {
 877                 if (info->close_delay) {
 878                         set_current_state(TASK_INTERRUPTIBLE);
 879                         schedule_timeout(info->close_delay);
 880                 }
 881                 wake_up_interruptible(&info->open_wait);
 882         }
 883
 884         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 885
 886         wake_up_interruptible(&info->close_wait);
 887
 888 cleanup:
 889         if (debug_level >= DEBUG_LEVEL_INFO)
 890                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 891                         tty->driver->name, info->count);
 892 }
 893
 894 /* Called by tty_hangup() when a hangup is signaled.
 895  * This is the same as closing all open descriptors for the port.
 896  */
 897 static void hangup(struct tty_struct *tty)
 898 {
 899         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 900
 901         if (debug_level >= DEBUG_LEVEL_INFO)
 902                 printk("%s(%d):%s hangup()\n",
 903                          __FILE__,__LINE__, info->device_name );
 904
 905         if (sanity_check(info, tty->name, "hangup"))
 906                 return;
 907
 908         flush_buffer(tty);
 909         shutdown(info);
 910
 911         info->count = 0;
 912         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 913         info->tty = 0;
 914
 915         wake_up_interruptible(&info->open_wait);
 916 }
 917
 918 /* Set new termios settings
 919  */
 920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 921 {
 922         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 923         unsigned long flags;
 924
 925         if (debug_level >= DEBUG_LEVEL_INFO)
 926                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 927                         tty->driver->name );
 928
 929         /* just return if nothing has changed */
 930         if ((tty->termios->c_cflag == old_termios->c_cflag)
 931             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 932                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 933           return;
 934
 935         change_params(info);
 936
 937         /* Handle transition to B0 status */
 938         if (old_termios->c_cflag & CBAUD &&
 939             !(tty->termios->c_cflag & CBAUD)) {
 940                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 set_signals(info);
 943                 spin_unlock_irqrestore(&info->lock,flags);
 944         }
 945
 946         /* Handle transition away from B0 status */
 947         if (!(old_termios->c_cflag & CBAUD) &&
 948             tty->termios->c_cflag & CBAUD) {
 949                 info->serial_signals |= SerialSignal_DTR;
 950                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 951                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 952                         info->serial_signals |= SerialSignal_RTS;
 953                 }
 954                 spin_lock_irqsave(&info->lock,flags);
 955                 set_signals(info);
 956                 spin_unlock_irqrestore(&info->lock,flags);
 957         }
 958
 959         /* Handle turning off CRTSCTS */
 960         if (old_termios->c_cflag & CRTSCTS &&
 961             !(tty->termios->c_cflag & CRTSCTS)) {
 962                 tty->hw_stopped = 0;
 963                 tx_release(tty);
 964         }
 965 }
 966
 967 /* Send a block of data
 968  *
 969  * Arguments:
 970  *
 971  *      tty             pointer to tty information structure
 972  *      from_user       flag: 1 = from user process
 973  *      buf             pointer to buffer containing send data
 974  *      count           size of send data in bytes
 975  *
 976  * Return Value:        number of characters written
 977  */
 978 static int write(struct tty_struct *tty, int from_user,
 979                  const unsigned char *buf, int count)
 980 {
 981         int     c, ret = 0, err;
 982         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 983         unsigned long flags;
 984
 985         if (debug_level >= DEBUG_LEVEL_INFO)
 986                 printk("%s(%d):%s write() count=%d\n",
 987                        __FILE__,__LINE__,info->device_name,count);
 988
 989         if (sanity_check(info, tty->name, "write"))
 990                 goto cleanup;
 991
 992         if (!tty || !info->tx_buf)
 993                 goto cleanup;
 994
 995         if (info->params.mode == MGSL_MODE_HDLC) {
 996                 if (count > info->max_frame_size) {
 997                         ret = -EIO;
 998                         goto cleanup;
 999                 }
1000                 if (info->tx_active)
1001                         goto cleanup;
1002                 if (info->tx_count) {
1003                         /* send accumulated data from send_char() calls */
1004                         /* as frame and wait before accepting more data. */
1005                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006                         goto start;
1007                 }
1008                 if (!from_user) {
1009                         ret = info->tx_count = count;
1010                         tx_load_dma_buffer(info, buf, count);
1011                         goto start;
1012                 }
1013         }
1014
1015         for (;;) {
1016                 c = MIN(count,
1017                         MIN(info->max_frame_size - info->tx_count - 1,
1018                             info->max_frame_size - info->tx_put));
1019                 if (c <= 0)
1020                         break;
1021
1022                 if (from_user) {
1023                         COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1024                         if (err) {
1025                                 if (!ret)
1026                                         ret = -EFAULT;
1027                                 break;
1028                         }
1029                 } else
1030                         memcpy(info->tx_buf + info->tx_put, buf, c);
1031
1032                 spin_lock_irqsave(&info->lock,flags);
1033                 info->tx_put += c;
1034                 if (info->tx_put >= info->max_frame_size)
1035                         info->tx_put -= info->max_frame_size;
1036                 info->tx_count += c;
1037                 spin_unlock_irqrestore(&info->lock,flags);
1038
1039                 buf += c;
1040                 count -= c;
1041                 ret += c;
1042         }
1043
1044         if (info->params.mode == MGSL_MODE_HDLC) {
1045                 if (count) {
1046                         ret = info->tx_count = 0;
1047                         goto cleanup;
1048                 }
1049                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1050         }
1051 start:
1052         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1053                 spin_lock_irqsave(&info->lock,flags);
1054                 if (!info->tx_active)
1055                         tx_start(info);
1056                 spin_unlock_irqrestore(&info->lock,flags);
1057         }
1058
1059 cleanup:
1060         if (debug_level >= DEBUG_LEVEL_INFO)
1061                 printk( "%s(%d):%s write() returning=%d\n",
1062                         __FILE__,__LINE__,info->device_name,ret);
1063         return ret;
1064 }
1065
1066 /* Add a character to the transmit buffer.
1067  */
1068 static void put_char(struct tty_struct *tty, unsigned char ch)
1069 {
1070         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1071         unsigned long flags;
1072
1073         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1074                 printk( "%s(%d):%s put_char(%d)\n",
1075                         __FILE__,__LINE__,info->device_name,ch);
1076         }
1077
1078         if (sanity_check(info, tty->name, "put_char"))
1079                 return;
1080
1081         if (!tty || !info->tx_buf)
1082                 return;
1083
1084         spin_lock_irqsave(&info->lock,flags);
1085
1086         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1087              !info->tx_active ) {
1088
1089                 if (info->tx_count < info->max_frame_size - 1) {
1090                         info->tx_buf[info->tx_put++] = ch;
1091                         if (info->tx_put >= info->max_frame_size)
1092                                 info->tx_put -= info->max_frame_size;
1093                         info->tx_count++;
1094                 }
1095         }
1096
1097         spin_unlock_irqrestore(&info->lock,flags);
1098 }
1099
1100 /* Send a high-priority XON/XOFF character
1101  */
1102 static void send_xchar(struct tty_struct *tty, char ch)
1103 {
1104         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1105         unsigned long flags;
1106
1107         if (debug_level >= DEBUG_LEVEL_INFO)
1108                 printk("%s(%d):%s send_xchar(%d)\n",
1109                          __FILE__,__LINE__, info->device_name, ch );
1110
1111         if (sanity_check(info, tty->name, "send_xchar"))
1112                 return;
1113
1114         info->x_char = ch;
1115         if (ch) {
1116                 /* Make sure transmit interrupts are on */
1117                 spin_lock_irqsave(&info->lock,flags);
1118                 if (!info->tx_enabled)
1119                         tx_start(info);
1120                 spin_unlock_irqrestore(&info->lock,flags);
1121         }
1122 }
1123
1124 /* Wait until the transmitter is empty.
1125  */
1126 static void wait_until_sent(struct tty_struct *tty, int timeout)
1127 {
1128         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1129         unsigned long orig_jiffies, char_time;
1130
1131         if (!info )
1132                 return;
1133
1134         if (debug_level >= DEBUG_LEVEL_INFO)
1135                 printk("%s(%d):%s wait_until_sent() entry\n",
1136                          __FILE__,__LINE__, info->device_name );
1137
1138         if (sanity_check(info, tty->name, "wait_until_sent"))
1139                 return;
1140
1141         if (!(info->flags & ASYNC_INITIALIZED))
1142                 goto exit;
1143
1144         orig_jiffies = jiffies;
1145
1146         /* Set check interval to 1/5 of estimated time to
1147          * send a character, and make it at least 1. The check
1148          * interval should also be less than the timeout.
1149          * Note: use tight timings here to satisfy the NIST-PCTS.
1150          */
1151
1152         if ( info->params.data_rate ) {
1153                 char_time = info->timeout/(32 * 5);
1154                 if (!char_time)
1155                         char_time++;
1156         } else
1157                 char_time = 1;
1158
1159         if (timeout)
1160                 char_time = MIN(char_time, timeout);
1161
1162         if ( info->params.mode == MGSL_MODE_HDLC ) {
1163                 while (info->tx_active) {
1164                         set_current_state(TASK_INTERRUPTIBLE);
1165                         schedule_timeout(char_time);
1166                         if (signal_pending(current))
1167                                 break;
1168                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1169                                 break;
1170                 }
1171         } else {
1172                 //TODO: determine if there is something similar to USC16C32
1173                 //      TXSTATUS_ALL_SENT status
1174                 while ( info->tx_active && info->tx_enabled) {
1175                         set_current_state(TASK_INTERRUPTIBLE);
1176                         schedule_timeout(char_time);
1177                         if (signal_pending(current))
1178                                 break;
1179                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1180                                 break;
1181                 }
1182         }
1183
1184 exit:
1185         if (debug_level >= DEBUG_LEVEL_INFO)
1186                 printk("%s(%d):%s wait_until_sent() exit\n",
1187                          __FILE__,__LINE__, info->device_name );
1188 }
1189
1190 /* Return the count of free bytes in transmit buffer
1191  */
1192 static int write_room(struct tty_struct *tty)
1193 {
1194         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1195         int ret;
1196
1197         if (sanity_check(info, tty->name, "write_room"))
1198                 return 0;
1199
1200         if (info->params.mode == MGSL_MODE_HDLC) {
1201                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1202         } else {
1203                 ret = info->max_frame_size - info->tx_count - 1;
1204                 if (ret < 0)
1205                         ret = 0;
1206         }
1207
1208         if (debug_level >= DEBUG_LEVEL_INFO)
1209                 printk("%s(%d):%s write_room()=%d\n",
1210                        __FILE__, __LINE__, info->device_name, ret);
1211
1212         return ret;
1213 }
1214
1215 /* enable transmitter and send remaining buffered characters
1216  */
1217 static void flush_chars(struct tty_struct *tty)
1218 {
1219         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1220         unsigned long flags;
1221
1222         if ( debug_level >= DEBUG_LEVEL_INFO )
1223                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1224                         __FILE__,__LINE__,info->device_name,info->tx_count);
1225
1226         if (sanity_check(info, tty->name, "flush_chars"))
1227                 return;
1228
1229         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1230             !info->tx_buf)
1231                 return;
1232
1233         if ( debug_level >= DEBUG_LEVEL_INFO )
1234                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1235                         __FILE__,__LINE__,info->device_name );
1236
1237         spin_lock_irqsave(&info->lock,flags);
1238
1239         if (!info->tx_active) {
1240                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1241                         info->tx_count ) {
1242                         /* operating in synchronous (frame oriented) mode */
1243                         /* copy data from circular tx_buf to */
1244                         /* transmit DMA buffer. */
1245                         tx_load_dma_buffer(info,
1246                                  info->tx_buf,info->tx_count);
1247                 }
1248                 tx_start(info);
1249         }
1250
1251         spin_unlock_irqrestore(&info->lock,flags);
1252 }
1253
1254 /* Discard all data in the send buffer
1255  */
1256 static void flush_buffer(struct tty_struct *tty)
1257 {
1258         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1259         unsigned long flags;
1260
1261         if (debug_level >= DEBUG_LEVEL_INFO)
1262                 printk("%s(%d):%s flush_buffer() entry\n",
1263                          __FILE__,__LINE__, info->device_name );
1264
1265         if (sanity_check(info, tty->name, "flush_buffer"))
1266                 return;
1267
1268         spin_lock_irqsave(&info->lock,flags);
1269         info->tx_count = info->tx_put = info->tx_get = 0;
1270         del_timer(&info->tx_timer);
1271         spin_unlock_irqrestore(&info->lock,flags);
1272
1273         wake_up_interruptible(&tty->write_wait);
1274         if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1275             tty->ldisc.write_wakeup)
1276                 (tty->ldisc.write_wakeup)(tty);
1277 }
1278
1279 /* throttle (stop) transmitter
1280  */
1281 static void tx_hold(struct tty_struct *tty)
1282 {
1283         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1284         unsigned long flags;
1285
1286         if (sanity_check(info, tty->name, "tx_hold"))
1287                 return;
1288
1289         if ( debug_level >= DEBUG_LEVEL_INFO )
1290                 printk("%s(%d):%s tx_hold()\n",
1291                         __FILE__,__LINE__,info->device_name);
1292
1293         spin_lock_irqsave(&info->lock,flags);
1294         if (info->tx_enabled)
1295                 tx_stop(info);
1296         spin_unlock_irqrestore(&info->lock,flags);
1297 }
1298
1299 /* release (start) transmitter
1300  */
1301 static void tx_release(struct tty_struct *tty)
1302 {
1303         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1304         unsigned long flags;
1305
1306         if (sanity_check(info, tty->name, "tx_release"))
1307                 return;
1308
1309         if ( debug_level >= DEBUG_LEVEL_INFO )
1310                 printk("%s(%d):%s tx_release()\n",
1311                         __FILE__,__LINE__,info->device_name);
1312
1313         spin_lock_irqsave(&info->lock,flags);
1314         if (!info->tx_enabled)
1315                 tx_start(info);
1316         spin_unlock_irqrestore(&info->lock,flags);
1317 }
1318
1319 /* Service an IOCTL request
1320  *
1321  * Arguments:
1322  *
1323  *      tty     pointer to tty instance data
1324  *      file    pointer to associated file object for device
1325  *      cmd     IOCTL command code
1326  *      arg     command argument/context
1327  *
1328  * Return Value:        0 if success, otherwise error code
1329  */
1330 static int ioctl(struct tty_struct *tty, struct file *file,
1331                  unsigned int cmd, unsigned long arg)
1332 {
1333         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1334         int error;
1335         struct mgsl_icount cnow;        /* kernel counter temps */
1336         struct serial_icounter_struct __user *p_cuser;  /* user space */
1337         unsigned long flags;
1338         void __user *argp = (void __user *)arg;
1339
1340         if (debug_level >= DEBUG_LEVEL_INFO)
1341                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1342                         info->device_name, cmd );
1343
1344         if (sanity_check(info, tty->name, "ioctl"))
1345                 return -ENODEV;
1346
1347         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1348             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1349                 if (tty->flags & (1 << TTY_IO_ERROR))
1350                     return -EIO;
1351         }
1352
1353         switch (cmd) {
1354         case MGSL_IOCGPARAMS:
1355                 return get_params(info, argp);
1356         case MGSL_IOCSPARAMS:
1357                 return set_params(info, argp);
1358         case MGSL_IOCGTXIDLE:
1359                 return get_txidle(info, argp);
1360         case MGSL_IOCSTXIDLE:
1361                 return set_txidle(info, (int)arg);
1362         case MGSL_IOCTXENABLE:
1363                 return tx_enable(info, (int)arg);
1364         case MGSL_IOCRXENABLE:
1365                 return rx_enable(info, (int)arg);
1366         case MGSL_IOCTXABORT:
1367                 return tx_abort(info);
1368         case MGSL_IOCGSTATS:
1369                 return get_stats(info, argp);
1370         case MGSL_IOCWAITEVENT:
1371                 return wait_mgsl_event(info, argp);
1372         case MGSL_IOCLOOPTXDONE:
1373                 return 0; // TODO: Not supported, need to document
1374                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1375                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1376                  */
1377         case TIOCMIWAIT:
1378                 return modem_input_wait(info,(int)arg);
1379
1380                 /*
1381                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1382                  * Return: write counters to the user passed counter struct
1383                  * NB: both 1->0 and 0->1 transitions are counted except for
1384                  *     RI where only 0->1 is counted.
1385                  */
1386         case TIOCGICOUNT:
1387                 spin_lock_irqsave(&info->lock,flags);
1388                 cnow = info->icount;
1389                 spin_unlock_irqrestore(&info->lock,flags);
1390                 p_cuser = argp;
1391                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1392                 if (error) return error;
1393                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1394                 if (error) return error;
1395                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1396                 if (error) return error;
1397                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1398                 if (error) return error;
1399                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1400                 if (error) return error;
1401                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1402                 if (error) return error;
1403                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1404                 if (error) return error;
1405                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1406                 if (error) return error;
1407                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1408                 if (error) return error;
1409                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1410                 if (error) return error;
1411                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1412                 if (error) return error;
1413                 return 0;
1414         default:
1415                 return -ENOIOCTLCMD;
1416         }
1417         return 0;
1418 }
1419
1420 /*
1421  * /proc fs routines....
1422  */
1423
1424 static inline int line_info(char *buf, SLMP_INFO *info)
1425 {
1426         char    stat_buf[30];
1427         int     ret;
1428         unsigned long flags;
1429
1430         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1431                        "\tIRQ=%d MaxFrameSize=%u\n",
1432                 info->device_name,
1433                 info->phys_sca_base,
1434                 info->phys_memory_base,
1435                 info->phys_statctrl_base,
1436                 info->phys_lcr_base,
1437                 info->irq_level,
1438                 info->max_frame_size );
1439
1440         /* output current serial signal states */
1441         spin_lock_irqsave(&info->lock,flags);
1442         get_signals(info);
1443         spin_unlock_irqrestore(&info->lock,flags);
1444
1445         stat_buf[0] = 0;
1446         stat_buf[1] = 0;
1447         if (info->serial_signals & SerialSignal_RTS)
1448                 strcat(stat_buf, "|RTS");
1449         if (info->serial_signals & SerialSignal_CTS)
1450                 strcat(stat_buf, "|CTS");
1451         if (info->serial_signals & SerialSignal_DTR)
1452                 strcat(stat_buf, "|DTR");
1453         if (info->serial_signals & SerialSignal_DSR)
1454                 strcat(stat_buf, "|DSR");
1455         if (info->serial_signals & SerialSignal_DCD)
1456                 strcat(stat_buf, "|CD");
1457         if (info->serial_signals & SerialSignal_RI)
1458                 strcat(stat_buf, "|RI");
1459
1460         if (info->params.mode == MGSL_MODE_HDLC) {
1461                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1462                               info->icount.txok, info->icount.rxok);
1463                 if (info->icount.txunder)
1464                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1465                 if (info->icount.txabort)
1466                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1467                 if (info->icount.rxshort)
1468                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1469                 if (info->icount.rxlong)
1470                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1471                 if (info->icount.rxover)
1472                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1473                 if (info->icount.rxcrc)
1474                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1475         } else {
1476                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1477                               info->icount.tx, info->icount.rx);
1478                 if (info->icount.frame)
1479                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1480                 if (info->icount.parity)
1481                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1482                 if (info->icount.brk)
1483                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1484                 if (info->icount.overrun)
1485                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1486         }
1487
1488         /* Append serial signal status to end */
1489         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1490
1491         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1492          info->tx_active,info->bh_requested,info->bh_running,
1493          info->pending_bh);
1494
1495         return ret;
1496 }
1497
1498 /* Called to print information about devices
1499  */
1500 int read_proc(char *page, char **start, off_t off, int count,
1501               int *eof, void *data)
1502 {
1503         int len = 0, l;
1504         off_t   begin = 0;
1505         SLMP_INFO *info;
1506
1507         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1508
1509         info = synclinkmp_device_list;
1510         while( info ) {
1511                 l = line_info(page + len, info);
1512                 len += l;
1513                 if (len+begin > off+count)
1514                         goto done;
1515                 if (len+begin < off) {
1516                         begin += len;
1517                         len = 0;
1518                 }
1519                 info = info->next_device;
1520         }
1521
1522         *eof = 1;
1523 done:
1524         if (off >= len+begin)
1525                 return 0;
1526         *start = page + (off-begin);
1527         return ((count < begin+len-off) ? count : begin+len-off);
1528 }
1529
1530 /* Return the count of bytes in transmit buffer
1531  */
1532 static int chars_in_buffer(struct tty_struct *tty)
1533 {
1534         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1535
1536         if (sanity_check(info, tty->name, "chars_in_buffer"))
1537                 return 0;
1538
1539         if (debug_level >= DEBUG_LEVEL_INFO)
1540                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1541                        __FILE__, __LINE__, info->device_name, info->tx_count);
1542
1543         return info->tx_count;
1544 }
1545
1546 /* Signal remote device to throttle send data (our receive data)
1547  */
1548 static void throttle(struct tty_struct * tty)
1549 {
1550         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1551         unsigned long flags;
1552
1553         if (debug_level >= DEBUG_LEVEL_INFO)
1554                 printk("%s(%d):%s throttle() entry\n",
1555                          __FILE__,__LINE__, info->device_name );
1556
1557         if (sanity_check(info, tty->name, "throttle"))
1558                 return;
1559
1560         if (I_IXOFF(tty))
1561                 send_xchar(tty, STOP_CHAR(tty));
1562
1563         if (tty->termios->c_cflag & CRTSCTS) {
1564                 spin_lock_irqsave(&info->lock,flags);
1565                 info->serial_signals &= ~SerialSignal_RTS;
1566                 set_signals(info);
1567                 spin_unlock_irqrestore(&info->lock,flags);
1568         }
1569 }
1570
1571 /* Signal remote device to stop throttling send data (our receive data)
1572  */
1573 static void unthrottle(struct tty_struct * tty)
1574 {
1575         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1576         unsigned long flags;
1577
1578         if (debug_level >= DEBUG_LEVEL_INFO)
1579                 printk("%s(%d):%s unthrottle() entry\n",
1580                          __FILE__,__LINE__, info->device_name );
1581
1582         if (sanity_check(info, tty->name, "unthrottle"))
1583                 return;
1584
1585         if (I_IXOFF(tty)) {
1586                 if (info->x_char)
1587                         info->x_char = 0;
1588                 else
1589                         send_xchar(tty, START_CHAR(tty));
1590         }
1591
1592         if (tty->termios->c_cflag & CRTSCTS) {
1593                 spin_lock_irqsave(&info->lock,flags);
1594                 info->serial_signals |= SerialSignal_RTS;
1595                 set_signals(info);
1596                 spin_unlock_irqrestore(&info->lock,flags);
1597         }
1598 }
1599
1600 /* set or clear transmit break condition
1601  * break_state  -1=set break condition, 0=clear
1602  */
1603 static void set_break(struct tty_struct *tty, int break_state)
1604 {
1605         unsigned char RegValue;
1606         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1607         unsigned long flags;
1608
1609         if (debug_level >= DEBUG_LEVEL_INFO)
1610                 printk("%s(%d):%s set_break(%d)\n",
1611                          __FILE__,__LINE__, info->device_name, break_state);
1612
1613         if (sanity_check(info, tty->name, "set_break"))
1614                 return;
1615
1616         spin_lock_irqsave(&info->lock,flags);
1617         RegValue = read_reg(info, CTL);
1618         if (break_state == -1)
1619                 RegValue |= BIT3;
1620         else
1621                 RegValue &= ~BIT3;
1622         write_reg(info, CTL, RegValue);
1623         spin_unlock_irqrestore(&info->lock,flags);
1624 }
1625
1626 #ifdef CONFIG_SYNCLINK_SYNCPPP
1627
1628 /* syncppp support and callbacks */
1629
1630 static void cb_setup(struct net_device *dev)
1631 {
1632         dev->open = sppp_cb_open;
1633         dev->stop = sppp_cb_close;
1634         dev->hard_start_xmit = sppp_cb_tx;
1635         dev->do_ioctl = sppp_cb_ioctl;
1636         dev->get_stats = sppp_cb_net_stats;
1637         dev->tx_timeout = sppp_cb_tx_timeout;
1638         dev->watchdog_timeo = 10*HZ;
1639 }
1640
1641 static void sppp_init(SLMP_INFO *info)
1642 {
1643         struct net_device *d;
1644
1645         sprintf(info->netname,"mgslm%dp%d",info->adapter_num,info->port_num);
1646
1647         d = alloc_netdev(0, info->netname, cb_setup);
1648         if (!d) {
1649                 printk(KERN_WARNING "%s: alloc_netdev failed.\n",
1650                                                 info->netname);
1651                 return;
1652         }
1653
1654         info->if_ptr = &info->pppdev;
1655         info->netdev = info->pppdev.dev = d;
1656
1657         d->irq = info->irq_level;
1658         d->priv = info;
1659
1660         sppp_attach(&info->pppdev);
1661         cb_setup(d);
1662
1663         if (register_netdev(d)) {
1664                 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
1665                 sppp_detach(info->netdev);
1666                 info->netdev = NULL;
1667                 info->pppdev.dev = NULL;
1668                 free_netdev(d);
1669                 return;
1670         }
1671
1672         if (debug_level >= DEBUG_LEVEL_INFO)
1673                 printk("sppp_init(%s)\n",info->netname);
1674 }
1675
1676 static void sppp_delete(SLMP_INFO *info)
1677 {
1678         if (debug_level >= DEBUG_LEVEL_INFO)
1679                 printk("sppp_delete(%s)\n",info->netname);
1680         unregister_netdev(info->netdev);
1681         sppp_detach(info->netdev);
1682         free_netdev(info->netdev);
1683         info->netdev = NULL;
1684         info->pppdev.dev = NULL;
1685 }
1686
1687 static int sppp_cb_open(struct net_device *d)
1688 {
1689         SLMP_INFO *info = d->priv;
1690         int err;
1691         unsigned long flags;
1692
1693         if (debug_level >= DEBUG_LEVEL_INFO)
1694                 printk("sppp_cb_open(%s)\n",info->netname);
1695
1696         spin_lock_irqsave(&info->netlock, flags);
1697         if (info->count != 0 || info->netcount != 0) {
1698                 printk(KERN_WARNING "%s: sppp_cb_open returning busy\n", info->netname);
1699                 spin_unlock_irqrestore(&info->netlock, flags);
1700                 return -EBUSY;
1701         }
1702         info->netcount=1;
1703         spin_unlock_irqrestore(&info->netlock, flags);
1704
1705         /* claim resources and init adapter */
1706         if ((err = startup(info)) != 0)
1707                 goto open_fail;
1708
1709         /* allow syncppp module to do open processing */
1710         if ((err = sppp_open(d)) != 0) {
1711                 shutdown(info);
1712                 goto open_fail;
1713         }
1714
1715         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1716         program_hw(info);
1717
1718         d->trans_start = jiffies;
1719         netif_start_queue(d);
1720         return 0;
1721
1722 open_fail:
1723         spin_lock_irqsave(&info->netlock, flags);
1724         info->netcount=0;
1725         spin_unlock_irqrestore(&info->netlock, flags);
1726         return err;
1727 }
1728
1729 static void sppp_cb_tx_timeout(struct net_device *dev)
1730 {
1731         SLMP_INFO *info = dev->priv;
1732         unsigned long flags;
1733
1734         if (debug_level >= DEBUG_LEVEL_INFO)
1735                 printk("sppp_tx_timeout(%s)\n",info->netname);
1736
1737         info->netstats.tx_errors++;
1738         info->netstats.tx_aborted_errors++;
1739
1740         spin_lock_irqsave(&info->lock,flags);
1741         tx_stop(info);
1742         spin_unlock_irqrestore(&info->lock,flags);
1743
1744         netif_wake_queue(dev);
1745 }
1746
1747 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev)
1748 {
1749         SLMP_INFO *info = dev->priv;
1750         unsigned long flags;
1751
1752         if (debug_level >= DEBUG_LEVEL_INFO)
1753                 printk("sppp_tx(%s)\n",info->netname);
1754
1755         netif_stop_queue(dev);
1756
1757         info->tx_count = skb->len;
1758         tx_load_dma_buffer(info, skb->data, skb->len);
1759         info->netstats.tx_packets++;
1760         info->netstats.tx_bytes += skb->len;
1761         dev_kfree_skb(skb);
1762
1763         dev->trans_start = jiffies;
1764
1765         spin_lock_irqsave(&info->lock,flags);
1766         if (!info->tx_active)
1767                 tx_start(info);
1768         spin_unlock_irqrestore(&info->lock,flags);
1769
1770         return 0;
1771 }
1772
1773 static int sppp_cb_close(struct net_device *d)
1774 {
1775         SLMP_INFO *info = d->priv;
1776         unsigned long flags;
1777
1778         if (debug_level >= DEBUG_LEVEL_INFO)
1779                 printk("sppp_cb_close(%s)\n",info->netname);
1780
1781         /* shutdown adapter and release resources */
1782         shutdown(info);
1783
1784         /* allow syncppp to do close processing */
1785         sppp_close(d);
1786         netif_stop_queue(d);
1787
1788         spin_lock_irqsave(&info->netlock, flags);
1789         info->netcount=0;
1790         spin_unlock_irqrestore(&info->netlock, flags);
1791         return 0;
1792 }
1793
1794 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size)
1795 {
1796         struct sk_buff *skb = dev_alloc_skb(size);
1797         if (debug_level >= DEBUG_LEVEL_INFO)
1798                 printk("sppp_rx_done(%s)\n",info->netname);
1799         if (skb == NULL) {
1800                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1801                         info->netname);
1802                 info->netstats.rx_dropped++;
1803                 return;
1804         }
1805
1806         memcpy(skb_put(skb, size),buf,size);
1807
1808         skb->protocol = htons(ETH_P_WAN_PPP);
1809         skb->dev = info->netdev;
1810         skb->mac.raw = skb->data;
1811         info->netstats.rx_packets++;
1812         info->netstats.rx_bytes += size;
1813         netif_rx(skb);
1814         info->netdev->trans_start = jiffies;
1815 }
1816
1817 static void sppp_tx_done(SLMP_INFO *info)
1818 {
1819         if (netif_queue_stopped(info->netdev))
1820             netif_wake_queue(info->netdev);
1821 }
1822
1823 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev)
1824 {
1825         SLMP_INFO *info = dev->priv;
1826         if (debug_level >= DEBUG_LEVEL_INFO)
1827                 printk("net_stats(%s)\n",info->netname);
1828         return &info->netstats;
1829 }
1830
1831 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1832 {
1833         SLMP_INFO *info = dev->priv;
1834         if (debug_level >= DEBUG_LEVEL_INFO)
1835                 printk("%s(%d):ioctl %s cmd=%08X\n", __FILE__,__LINE__,
1836                         info->netname, cmd );
1837         return sppp_do_ioctl(dev, ifr, cmd);
1838 }
1839
1840 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
1841
1842
1843 /* Return next bottom half action to perform.
1844  * Return Value:        BH action code or 0 if nothing to do.
1845  */
1846 int bh_action(SLMP_INFO *info)
1847 {
1848         unsigned long flags;
1849         int rc = 0;
1850
1851         spin_lock_irqsave(&info->lock,flags);
1852
1853         if (info->pending_bh & BH_RECEIVE) {
1854                 info->pending_bh &= ~BH_RECEIVE;
1855                 rc = BH_RECEIVE;
1856         } else if (info->pending_bh & BH_TRANSMIT) {
1857                 info->pending_bh &= ~BH_TRANSMIT;
1858                 rc = BH_TRANSMIT;
1859         } else if (info->pending_bh & BH_STATUS) {
1860                 info->pending_bh &= ~BH_STATUS;
1861                 rc = BH_STATUS;
1862         }
1863
1864         if (!rc) {
1865                 /* Mark BH routine as complete */
1866                 info->bh_running   = 0;
1867                 info->bh_requested = 0;
1868         }
1869
1870         spin_unlock_irqrestore(&info->lock,flags);
1871
1872         return rc;
1873 }
1874
1875 /* Perform bottom half processing of work items queued by ISR.
1876  */
1877 void bh_handler(void* Context)
1878 {
1879         SLMP_INFO *info = (SLMP_INFO*)Context;
1880         int action;
1881
1882         if (!info)
1883                 return;
1884
1885         if ( debug_level >= DEBUG_LEVEL_BH )
1886                 printk( "%s(%d):%s bh_handler() entry\n",
1887                         __FILE__,__LINE__,info->device_name);
1888
1889         info->bh_running = 1;
1890
1891         while((action = bh_action(info)) != 0) {
1892
1893                 /* Process work item */
1894                 if ( debug_level >= DEBUG_LEVEL_BH )
1895                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
1896                                 __FILE__,__LINE__,info->device_name, action);
1897
1898                 switch (action) {
1899
1900                 case BH_RECEIVE:
1901                         bh_receive(info);
1902                         break;
1903                 case BH_TRANSMIT:
1904                         bh_transmit(info);
1905                         break;
1906                 case BH_STATUS:
1907                         bh_status(info);
1908                         break;
1909                 default:
1910                         /* unknown work item ID */
1911                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
1912                                 __FILE__,__LINE__,info->device_name,action);
1913                         break;
1914                 }
1915         }
1916
1917         if ( debug_level >= DEBUG_LEVEL_BH )
1918                 printk( "%s(%d):%s bh_handler() exit\n",
1919                         __FILE__,__LINE__,info->device_name);
1920 }
1921
1922 void bh_receive(SLMP_INFO *info)
1923 {
1924         if ( debug_level >= DEBUG_LEVEL_BH )
1925                 printk( "%s(%d):%s bh_receive()\n",
1926                         __FILE__,__LINE__,info->device_name);
1927
1928         while( rx_get_frame(info) );
1929 }
1930
1931 void bh_transmit(SLMP_INFO *info)
1932 {
1933         struct tty_struct *tty = info->tty;
1934
1935         if ( debug_level >= DEBUG_LEVEL_BH )
1936                 printk( "%s(%d):%s bh_transmit() entry\n",
1937                         __FILE__,__LINE__,info->device_name);
1938
1939         if (tty) {
1940                 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1941                     tty->ldisc.write_wakeup) {
1942                         if ( debug_level >= DEBUG_LEVEL_BH )
1943                                 printk( "%s(%d):%s calling ldisc.write_wakeup\n",
1944                                         __FILE__,__LINE__,info->device_name);
1945                         (tty->ldisc.write_wakeup)(tty);
1946                 }
1947                 wake_up_interruptible(&tty->write_wait);
1948         }
1949 }
1950
1951 void bh_status(SLMP_INFO *info)
1952 {
1953         if ( debug_level >= DEBUG_LEVEL_BH )
1954                 printk( "%s(%d):%s bh_status() entry\n",
1955                         __FILE__,__LINE__,info->device_name);
1956
1957         info->ri_chkcount = 0;
1958         info->dsr_chkcount = 0;
1959         info->dcd_chkcount = 0;
1960         info->cts_chkcount = 0;
1961 }
1962
1963 void isr_timer(SLMP_INFO * info)
1964 {
1965         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
1966
1967         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
1968         write_reg(info, IER2, 0);
1969
1970         /* TMCS, Timer Control/Status Register
1971          *
1972          * 07      CMF, Compare match flag (read only) 1=match
1973          * 06      ECMI, CMF Interrupt Enable: 0=disabled
1974          * 05      Reserved, must be 0
1975          * 04      TME, Timer Enable
1976          * 03..00  Reserved, must be 0
1977          *
1978          * 0000 0000
1979          */
1980         write_reg(info, (unsigned char)(timer + TMCS), 0);
1981
1982         info->irq_occurred = TRUE;
1983
1984         if ( debug_level >= DEBUG_LEVEL_ISR )
1985                 printk("%s(%d):%s isr_timer()\n",
1986                         __FILE__,__LINE__,info->device_name);
1987 }
1988
1989 void isr_rxint(SLMP_INFO * info)
1990 {
1991         struct tty_struct *tty = info->tty;
1992         struct  mgsl_icount *icount = &info->icount;
1993         unsigned char status = read_reg(info, SR1);
1994         unsigned char status2 = read_reg(info, SR2);
1995
1996         /* clear status bits */
1997         if ( status & (FLGD + IDLD + CDCD + BRKD) )
1998                 write_reg(info, SR1,
1999                                 (unsigned char)(status & (FLGD + IDLD + CDCD + BRKD)));
2000
2001         if ( status2 & OVRN )
2002                 write_reg(info, SR2, (unsigned char)(status2 & OVRN));
2003
2004         if ( debug_level >= DEBUG_LEVEL_ISR )
2005                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2006                         __FILE__,__LINE__,info->device_name,status,status2);
2007
2008         if (info->params.mode == MGSL_MODE_ASYNC) {
2009                 if (status & BRKD) {
2010                         icount->brk++;
2011
2012                         /* process break detection if tty control
2013                          * is not set to ignore it
2014                          */
2015                         if ( tty ) {
2016                                 if (!(status & info->ignore_status_mask1)) {
2017                                         if (info->read_status_mask1 & BRKD) {
2018                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2019                                                 if (info->flags & ASYNC_SAK)
2020                                                         do_SAK(tty);
2021                                         }
2022                                 }
2023                         }
2024                 }
2025         }
2026         else {
2027                 if (status & (FLGD|IDLD)) {
2028                         if (status & FLGD)
2029                                 info->icount.exithunt++;
2030                         else if (status & IDLD)
2031                                 info->icount.rxidle++;
2032                         wake_up_interruptible(&info->event_wait_q);
2033                 }
2034         }
2035
2036         if (status & CDCD) {
2037                 /* simulate a common modem status change interrupt
2038                  * for our handler
2039                  */
2040                 get_signals( info );
2041                 isr_io_pin(info,
2042                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2043         }
2044 }
2045
2046 /*
2047  * handle async rx data interrupts
2048  */
2049 void isr_rxrdy(SLMP_INFO * info)
2050 {
2051         u16 status;
2052         unsigned char DataByte;
2053         struct tty_struct *tty = info->tty;
2054         struct  mgsl_icount *icount = &info->icount;
2055
2056         if ( debug_level >= DEBUG_LEVEL_ISR )
2057                 printk("%s(%d):%s isr_rxrdy\n",
2058                         __FILE__,__LINE__,info->device_name);
2059
2060         while((status = read_reg(info,CST0)) & BIT0)
2061         {
2062                 DataByte = read_reg(info,TRB);
2063
2064                 if ( tty ) {
2065                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2066                                 continue;
2067
2068                         *tty->flip.char_buf_ptr = DataByte;
2069                         *tty->flip.flag_buf_ptr = 0;
2070                 }
2071
2072                 icount->rx++;
2073
2074                 if ( status & (PE + FRME + OVRN) ) {
2075                         printk("%s(%d):%s rxerr=%04X\n",
2076                                 __FILE__,__LINE__,info->device_name,status);
2077
2078                         /* update error statistics */
2079                         if (status & PE)
2080                                 icount->parity++;
2081                         else if (status & FRME)
2082                                 icount->frame++;
2083                         else if (status & OVRN)
2084                                 icount->overrun++;
2085
2086                         /* discard char if tty control flags say so */
2087                         if (status & info->ignore_status_mask2)
2088                                 continue;
2089
2090                         status &= info->read_status_mask2;
2091
2092                         if ( tty ) {
2093                                 if (status & PE)
2094                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2095                                 else if (status & FRME)
2096                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2097                                 if (status & OVRN) {
2098                                         /* Overrun is special, since it's
2099                                          * reported immediately, and doesn't
2100                                          * affect the current character
2101                                          */
2102                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2103                                                 tty->flip.count++;
2104                                                 tty->flip.flag_buf_ptr++;
2105                                                 tty->flip.char_buf_ptr++;
2106                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2107                                         }
2108                                 }
2109                         }
2110                 }       /* end of if (error) */
2111
2112                 if ( tty ) {
2113                         tty->flip.flag_buf_ptr++;
2114                         tty->flip.char_buf_ptr++;
2115                         tty->flip.count++;
2116                 }
2117         }
2118
2119         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2120                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2121                         __FILE__,__LINE__,info->device_name,
2122                         tty ? tty->flip.count : 0);
2123                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2124                         __FILE__,__LINE__,info->device_name,
2125                         icount->rx,icount->brk,icount->parity,
2126                         icount->frame,icount->overrun);
2127         }
2128
2129         if ( tty && tty->flip.count )
2130                 tty_flip_buffer_push(tty);
2131 }
2132
2133 void isr_txeom(SLMP_INFO * info, unsigned char status)
2134 {
2135         if ( debug_level >= DEBUG_LEVEL_ISR )
2136                 printk("%s(%d):%s isr_txeom status=%02x\n",
2137                         __FILE__,__LINE__,info->device_name,status);
2138
2139         /* disable and clear MSCI interrupts */
2140         info->ie1_value &= ~(IDLE + UDRN);
2141         write_reg(info, IE1, info->ie1_value);
2142         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2143
2144         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2145         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2146         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2147
2148         if ( info->tx_active ) {
2149                 if (info->params.mode != MGSL_MODE_ASYNC) {
2150                         if (status & UDRN)
2151                                 info->icount.txunder++;
2152                         else if (status & IDLE)
2153                                 info->icount.txok++;
2154                 }
2155
2156                 info->tx_active = 0;
2157                 info->tx_count = info->tx_put = info->tx_get = 0;
2158
2159                 del_timer(&info->tx_timer);
2160
2161                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2162                         info->serial_signals &= ~SerialSignal_RTS;
2163                         info->drop_rts_on_tx_done = 0;
2164                         set_signals(info);
2165                 }
2166
2167 #ifdef CONFIG_SYNCLINK_SYNCPPP
2168                 if (info->netcount)
2169                         sppp_tx_done(info);
2170                 else
2171 #endif
2172                 {
2173                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2174                                 tx_stop(info);
2175                                 return;
2176                         }
2177                         info->pending_bh |= BH_TRANSMIT;
2178                 }
2179         }
2180 }
2181
2182
2183 /*
2184  * handle tx status interrupts
2185  */
2186 void isr_txint(SLMP_INFO * info)
2187 {
2188         unsigned char status = read_reg(info, SR1);
2189
2190         /* clear status bits */
2191         write_reg(info, SR1, (unsigned char)(status & (UDRN + IDLE + CCTS)));
2192
2193         if ( debug_level >= DEBUG_LEVEL_ISR )
2194                 printk("%s(%d):%s isr_txint status=%02x\n",
2195                         __FILE__,__LINE__,info->device_name,status);
2196
2197         if (status & (UDRN + IDLE))
2198                 isr_txeom(info, status);
2199
2200         if (status & CCTS) {
2201                 /* simulate a common modem status change interrupt
2202                  * for our handler
2203                  */
2204                 get_signals( info );
2205                 isr_io_pin(info,
2206                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2207
2208         }
2209 }
2210
2211 /*
2212  * handle async tx data interrupts
2213  */
2214 void isr_txrdy(SLMP_INFO * info)
2215 {
2216         if ( debug_level >= DEBUG_LEVEL_ISR )
2217                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2218                         __FILE__,__LINE__,info->device_name,info->tx_count);
2219
2220         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2221                 tx_stop(info);
2222                 return;
2223         }
2224
2225         if ( info->tx_count )
2226                 tx_load_fifo( info );
2227         else {
2228                 info->tx_active = 0;
2229                 info->ie0_value &= ~TXRDYE;
2230                 write_reg(info, IE0, info->ie0_value);
2231         }
2232
2233         if (info->tx_count < WAKEUP_CHARS)
2234                 info->pending_bh |= BH_TRANSMIT;
2235 }
2236
2237 void isr_rxdmaok(SLMP_INFO * info)
2238 {
2239         /* BIT7 = EOT (end of transfer)
2240          * BIT6 = EOM (end of message/frame)
2241          */
2242         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2243
2244         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2245         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2246
2247         if ( debug_level >= DEBUG_LEVEL_ISR )
2248                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2249                         __FILE__,__LINE__,info->device_name,status);
2250
2251         info->pending_bh |= BH_RECEIVE;
2252 }
2253
2254 void isr_rxdmaerror(SLMP_INFO * info)
2255 {
2256         /* BIT5 = BOF (buffer overflow)
2257          * BIT4 = COF (counter overflow)
2258          */
2259         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2260
2261         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2262         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2263
2264         if ( debug_level >= DEBUG_LEVEL_ISR )
2265                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2266                         __FILE__,__LINE__,info->device_name,status);
2267
2268         info->rx_overflow = TRUE;
2269         info->pending_bh |= BH_RECEIVE;
2270 }
2271
2272 void isr_txdmaok(SLMP_INFO * info)
2273 {
2274         /* BIT7 = EOT (end of transfer, used for async mode)
2275          * BIT6 = EOM (end of message/frame, used for sync mode)
2276          *
2277          * We don't look at DMA status because only EOT is enabled
2278          * and we always clear and disable all tx DMA IRQs.
2279          */
2280 //      unsigned char dma_status = read_reg(info,TXDMA + DSR) & 0xc0;
2281         unsigned char status_reg1 = read_reg(info, SR1);
2282
2283         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2284         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2285         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2286
2287         if ( debug_level >= DEBUG_LEVEL_ISR )
2288                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2289                         __FILE__,__LINE__,info->device_name,status_reg1);
2290
2291         /* If transmitter already idle, do end of frame processing,
2292          * otherwise enable interrupt for tx IDLE.
2293          */
2294         if (status_reg1 & IDLE)
2295                 isr_txeom(info, IDLE);
2296         else {
2297                 /* disable and clear underrun IRQ, enable IDLE interrupt */
2298                 info->ie1_value |= IDLE;
2299                 info->ie1_value &= ~UDRN;
2300                 write_reg(info, IE1, info->ie1_value);
2301
2302                 write_reg(info, SR1, UDRN);
2303         }
2304 }
2305
2306 void isr_txdmaerror(SLMP_INFO * info)
2307 {
2308         /* BIT5 = BOF (buffer overflow)
2309          * BIT4 = COF (counter overflow)
2310          */
2311         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2312
2313         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2314         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2315
2316         if ( debug_level >= DEBUG_LEVEL_ISR )
2317                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2318                         __FILE__,__LINE__,info->device_name,status);
2319 }
2320
2321 /* handle input serial signal changes
2322  */
2323 void isr_io_pin( SLMP_INFO *info, u16 status )
2324 {
2325         struct  mgsl_icount *icount;
2326
2327         if ( debug_level >= DEBUG_LEVEL_ISR )
2328                 printk("%s(%d):isr_io_pin status=%04X\n",
2329                         __FILE__,__LINE__,status);
2330
2331         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2332                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2333                 icount = &info->icount;
2334                 /* update input line counters */
2335                 if (status & MISCSTATUS_RI_LATCHED) {
2336                         icount->rng++;
2337                         if ( status & SerialSignal_RI )
2338                                 info->input_signal_events.ri_up++;
2339                         else
2340                                 info->input_signal_events.ri_down++;
2341                 }
2342                 if (status & MISCSTATUS_DSR_LATCHED) {
2343                         icount->dsr++;
2344                         if ( status & SerialSignal_DSR )
2345                                 info->input_signal_events.dsr_up++;
2346                         else
2347                                 info->input_signal_events.dsr_down++;
2348                 }
2349                 if (status & MISCSTATUS_DCD_LATCHED) {
2350                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2351                                 info->ie1_value &= ~CDCD;
2352                                 write_reg(info, IE1, info->ie1_value);
2353                         }
2354                         icount->dcd++;
2355                         if (status & SerialSignal_DCD) {
2356                                 info->input_signal_events.dcd_up++;
2357 #ifdef CONFIG_SYNCLINK_SYNCPPP
2358                                 if (info->netcount)
2359                                         sppp_reopen(info->netdev);
2360 #endif
2361                         } else
2362                                 info->input_signal_events.dcd_down++;
2363                 }
2364                 if (status & MISCSTATUS_CTS_LATCHED)
2365                 {
2366                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2367                                 info->ie1_value &= ~CCTS;
2368                                 write_reg(info, IE1, info->ie1_value);
2369                         }
2370                         icount->cts++;
2371                         if ( status & SerialSignal_CTS )
2372                                 info->input_signal_events.cts_up++;
2373                         else
2374                                 info->input_signal_events.cts_down++;
2375                 }
2376                 wake_up_interruptible(&info->status_event_wait_q);
2377                 wake_up_interruptible(&info->event_wait_q);
2378
2379                 if ( (info->flags & ASYNC_CHECK_CD) &&
2380                      (status & MISCSTATUS_DCD_LATCHED) ) {
2381                         if ( debug_level >= DEBUG_LEVEL_ISR )
2382                                 printk("%s CD now %s...", info->device_name,
2383                                        (status & SerialSignal_DCD) ? "on" : "off");
2384                         if (status & SerialSignal_DCD)
2385                                 wake_up_interruptible(&info->open_wait);
2386                         else {
2387                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2388                                         printk("doing serial hangup...");
2389                                 if (info->tty)
2390                                         tty_hangup(info->tty);
2391                         }
2392                 }
2393
2394                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2395                      (status & MISCSTATUS_CTS_LATCHED) ) {
2396                         if ( info->tty ) {
2397                                 if (info->tty->hw_stopped) {
2398                                         if (status & SerialSignal_CTS) {
2399                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2400                                                         printk("CTS tx start...");
2401                                                 info->tty->hw_stopped = 0;
2402                                                 tx_start(info);
2403                                                 info->pending_bh |= BH_TRANSMIT;
2404                                                 return;
2405                                         }
2406                                 } else {
2407                                         if (!(status & SerialSignal_CTS)) {
2408                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2409                                                         printk("CTS tx stop...");
2410                                                 info->tty->hw_stopped = 1;
2411                                                 tx_stop(info);
2412                                         }
2413                                 }
2414                         }
2415                 }
2416         }
2417
2418         info->pending_bh |= BH_STATUS;
2419 }
2420
2421 /* Interrupt service routine entry point.
2422  *
2423  * Arguments:
2424  *      irq             interrupt number that caused interrupt
2425  *      dev_id          device ID supplied during interrupt registration
2426  *      regs            interrupted processor context
2427  */
2428 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2429                                         struct pt_regs *regs)
2430 {
2431         SLMP_INFO * info;
2432         unsigned char status, status0, status1=0;
2433         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2434         unsigned char timerstatus0, timerstatus1=0;
2435         unsigned char shift;
2436         unsigned int i;
2437         unsigned short tmp;
2438
2439         if ( debug_level >= DEBUG_LEVEL_ISR )
2440                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2441                         __FILE__,__LINE__,irq);
2442
2443         info = (SLMP_INFO *)dev_id;
2444         if (!info)
2445                 return IRQ_NONE;
2446
2447         spin_lock(&info->lock);
2448
2449         for(;;) {
2450
2451                 /* get status for SCA0 (ports 0-1) */
2452                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2453                 status0 = (unsigned char)tmp;
2454                 dmastatus0 = (unsigned char)(tmp>>8);
2455                 timerstatus0 = read_reg(info, ISR2);
2456
2457                 if ( debug_level >= DEBUG_LEVEL_ISR )
2458                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2459                                 __FILE__,__LINE__,info->device_name,
2460                                 status0,dmastatus0,timerstatus0);
2461
2462                 if (info->port_count == 4) {
2463                         /* get status for SCA1 (ports 2-3) */
2464                         tmp = read_reg16(info->port_array[2], ISR0);
2465                         status1 = (unsigned char)tmp;
2466                         dmastatus1 = (unsigned char)(tmp>>8);
2467                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2468
2469                         if ( debug_level >= DEBUG_LEVEL_ISR )
2470                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2471                                         __FILE__,__LINE__,info->device_name,
2472                                         status1,dmastatus1,timerstatus1);
2473                 }
2474
2475                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2476                          !status1 && !dmastatus1 && !timerstatus1)
2477                         break;
2478
2479                 for(i=0; i < info->port_count ; i++) {
2480                         if (info->port_array[i] == NULL)
2481                                 continue;
2482                         if (i < 2) {
2483                                 status = status0;
2484                                 dmastatus = dmastatus0;
2485                         } else {
2486                                 status = status1;
2487                                 dmastatus = dmastatus1;
2488                         }
2489
2490                         shift = i & 1 ? 4 :0;
2491
2492                         if (status & BIT0 << shift)
2493                                 isr_rxrdy(info->port_array[i]);
2494                         if (status & BIT1 << shift)
2495                                 isr_txrdy(info->port_array[i]);
2496                         if (status & BIT2 << shift)
2497                                 isr_rxint(info->port_array[i]);
2498                         if (status & BIT3 << shift)
2499                                 isr_txint(info->port_array[i]);
2500
2501                         if (dmastatus & BIT0 << shift)
2502                                 isr_rxdmaerror(info->port_array[i]);
2503                         if (dmastatus & BIT1 << shift)
2504                                 isr_rxdmaok(info->port_array[i]);
2505                         if (dmastatus & BIT2 << shift)
2506                                 isr_txdmaerror(info->port_array[i]);
2507                         if (dmastatus & BIT3 << shift)
2508                                 isr_txdmaok(info->port_array[i]);
2509                 }
2510
2511                 if (timerstatus0 & (BIT5 | BIT4))
2512                         isr_timer(info->port_array[0]);
2513                 if (timerstatus0 & (BIT7 | BIT6))
2514                         isr_timer(info->port_array[1]);
2515                 if (timerstatus1 & (BIT5 | BIT4))
2516                         isr_timer(info->port_array[2]);
2517                 if (timerstatus1 & (BIT7 | BIT6))
2518                         isr_timer(info->port_array[3]);
2519         }
2520
2521         for(i=0; i < info->port_count ; i++) {
2522                 SLMP_INFO * port = info->port_array[i];
2523
2524                 /* Request bottom half processing if there's something
2525                  * for it to do and the bh is not already running.
2526                  *
2527                  * Note: startup adapter diags require interrupts.
2528                  * do not request bottom half processing if the
2529                  * device is not open in a normal mode.
2530                  */
2531                 if ( port && (port->count || port->netcount) &&
2532                      port->pending_bh && !port->bh_running &&
2533                      !port->bh_requested ) {
2534                         if ( debug_level >= DEBUG_LEVEL_ISR )
2535                                 printk("%s(%d):%s queueing bh task.\n",
2536                                         __FILE__,__LINE__,port->device_name);
2537                         schedule_work(&port->task);
2538                         port->bh_requested = 1;
2539                 }
2540         }
2541
2542         spin_unlock(&info->lock);
2543
2544         if ( debug_level >= DEBUG_LEVEL_ISR )
2545                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2546                         __FILE__,__LINE__,irq);
2547         return IRQ_HANDLED;
2548 }
2549
2550 /* Initialize and start device.
2551  */
2552 static int startup(SLMP_INFO * info)
2553 {
2554         if ( debug_level >= DEBUG_LEVEL_INFO )
2555                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2556
2557         if (info->flags & ASYNC_INITIALIZED)
2558                 return 0;
2559
2560         if (!info->tx_buf) {
2561                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2562                 if (!info->tx_buf) {
2563                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2564                                 __FILE__,__LINE__,info->device_name);
2565                         return -ENOMEM;
2566                 }
2567         }
2568
2569         info->pending_bh = 0;
2570
2571         /* program hardware for current parameters */
2572         reset_port(info);
2573
2574         change_params(info);
2575
2576         info->status_timer.expires = jiffies + jiffies_from_ms(10);
2577         add_timer(&info->status_timer);
2578
2579         if (info->tty)
2580                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2581
2582         info->flags |= ASYNC_INITIALIZED;
2583
2584         return 0;
2585 }
2586
2587 /* Called by close() and hangup() to shutdown hardware
2588  */
2589 static void shutdown(SLMP_INFO * info)
2590 {
2591         unsigned long flags;
2592
2593         if (!(info->flags & ASYNC_INITIALIZED))
2594                 return;
2595
2596         if (debug_level >= DEBUG_LEVEL_INFO)
2597                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2598                          __FILE__,__LINE__, info->device_name );
2599
2600         /* clear status wait queue because status changes */
2601         /* can't happen after shutting down the hardware */
2602         wake_up_interruptible(&info->status_event_wait_q);
2603         wake_up_interruptible(&info->event_wait_q);
2604
2605         del_timer(&info->tx_timer);
2606         del_timer(&info->status_timer);
2607
2608         if (info->tx_buf) {
2609                 kfree(info->tx_buf);
2610                 info->tx_buf = 0;
2611         }
2612
2613         spin_lock_irqsave(&info->lock,flags);
2614
2615         reset_port(info);
2616
2617         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2618                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2619                 set_signals(info);
2620         }
2621
2622         spin_unlock_irqrestore(&info->lock,flags);
2623
2624         if (info->tty)
2625                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2626
2627         info->flags &= ~ASYNC_INITIALIZED;
2628 }
2629
2630 static void program_hw(SLMP_INFO *info)
2631 {
2632         unsigned long flags;
2633
2634         spin_lock_irqsave(&info->lock,flags);
2635
2636         rx_stop(info);
2637         tx_stop(info);
2638
2639         info->tx_count = info->tx_put = info->tx_get = 0;
2640
2641         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2642                 hdlc_mode(info);
2643         else
2644                 async_mode(info);
2645
2646         set_signals(info);
2647
2648         info->dcd_chkcount = 0;
2649         info->cts_chkcount = 0;
2650         info->ri_chkcount = 0;
2651         info->dsr_chkcount = 0;
2652
2653         info->ie1_value |= (CDCD|CCTS);
2654         write_reg(info, IE1, info->ie1_value);
2655
2656         get_signals(info);
2657
2658         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2659                 rx_start(info);
2660
2661         spin_unlock_irqrestore(&info->lock,flags);
2662 }
2663
2664 /* Reconfigure adapter based on new parameters
2665  */
2666 static void change_params(SLMP_INFO *info)
2667 {
2668         unsigned cflag;
2669         int bits_per_char;
2670
2671         if (!info->tty || !info->tty->termios)
2672                 return;
2673
2674         if (debug_level >= DEBUG_LEVEL_INFO)
2675                 printk("%s(%d):%s change_params()\n",
2676                          __FILE__,__LINE__, info->device_name );
2677
2678         cflag = info->tty->termios->c_cflag;
2679
2680         /* if B0 rate (hangup) specified then negate DTR and RTS */
2681         /* otherwise assert DTR and RTS */
2682         if (cflag & CBAUD)
2683                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2684         else
2685                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2686
2687         /* byte size and parity */
2688
2689         switch (cflag & CSIZE) {
2690               case CS5: info->params.data_bits = 5; break;
2691               case CS6: info->params.data_bits = 6; break;
2692               case CS7: info->params.data_bits = 7; break;
2693               case CS8: info->params.data_bits = 8; break;
2694               /* Never happens, but GCC is too dumb to figure it out */
2695               default:  info->params.data_bits = 7; break;
2696               }
2697
2698         if (cflag & CSTOPB)
2699                 info->params.stop_bits = 2;
2700         else
2701                 info->params.stop_bits = 1;
2702
2703         info->params.parity = ASYNC_PARITY_NONE;
2704         if (cflag & PARENB) {
2705                 if (cflag & PARODD)
2706                         info->params.parity = ASYNC_PARITY_ODD;
2707                 else
2708                         info->params.parity = ASYNC_PARITY_EVEN;
2709 #ifdef CMSPAR
2710                 if (cflag & CMSPAR)
2711                         info->params.parity = ASYNC_PARITY_SPACE;
2712 #endif
2713         }
2714
2715         /* calculate number of jiffies to transmit a full
2716          * FIFO (32 bytes) at specified data rate
2717          */
2718         bits_per_char = info->params.data_bits +
2719                         info->params.stop_bits + 1;
2720
2721         /* if port data rate is set to 460800 or less then
2722          * allow tty settings to override, otherwise keep the
2723          * current data rate.
2724          */
2725         if (info->params.data_rate <= 460800) {
2726                 info->params.data_rate = tty_get_baud_rate(info->tty);
2727         }
2728
2729         if ( info->params.data_rate ) {
2730                 info->timeout = (32*HZ*bits_per_char) /
2731                                 info->params.data_rate;
2732         }
2733         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2734
2735         if (cflag & CRTSCTS)
2736                 info->flags |= ASYNC_CTS_FLOW;
2737         else
2738                 info->flags &= ~ASYNC_CTS_FLOW;
2739
2740         if (cflag & CLOCAL)
2741                 info->flags &= ~ASYNC_CHECK_CD;
2742         else
2743                 info->flags |= ASYNC_CHECK_CD;
2744
2745         /* process tty input control flags */
2746
2747         info->read_status_mask2 = OVRN;
2748         if (I_INPCK(info->tty))
2749                 info->read_status_mask2 |= PE | FRME;
2750         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2751                 info->read_status_mask1 |= BRKD;
2752         if (I_IGNPAR(info->tty))
2753                 info->ignore_status_mask2 |= PE | FRME;
2754         if (I_IGNBRK(info->tty)) {
2755                 info->ignore_status_mask1 |= BRKD;
2756                 /* If ignoring parity and break indicators, ignore
2757                  * overruns too.  (For real raw support).
2758                  */
2759                 if (I_IGNPAR(info->tty))
2760                         info->ignore_status_mask2 |= OVRN;
2761         }
2762
2763         program_hw(info);
2764 }
2765
2766 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2767 {
2768         int err;
2769
2770         if (debug_level >= DEBUG_LEVEL_INFO)
2771                 printk("%s(%d):%s get_params()\n",
2772                          __FILE__,__LINE__, info->device_name);
2773
2774         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2775         if (err) {
2776                 if ( debug_level >= DEBUG_LEVEL_INFO )
2777                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2778                                 __FILE__,__LINE__,info->device_name);
2779                 return -EFAULT;
2780         }
2781
2782         return 0;
2783 }
2784
2785 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2786 {
2787         int err;
2788         if (debug_level >= DEBUG_LEVEL_INFO)
2789                 printk("%s(%d):%s get_params()\n",
2790                          __FILE__,__LINE__, info->device_name);
2791
2792         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2793         if (err) {
2794                 if ( debug_level >= DEBUG_LEVEL_INFO )
2795                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2796                                 __FILE__,__LINE__,info->device_name);
2797                 return -EFAULT;
2798         }
2799
2800         return 0;
2801 }
2802
2803 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2804 {
2805         unsigned long flags;
2806         MGSL_PARAMS tmp_params;
2807         int err;
2808
2809         if (debug_level >= DEBUG_LEVEL_INFO)
2810                 printk("%s(%d):%s set_params\n",
2811                         __FILE__,__LINE__,info->device_name );
2812         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2813         if (err) {
2814                 if ( debug_level >= DEBUG_LEVEL_INFO )
2815                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2816                                 __FILE__,__LINE__,info->device_name);
2817                 return -EFAULT;
2818         }
2819
2820         spin_lock_irqsave(&info->lock,flags);
2821         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2822         spin_unlock_irqrestore(&info->lock,flags);
2823
2824         change_params(info);
2825
2826         return 0;
2827 }
2828
2829 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2830 {
2831         int err;
2832
2833         if (debug_level >= DEBUG_LEVEL_INFO)
2834                 printk("%s(%d):%s get_txidle()=%d\n",
2835                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2836
2837         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2838         if (err) {
2839                 if ( debug_level >= DEBUG_LEVEL_INFO )
2840                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2841                                 __FILE__,__LINE__,info->device_name);
2842                 return -EFAULT;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static int set_txidle(SLMP_INFO * info, int idle_mode)
2849 {
2850         unsigned long flags;
2851
2852         if (debug_level >= DEBUG_LEVEL_INFO)
2853                 printk("%s(%d):%s set_txidle(%d)\n",
2854                         __FILE__,__LINE__,info->device_name, idle_mode );
2855
2856         spin_lock_irqsave(&info->lock,flags);
2857         info->idle_mode = idle_mode;
2858         tx_set_idle( info );
2859         spin_unlock_irqrestore(&info->lock,flags);
2860         return 0;
2861 }
2862
2863 static int tx_enable(SLMP_INFO * info, int enable)
2864 {
2865         unsigned long flags;
2866
2867         if (debug_level >= DEBUG_LEVEL_INFO)
2868                 printk("%s(%d):%s tx_enable(%d)\n",
2869                         __FILE__,__LINE__,info->device_name, enable);
2870
2871         spin_lock_irqsave(&info->lock,flags);
2872         if ( enable ) {
2873                 if ( !info->tx_enabled ) {
2874                         tx_start(info);
2875                 }
2876         } else {
2877                 if ( info->tx_enabled )
2878                         tx_stop(info);
2879         }
2880         spin_unlock_irqrestore(&info->lock,flags);
2881         return 0;
2882 }
2883
2884 /* abort send HDLC frame
2885  */
2886 static int tx_abort(SLMP_INFO * info)
2887 {
2888         unsigned long flags;
2889
2890         if (debug_level >= DEBUG_LEVEL_INFO)
2891                 printk("%s(%d):%s tx_abort()\n",
2892                         __FILE__,__LINE__,info->device_name);
2893
2894         spin_lock_irqsave(&info->lock,flags);
2895         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2896                 info->ie1_value &= ~UDRN;
2897                 info->ie1_value |= IDLE;
2898                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2899                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
2900
2901                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
2902                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2903
2904                 write_reg(info, CMD, TXABORT);
2905         }
2906         spin_unlock_irqrestore(&info->lock,flags);
2907         return 0;
2908 }
2909
2910 static int rx_enable(SLMP_INFO * info, int enable)
2911 {
2912         unsigned long flags;
2913
2914         if (debug_level >= DEBUG_LEVEL_INFO)
2915                 printk("%s(%d):%s rx_enable(%d)\n",
2916                         __FILE__,__LINE__,info->device_name,enable);
2917
2918         spin_lock_irqsave(&info->lock,flags);
2919         if ( enable ) {
2920                 if ( !info->rx_enabled )
2921                         rx_start(info);
2922         } else {
2923                 if ( info->rx_enabled )
2924                         rx_stop(info);
2925         }
2926         spin_unlock_irqrestore(&info->lock,flags);
2927         return 0;
2928 }
2929
2930 static int map_status(int signals)
2931 {
2932         /* Map status bits to API event bits */
2933
2934         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
2935                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
2936                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
2937                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
2938 }
2939
2940 /* wait for specified event to occur
2941  */
2942 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2943 {
2944         unsigned long flags;
2945         int s;
2946         int rc=0;
2947         struct mgsl_icount cprev, cnow;
2948         int events;
2949         int mask;
2950         struct  _input_signal_events oldsigs, newsigs;
2951         DECLARE_WAITQUEUE(wait, current);
2952
2953         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2954         if (rc) {
2955                 return  -EFAULT;
2956         }
2957
2958         if (debug_level >= DEBUG_LEVEL_INFO)
2959                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
2960                         __FILE__,__LINE__,info->device_name,mask);
2961
2962         spin_lock_irqsave(&info->lock,flags);
2963
2964         /* return immediately if state matches requested events */
2965         get_signals(info);
2966         s = map_status(info->serial_signals);
2967
2968         events = mask &
2969                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2970                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2971                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2972                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2973         if (events) {
2974                 spin_unlock_irqrestore(&info->lock,flags);
2975                 goto exit;
2976         }
2977
2978         /* save current irq counts */
2979         cprev = info->icount;
2980         oldsigs = info->input_signal_events;
2981
2982         /* enable hunt and idle irqs if needed */
2983         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2984                 unsigned char oldval = info->ie1_value;
2985                 unsigned char newval = oldval +
2986                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
2987                          (mask & MgslEvent_IdleReceived ? IDLE:0);
2988                 if ( oldval != newval ) {
2989                         info->ie1_value = newval;
2990                         write_reg(info, IE1, info->ie1_value);
2991                 }
2992         }
2993
2994         set_current_state(TASK_INTERRUPTIBLE);
2995         add_wait_queue(&info->event_wait_q, &wait);
2996
2997         spin_unlock_irqrestore(&info->lock,flags);
2998
2999         for(;;) {
3000                 schedule();
3001                 if (signal_pending(current)) {
3002                         rc = -ERESTARTSYS;
3003                         break;
3004                 }
3005
3006                 /* get current irq counts */
3007                 spin_lock_irqsave(&info->lock,flags);
3008                 cnow = info->icount;
3009                 newsigs = info->input_signal_events;
3010                 set_current_state(TASK_INTERRUPTIBLE);
3011                 spin_unlock_irqrestore(&info->lock,flags);
3012
3013                 /* if no change, wait aborted for some reason */
3014                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3015                     newsigs.dsr_down == oldsigs.dsr_down &&
3016                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3017                     newsigs.dcd_down == oldsigs.dcd_down &&
3018                     newsigs.cts_up   == oldsigs.cts_up   &&
3019                     newsigs.cts_down == oldsigs.cts_down &&
3020                     newsigs.ri_up    == oldsigs.ri_up    &&
3021                     newsigs.ri_down  == oldsigs.ri_down  &&
3022                     cnow.exithunt    == cprev.exithunt   &&
3023                     cnow.rxidle      == cprev.rxidle) {
3024                         rc = -EIO;
3025                         break;
3026                 }
3027
3028                 events = mask &
3029                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3030                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3031                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3032                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3033                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3034                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3035                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3036                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3037                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3038                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3039                 if (events)
3040                         break;
3041
3042                 cprev = cnow;
3043                 oldsigs = newsigs;
3044         }
3045
3046         remove_wait_queue(&info->event_wait_q, &wait);
3047         set_current_state(TASK_RUNNING);
3048
3049
3050         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3051                 spin_lock_irqsave(&info->lock,flags);
3052                 if (!waitqueue_active(&info->event_wait_q)) {
3053                         /* disable enable exit hunt mode/idle rcvd IRQs */
3054                         info->ie1_value &= ~(FLGD|IDLE);
3055                         write_reg(info, IE1, info->ie1_value);
3056                 }
3057                 spin_unlock_irqrestore(&info->lock,flags);
3058         }
3059 exit:
3060         if ( rc == 0 )
3061                 PUT_USER(rc, events, mask_ptr);
3062
3063         return rc;
3064 }
3065
3066 static int modem_input_wait(SLMP_INFO *info,int arg)
3067 {
3068         unsigned long flags;
3069         int rc;
3070         struct mgsl_icount cprev, cnow;
3071         DECLARE_WAITQUEUE(wait, current);
3072
3073         /* save current irq counts */
3074         spin_lock_irqsave(&info->lock,flags);
3075         cprev = info->icount;
3076         add_wait_queue(&info->status_event_wait_q, &wait);
3077         set_current_state(TASK_INTERRUPTIBLE);
3078         spin_unlock_irqrestore(&info->lock,flags);
3079
3080         for(;;) {
3081                 schedule();
3082                 if (signal_pending(current)) {
3083                         rc = -ERESTARTSYS;
3084                         break;
3085                 }
3086
3087                 /* get new irq counts */
3088                 spin_lock_irqsave(&info->lock,flags);
3089                 cnow = info->icount;
3090                 set_current_state(TASK_INTERRUPTIBLE);
3091                 spin_unlock_irqrestore(&info->lock,flags);
3092
3093                 /* if no change, wait aborted for some reason */
3094                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3095                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3096                         rc = -EIO;
3097                         break;
3098                 }
3099
3100                 /* check for change in caller specified modem input */
3101                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3102                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3103                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3104                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3105                         rc = 0;
3106                         break;
3107                 }
3108
3109                 cprev = cnow;
3110         }
3111         remove_wait_queue(&info->status_event_wait_q, &wait);
3112         set_current_state(TASK_RUNNING);
3113         return rc;
3114 }
3115
3116 /* return the state of the serial control and status signals
3117  */
3118 static int tiocmget(struct tty_struct *tty, struct file *file)
3119 {
3120         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3121         unsigned int result;
3122         unsigned long flags;
3123
3124         spin_lock_irqsave(&info->lock,flags);
3125         get_signals(info);
3126         spin_unlock_irqrestore(&info->lock,flags);
3127
3128         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3129                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3130                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3131                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3132                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3133                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3134
3135         if (debug_level >= DEBUG_LEVEL_INFO)
3136                 printk("%s(%d):%s tiocmget() value=%08X\n",
3137                          __FILE__,__LINE__, info->device_name, result );
3138         return result;
3139 }
3140
3141 /* set modem control signals (DTR/RTS)
3142  */
3143 static int tiocmset(struct tty_struct *tty, struct file *file,
3144                     unsigned int set, unsigned int clear)
3145 {
3146         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3147         unsigned long flags;
3148
3149         if (debug_level >= DEBUG_LEVEL_INFO)
3150                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3151                         __FILE__,__LINE__,info->device_name, set, clear);
3152
3153         if (set & TIOCM_RTS)
3154                 info->serial_signals |= SerialSignal_RTS;
3155         if (set & TIOCM_DTR)
3156                 info->serial_signals |= SerialSignal_DTR;
3157         if (clear & TIOCM_RTS)
3158                 info->serial_signals &= ~SerialSignal_RTS;
3159         if (clear & TIOCM_DTR)
3160                 info->serial_signals &= ~SerialSignal_DTR;
3161
3162         spin_lock_irqsave(&info->lock,flags);
3163         set_signals(info);
3164         spin_unlock_irqrestore(&info->lock,flags);
3165
3166         return 0;
3167 }
3168
3169
3170
3171 /* Block the current process until the specified port is ready to open.
3172  */
3173 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3174                            SLMP_INFO *info)
3175 {
3176         DECLARE_WAITQUEUE(wait, current);
3177         int             retval;
3178         int             do_clocal = 0, extra_count = 0;
3179         unsigned long   flags;
3180
3181         if (debug_level >= DEBUG_LEVEL_INFO)
3182                 printk("%s(%d):%s block_til_ready()\n",
3183                          __FILE__,__LINE__, tty->driver->name );
3184
3185         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3186                 /* nonblock mode is set or port is not enabled */
3187                 /* just verify that callout device is not active */
3188                 info->flags |= ASYNC_NORMAL_ACTIVE;
3189                 return 0;
3190         }
3191
3192         if (tty->termios->c_cflag & CLOCAL)
3193                 do_clocal = 1;
3194
3195         /* Wait for carrier detect and the line to become
3196          * free (i.e., not in use by the callout).  While we are in
3197          * this loop, info->count is dropped by one, so that
3198          * close() knows when to free things.  We restore it upon
3199          * exit, either normal or abnormal.
3200          */
3201
3202         retval = 0;
3203         add_wait_queue(&info->open_wait, &wait);
3204
3205         if (debug_level >= DEBUG_LEVEL_INFO)
3206                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3207                          __FILE__,__LINE__, tty->driver->name, info->count );
3208
3209         spin_lock_irqsave(&info->lock, flags);
3210         if (!tty_hung_up_p(filp)) {
3211                 extra_count = 1;
3212                 info->count--;
3213         }
3214         spin_unlock_irqrestore(&info->lock, flags);
3215         info->blocked_open++;
3216
3217         while (1) {
3218                 if ((tty->termios->c_cflag & CBAUD)) {
3219                         spin_lock_irqsave(&info->lock,flags);
3220                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3221                         set_signals(info);
3222                         spin_unlock_irqrestore(&info->lock,flags);
3223                 }
3224
3225                 set_current_state(TASK_INTERRUPTIBLE);
3226
3227                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3228                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3229                                         -EAGAIN : -ERESTARTSYS;
3230                         break;
3231                 }
3232
3233                 spin_lock_irqsave(&info->lock,flags);
3234                 get_signals(info);
3235                 spin_unlock_irqrestore(&info->lock,flags);
3236
3237                 if (!(info->flags & ASYNC_CLOSING) &&
3238                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3239                         break;
3240                 }
3241
3242                 if (signal_pending(current)) {
3243                         retval = -ERESTARTSYS;
3244                         break;
3245                 }
3246
3247                 if (debug_level >= DEBUG_LEVEL_INFO)
3248                         printk("%s(%d):%s block_til_ready() count=%d\n",
3249                                  __FILE__,__LINE__, tty->driver->name, info->count );
3250
3251                 schedule();
3252         }
3253
3254         set_current_state(TASK_RUNNING);
3255         remove_wait_queue(&info->open_wait, &wait);
3256
3257         if (extra_count)
3258                 info->count++;
3259         info->blocked_open--;
3260
3261         if (debug_level >= DEBUG_LEVEL_INFO)
3262                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3263                          __FILE__,__LINE__, tty->driver->name, info->count );
3264
3265         if (!retval)
3266                 info->flags |= ASYNC_NORMAL_ACTIVE;
3267
3268         return retval;
3269 }
3270
3271 int alloc_dma_bufs(SLMP_INFO *info)
3272 {
3273         unsigned short BuffersPerFrame;
3274         unsigned short BufferCount;
3275
3276         // Force allocation to start at 64K boundary for each port.
3277         // This is necessary because *all* buffer descriptors for a port
3278         // *must* be in the same 64K block. All descriptors on a port
3279         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3280         // into the CBP register.
3281         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3282
3283         /* Calculate the number of DMA buffers necessary to hold the */
3284         /* largest allowable frame size. Note: If the max frame size is */
3285         /* not an even multiple of the DMA buffer size then we need to */
3286         /* round the buffer count per frame up one. */
3287
3288         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3289         if ( info->max_frame_size % SCABUFSIZE )
3290                 BuffersPerFrame++;
3291
3292         /* calculate total number of data buffers (SCABUFSIZE) possible
3293          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3294          * for the descriptor list (BUFFERLISTSIZE).
3295          */
3296         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3297
3298         /* limit number of buffers to maximum amount of descriptors */
3299         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3300                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3301
3302         /* use enough buffers to transmit one max size frame */
3303         info->tx_buf_count = BuffersPerFrame + 1;
3304
3305         /* never use more than half the available buffers for transmit */
3306         if (info->tx_buf_count > (BufferCount/2))
3307                 info->tx_buf_count = BufferCount/2;
3308
3309         if (info->tx_buf_count > SCAMAXDESC)
3310                 info->tx_buf_count = SCAMAXDESC;
3311
3312         /* use remaining buffers for receive */
3313         info->rx_buf_count = BufferCount - info->tx_buf_count;
3314
3315         if (info->rx_buf_count > SCAMAXDESC)
3316                 info->rx_buf_count = SCAMAXDESC;
3317
3318         if ( debug_level >= DEBUG_LEVEL_INFO )
3319                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3320                         __FILE__,__LINE__, info->device_name,
3321                         info->tx_buf_count,info->rx_buf_count);
3322
3323         if ( alloc_buf_list( info ) < 0 ||
3324                 alloc_frame_bufs(info,
3325                                         info->rx_buf_list,
3326                                         info->rx_buf_list_ex,
3327                                         info->rx_buf_count) < 0 ||
3328                 alloc_frame_bufs(info,
3329                                         info->tx_buf_list,
3330                                         info->tx_buf_list_ex,
3331                                         info->tx_buf_count) < 0 ||
3332                 alloc_tmp_rx_buf(info) < 0 ) {
3333                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3334                         __FILE__,__LINE__, info->device_name);
3335                 return -ENOMEM;
3336         }
3337
3338         rx_reset_buffers( info );
3339
3340         return 0;
3341 }
3342
3343 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3344  */
3345 int alloc_buf_list(SLMP_INFO *info)
3346 {
3347         unsigned int i;
3348
3349         /* build list in adapter shared memory */
3350         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3351         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3352         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3353
3354         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3355
3356         /* Save virtual address pointers to the receive and */
3357         /* transmit buffer lists. (Receive 1st). These pointers will */
3358         /* be used by the processor to access the lists. */
3359         info->rx_buf_list = (SCADESC *)info->buffer_list;
3360
3361         info->tx_buf_list = (SCADESC *)info->buffer_list;
3362         info->tx_buf_list += info->rx_buf_count;
3363
3364         /* Build links for circular buffer entry lists (tx and rx)
3365          *
3366          * Note: links are physical addresses read by the SCA device
3367          * to determine the next buffer entry to use.
3368          */
3369
3370         for ( i = 0; i < info->rx_buf_count; i++ ) {
3371                 /* calculate and store physical address of this buffer entry */
3372                 info->rx_buf_list_ex[i].phys_entry =
3373                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3374
3375                 /* calculate and store physical address of */
3376                 /* next entry in cirular list of entries */
3377                 info->rx_buf_list[i].next = info->buffer_list_phys;
3378                 if ( i < info->rx_buf_count - 1 )
3379                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3380
3381                 info->rx_buf_list[i].length = SCABUFSIZE;
3382         }
3383
3384         for ( i = 0; i < info->tx_buf_count; i++ ) {
3385                 /* calculate and store physical address of this buffer entry */
3386                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3387                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3388
3389                 /* calculate and store physical address of */
3390                 /* next entry in cirular list of entries */
3391
3392                 info->tx_buf_list[i].next = info->buffer_list_phys +
3393                         info->rx_buf_count * sizeof(SCADESC);
3394
3395                 if ( i < info->tx_buf_count - 1 )
3396                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3397         }
3398
3399         return 0;
3400 }
3401
3402 /* Allocate the frame DMA buffers used by the specified buffer list.
3403  */
3404 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3405 {
3406         int i;
3407         unsigned long phys_addr;
3408
3409         for ( i = 0; i < count; i++ ) {
3410                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3411                 phys_addr = info->port_array[0]->last_mem_alloc;
3412                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3413
3414                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3415                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3416         }
3417
3418         return 0;
3419 }
3420
3421 void free_dma_bufs(SLMP_INFO *info)
3422 {
3423         info->buffer_list = NULL;
3424         info->rx_buf_list = NULL;
3425         info->tx_buf_list = NULL;
3426 }
3427
3428 /* allocate buffer large enough to hold max_frame_size.
3429  * This buffer is used to pass an assembled frame to the line discipline.
3430  */
3431 int alloc_tmp_rx_buf(SLMP_INFO *info)
3432 {
3433         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3434         if (info->tmp_rx_buf == NULL)
3435                 return -ENOMEM;
3436         return 0;
3437 }
3438
3439 void free_tmp_rx_buf(SLMP_INFO *info)
3440 {
3441         if (info->tmp_rx_buf)
3442                 kfree(info->tmp_rx_buf);
3443         info->tmp_rx_buf = NULL;
3444 }
3445
3446 int claim_resources(SLMP_INFO *info)
3447 {
3448         if (request_mem_region(info->phys_memory_base,0x40000,"synclinkmp") == NULL) {
3449                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3450                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3451                 goto errout;
3452         }
3453         else
3454                 info->shared_mem_requested = 1;
3455
3456         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3457                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3458                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3459                 goto errout;
3460         }
3461         else
3462                 info->lcr_mem_requested = 1;
3463
3464         if (request_mem_region(info->phys_sca_base + info->sca_offset,512,"synclinkmp") == NULL) {
3465                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3466                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3467                 goto errout;
3468         }
3469         else
3470                 info->sca_base_requested = 1;
3471
3472         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,16,"synclinkmp") == NULL) {
3473                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3474                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3475                 goto errout;
3476         }
3477         else
3478                 info->sca_statctrl_requested = 1;
3479
3480         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3481         if (!info->memory_base) {
3482                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3483                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3484                 goto errout;
3485         }
3486
3487         if ( !memory_test(info) ) {
3488                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3489                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3490                 goto errout;
3491         }
3492
3493         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
3494         if (!info->lcr_base) {
3495                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3496                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3497                 goto errout;
3498         }
3499
3500         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE) + info->sca_offset;
3501         if (!info->sca_base) {
3502                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3503                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3504                 goto errout;
3505         }
3506
3507         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE) + info->statctrl_offset;
3508         if (!info->statctrl_base) {
3509                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3510                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3511                 goto errout;
3512         }
3513
3514         return 0;
3515
3516 errout:
3517         release_resources( info );
3518         return -ENODEV;
3519 }
3520
3521 void release_resources(SLMP_INFO *info)
3522 {
3523         if ( debug_level >= DEBUG_LEVEL_INFO )
3524                 printk( "%s(%d):%s release_resources() entry\n",
3525                         __FILE__,__LINE__,info->device_name );
3526
3527         if ( info->irq_requested ) {
3528                 free_irq(info->irq_level, info);
3529                 info->irq_requested = 0;
3530         }
3531
3532         if ( info->shared_mem_requested ) {
3533                 release_mem_region(info->phys_memory_base,0x40000);
3534                 info->shared_mem_requested = 0;
3535         }
3536         if ( info->lcr_mem_requested ) {
3537                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3538                 info->lcr_mem_requested = 0;
3539         }
3540         if ( info->sca_base_requested ) {
3541                 release_mem_region(info->phys_sca_base + info->sca_offset,512);
3542                 info->sca_base_requested = 0;
3543         }
3544         if ( info->sca_statctrl_requested ) {
3545                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,16);
3546                 info->sca_statctrl_requested = 0;
3547         }
3548
3549         if (info->memory_base){
3550                 iounmap(info->memory_base);
3551                 info->memory_base = 0;
3552         }
3553
3554         if (info->sca_base) {
3555                 iounmap(info->sca_base - info->sca_offset);
3556                 info->sca_base=0;
3557         }
3558
3559         if (info->statctrl_base) {
3560                 iounmap(info->statctrl_base - info->statctrl_offset);
3561                 info->statctrl_base=0;
3562         }
3563
3564         if (info->lcr_base){
3565                 iounmap(info->lcr_base - info->lcr_offset);
3566                 info->lcr_base = 0;
3567         }
3568
3569         if ( debug_level >= DEBUG_LEVEL_INFO )
3570                 printk( "%s(%d):%s release_resources() exit\n",
3571                         __FILE__,__LINE__,info->device_name );
3572 }
3573
3574 /* Add the specified device instance data structure to the
3575  * global linked list of devices and increment the device count.
3576  */
3577 void add_device(SLMP_INFO *info)
3578 {
3579         info->next_device = NULL;
3580         info->line = synclinkmp_device_count;
3581         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3582
3583         if (info->line < MAX_DEVICES) {
3584                 if (maxframe[info->line])
3585                         info->max_frame_size = maxframe[info->line];
3586                 info->dosyncppp = dosyncppp[info->line];
3587         }
3588
3589         synclinkmp_device_count++;
3590
3591         if ( !synclinkmp_device_list )
3592                 synclinkmp_device_list = info;
3593         else {
3594                 SLMP_INFO *current_dev = synclinkmp_device_list;
3595                 while( current_dev->next_device )
3596                         current_dev = current_dev->next_device;
3597                 current_dev->next_device = info;
3598         }
3599
3600         if ( info->max_frame_size < 4096 )
3601                 info->max_frame_size = 4096;
3602         else if ( info->max_frame_size > 65535 )
3603                 info->max_frame_size = 65535;
3604
3605         printk( "SyncLink MultiPort %s: "
3606                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3607                 info->device_name,
3608                 info->phys_sca_base,
3609                 info->phys_memory_base,
3610                 info->phys_statctrl_base,
3611                 info->phys_lcr_base,
3612                 info->irq_level,
3613                 info->max_frame_size );
3614
3615 #ifdef CONFIG_SYNCLINK_SYNCPPP
3616         if (info->dosyncppp)
3617                 sppp_init(info);
3618 #endif
3619 }
3620
3621 /* Allocate and initialize a device instance structure
3622  *
3623  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3624  */
3625 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3626 {
3627         SLMP_INFO *info;
3628
3629         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3630                  GFP_KERNEL);
3631
3632         if (!info) {
3633                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3634                         __FILE__,__LINE__, adapter_num, port_num);
3635         } else {
3636                 memset(info, 0, sizeof(SLMP_INFO));
3637                 info->magic = MGSL_MAGIC;
3638                 INIT_WORK(&info->task, bh_handler, info);
3639                 info->max_frame_size = 4096;
3640                 info->close_delay = 5*HZ/10;
3641                 info->closing_wait = 30*HZ;
3642                 init_waitqueue_head(&info->open_wait);
3643                 init_waitqueue_head(&info->close_wait);
3644                 init_waitqueue_head(&info->status_event_wait_q);
3645                 init_waitqueue_head(&info->event_wait_q);
3646                 spin_lock_init(&info->netlock);
3647                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3648                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3649                 info->adapter_num = adapter_num;
3650                 info->port_num = port_num;
3651
3652                 /* Copy configuration info to device instance data */
3653                 info->irq_level = pdev->irq;
3654                 info->phys_lcr_base = pci_resource_start(pdev,0);
3655                 info->phys_sca_base = pci_resource_start(pdev,2);
3656                 info->phys_memory_base = pci_resource_start(pdev,3);
3657                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3658
3659                 /* Because veremap only works on page boundaries we must map
3660                  * a larger area than is actually implemented for the LCR
3661                  * memory range. We map a full page starting at the page boundary.
3662                  */
3663                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3664                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3665
3666                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3667                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3668
3669                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3670                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3671
3672                 info->bus_type = MGSL_BUS_TYPE_PCI;
3673                 info->irq_flags = SA_SHIRQ;
3674
3675                 init_timer(&info->tx_timer);
3676                 info->tx_timer.data = (unsigned long)info;
3677                 info->tx_timer.function = tx_timeout;
3678
3679                 init_timer(&info->status_timer);
3680                 info->status_timer.data = (unsigned long)info;
3681                 info->status_timer.function = status_timeout;
3682
3683                 /* Store the PCI9050 misc control register value because a flaw
3684                  * in the PCI9050 prevents LCR registers from being read if
3685                  * BIOS assigns an LCR base address with bit 7 set.
3686                  *
3687                  * Only the misc control register is accessed for which only
3688                  * write access is needed, so set an initial value and change
3689                  * bits to the device instance data as we write the value
3690                  * to the actual misc control register.
3691                  */
3692                 info->misc_ctrl_value = 0x087e4546;
3693
3694                 /* initial port state is unknown - if startup errors
3695                  * occur, init_error will be set to indicate the
3696                  * problem. Once the port is fully initialized,
3697                  * this value will be set to 0 to indicate the
3698                  * port is available.
3699                  */
3700                 info->init_error = -1;
3701         }
3702
3703         return info;
3704 }
3705
3706 void device_init(int adapter_num, struct pci_dev *pdev)
3707 {
3708         SLMP_INFO *port_array[SCA_MAX_PORTS];
3709         int port;
3710
3711         /* allocate device instances for up to SCA_MAX_PORTS devices */
3712         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3713                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3714                 if( port_array[port] == NULL ) {
3715                         for ( --port; port >= 0; --port )
3716                                 kfree(port_array[port]);
3717                         return;
3718                 }
3719         }
3720
3721         /* give copy of port_array to all ports and add to device list  */
3722         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3723                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3724                 add_device( port_array[port] );
3725                 spin_lock_init(&port_array[port]->lock);
3726         }
3727
3728         /* Allocate and claim adapter resources */
3729         if ( !claim_resources(port_array[0]) ) {
3730
3731                 alloc_dma_bufs(port_array[0]);
3732
3733                 /* copy resource information from first port to others */
3734                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3735                         port_array[port]->lock  = port_array[0]->lock;
3736                         port_array[port]->irq_level     = port_array[0]->irq_level;
3737                         port_array[port]->memory_base   = port_array[0]->memory_base;
3738                         port_array[port]->sca_base      = port_array[0]->sca_base;
3739                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3740                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3741                         alloc_dma_bufs(port_array[port]);
3742                 }
3743
3744                 if ( request_irq(port_array[0]->irq_level,
3745                                         synclinkmp_interrupt,
3746                                         port_array[0]->irq_flags,
3747                                         port_array[0]->device_name,
3748                                         port_array[0]) < 0 ) {
3749                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3750                                 __FILE__,__LINE__,
3751                                 port_array[0]->device_name,
3752                                 port_array[0]->irq_level );
3753                 }
3754                 else {
3755                         port_array[0]->irq_requested = 1;
3756                         adapter_test(port_array[0]);
3757                 }
3758         }
3759 }
3760
3761 static struct tty_operations ops = {
3762         .open = open,
3763         .close = close,
3764         .write = write,
3765         .put_char = put_char,
3766         .flush_chars = flush_chars,
3767         .write_room = write_room,
3768         .chars_in_buffer = chars_in_buffer,
3769         .flush_buffer = flush_buffer,
3770         .ioctl = ioctl,
3771         .throttle = throttle,
3772         .unthrottle = unthrottle,
3773         .send_xchar = send_xchar,
3774         .break_ctl = set_break,
3775         .wait_until_sent = wait_until_sent,
3776         .read_proc = read_proc,
3777         .set_termios = set_termios,
3778         .stop = tx_hold,
3779         .start = tx_release,
3780         .hangup = hangup,
3781         .tiocmget = tiocmget,
3782         .tiocmset = tiocmset,
3783 };
3784
3785 static void synclinkmp_cleanup(void)
3786 {
3787         unsigned long flags;
3788         int rc;
3789         SLMP_INFO *info;
3790         SLMP_INFO *tmp;
3791
3792         printk("Unloading %s %s\n", driver_name, driver_version);
3793
3794         if (serial_driver) {
3795                 if ((rc = tty_unregister_driver(serial_driver)))
3796                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3797                                __FILE__,__LINE__,rc);
3798                 put_tty_driver(serial_driver);
3799         }
3800
3801         info = synclinkmp_device_list;
3802         while(info) {
3803 #ifdef CONFIG_SYNCLINK_SYNCPPP
3804                 if (info->dosyncppp)
3805                         sppp_delete(info);
3806 #endif
3807                 reset_port(info);
3808                 if ( info->port_num == 0 ) {
3809                         if ( info->irq_requested ) {
3810                                 free_irq(info->irq_level, info);
3811                                 info->irq_requested = 0;
3812                         }
3813                 }
3814                 info = info->next_device;
3815         }
3816
3817         /* port 0 of each adapter originally claimed
3818          * all resources, release those now
3819          */
3820         info = synclinkmp_device_list;
3821         while(info) {
3822                 free_dma_bufs(info);
3823                 free_tmp_rx_buf(info);
3824                 if ( info->port_num == 0 ) {
3825                         spin_lock_irqsave(&info->lock,flags);
3826                         reset_adapter(info);
3827                         write_reg(info, LPR, 1);                /* set low power mode */
3828                         spin_unlock_irqrestore(&info->lock,flags);
3829                         release_resources(info);
3830                 }
3831                 tmp = info;
3832                 info = info->next_device;
3833                 kfree(tmp);
3834         }
3835
3836         pci_unregister_driver(&synclinkmp_pci_driver);
3837 }
3838
3839 /* Driver initialization entry point.
3840  */
3841
3842 static int __init synclinkmp_init(void)
3843 {
3844         int rc;
3845
3846         if (break_on_load) {
3847                 synclinkmp_get_text_ptr();
3848                 BREAKPOINT();
3849         }
3850
3851         printk("%s %s\n", driver_name, driver_version);
3852
3853         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3854                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3855                 return rc;
3856         }
3857
3858         serial_driver = alloc_tty_driver(128);
3859         if (!serial_driver) {
3860                 rc = -ENOMEM;
3861                 goto error;
3862         }
3863
3864         /* Initialize the tty_driver structure */
3865
3866         serial_driver->owner = THIS_MODULE;
3867         serial_driver->driver_name = "synclinkmp";
3868         serial_driver->name = "ttySLM";
3869         serial_driver->major = ttymajor;
3870         serial_driver->minor_start = 64;
3871         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3872         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3873         serial_driver->init_termios = tty_std_termios;
3874         serial_driver->init_termios.c_cflag =
3875                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3876         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3877         tty_set_operations(serial_driver, &ops);
3878         if ((rc = tty_register_driver(serial_driver)) < 0) {
3879                 printk("%s(%d):Couldn't register serial driver\n",
3880                         __FILE__,__LINE__);
3881                 put_tty_driver(serial_driver);
3882                 serial_driver = NULL;
3883                 goto error;
3884         }
3885
3886         printk("%s %s, tty major#%d\n",
3887                 driver_name, driver_version,
3888                 serial_driver->major);
3889
3890         return 0;
3891
3892 error:
3893         synclinkmp_cleanup();
3894         return rc;
3895 }
3896
3897 static void __exit synclinkmp_exit(void)
3898 {
3899         synclinkmp_cleanup();
3900 }
3901
3902 module_init(synclinkmp_init);
3903 module_exit(synclinkmp_exit);
3904
3905 /* Set the port for internal loopback mode.
3906  * The TxCLK and RxCLK signals are generated from the BRG and
3907  * the TxD is looped back to the RxD internally.
3908  */
3909 void enable_loopback(SLMP_INFO *info, int enable)
3910 {
3911         if (enable) {
3912                 /* MD2 (Mode Register 2)
3913                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
3914                  */
3915                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
3916
3917                 /* degate external TxC clock source */
3918                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
3919                 write_control_reg(info);
3920
3921                 /* RXS/TXS (Rx/Tx clock source)
3922                  * 07      Reserved, must be 0
3923                  * 06..04  Clock Source, 100=BRG
3924                  * 03..00  Clock Divisor, 0000=1
3925                  */
3926                 write_reg(info, RXS, 0x40);
3927                 write_reg(info, TXS, 0x40);
3928
3929         } else {
3930                 /* MD2 (Mode Register 2)
3931                  * 01..00  CNCT<1..0> Channel connection, 0=normal
3932                  */
3933                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
3934
3935                 /* RXS/TXS (Rx/Tx clock source)
3936                  * 07      Reserved, must be 0
3937                  * 06..04  Clock Source, 000=RxC/TxC Pin
3938                  * 03..00  Clock Divisor, 0000=1
3939                  */
3940                 write_reg(info, RXS, 0x00);
3941                 write_reg(info, TXS, 0x00);
3942         }
3943
3944         /* set LinkSpeed if available, otherwise default to 2Mbps */
3945         if (info->params.clock_speed)
3946                 set_rate(info, info->params.clock_speed);
3947         else
3948                 set_rate(info, 3686400);
3949 }
3950
3951 /* Set the baud rate register to the desired speed
3952  *
3953  *      data_rate       data rate of clock in bits per second
3954  *                      A data rate of 0 disables the AUX clock.
3955  */
3956 void set_rate( SLMP_INFO *info, u32 data_rate )
3957 {
3958         u32 TMCValue;
3959         unsigned char BRValue;
3960         u32 Divisor=0;
3961
3962         /* fBRG = fCLK/(TMC * 2^BR)
3963          */
3964         if (data_rate != 0) {
3965                 Divisor = 14745600/data_rate;
3966                 if (!Divisor)
3967                         Divisor = 1;
3968
3969                 TMCValue = Divisor;
3970
3971                 BRValue = 0;
3972                 if (TMCValue != 1 && TMCValue != 2) {
3973                         /* BRValue of 0 provides 50/50 duty cycle *only* when
3974                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
3975                          * 50/50 duty cycle.
3976                          */
3977                         BRValue = 1;
3978                         TMCValue >>= 1;
3979                 }
3980
3981                 /* while TMCValue is too big for TMC register, divide
3982                  * by 2 and increment BR exponent.
3983                  */
3984                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
3985                         TMCValue >>= 1;
3986
3987                 write_reg(info, TXS,
3988                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
3989                 write_reg(info, RXS,
3990                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
3991                 write_reg(info, TMC, (unsigned char)TMCValue);
3992         }
3993         else {
3994                 write_reg(info, TXS,0);
3995                 write_reg(info, RXS,0);
3996                 write_reg(info, TMC, 0);
3997         }
3998 }
3999
4000 /* Disable receiver
4001  */
4002 void rx_stop(SLMP_INFO *info)
4003 {
4004         if (debug_level >= DEBUG_LEVEL_ISR)
4005                 printk("%s(%d):%s rx_stop()\n",
4006                          __FILE__,__LINE__, info->device_name );
4007
4008         write_reg(info, CMD, RXRESET);
4009
4010         info->ie0_value &= ~RXRDYE;
4011         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4012
4013         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4014         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4015         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4016
4017         info->rx_enabled = 0;
4018         info->rx_overflow = 0;
4019 }
4020
4021 /* enable the receiver
4022  */
4023 void rx_start(SLMP_INFO *info)
4024 {
4025         int i;
4026
4027         if (debug_level >= DEBUG_LEVEL_ISR)
4028                 printk("%s(%d):%s rx_start()\n",
4029                          __FILE__,__LINE__, info->device_name );
4030
4031         write_reg(info, CMD, RXRESET);
4032
4033         if ( info->params.mode == MGSL_MODE_HDLC ) {
4034                 /* HDLC, disabe IRQ on rxdata */
4035                 info->ie0_value &= ~RXRDYE;
4036                 write_reg(info, IE0, info->ie0_value);
4037
4038                 /* Reset all Rx DMA buffers and program rx dma */
4039                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4040                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4041
4042                 for (i = 0; i < info->rx_buf_count; i++) {
4043                         info->rx_buf_list[i].status = 0xff;
4044
4045                         // throttle to 4 shared memory writes at a time to prevent
4046                         // hogging local bus (keep latency time for DMA requests low).
4047                         if (!(i % 4))
4048                                 read_status_reg(info);
4049                 }
4050                 info->current_rx_buf = 0;
4051
4052                 /* set current/1st descriptor address */
4053                 write_reg16(info, RXDMA + CDA,
4054                         info->rx_buf_list_ex[0].phys_entry);
4055
4056                 /* set new last rx descriptor address */
4057                 write_reg16(info, RXDMA + EDA,
4058                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4059
4060                 /* set buffer length (shared by all rx dma data buffers) */
4061                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4062
4063                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4064                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4065         } else {
4066                 /* async, enable IRQ on rxdata */
4067                 info->ie0_value |= RXRDYE;
4068                 write_reg(info, IE0, info->ie0_value);
4069         }
4070
4071         write_reg(info, CMD, RXENABLE);
4072
4073         info->rx_overflow = FALSE;
4074         info->rx_enabled = 1;
4075 }
4076
4077 /* Enable the transmitter and send a transmit frame if
4078  * one is loaded in the DMA buffers.
4079  */
4080 void tx_start(SLMP_INFO *info)
4081 {
4082         if (debug_level >= DEBUG_LEVEL_ISR)
4083                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4084                          __FILE__,__LINE__, info->device_name,info->tx_count );
4085
4086         if (!info->tx_enabled ) {
4087                 write_reg(info, CMD, TXRESET);
4088                 write_reg(info, CMD, TXENABLE);
4089                 info->tx_enabled = TRUE;
4090         }
4091
4092         if ( info->tx_count ) {
4093
4094                 /* If auto RTS enabled and RTS is inactive, then assert */
4095                 /* RTS and set a flag indicating that the driver should */
4096                 /* negate RTS when the transmission completes. */
4097
4098                 info->drop_rts_on_tx_done = 0;
4099
4100                 if (info->params.mode != MGSL_MODE_ASYNC) {
4101
4102                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4103                                 get_signals( info );
4104                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4105                                         info->serial_signals |= SerialSignal_RTS;
4106                                         set_signals( info );
4107                                         info->drop_rts_on_tx_done = 1;
4108                                 }
4109                         }
4110
4111                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4112                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4113
4114                         /* set TX CDA (current descriptor address) */
4115                         write_reg16(info, TXDMA + CDA,
4116                                 info->tx_buf_list_ex[0].phys_entry);
4117
4118                         /* set TX EDA (last descriptor address) */
4119                         write_reg16(info, TXDMA + EDA,
4120                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4121
4122                         /* clear IDLE and UDRN status bit */
4123                         info->ie1_value &= ~(IDLE + UDRN);
4124                         if (info->params.mode != MGSL_MODE_ASYNC)
4125                                 info->ie1_value |= UDRN;                /* HDLC, IRQ on underrun */
4126                         write_reg(info, IE1, info->ie1_value);  /* enable MSCI interrupts */
4127                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4128
4129                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4130                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4131
4132                         info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
4133                         add_timer(&info->tx_timer);
4134                 }
4135                 else {
4136                         tx_load_fifo(info);
4137                         /* async, enable IRQ on txdata */
4138                         info->ie0_value |= TXRDYE;
4139                         write_reg(info, IE0, info->ie0_value);
4140                 }
4141
4142                 info->tx_active = 1;
4143         }
4144 }
4145
4146 /* stop the transmitter and DMA
4147  */
4148 void tx_stop( SLMP_INFO *info )
4149 {
4150         if (debug_level >= DEBUG_LEVEL_ISR)
4151                 printk("%s(%d):%s tx_stop()\n",
4152                          __FILE__,__LINE__, info->device_name );
4153
4154         del_timer(&info->tx_timer);
4155
4156         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4157         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4158
4159         write_reg(info, CMD, TXRESET);
4160
4161         info->ie1_value &= ~(UDRN + IDLE);
4162         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4163         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4164
4165         info->ie0_value &= ~TXRDYE;
4166         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4167
4168         info->tx_enabled = 0;
4169         info->tx_active  = 0;
4170 }
4171
4172 /* Fill the transmit FIFO until the FIFO is full or
4173  * there is no more data to load.
4174  */
4175 void tx_load_fifo(SLMP_INFO *info)
4176 {
4177         u8 TwoBytes[2];
4178
4179         /* do nothing is now tx data available and no XON/XOFF pending */
4180
4181         if ( !info->tx_count && !info->x_char )
4182                 return;
4183
4184         /* load the Transmit FIFO until FIFOs full or all data sent */
4185
4186         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4187
4188                 /* there is more space in the transmit FIFO and */
4189                 /* there is more data in transmit buffer */
4190
4191                 if ( (info->tx_count > 1) && !info->x_char ) {
4192                         /* write 16-bits */
4193                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4194                         if (info->tx_get >= info->max_frame_size)
4195                                 info->tx_get -= info->max_frame_size;
4196                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4197                         if (info->tx_get >= info->max_frame_size)
4198                                 info->tx_get -= info->max_frame_size;
4199
4200                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4201
4202                         info->tx_count -= 2;
4203                         info->icount.tx += 2;
4204                 } else {
4205                         /* only 1 byte left to transmit or 1 FIFO slot left */
4206
4207                         if (info->x_char) {
4208                                 /* transmit pending high priority char */
4209                                 write_reg(info, TRB, info->x_char);
4210                                 info->x_char = 0;
4211                         } else {
4212                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4213                                 if (info->tx_get >= info->max_frame_size)
4214                                         info->tx_get -= info->max_frame_size;
4215                                 info->tx_count--;
4216                         }
4217                         info->icount.tx++;
4218                 }
4219         }
4220 }
4221
4222 /* Reset a port to a known state
4223  */
4224 void reset_port(SLMP_INFO *info)
4225 {
4226         if (info->sca_base) {
4227
4228                 tx_stop(info);
4229                 rx_stop(info);
4230
4231                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4232                 set_signals(info);
4233
4234                 /* disable all port interrupts */
4235                 info->ie0_value = 0;
4236                 info->ie1_value = 0;
4237                 info->ie2_value = 0;
4238                 write_reg(info, IE0, info->ie0_value);
4239                 write_reg(info, IE1, info->ie1_value);
4240                 write_reg(info, IE2, info->ie2_value);
4241
4242                 write_reg(info, CMD, CHRESET);
4243         }
4244 }
4245
4246 /* Reset all the ports to a known state.
4247  */
4248 void reset_adapter(SLMP_INFO *info)
4249 {
4250         int i;
4251
4252         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4253                 if (info->port_array[i])
4254                         reset_port(info->port_array[i]);
4255         }
4256 }
4257
4258 /* Program port for asynchronous communications.
4259  */
4260 void async_mode(SLMP_INFO *info)
4261 {
4262
4263         unsigned char RegValue;
4264
4265         tx_stop(info);
4266         rx_stop(info);
4267
4268         /* MD0, Mode Register 0
4269          *
4270          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4271          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4272          * 03      Reserved, must be 0
4273          * 02      CRCCC, CRC Calculation, 0=disabled
4274          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4275          *
4276          * 0000 0000
4277          */
4278         RegValue = 0x00;
4279         if (info->params.stop_bits != 1)
4280                 RegValue |= BIT1;
4281         write_reg(info, MD0, RegValue);
4282
4283         /* MD1, Mode Register 1
4284          *
4285          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4286          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4287          * 03..02  RXCHR<1..0>, rx char size
4288          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4289          *
4290          * 0100 0000
4291          */
4292         RegValue = 0x40;
4293         switch (info->params.data_bits) {
4294         case 7: RegValue |= BIT4 + BIT2; break;
4295         case 6: RegValue |= BIT5 + BIT3; break;
4296         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4297         }
4298         if (info->params.parity != ASYNC_PARITY_NONE) {
4299                 RegValue |= BIT1;
4300                 if (info->params.parity == ASYNC_PARITY_ODD)
4301                         RegValue |= BIT0;
4302         }
4303         write_reg(info, MD1, RegValue);
4304
4305         /* MD2, Mode Register 2
4306          *
4307          * 07..02  Reserved, must be 0
4308          * 01..00  CNCT<1..0> Channel connection, 0=normal
4309          *
4310          * 0000 0000
4311          */
4312         RegValue = 0x00;
4313         write_reg(info, MD2, RegValue);
4314
4315         /* RXS, Receive clock source
4316          *
4317          * 07      Reserved, must be 0
4318          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4319          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4320          */
4321         RegValue=BIT6;
4322         write_reg(info, RXS, RegValue);
4323
4324         /* TXS, Transmit clock source
4325          *
4326          * 07      Reserved, must be 0
4327          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4328          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4329          */
4330         RegValue=BIT6;
4331         write_reg(info, TXS, RegValue);
4332
4333         /* Control Register
4334          *
4335          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4336          */
4337         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4338         write_control_reg(info);
4339
4340         tx_set_idle(info);
4341
4342         /* RRC Receive Ready Control 0
4343          *
4344          * 07..05  Reserved, must be 0
4345          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4346          */
4347         write_reg(info, TRC0, 0x00);
4348
4349         /* TRC0 Transmit Ready Control 0
4350          *
4351          * 07..05  Reserved, must be 0
4352          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4353          */
4354         write_reg(info, TRC0, 0x10);
4355
4356         /* TRC1 Transmit Ready Control 1
4357          *
4358          * 07..05  Reserved, must be 0
4359          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4360          */
4361         write_reg(info, TRC1, 0x1e);
4362
4363         /* CTL, MSCI control register
4364          *
4365          * 07..06  Reserved, set to 0
4366          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4367          * 04      IDLC, idle control, 0=mark 1=idle register
4368          * 03      BRK, break, 0=off 1 =on (async)
4369          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4370          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4371          * 00      RTS, RTS output control, 0=active 1=inactive
4372          *
4373          * 0001 0001
4374          */
4375         RegValue = 0x10;
4376         if (!(info->serial_signals & SerialSignal_RTS))
4377                 RegValue |= 0x01;
4378         write_reg(info, CTL, RegValue);
4379
4380         /* enable status interrupts */
4381         info->ie0_value |= TXINTE + RXINTE;
4382         write_reg(info, IE0, info->ie0_value);
4383
4384         /* enable break detect interrupt */
4385         info->ie1_value = BRKD;
4386         write_reg(info, IE1, info->ie1_value);
4387
4388         /* enable rx overrun interrupt */
4389         info->ie2_value = OVRN;
4390         write_reg(info, IE2, info->ie2_value);
4391
4392         set_rate( info, info->params.data_rate * 16 );
4393
4394         if (info->params.loopback)
4395                 enable_loopback(info,1);
4396 }
4397
4398 /* Program the SCA for HDLC communications.
4399  */
4400 void hdlc_mode(SLMP_INFO *info)
4401 {
4402         unsigned char RegValue;
4403         u32 DpllDivisor;
4404
4405         // Can't use DPLL because SCA outputs recovered clock on RxC when
4406         // DPLL mode selected. This causes output contention with RxC receiver.
4407         // Use of DPLL would require external hardware to disable RxC receiver
4408         // when DPLL mode selected.
4409         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4410
4411         /* disable DMA interrupts */
4412         write_reg(info, TXDMA + DIR, 0);
4413         write_reg(info, RXDMA + DIR, 0);
4414
4415         /* MD0, Mode Register 0
4416          *
4417          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4418          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4419          * 03      Reserved, must be 0
4420          * 02      CRCCC, CRC Calculation, 1=enabled
4421          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4422          * 00      CRC0, CRC initial value, 1 = all 1s
4423          *
4424          * 1000 0001
4425          */
4426         RegValue = 0x81;
4427         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4428                 RegValue |= BIT4;
4429         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4430                 RegValue |= BIT4;
4431         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4432                 RegValue |= BIT2 + BIT1;
4433         write_reg(info, MD0, RegValue);
4434
4435         /* MD1, Mode Register 1
4436          *
4437          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4438          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4439          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4440          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4441          *
4442          * 0000 0000
4443          */
4444         RegValue = 0x00;
4445         write_reg(info, MD1, RegValue);
4446
4447         /* MD2, Mode Register 2
4448          *
4449          * 07      NRZFM, 0=NRZ, 1=FM
4450          * 06..05  CODE<1..0> Encoding, 00=NRZ
4451          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4452          * 02      Reserved, must be 0
4453          * 01..00  CNCT<1..0> Channel connection, 0=normal
4454          *
4455          * 0000 0000
4456          */
4457         RegValue = 0x00;
4458         switch(info->params.encoding) {
4459         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4460         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4461         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4462         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4463 #if 0
4464         case HDLC_ENCODING_NRZB:                                        /* not supported */
4465         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4466         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4467 #endif
4468         }
4469         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4470                 DpllDivisor = 16;
4471                 RegValue |= BIT3;
4472         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4473                 DpllDivisor = 8;
4474         } else {
4475                 DpllDivisor = 32;
4476                 RegValue |= BIT4;
4477         }
4478         write_reg(info, MD2, RegValue);
4479
4480
4481         /* RXS, Receive clock source
4482          *
4483          * 07      Reserved, must be 0
4484          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4485          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4486          */
4487         RegValue=0;
4488         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4489                 RegValue |= BIT6;
4490         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4491                 RegValue |= BIT6 + BIT5;
4492         write_reg(info, RXS, RegValue);
4493
4494         /* TXS, Transmit clock source
4495          *
4496          * 07      Reserved, must be 0
4497          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4498          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4499          */
4500         RegValue=0;
4501         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4502                 RegValue |= BIT6;
4503         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4504                 RegValue |= BIT6 + BIT5;
4505         write_reg(info, TXS, RegValue);
4506
4507         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4508                 set_rate(info, info->params.clock_speed * DpllDivisor);
4509         else
4510                 set_rate(info, info->params.clock_speed);
4511
4512         /* GPDATA (General Purpose I/O Data Register)
4513          *
4514          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4515          */
4516         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4517                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4518         else
4519                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4520         write_control_reg(info);
4521
4522         /* RRC Receive Ready Control 0
4523          *
4524          * 07..05  Reserved, must be 0
4525          * 04..00  RRC<4..0> Rx FIFO trigger active
4526          */
4527         write_reg(info, RRC, rx_active_fifo_level);
4528
4529         /* TRC0 Transmit Ready Control 0
4530          *
4531          * 07..05  Reserved, must be 0
4532          * 04..00  TRC<4..0> Tx FIFO trigger active
4533          */
4534         write_reg(info, TRC0, tx_active_fifo_level);
4535
4536         /* TRC1 Transmit Ready Control 1
4537          *
4538          * 07..05  Reserved, must be 0
4539          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4540          */
4541         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4542
4543         /* DMR, DMA Mode Register
4544          *
4545          * 07..05  Reserved, must be 0
4546          * 04      TMOD, Transfer Mode: 1=chained-block
4547          * 03      Reserved, must be 0
4548          * 02      NF, Number of Frames: 1=multi-frame
4549          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4550          * 00      Reserved, must be 0
4551          *
4552          * 0001 0100
4553          */
4554         write_reg(info, TXDMA + DMR, 0x14);
4555         write_reg(info, RXDMA + DMR, 0x14);
4556
4557         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4558         write_reg(info, RXDMA + CPB,
4559                 (unsigned char)(info->buffer_list_phys >> 16));
4560
4561         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4562         write_reg(info, TXDMA + CPB,
4563                 (unsigned char)(info->buffer_list_phys >> 16));
4564
4565         /* enable status interrupts. other code enables/disables
4566          * the individual sources for these two interrupt classes.
4567          */
4568         info->ie0_value |= TXINTE + RXINTE;
4569         write_reg(info, IE0, info->ie0_value);
4570
4571         /* CTL, MSCI control register
4572          *
4573          * 07..06  Reserved, set to 0
4574          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4575          * 04      IDLC, idle control, 0=mark 1=idle register
4576          * 03      BRK, break, 0=off 1 =on (async)
4577          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4578          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4579          * 00      RTS, RTS output control, 0=active 1=inactive
4580          *
4581          * 0001 0001
4582          */
4583         RegValue = 0x10;
4584         if (!(info->serial_signals & SerialSignal_RTS))
4585                 RegValue |= 0x01;
4586         write_reg(info, CTL, RegValue);
4587
4588         /* preamble not supported ! */
4589
4590         tx_set_idle(info);
4591         tx_stop(info);
4592         rx_stop(info);
4593
4594         set_rate(info, info->params.clock_speed);
4595
4596         if (info->params.loopback)
4597                 enable_loopback(info,1);
4598 }
4599
4600 /* Set the transmit HDLC idle mode
4601  */
4602 void tx_set_idle(SLMP_INFO *info)
4603 {
4604         unsigned char RegValue = 0xff;
4605
4606         /* Map API idle mode to SCA register bits */
4607         switch(info->idle_mode) {
4608         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4609         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4610         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4611         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4612         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4613         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4614         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4615         }
4616
4617         write_reg(info, IDL, RegValue);
4618 }
4619
4620 /* Query the adapter for the state of the V24 status (input) signals.
4621  */
4622 void get_signals(SLMP_INFO *info)
4623 {
4624         u16 status = read_reg(info, SR3);
4625         u16 gpstatus = read_status_reg(info);
4626         u16 testbit;
4627
4628         /* clear all serial signals except DTR and RTS */
4629         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4630
4631         /* set serial signal bits to reflect MISR */
4632
4633         if (!(status & BIT3))
4634                 info->serial_signals |= SerialSignal_CTS;
4635
4636         if ( !(status & BIT2))
4637                 info->serial_signals |= SerialSignal_DCD;
4638
4639         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4640         if (!(gpstatus & testbit))
4641                 info->serial_signals |= SerialSignal_RI;
4642
4643         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4644         if (!(gpstatus & testbit))
4645                 info->serial_signals |= SerialSignal_DSR;
4646 }
4647
4648 /* Set the state of DTR and RTS based on contents of
4649  * serial_signals member of device context.
4650  */
4651 void set_signals(SLMP_INFO *info)
4652 {
4653         unsigned char RegValue;
4654         u16 EnableBit;
4655
4656         RegValue = read_reg(info, CTL);
4657         if (info->serial_signals & SerialSignal_RTS)
4658                 RegValue &= ~BIT0;
4659         else
4660                 RegValue |= BIT0;
4661         write_reg(info, CTL, RegValue);
4662
4663         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4664         EnableBit = BIT1 << (info->port_num*2);
4665         if (info->serial_signals & SerialSignal_DTR)
4666                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4667         else
4668                 info->port_array[0]->ctrlreg_value |= EnableBit;
4669         write_control_reg(info);
4670 }
4671
4672 /*******************/
4673 /* DMA Buffer Code */
4674 /*******************/
4675
4676 /* Set the count for all receive buffers to SCABUFSIZE
4677  * and set the current buffer to the first buffer. This effectively
4678  * makes all buffers free and discards any data in buffers.
4679  */
4680 void rx_reset_buffers(SLMP_INFO *info)
4681 {
4682         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4683 }
4684
4685 /* Free the buffers used by a received frame
4686  *
4687  * info   pointer to device instance data
4688  * first  index of 1st receive buffer of frame
4689  * last   index of last receive buffer of frame
4690  */
4691 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4692 {
4693         int done = 0;
4694
4695         while(!done) {
4696                 /* reset current buffer for reuse */
4697                 info->rx_buf_list[first].status = 0xff;
4698
4699                 if (first == last) {
4700                         done = 1;
4701                         /* set new last rx descriptor address */
4702                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4703                 }
4704
4705                 first++;
4706                 if (first == info->rx_buf_count)
4707                         first = 0;
4708         }
4709
4710         /* set current buffer to next buffer after last buffer of frame */
4711         info->current_rx_buf = first;
4712 }
4713
4714 /* Return a received frame from the receive DMA buffers.
4715  * Only frames received without errors are returned.
4716  *
4717  * Return Value:        1 if frame returned, otherwise 0
4718  */
4719 int rx_get_frame(SLMP_INFO *info)
4720 {
4721         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4722         unsigned short status;
4723         unsigned int framesize = 0;
4724         int ReturnCode = 0;
4725         unsigned long flags;
4726         struct tty_struct *tty = info->tty;
4727         unsigned char addr_field = 0xff;
4728         SCADESC *desc;
4729         SCADESC_EX *desc_ex;
4730
4731 CheckAgain:
4732         /* assume no frame returned, set zero length */
4733         framesize = 0;
4734         addr_field = 0xff;
4735
4736         /*
4737          * current_rx_buf points to the 1st buffer of the next available
4738          * receive frame. To find the last buffer of the frame look for
4739          * a non-zero status field in the buffer entries. (The status
4740          * field is set by the 16C32 after completing a receive frame.
4741          */
4742         StartIndex = EndIndex = info->current_rx_buf;
4743
4744         for ( ;; ) {
4745                 desc = &info->rx_buf_list[EndIndex];
4746                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4747
4748                 if (desc->status == 0xff)
4749                         goto Cleanup;   /* current desc still in use, no frames available */
4750
4751                 if (framesize == 0 && info->params.addr_filter != 0xff)
4752                         addr_field = desc_ex->virt_addr[0];
4753
4754                 framesize += desc->length;
4755
4756                 /* Status != 0 means last buffer of frame */
4757                 if (desc->status)
4758                         break;
4759
4760                 EndIndex++;
4761                 if (EndIndex == info->rx_buf_count)
4762                         EndIndex = 0;
4763
4764                 if (EndIndex == info->current_rx_buf) {
4765                         /* all buffers have been 'used' but none mark      */
4766                         /* the end of a frame. Reset buffers and receiver. */
4767                         if ( info->rx_enabled ){
4768                                 spin_lock_irqsave(&info->lock,flags);
4769                                 rx_start(info);
4770                                 spin_unlock_irqrestore(&info->lock,flags);
4771                         }
4772                         goto Cleanup;
4773                 }
4774
4775         }
4776
4777         /* check status of receive frame */
4778
4779         /* frame status is byte stored after frame data
4780          *
4781          * 7 EOM (end of msg), 1 = last buffer of frame
4782          * 6 Short Frame, 1 = short frame
4783          * 5 Abort, 1 = frame aborted
4784          * 4 Residue, 1 = last byte is partial
4785          * 3 Overrun, 1 = overrun occurred during frame reception
4786          * 2 CRC,     1 = CRC error detected
4787          *
4788          */
4789         status = desc->status;
4790
4791         /* ignore CRC bit if not using CRC (bit is undefined) */
4792         /* Note:CRC is not save to data buffer */
4793         if (info->params.crc_type == HDLC_CRC_NONE)
4794                 status &= ~BIT2;
4795
4796         if (framesize == 0 ||
4797                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4798                 /* discard 0 byte frames, this seems to occur sometime
4799                  * when remote is idling flags.
4800                  */
4801                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4802                 goto CheckAgain;
4803         }
4804
4805         if (framesize < 2)
4806                 status |= BIT6;
4807
4808         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4809                 /* received frame has errors,
4810                  * update counts and mark frame size as 0
4811                  */
4812                 if (status & BIT6)
4813                         info->icount.rxshort++;
4814                 else if (status & BIT5)
4815                         info->icount.rxabort++;
4816                 else if (status & BIT3)
4817                         info->icount.rxover++;
4818                 else
4819                         info->icount.rxcrc++;
4820
4821                 framesize = 0;
4822
4823 #ifdef CONFIG_SYNCLINK_SYNCPPP
4824                 info->netstats.rx_errors++;
4825                 info->netstats.rx_frame_errors++;
4826 #endif
4827         }
4828
4829         if ( debug_level >= DEBUG_LEVEL_BH )
4830                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4831                         __FILE__,__LINE__,info->device_name,status,framesize);
4832
4833         if ( debug_level >= DEBUG_LEVEL_DATA )
4834                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4835                         MIN(framesize,SCABUFSIZE),0);
4836
4837         if (framesize) {
4838                 if (framesize > info->max_frame_size)
4839                         info->icount.rxlong++;
4840                 else {
4841                         /* copy dma buffer(s) to contiguous intermediate buffer */
4842                         int copy_count = framesize;
4843                         int index = StartIndex;
4844                         unsigned char *ptmp = info->tmp_rx_buf;
4845                         info->tmp_rx_buf_count = framesize;
4846
4847                         info->icount.rxok++;
4848
4849                         while(copy_count) {
4850                                 int partial_count = MIN(copy_count,SCABUFSIZE);
4851                                 memcpy( ptmp,
4852                                         info->rx_buf_list_ex[index].virt_addr,
4853                                         partial_count );
4854                                 ptmp += partial_count;
4855                                 copy_count -= partial_count;
4856
4857                                 if ( ++index == info->rx_buf_count )
4858                                         index = 0;
4859                         }
4860
4861 #ifdef CONFIG_SYNCLINK_SYNCPPP
4862                         if (info->netcount) {
4863                                 /* pass frame to syncppp device */
4864                                 sppp_rx_done(info,info->tmp_rx_buf,framesize);
4865                         }
4866                         else
4867 #endif
4868                         {
4869                                 if ( tty && tty->ldisc.receive_buf ) {
4870                                         /* Call the line discipline receive callback directly. */
4871                                         tty->ldisc.receive_buf(tty,
4872                                                 info->tmp_rx_buf,
4873                                                 info->flag_buf,
4874                                                 framesize);
4875                                 }
4876                         }
4877                 }
4878         }
4879         /* Free the buffers used by this frame. */
4880         rx_free_frame_buffers( info, StartIndex, EndIndex );
4881
4882         ReturnCode = 1;
4883
4884 Cleanup:
4885         if ( info->rx_enabled && info->rx_overflow ) {
4886                 /* Receiver is enabled, but needs to restarted due to
4887                  * rx buffer overflow. If buffers are empty, restart receiver.
4888                  */
4889                 if (info->rx_buf_list[EndIndex].status == 0xff) {
4890                         spin_lock_irqsave(&info->lock,flags);
4891                         rx_start(info);
4892                         spin_unlock_irqrestore(&info->lock,flags);
4893                 }
4894         }
4895
4896         return ReturnCode;
4897 }
4898
4899 /* load the transmit DMA buffer with data
4900  */
4901 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4902 {
4903         unsigned short copy_count;
4904         unsigned int i = 0;
4905         SCADESC *desc;
4906         SCADESC_EX *desc_ex;
4907
4908         if ( debug_level >= DEBUG_LEVEL_DATA )
4909                 trace_block(info,buf, MIN(count,SCABUFSIZE), 1);
4910
4911         /* Copy source buffer to one or more DMA buffers, starting with
4912          * the first transmit dma buffer.
4913          */
4914         for(i=0;;)
4915         {
4916                 copy_count = MIN(count,SCABUFSIZE);
4917
4918                 desc = &info->tx_buf_list[i];
4919                 desc_ex = &info->tx_buf_list_ex[i];
4920
4921                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
4922
4923                 desc->length = copy_count;
4924                 desc->status = 0;
4925
4926                 buf += copy_count;
4927                 count -= copy_count;
4928
4929                 if (!count)
4930                         break;
4931
4932                 i++;
4933                 if (i >= info->tx_buf_count)
4934                         i = 0;
4935         }
4936
4937         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
4938         info->last_tx_buf = ++i;
4939 }
4940
4941 int register_test(SLMP_INFO *info)
4942 {
4943         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
4944         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
4945         unsigned int i;
4946         int rc = TRUE;
4947         unsigned long flags;
4948
4949         spin_lock_irqsave(&info->lock,flags);
4950         reset_port(info);
4951
4952         /* assume failure */
4953         info->init_error = DiagStatus_AddressFailure;
4954
4955         /* Write bit patterns to various registers but do it out of */
4956         /* sync, then read back and verify values. */
4957
4958         for (i = 0 ; i < count ; i++) {
4959                 write_reg(info, TMC, testval[i]);
4960                 write_reg(info, IDL, testval[(i+1)%count]);
4961                 write_reg(info, SA0, testval[(i+2)%count]);
4962                 write_reg(info, SA1, testval[(i+3)%count]);
4963
4964                 if ( (read_reg(info, TMC) != testval[i]) ||
4965                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
4966                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
4967                           (read_reg(info, SA1) != testval[(i+3)%count]) )
4968                 {
4969                         rc = FALSE;
4970                         break;
4971                 }
4972         }
4973
4974         reset_port(info);
4975         spin_unlock_irqrestore(&info->lock,flags);
4976
4977         return rc;
4978 }
4979
4980 int irq_test(SLMP_INFO *info)
4981 {
4982         unsigned long timeout;
4983         unsigned long flags;
4984
4985         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
4986
4987         spin_lock_irqsave(&info->lock,flags);
4988         reset_port(info);
4989
4990         /* assume failure */
4991         info->init_error = DiagStatus_IrqFailure;
4992         info->irq_occurred = FALSE;
4993
4994         /* setup timer0 on SCA0 to interrupt */
4995
4996         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
4997         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
4998
4999         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5000         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5001
5002
5003         /* TMCS, Timer Control/Status Register
5004          *
5005          * 07      CMF, Compare match flag (read only) 1=match
5006          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5007          * 05      Reserved, must be 0
5008          * 04      TME, Timer Enable
5009          * 03..00  Reserved, must be 0
5010          *
5011          * 0101 0000
5012          */
5013         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5014
5015         spin_unlock_irqrestore(&info->lock,flags);
5016
5017         timeout=100;
5018         while( timeout-- && !info->irq_occurred ) {
5019                 set_current_state(TASK_INTERRUPTIBLE);
5020                 schedule_timeout(jiffies_from_ms(10));
5021         }
5022
5023         spin_lock_irqsave(&info->lock,flags);
5024         reset_port(info);
5025         spin_unlock_irqrestore(&info->lock,flags);
5026
5027         return info->irq_occurred;
5028 }
5029
5030 /* initialize individual SCA device (2 ports)
5031  */
5032 int sca_init(SLMP_INFO *info)
5033 {
5034         /* set wait controller to single mem partition (low), no wait states */
5035         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5036         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5037         write_reg(info, WCRL, 0);       /* wait controller low range */
5038         write_reg(info, WCRM, 0);       /* wait controller mid range */
5039         write_reg(info, WCRH, 0);       /* wait controller high range */
5040
5041         /* DPCR, DMA Priority Control
5042          *
5043          * 07..05  Not used, must be 0
5044          * 04      BRC, bus release condition: 0=all transfers complete
5045          * 03      CCC, channel change condition: 0=every cycle
5046          * 02..00  PR<2..0>, priority 100=round robin
5047          *
5048          * 00000100 = 0x04
5049          */
5050         write_reg(info, DPCR, dma_priority);
5051
5052         /* DMA Master Enable, BIT7: 1=enable all channels */
5053         write_reg(info, DMER, 0x80);
5054
5055         /* enable all interrupt classes */
5056         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5057         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5058         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5059
5060         /* ITCR, interrupt control register
5061          * 07      IPC, interrupt priority, 0=MSCI->DMA
5062          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5063          * 04      VOS, Vector Output, 0=unmodified vector
5064          * 03..00  Reserved, must be 0
5065          */
5066         write_reg(info, ITCR, 0);
5067
5068         return TRUE;
5069 }
5070
5071 /* initialize adapter hardware
5072  */
5073 int init_adapter(SLMP_INFO *info)
5074 {
5075         int i;
5076
5077         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5078         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5079         u32 readval;
5080
5081         info->misc_ctrl_value |= BIT30;
5082         *MiscCtrl = info->misc_ctrl_value;
5083
5084         /*
5085          * Force at least 170ns delay before clearing
5086          * reset bit. Each read from LCR takes at least
5087          * 30ns so 10 times for 300ns to be safe.
5088          */
5089         for(i=0;i<10;i++)
5090                 readval = *MiscCtrl;
5091
5092         info->misc_ctrl_value &= ~BIT30;
5093         *MiscCtrl = info->misc_ctrl_value;
5094
5095         /* init control reg (all DTRs off, all clksel=input) */
5096         info->ctrlreg_value = 0xaa;
5097         write_control_reg(info);
5098
5099         {
5100                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5101                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5102
5103                 switch(read_ahead_count)
5104                 {
5105                 case 16:
5106                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5107                         break;
5108                 case 8:
5109                         lcr1_brdr_value |= BIT5 + BIT4;
5110                         break;
5111                 case 4:
5112                         lcr1_brdr_value |= BIT5 + BIT3;
5113                         break;
5114                 case 0:
5115                         lcr1_brdr_value |= BIT5;
5116                         break;
5117                 }
5118
5119                 *LCR1BRDR = lcr1_brdr_value;
5120                 *MiscCtrl = misc_ctrl_value;
5121         }
5122
5123         sca_init(info->port_array[0]);
5124         sca_init(info->port_array[2]);
5125
5126         return TRUE;
5127 }
5128
5129 /* Loopback an HDLC frame to test the hardware
5130  * interrupt and DMA functions.
5131  */
5132 int loopback_test(SLMP_INFO *info)
5133 {
5134 #define TESTFRAMESIZE 20
5135
5136         unsigned long timeout;
5137         u16 count = TESTFRAMESIZE;
5138         unsigned char buf[TESTFRAMESIZE];
5139         int rc = FALSE;
5140         unsigned long flags;
5141
5142         struct tty_struct *oldtty = info->tty;
5143         u32 speed = info->params.clock_speed;
5144
5145         info->params.clock_speed = 3686400;
5146         info->tty = 0;
5147
5148         /* assume failure */
5149         info->init_error = DiagStatus_DmaFailure;
5150
5151         /* build and send transmit frame */
5152         for (count = 0; count < TESTFRAMESIZE;++count)
5153                 buf[count] = (unsigned char)count;
5154
5155         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5156
5157         /* program hardware for HDLC and enabled receiver */
5158         spin_lock_irqsave(&info->lock,flags);
5159         hdlc_mode(info);
5160         enable_loopback(info,1);
5161         rx_start(info);
5162         info->tx_count = count;
5163         tx_load_dma_buffer(info,buf,count);
5164         tx_start(info);
5165         spin_unlock_irqrestore(&info->lock,flags);
5166
5167         /* wait for receive complete */
5168         /* Set a timeout for waiting for interrupt. */
5169         for ( timeout = 100; timeout; --timeout ) {
5170                 set_current_state(TASK_INTERRUPTIBLE);
5171                 schedule_timeout(jiffies_from_ms(10));
5172
5173                 if (rx_get_frame(info)) {
5174                         rc = TRUE;
5175                         break;
5176                 }
5177         }
5178
5179         /* verify received frame length and contents */
5180         if (rc == TRUE &&
5181                 ( info->tmp_rx_buf_count != count ||
5182                   memcmp(buf, info->tmp_rx_buf,count))) {
5183                 rc = FALSE;
5184         }
5185
5186         spin_lock_irqsave(&info->lock,flags);
5187         reset_adapter(info);
5188         spin_unlock_irqrestore(&info->lock,flags);
5189
5190         info->params.clock_speed = speed;
5191         info->tty = oldtty;
5192
5193         return rc;
5194 }
5195
5196 /* Perform diagnostics on hardware
5197  */
5198 int adapter_test( SLMP_INFO *info )
5199 {
5200         unsigned long flags;
5201         if ( debug_level >= DEBUG_LEVEL_INFO )
5202                 printk( "%s(%d):Testing device %s\n",
5203                         __FILE__,__LINE__,info->device_name );
5204
5205         spin_lock_irqsave(&info->lock,flags);
5206         init_adapter(info);
5207         spin_unlock_irqrestore(&info->lock,flags);
5208
5209         info->port_array[0]->port_count = 0;
5210
5211         if ( register_test(info->port_array[0]) &&
5212                 register_test(info->port_array[1])) {
5213
5214                 info->port_array[0]->port_count = 2;
5215
5216                 if ( register_test(info->port_array[2]) &&
5217                         register_test(info->port_array[3]) )
5218                         info->port_array[0]->port_count += 2;
5219         }
5220         else {
5221                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5222                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5223                 return -ENODEV;
5224         }
5225
5226         if ( !irq_test(info->port_array[0]) ||
5227                 !irq_test(info->port_array[1]) ||
5228                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5229                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5230                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5231                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5232                 return -ENODEV;
5233         }
5234
5235         if (!loopback_test(info->port_array[0]) ||
5236                 !loopback_test(info->port_array[1]) ||
5237                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5238                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5239                 printk( "%s(%d):DMA test failure for device %s\n",
5240                         __FILE__,__LINE__,info->device_name);
5241                 return -ENODEV;
5242         }
5243
5244         if ( debug_level >= DEBUG_LEVEL_INFO )
5245                 printk( "%s(%d):device %s passed diagnostics\n",
5246                         __FILE__,__LINE__,info->device_name );
5247
5248         info->port_array[0]->init_error = 0;
5249         info->port_array[1]->init_error = 0;
5250         if ( info->port_count > 2 ) {
5251                 info->port_array[2]->init_error = 0;
5252                 info->port_array[3]->init_error = 0;
5253         }
5254
5255         return 0;
5256 }
5257
5258 /* Test the shared memory on a PCI adapter.
5259  */
5260 int memory_test(SLMP_INFO *info)
5261 {
5262         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5263                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5264         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5265         unsigned long i;
5266         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5267         unsigned long * addr = (unsigned long *)info->memory_base;
5268
5269         /* Test data lines with test pattern at one location. */
5270
5271         for ( i = 0 ; i < count ; i++ ) {
5272                 *addr = testval[i];
5273                 if ( *addr != testval[i] )
5274                         return FALSE;
5275         }
5276
5277         /* Test address lines with incrementing pattern over */
5278         /* entire address range. */
5279
5280         for ( i = 0 ; i < limit ; i++ ) {
5281                 *addr = i * 4;
5282                 addr++;
5283         }
5284
5285         addr = (unsigned long *)info->memory_base;
5286
5287         for ( i = 0 ; i < limit ; i++ ) {
5288                 if ( *addr != i * 4 )
5289                         return FALSE;
5290                 addr++;
5291         }
5292
5293         memset( info->memory_base, 0, SCA_MEM_SIZE );
5294         return TRUE;
5295 }
5296
5297 /* Load data into PCI adapter shared memory.
5298  *
5299  * The PCI9050 releases control of the local bus
5300  * after completing the current read or write operation.
5301  *
5302  * While the PCI9050 write FIFO not empty, the
5303  * PCI9050 treats all of the writes as a single transaction
5304  * and does not release the bus. This causes DMA latency problems
5305  * at high speeds when copying large data blocks to the shared memory.
5306  *
5307  * This function breaks a write into multiple transations by
5308  * interleaving a read which flushes the write FIFO and 'completes'
5309  * the write transation. This allows any pending DMA request to gain control
5310  * of the local bus in a timely fasion.
5311  */
5312 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5313 {
5314         /* A load interval of 16 allows for 4 32-bit writes at */
5315         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5316
5317         unsigned short interval = count / sca_pci_load_interval;
5318         unsigned short i;
5319
5320         for ( i = 0 ; i < interval ; i++ )
5321         {
5322                 memcpy(dest, src, sca_pci_load_interval);
5323                 read_status_reg(info);
5324                 dest += sca_pci_load_interval;
5325                 src += sca_pci_load_interval;
5326         }
5327
5328         memcpy(dest, src, count % sca_pci_load_interval);
5329 }
5330
5331 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5332 {
5333         int i;
5334         int linecount;
5335         if (xmit)
5336                 printk("%s tx data:\n",info->device_name);
5337         else
5338                 printk("%s rx data:\n",info->device_name);
5339
5340         while(count) {
5341                 if (count > 16)
5342                         linecount = 16;
5343                 else
5344                         linecount = count;
5345
5346                 for(i=0;i<linecount;i++)
5347                         printk("%02X ",(unsigned char)data[i]);
5348                 for(;i<17;i++)
5349                         printk("   ");
5350                 for(i=0;i<linecount;i++) {
5351                         if (data[i]>=040 && data[i]<=0176)
5352                                 printk("%c",data[i]);
5353                         else
5354                                 printk(".");
5355                 }
5356                 printk("\n");
5357
5358                 data  += linecount;
5359                 count -= linecount;
5360         }
5361 }       /* end of trace_block() */
5362
5363 /* called when HDLC frame times out
5364  * update stats and do tx completion processing
5365  */
5366 void tx_timeout(unsigned long context)
5367 {
5368         SLMP_INFO *info = (SLMP_INFO*)context;
5369         unsigned long flags;
5370
5371         if ( debug_level >= DEBUG_LEVEL_INFO )
5372                 printk( "%s(%d):%s tx_timeout()\n",
5373                         __FILE__,__LINE__,info->device_name);
5374         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5375                 info->icount.txtimeout++;
5376         }
5377         spin_lock_irqsave(&info->lock,flags);
5378         info->tx_active = 0;
5379         info->tx_count = info->tx_put = info->tx_get = 0;
5380
5381         spin_unlock_irqrestore(&info->lock,flags);
5382
5383 #ifdef CONFIG_SYNCLINK_SYNCPPP
5384         if (info->netcount)
5385                 sppp_tx_done(info);
5386         else
5387 #endif
5388                 bh_transmit(info);
5389 }
5390
5391 /* called to periodically check the DSR/RI modem signal input status
5392  */
5393 void status_timeout(unsigned long context)
5394 {
5395         u16 status = 0;
5396         SLMP_INFO *info = (SLMP_INFO*)context;
5397         unsigned long flags;
5398         unsigned char delta;
5399
5400
5401         spin_lock_irqsave(&info->lock,flags);
5402         get_signals(info);
5403         spin_unlock_irqrestore(&info->lock,flags);
5404
5405         /* check for DSR/RI state change */
5406
5407         delta = info->old_signals ^ info->serial_signals;
5408         info->old_signals = info->serial_signals;
5409
5410         if (delta & SerialSignal_DSR)
5411                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5412
5413         if (delta & SerialSignal_RI)
5414                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5415
5416         if (delta & SerialSignal_DCD)
5417                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5418
5419         if (delta & SerialSignal_CTS)
5420                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5421
5422         if (status)
5423                 isr_io_pin(info,status);
5424
5425         info->status_timer.data = (unsigned long)info;
5426         info->status_timer.function = status_timeout;
5427         info->status_timer.expires = jiffies + jiffies_from_ms(10);
5428         add_timer(&info->status_timer);
5429 }
5430
5431
5432 /* Register Access Routines -
5433  * All registers are memory mapped
5434  */
5435 #define CALC_REGADDR() \
5436         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5437         if (info->port_num > 1) \
5438                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5439         if ( info->port_num & 1) { \
5440                 if (Addr > 0x7f) \
5441                         RegAddr += 0x40;        /* DMA access */ \
5442                 else if (Addr > 0x1f && Addr < 0x60) \
5443                         RegAddr += 0x20;        /* MSCI access */ \
5444         }
5445
5446
5447 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5448 {
5449         CALC_REGADDR();
5450         return *RegAddr;
5451 }
5452 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5453 {
5454         CALC_REGADDR();
5455         *RegAddr = Value;
5456 }
5457
5458 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5459 {
5460         CALC_REGADDR();
5461         return *((u16 *)RegAddr);
5462 }
5463
5464 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5465 {
5466         CALC_REGADDR();
5467         *((u16 *)RegAddr) = Value;
5468 }
5469
5470 unsigned char read_status_reg(SLMP_INFO * info)
5471 {
5472         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5473         return *RegAddr;
5474 }
5475
5476 void write_control_reg(SLMP_INFO * info)
5477 {
5478         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5479         *RegAddr = info->port_array[0]->ctrlreg_value;
5480 }
5481
5482
5483 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5484                                           const struct pci_device_id *ent)
5485 {
5486         if (pci_enable_device(dev)) {
5487                 printk("error enabling pci device %p\n", dev);
5488                 return -EIO;
5489         }
5490         device_init( ++synclinkmp_adapter_count, dev );
5491         return 0;
5492 }
5493
5494 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5495 {
5496 }