2 * AMD K8 class Memory Controller kernel module
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh Linux Networx (http://lnxi.com)
9 * Changes by Douglas "norsk" Thompson <norsk5@xmission.com>:
10 * - K8 CPU Revision D and greater support
12 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
13 * - Module largely rewritten, with new (and hopefully correct)
14 * code for dealing with node and chip select interleaving, various
15 * code cleanup, and bug fixes
16 * - Added support for memory hoisting using DRAM hole address
19 * This module is based on the following document (available from
20 * http://www.amd.com/):
22 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
24 * AMD publication #: 26094
27 * Unless otherwise stated, section numbers mentioned in the comments below
28 * refer to this document.
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/slab.h>
36 #include <asm/mmzone.h>
39 #define k8_printk(level, fmt, arg...) \
40 edac_printk(level, "k8", fmt, ##arg)
42 #define k8_mc_printk(mci, level, fmt, arg...) \
43 edac_mc_chipset_printk(mci, level, "k8", fmt, ##arg)
45 /* Throughout the comments in this code, the terms SysAddr, DramAddr, and
46 * InputAddr are used. These terms come directly from the k8 documentation
47 * (AMD publication #26094). They are defined as follows:
50 * This is a physical address generated by a CPU core or a device
51 * doing DMA. If generated by a CPU core, a SysAddr is the result of
52 * a virtual to physical address translation by the CPU core's address
53 * translation mechanism (MMU).
56 * A DramAddr is derived from a SysAddr by subtracting an offset that
57 * depends on which node the SysAddr maps to and whether the SysAddr
58 * is within a range affected by memory hoisting. The DRAM Base
59 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * determine which node a SysAddr maps to.
62 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
63 * is within the range of addresses specified by this register, then
64 * a value x from the DHAR is subtracted from the SysAddr to produce a
65 * DramAddr. Here, x represents the base address for the node that
66 * the SysAddr maps to plus an offset due to memory hoisting. See
67 * section 3.4.8 and the comments in get_dram_hole_info() and
68 * sys_addr_to_dram_addr() below for more information.
70 * If the SysAddr is not affected by the DHAR then a value y is
71 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
72 * base address for the node that the SysAddr maps to. See section
73 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
77 * A DramAddr is translated to an InputAddr before being passed to the
78 * memory controller for the node that the DramAddr is associated
79 * with. The memory controller then maps the InputAddr to a csrow.
80 * If node interleaving is not in use, then the InputAddr has the same
81 * value as the DramAddr. Otherwise, the InputAddr is produced by
82 * discarding the bits used for node interleaving from the DramAddr.
83 * See section 3.4.4 for more information.
85 * The memory controller for a given node uses its DRAM CS Base and
86 * DRAM CS Mask registers to map an InputAddr to a csrow. See
87 * sections 3.5.4 and 3.5.5 for more information.
91 * Alter this version for the K8 module when modifications are made
93 #define EDAC_K8_VERSION " Ver: 2.0.2 " __DATE__
94 #define EDAC_MOD_STR "k8_edac"
96 #ifndef PCI_DEVICE_ID_AMD_OPT_0_HT
97 #define PCI_DEVICE_ID_AMD_OPT_0_HT 0x1100
98 #endif /* PCI_DEVICE_ID_AMD_OPT_0_HT */
100 #ifndef PCI_DEVICE_ID_AMD_OPT_1_ADDRMAP
101 #define PCI_DEVICE_ID_AMD_OPT_1_ADDRMAP 0x1101
102 #endif /* PCI_DEVICE_ID_AMD_OPT_1_ADDRMAP */
104 #ifndef PCI_DEVICE_ID_AMD_OPT_2_MEMCTL
105 #define PCI_DEVICE_ID_AMD_OPT_2_MEMCTL 0x1102
106 #endif /* PCI_DEVICE_ID_AMD_OPT_2_MEMCTL */
108 #ifndef PCI_DEVICE_ID_AMD_OPT_3_MISCCTL
109 #define PCI_DEVICE_ID_AMD_OPT_3_MISCCTL 0x1103
110 #endif /* PCI_DEVICE_ID_AMD_OPT_3_MISCCTL */
112 /* Extended Model from CPUID, for CPU Revision numbers */
113 #define OPTERON_CPU_LE_REV_C 0
114 #define OPTERON_CPU_REV_D 1
115 #define OPTERON_CPU_REV_E 2
116 /* Unknown Extended Model value */
117 #define OPTERON_CPU_REV_X 3
118 /* NPT processors have the following Extended Models */
119 #define OPTERON_CPU_REV_F 4
120 #define OPTERON_CPU_REV_FA 5
122 #define K8_NR_CSROWS 8
123 #define MAX_K8_NODES 8
125 /* K8 register addresses - device 0 function 1 - Address Map */
126 #define K8_DBR 0x40 /* DRAM Base Register (8 x 32b
127 * interlaced with K8_DLR)
129 * 31:16 DRAM Base addr 39:24
131 * 10:8 interleave enable
137 #define K8_DLR 0x44 /* DRAM Limit Register (8 x 32b
138 * interlaced with K8_DBR)
140 * 31:16 DRAM Limit addr 32:24
142 * 10:8 interleave select
144 * 2:0 destination node ID
147 #define K8_DHAR 0xf0 /* DRAM Hole Address Register
151 * 15:8 DramHoleOffset
156 /* K8 register addresses - device 0 function 2 - DRAM controller */
157 #define K8_DCSB 0x40 /* DRAM Chip-Select Base (8 x 32b)
159 * For Rev E and prior
160 * 31:21 Base addr high 35:25
162 * 15:9 Base addr low 19:13 (interlvd)
164 * 0 chip-select bank enable
166 * For Rev F (NPT) and later
168 * 28:19 Base address (36:27)
170 * 13:5 Base address (21:13)
176 #define K8_DCSB_CS_ENABLE 0x1
177 #define K8_DCSB_NPT_SPARE 0x2
178 #define K8_DCSB_NPT_TESTFAIL 0x4
180 /* REV E: selects bits 31-21 and 15-9 from DCSB
181 * and the shift amount to form address
183 #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
184 #define REV_E_DCS_SHIFT 4
185 #define REV_E_DCSM_SHIFT 0
186 #define REF_E_DCSM_COUNT 4
188 /* REV F: selects bits 28-19 and 13-5 from DCSB
189 * and the shift amount to form address
191 #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
192 #define REV_F_DCS_SHIFT 8
193 #define REV_F_DCSM_SHIFT 1
194 #define REF_F_DCSM_COUNT 8
196 #define K8_DCSM 0x60 /* DRAM Chip-Select Mask (8 x 32b)
199 * 29:21 addr mask high 33:25
201 * 15:9 addr mask low 19:13
205 /* REV E: selects bits 29-21 and 15-9 from DCSM */
206 #define REV_E_DCSM_MASK_BITS 0x3FE0FE00
207 /* represents unused bits [24-20] and [12-0] */
208 #define REV_E_DCS_NOTUSED_BITS 0x1f01fff
210 /* REV F: selects bits 28-19 and 13-5 from DCSM */
211 #define REV_F_DCSM_MASK_BITS 0x1FF83FC0
212 /* represents unused bits [26-22] and [12-0] */
213 #define REV_F_DCS_NOTUSED_BITS 0x03c1fff
215 #define K8_DBAM 0x80 /* DRAM Base Addr Mapping (32b) */
217 #define K8_DCL 0x90 /* DRAM configuration low reg (32b)
219 * Rev E and earlier CPUS:
222 * 27:25 Bypass Max: 000b=respect
223 * 24 Dissable receivers - no sockets
228 * 16 128/64 bit (dual/single chan)
229 * 15:14 R/W Queue bypass count
231 * 12 exit self refresh
232 * 11 mem clear status
237 * 3 dis DQS hysteresis
239 * 1 DRAM drive strength
240 * 0 Digital Locked Loop disable
242 * Rev F and later CPUs:
261 /* K8 register addresses - device 0 function 3 - Misc Control */
262 #define K8_NBCTL 0x40 /* MCA NB Control (32b)
268 #define K8_NBCFG 0x44 /* MCA NB Config (32b)
270 * 23 Chip-kill x4 ECC enable
274 #define K8_NBCFG_CHIPKILL 23
275 #define K8_NBCFG_ECC_ENABLE 22
277 #define K8_NBSL 0x48 /* MCA NB Status Low (32b)
279 * 31:24 Syndrome 15:8 chip-kill x4
281 * 19:16 Extended err code
285 #define K8_NBSH 0x4C /* MCA NB Status High (32b)
291 * 27 Misc err reg valid
293 * 25 proc context corrupt
299 * 8 err found by scrubber
301 * 6:4 Hyper-transport link number
307 #define K8_NBSH_VALID_BIT BIT(31)
309 #define K8_NBEAL 0x50 /* MCA NB err addr low (32b)
311 * 31:3 Err addr low 31:3
315 #define K8_NBEAH 0x54 /* MCA NB err addr high (32b)
318 * 7:0 Err addr high 39:32
321 #define K8_NBCAP 0xE8 /* MCA NB capabilities (32b)
327 #define K8_NBCAP_CHIPKILL 4
328 #define K8_NBCAP_SECDED 3
333 * K8_MSR_MCxCTL (64b)
334 * (0x400,404,408,40C,410)
335 * 63 Enable reporting source 63
339 * 2 Enable error source 2
340 * 1 Enable error source 1
341 * 0 Enable error source 0
345 * K8_MSR_MCxSTAT (64b)
346 * (0x401,405,409,40D,411)
350 * 60 Enabled error condition
351 * 59 Misc register valid (not used)
352 * 58 Err addr register valid
353 * 57 Processor context corrupt
354 * 56:32 Other information
355 * 31:16 Model specific error code
360 * K8_MSR_MCxADDR (64b)
361 * (0x402,406,40A,40E,412)
367 * K8_MSR_MCxMISC (64b)
368 * (0x403,407,40B,40F,413)
369 * Unused on Athlon64 and K8
372 #define K8_MSR_MCGCTL 0x017b /* Machine Chk Global report ctl (64b)
378 * 1 Instruction Cache
382 #define K8_MSR_MC4CTL 0x0410 /* North Bridge Check report ctl (64b) */
383 #define K8_MSR_MC4STAT 0x0411 /* North Bridge status (64b) */
384 #define K8_MSR_MC4ADDR 0x0412 /* North Bridge Address (64b) */
386 static inline int MCI_TO_NODE_ID(struct pci_dev *pdev)
388 return PCI_SLOT(pdev->devfn) - 0x18;
391 /* Ugly hack that allows module to compile when built as part of a 32-bit
392 * kernel. Just in case anyone wants to run a 32-bit kernel on their Opteron.
398 /* Each entry holds the CPU revision of all CPU cores for the given node. */
399 static int k8_node_revision_table[MAXNODE] = { 0 };
401 static inline int node_rev(int node_id)
403 return k8_node_revision_table[node_id];
406 static void store_node_revision(void *param)
408 int node_id, revision;
410 /* Multiple CPU cores on the same node will all write their revision
411 * number to the same array entry. This is ok. For a given node, all
412 * CPU cores are on the same piece of silicon and share the same
415 node_id = (cpuid_ebx(1) >> 24) & 0x07;
416 revision = (cpuid_eax(1) >> 16) & 0x0f;
417 k8_node_revision_table[node_id] = revision;
420 /* Initialize k8_node_revision_table. */
421 static void build_node_revision_table(void)
423 static int initialized = 0;
428 on_each_cpu(store_node_revision, NULL, 1, 1);
437 struct pci_dev *addr_map;
438 struct pci_dev *misc_ctl;
440 int node_id; /* ID of this node */
443 /* The values of these registers will remain constant so we might as
444 * well cache them here.
447 u32 dbr[MAX_K8_NODES];
448 u32 dlr[MAX_K8_NODES];
451 u32 dcsb[K8_NR_CSROWS];
452 u32 dcsm[K8_NR_CSROWS];
454 /* The following 3 fields are set at run time, after Revision has
455 * been determine, since the dcsb and dcsm registers vary
458 u32 dcsb_mask; /* DCSB mask bits */
459 u32 dcsm_mask; /* DCSM mask bits */
460 u32 num_dcsm; /* Number of DCSM registers */
461 u32 dcs_mask_notused; /* DCSM notused mask bits */
462 u32 dcs_shift; /* DCSB and DCSM shift value */
464 /* On Rev E there are 8 DCSM registers,
465 * On Rev F there are 4 DCSM registers.
466 * This field is set as a 0 (Rev E) or 1 (Rev F) to indicate
467 * number of bits to shift the index for DCSM array look ups
475 struct k8_error_info_regs {
482 struct k8_error_info {
483 struct k8_error_info_regs error_info;
484 int race_condition_detected;
488 const char *ctl_name;
493 static const struct k8_dev_info k8_devs[] = {
495 .ctl_name = "Athlon64/Opteron",
496 .addr_map = PCI_DEVICE_ID_AMD_OPT_1_ADDRMAP,
497 .misc_ctl = PCI_DEVICE_ID_AMD_OPT_3_MISCCTL},
500 static struct pci_dev * pci_get_related_function(unsigned int vendor,
501 unsigned int device, struct pci_dev *related)
507 while ((dev = pci_get_device(vendor, device, dev)) != NULL) {
508 if ((dev->bus->number == related->bus->number) &&
509 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
516 /* FIXME - stolen from msr.c - the calls in msr.c could be exported */
524 static void smp_wrmsr(void *cmd_block)
526 struct msr_command *cmd = cmd_block;
527 wrmsr(cmd->reg, cmd->data[0], cmd->data[1]);
530 static void smp_rdmsr(void *cmd_block)
532 struct msr_command *cmd = cmd_block;
533 rdmsr(cmd->reg, cmd->data[0], cmd->data[1]);
536 static void do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx)
538 struct msr_command cmd;
540 cmd.cpu = raw_smp_processor_id();
544 on_each_cpu(smp_wrmsr, &cmd, 1, 1);
547 static void do_rdmsr(int cpu, u32 reg, u32 *eax, u32 *edx)
549 struct msr_command cmd;
551 cmd.cpu = raw_smp_processor_id();
553 on_each_cpu(smp_rdmsr, &cmd, 1, 1);
559 * FIXME - This is a large chunk of memory to suck up just to decode the
560 * syndrome. It would be nice to discover a pattern in the syndromes that
561 * could be used to quickly identify the channel. The big problems with
562 * this table is memory usage, lookup speed (could sort and binary search),
563 * correctness (there could be a transcription error). A zero in any nibble
564 * for a syndrom is always channel 0, but that only decodes some of the
565 * syndromes. Can anyone find any other patterns?
567 * The comment in the left column is the nibble that is in error. The least
568 * significant nibble of the syndrome is the mask for the bits that are
569 * in error (need to be toggled) for the particular nibble.
571 #define SYNDROME_TABLE_SIZE 270
572 static const unsigned long syndromes_chan0[SYNDROME_TABLE_SIZE] = {
573 /*0 */ 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57,
574 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df,
575 /*1 */ 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7,
576 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f,
577 /*2 */ 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
578 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
579 /*3 */ 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057,
580 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df,
581 /*4 */ 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097,
582 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f,
583 /*5 */ 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857,
584 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf,
585 /*6 */ 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467,
586 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f,
587 /*7 */ 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27,
588 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff,
589 /*8 */ 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177,
590 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f,
591 /*9 */ 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07,
592 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f,
593 /*a */ 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07,
594 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f,
595 /*b */ 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7,
596 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f,
597 /*c */ 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87,
598 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f,
599 /*d */ 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067,
600 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f,
601 /*e */ 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77,
602 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f,
603 /*f */ 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77,
604 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x9562, 0xa6ee, 0xb72f,
606 /*20 */ 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807,
607 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f,
608 /*21 */ 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07,
609 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f
612 static const unsigned long syndromes_chan1[SYNDROME_TABLE_SIZE] = {
613 /*10 */ 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187,
614 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f,
615 /*11 */ 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627,
616 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff,
617 /*12 */ 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97,
618 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f,
619 /*13 */ 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97,
620 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f,
621 /*14 */ 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987,
622 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f,
623 /*15 */ 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677,
624 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f,
625 /*16 */ 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387,
626 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f,
627 /*17 */ 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17,
628 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf,
629 /*18 */ 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7,
630 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f,
631 /*19 */ 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397,
632 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f,
633 /*1a */ 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617,
634 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf,
635 /*1b */ 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527,
636 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff,
637 /*1c */ 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7,
638 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef,
639 /*1d */ 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7,
640 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def,
641 /*1e */ 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67,
642 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f,
643 /*1f */ 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377,
644 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f,
646 /*22 */ 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97,
647 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f,
648 /*23 */ 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757,
649 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df
652 static int chan_from_chipkill_syndrome(unsigned long syndrome)
656 debugf0("%s()\n", __func__);
658 for (i = 0; i < SYNDROME_TABLE_SIZE; i++) {
659 if (syndromes_chan0[i] == syndrome)
661 if (syndromes_chan1[i] == syndrome)
665 debugf0("%s(): syndrome(%lx) not found\n", __func__, syndrome);
669 static const char *tt_msgs[] = { /* transaction type */
676 static const char *ll_msgs[] = { /* cache level */
683 static const char *memtt_msgs[] = {
702 static const char *pp_msgs[] = { /* participating processor */
704 "local node response",
705 "local node observed",
709 static const char *to_msgs[] = {
714 static const char *ii_msgs[] = { /* memory or i/o */
721 static const char *ext_msgs[] = { /* extended error */
730 "ECC chipkill x4 error",
740 static const char *htlink_msgs[] = {
752 * The DCSB and DCSM registers differ between Rev E and Rev F CPUs
753 * The following several functions intialize and extract information
754 * from this registers
758 * set_dcsb_dcsm_rev_specific(pvt)
760 * NOTE: CPU Revision Dependent code
762 * Set the DCSB and DCSM mask values depending on the
763 * CPU revision value.
764 * Also set the shift factor for the DCSB and DCSM values
766 * member dcs_mask_notused, REV E:
768 * To find the max InputAddr for the csrow, start with the base
769 * address and set all bits that are "don't care" bits in the test at
770 * the start of section 3.5.4 (p. 84).
772 * The "don't care" bits are all set bits in the mask and
773 * all bits in the gaps between bit ranges [35-25] and [19-13].
774 * The value REV_E_DCS_NOTUSED_BITS represents bits [24-20] and [12-0],
775 * which are all bits in the above-mentioned gaps.
777 * member dcs_mask_notused, REV F:
779 * To find the max InputAddr for the csrow, start with the base
780 * address and set all bits that are "don't care" bits in the test at
781 * the start of NPT section 4.5.4 (p. 87).
783 * The "don't care" bits are all set bits in the mask and
784 * all bits in the gaps between bit ranges [36-27] and [21-13].
785 * The value REV_F_DCS_NOTUSED_BITS represents bits [26-22] and [12-0],
786 * which are all bits in the above-mentioned gaps.
788 static void set_dcsb_dcsm_rev_specific(struct k8_pvt *pvt)
790 if ( pvt->ext_model >= OPTERON_CPU_REV_F) {
791 pvt->dcsb_mask = REV_F_DCSB_BASE_BITS;
792 pvt->dcsm_mask = REV_F_DCSM_MASK_BITS;
793 pvt->dcs_mask_notused = REV_F_DCS_NOTUSED_BITS;
794 pvt->dcs_shift = REV_F_DCS_SHIFT;
795 pvt->dcsm_shift_bit = REV_F_DCSM_SHIFT;
796 pvt->num_dcsm = REF_F_DCSM_COUNT;
798 pvt->dcsb_mask = REV_E_DCSB_BASE_BITS;
799 pvt->dcsm_mask = REV_E_DCSM_MASK_BITS;
800 pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS;
801 pvt->dcs_shift = REV_E_DCS_SHIFT;
802 pvt->dcsm_shift_bit = REV_E_DCSM_SHIFT;
803 pvt->num_dcsm = REF_E_DCSM_COUNT;
810 * getter function to return the 'base' address the i'th CS entry.
812 static u32 get_dcsb(struct k8_pvt *pvt, int csrow)
814 /* 0xffe0fe00 selects bits 31-21 and 15-9 of a DRAM CS Base Address
815 * Register (section 3.5.4). Shifting the bits left 4 puts them in
816 * their proper bit positions of 35-25 and 19-13.
818 return pvt->dcsb[csrow];
824 * getter function to return the 'mask' address the i'th CS entry.
825 * This getter function is needed because there different number
826 * of DCSM registers on Rev E and prior vs Rev F and later
828 static u32 get_dcsm(struct k8_pvt *pvt, int csrow)
830 return pvt->dcsm[csrow >> pvt->dcsm_shift_bit];
837 * Extract the DRAM CS base address from selected csrow register
839 static u64 base_from_dcsb(struct k8_pvt *pvt, int csrow)
841 return ((u64)(get_dcsb(pvt, csrow) & pvt->dcsb_mask)) <<
845 static u64 mask_from_dcsm(struct k8_pvt *pvt, int csrow)
847 u64 dcsm_bits, other_bits;
849 /* Extract bits bits 29-21 and 15-9 from DCSM (section 3.5.5). */
850 dcsm_bits = get_dcsm(pvt, csrow) & pvt->dcsm_mask;
852 /* Set all bits except bits 33-25 and 19-13. */
853 other_bits = pvt->dcsm_mask;
854 other_bits = ~(other_bits << pvt->dcs_shift);
856 /* The extracted bits from DCSM belong in the spaces represented by
857 * the cleared bits in other_bits.
859 return (dcsm_bits << pvt->dcs_shift) | other_bits;
865 * Setup the DCSB and DCSM arrays from hardware
867 static void setup_dcsb_dcsm(struct k8_pvt *pvt, struct pci_dev *pdev)
871 /* Set the dcsb and dcsm mask bits and their shift value */
872 set_dcsb_dcsm_rev_specific(pvt);
874 /* Retrieve the DRAM CS Base Address Registers from hardware
876 for (i = 0; i < K8_NR_CSROWS; i++) {
877 pci_read_config_dword(pdev, K8_DCSB + (i * 4), &pvt->dcsb[i]);
878 debugf1(" dcsb[%d]: 0x%x\n", i, pvt->dcsb[i]);
881 /* The number of DCSMs differents at the Rev E/Rev F boundary
882 * so we retrieve the number of registers defined for this processor
884 for (i = 0; i < pvt->num_dcsm; i++) {
885 pci_read_config_dword(pdev, K8_DCSM + (i * 4), &pvt->dcsm[i]);
886 debugf1(" dcsm[%d]: 0x%x\n", i, pvt->dcsm[i]);
889 /* Debug dump only of DCSB and DCSM registers */
890 for (i = 0; i < K8_NR_CSROWS; i++) {
891 debugf1(" dcsb[%d]: 0x%8.8x dcsm[%d]: 0x%x\n",
893 i>> pvt->dcsm_shift_bit, get_dcsm(pvt,i));
897 /* In *base and *limit, pass back the full 40-bit base and limit physical
898 * addresses for the node given by node_id. This information is obtained from
899 * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
900 * base and limit addresses are of type SysAddr, as defined at the start of
901 * section 3.4.4 (p. 70). They are the lowest and highest physical addresses
902 * in the address range they represent.
904 static void get_base_and_limit(struct k8_pvt *pvt, int node_id,
905 u64 *base, u64 *limit)
907 *base = ((u64) (pvt->dbr[node_id] & 0xffff0000)) << 8;
909 /* Since the limit represents the highest address in the range, we
910 * must set its lowest 24 bits to 1.
912 *limit = (((u64) (pvt->dlr[node_id] & 0xffff0000)) << 8) | 0xffffff;
915 /* Return 1 if the SysAddr given by sys_addr matches the base/limit associated
918 static int base_limit_match(struct k8_pvt *pvt, u64 sys_addr, int node_id)
920 u64 base, limit, addr;
922 get_base_and_limit(pvt, node_id, &base, &limit);
924 /* The k8 treats this as a 40-bit value. However, bits 63-40 will be
925 * all ones if the most significant implemented address bit is 1.
926 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
927 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
928 * Application Programming.
930 addr = sys_addr & 0x000000ffffffffffull;
932 return (addr >= base) && (addr <= limit);
935 /* Attempt to map a SysAddr to a node. On success, return a pointer to the
936 * mem_ctl_info structure for the node that the SysAddr maps to. On failure,
939 static struct mem_ctl_info * find_mc_by_sys_addr(struct mem_ctl_info *mci,
946 /* Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
947 * 3.4.4.2) registers to map the SysAddr to a node ID.
952 /* The value of this field should be the same for all DRAM Base
953 * registers. Therefore we arbitrarily choose to read it from the
954 * register for node 0.
956 intlv_en = pvt->dbr[0] & (0x07 << 8);
958 if (intlv_en == 0) { /* node interleaving is disabled */
959 debugf2("%s(): node interleaving disabled\n", __func__);
960 for (node_id = 0; ; ) {
961 if (base_limit_match(pvt, sys_addr, node_id))
964 if (++node_id == MAX_K8_NODES) {
965 debugf2("%s(): sys_addr 0x%lx "
966 "does not match any node\n", __func__,
967 (unsigned long) sys_addr);
975 if (unlikely((intlv_en != (0x01 << 8)) &&
976 (intlv_en != (0x03 << 8)) &&
977 (intlv_en != (0x07 << 8)))) {
978 k8_printk(KERN_WARNING,
979 "%s(): junk value of 0x%x extracted from IntlvEn "
980 "field of DRAM Base Register for node 0: This "
981 "probably indicates a BIOS bug.\n", __func__,
986 /* If we get this far, node interleaving is enabled. */
987 debugf2("%s(): node interleaving enabled\n", __func__);
988 bits = (((u32) sys_addr) >> 12) & intlv_en;
990 for (node_id = 0; ; ) {
991 if ((pvt->dlr[node_id] & intlv_en) == bits)
992 break; /* intlv_sel field matches */
994 if (++node_id == MAX_K8_NODES) {
995 debugf2("%s(): sys_addr 0x%lx does not match any "
996 "node\n", __func__, (unsigned long) sys_addr);
1001 /* sanity test for sys_addr */
1002 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
1003 k8_printk(KERN_WARNING,
1004 "%s(): sys_addr 0x%lx falls outside base/limit "
1005 "address range for node %d with node interleaving "
1006 "enabled.\n", __func__, (unsigned long) sys_addr,
1012 debugf2("%s(): sys_addr 0x%lx matches node %d\n", __func__,
1013 (unsigned long) sys_addr, node_id);
1014 return edac_mc_find(node_id);
1017 /* Return the base value defined by the DRAM Base register for the node
1018 * represented by mci. This function returns the full 40-bit value despite
1019 * the fact that the register only stores bits 39-24 of the value. See
1022 static inline u64 get_dram_base(struct mem_ctl_info *mci)
1026 pvt = mci->pvt_info;
1027 return ((u64) (pvt->dbr[pvt->node_id] & 0xffff0000)) << 8;
1030 /* Obtain info from the DRAM Hole Address Register (section 3.4.8) for the
1031 * node represented by mci. Info is passed back in *hole_base, *hole_offset,
1032 * and *hole_size. Function returns 0 if info is valid or 1 if info is
1033 * invalid. Info may be invalid for either of the following reasons:
1035 * - The revision of the node is not E or greater. In this case, the DRAM
1036 * Hole Address Register does not exist.
1037 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
1038 * indicating that its contents are not valid.
1040 * The values passed back in *hole_base, *hole_offset, and *hole_size are
1041 * complete 32-bit values despite the fact that the bitfields in the DHAR
1042 * only represent bits 31-24 of the base and offset values.
1044 static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
1045 u64 *hole_offset, u64 *hole_size)
1050 pvt = mci->pvt_info;
1052 if (pvt->ext_model < OPTERON_CPU_REV_E) {
1053 debugf2("revision %d for node %d does not support DHAR\n",
1054 pvt->ext_model, pvt->node_id);
1058 if ((pvt->dhar & 0x01) == 0) {
1059 debugf2("DramHoleValid bit cleared in DHAR for node %d\n",
1061 return 1; /* DramHoleValid bit is cleared */
1064 /* +------------------+--------------------+--------------------+-----
1065 * | memory | DRAM hole | relocated |
1066 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
1068 * | | | [0x100000000, |
1069 * | | | (0x100000000+ |
1070 * | | | (0xffffffff-x))] |
1071 * +------------------+--------------------+--------------------+-----
1073 * Above is a diagram of physical memory showing the DRAM hole and the
1074 * relocated addresses from the DRAM hole. As shown, the DRAM hole
1075 * starts at address x (the base address) and extends through address
1076 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
1077 * addresses in the hole so that they start at 0x100000000.
1080 base = pvt->dhar & 0xff000000;
1082 *hole_offset = (pvt->dhar & 0x0000ff00) << 16;
1083 *hole_size = (0x1ull << 32) - base;
1084 debugf2("DHAR info for node %d: base 0x%lx offset 0x%lx size 0x%lx\n",
1085 pvt->node_id, (unsigned long) *hole_base,
1086 (unsigned long) *hole_offset, (unsigned long) *hole_size);
1090 /* Return the DramAddr that the SysAddr given by sys_addr maps to. It is
1091 * assumed that sys_addr maps to the node given by mci.
1093 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
1095 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
1097 /* The first part of section 3.4.4 (p. 70) shows how the DRAM Base
1098 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are
1099 * used to translate a SysAddr to a DramAddr. If the DRAM Hole
1100 * Address Register (DHAR) is enabled, then it is also involved in
1101 * translating a SysAddr to a DramAddr. Sections 3.4.8 and 3.5.8.2
1102 * describe the DHAR and how it is used for memory hoisting. These
1103 * parts of the documentation are unclear. I interpret them as
1106 * When node n receives a SysAddr, it processes the SysAddr as
1109 * 1. It extracts the DRAMBase and DRAMLimit values from the
1110 * DRAM Base and DRAM Limit registers for node n. If the
1111 * SysAddr is not within the range specified by the base
1112 * and limit values, then node n ignores the Sysaddr
1113 * (since it does not map to node n). Otherwise continue
1116 * 2. If the DramHoleValid bit of the DHAR for node n is
1117 * clear, the DHAR is disabled so skip to step 3 below.
1118 * Otherwise see if the SysAddr is within the range of
1119 * relocated addresses (starting at 0x100000000) from the
1120 * DRAM hole. If not, skip to step 3 below. Else get the
1121 * value of the DramHoleOffset field from the DHAR. To
1122 * obtain the DramAddr, subtract the offset defined by
1123 * this value from the SysAddr.
1125 * 3. Obtain the base address for node n from the DRAMBase
1126 * field of the DRAM Base register for node n. To obtain
1127 * the DramAddr, subtract the base address from the
1128 * SysAddr, as shown near the start of section 3.4.4
1132 dram_base = get_dram_base(mci);
1134 if (!get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size)) {
1135 if ((sys_addr >= (1ull << 32)) &&
1136 (sys_addr < ((1ull << 32) + hole_size))) {
1137 /* use DHAR to translate SysAddr to DramAddr */
1138 dram_addr = sys_addr - hole_offset;
1139 debugf2("using DHAR to translate SysAddr 0x%lx to "
1141 (unsigned long) sys_addr,
1142 (unsigned long) dram_addr);
1147 /* Translate the SysAddr to a DramAddr as shown near the start of
1148 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
1149 * only deals with 40-bit values. Therefore we discard bits 63-40 of
1150 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
1151 * discard are all 1s. Otherwise the bits we discard are all 0s. See
1152 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
1153 * Programmer's Manual Volume 1 Application Programming.
1155 dram_addr = (sys_addr & 0xffffffffffull) - dram_base;
1157 debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
1158 "DramAddr 0x%lx\n", (unsigned long) sys_addr,
1159 (unsigned long) dram_addr);
1163 /* Parameter intlv_en is the value of the IntlvEn field from a DRAM Base
1164 * register (section 3.4.4.1). Return the number of bits from a SysAddr that
1165 * are used for node interleaving.
1167 static int num_node_interleave_bits(unsigned intlv_en)
1169 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
1172 BUG_ON(intlv_en > 7);
1173 n = intlv_shift_table[intlv_en];
1174 debugf2("using %d bits for node interleave\n", n);
1178 /* Translate the DramAddr given by dram_addr to an InputAddr and return the
1181 static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
1187 pvt = mci->pvt_info;
1189 /* Near the start of section 3.4.4 (p. 70), the k8 documentation gives
1190 * instructions for translating a DramAddr to an InputAddr. Here we
1191 * are following these instructions.
1193 intlv_shift = num_node_interleave_bits((pvt->dbr[0] >> 8) & 0x07);
1194 input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) +
1195 (dram_addr & 0xfff);
1197 debugf2("DramAddr 0x%lx translates to InputAddr 0x%lx\n",
1198 (unsigned long) dram_addr, (unsigned long) input_addr);
1202 /* Translate the SysAddr represented by sys_addr to an InputAddr and return
1203 * the result. It is assumed that sys_addr maps to the node given by mci.
1205 static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
1209 input_addr = dram_addr_to_input_addr(
1210 mci, sys_addr_to_dram_addr(mci, sys_addr));
1211 debugf2("%s(): SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
1212 __func__, (unsigned long) sys_addr,
1213 (unsigned long) input_addr);
1217 /* input_addr is an InputAddr associated with the node given by mci. Return
1218 * the csrow that input_addr maps to, or -1 on failure (no csrow claims
1221 static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
1228 pvt = mci->pvt_info;
1230 /* Here we use the DRAM CS Base (section 3.5.4) and DRAM CS Mask
1231 * (section 3.5.5) registers. For each CS base/mask register pair,
1232 * test the condition shown near the start of section 3.5.4 (p. 84).
1235 for (i = 0; i < K8_NR_CSROWS; i++) {
1236 dcsb = pvt->dcsb[i];
1237 dcsm = pvt->dcsm[i];
1239 if ((dcsb & K8_DCSB_CS_ENABLE) == 0) {
1240 debugf2("input_addr_to_csrow: CSBE bit is cleared "
1241 "for csrow %d (node %d)\n", i,
1243 continue; /* CSBE bit is cleared */
1246 base = base_from_dcsb(pvt, i);
1247 mask = ~mask_from_dcsm(pvt, i);
1249 if ((input_addr & mask) == (base & mask)) {
1250 debugf2("InputAddr 0x%lx matches csrow %d "
1251 "(node %d)\n", (unsigned long) input_addr, i,
1253 return i; /* success: csrow i matches */
1257 debugf2("no matching csrow for InputAddr 0x%lx (node %d)\n",
1258 (unsigned long) input_addr, pvt->node_id);
1259 return -1; /* failed to find matching csrow */
1262 /* input_addr is an InputAddr associated with the node represented by mci.
1263 * Translate input_addr to a DramAddr and return the result.
1265 static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
1268 int node_id, intlv_shift;
1269 u64 bits, dram_addr;
1272 /* Near the start of section 3.4.4 (p. 70), the k8 documentation shows
1273 * how to translate a DramAddr to an InputAddr. Here we reverse this
1274 * procedure. When translating from a DramAddr to an InputAddr, the
1275 * bits used for node interleaving are discarded. Here we recover
1276 * these bits from the IntlvSel field of the DRAM Limit register
1277 * (section 3.4.4.2) for the node that input_addr is associated with.
1280 pvt = mci->pvt_info;
1281 node_id = pvt->node_id;
1282 BUG_ON((node_id < 0) || (node_id > 7));
1283 intlv_shift = num_node_interleave_bits((pvt->dbr[0] >> 8) & 0x07);
1285 if (intlv_shift == 0) {
1286 debugf1("node interleaving disabled: InputAddr 0x%lx "
1287 "translates to DramAddr of same value\n",
1288 (unsigned long) input_addr);
1292 bits = ((input_addr & 0xffffff000ull) << intlv_shift) +
1293 (input_addr & 0xfff);
1294 intlv_sel = pvt->dlr[node_id] & (((1 << intlv_shift) - 1) << 8);
1295 dram_addr = bits + (intlv_sel << 4);
1296 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
1297 "(%d node interleave bits)\n", (unsigned long) input_addr,
1298 (unsigned long) dram_addr, intlv_shift);
1302 /* dram_addr is a DramAddr that maps to the node represented by mci. Convert
1303 * dram_addr to a SysAddr and return the result.
1305 static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
1308 u64 hole_base, hole_offset, hole_size, base, limit, sys_addr;
1310 pvt = mci->pvt_info;
1312 if (!get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size)) {
1313 if ((dram_addr >= hole_base) &&
1314 (dram_addr < (hole_base + hole_size))) {
1315 /* use DHAR to translate DramAddr to SysAddr */
1316 sys_addr = dram_addr + hole_offset;
1317 debugf1("using DHAR to translate DramAddr 0x%lx to "
1318 "SysAddr 0x%lx\n", (unsigned long) dram_addr,
1319 (unsigned long) sys_addr);
1324 get_base_and_limit(pvt, pvt->node_id, &base, &limit);
1325 sys_addr = dram_addr + base;
1327 /* The sys_addr we have computed up to this point is a 40-bit value
1328 * because the k8 deals with 40-bit values. However, the value we are
1329 * supposed to return is a full 64-bit physical address. The AMD
1330 * x86-64 architecture specifies that the most significant implemented
1331 * address bit through bit 63 of a physical address must be either all
1332 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
1333 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
1334 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
1337 sys_addr |= ~((sys_addr & (1ull << 39)) - 1);
1339 debugf1("Using DRAM Base register for node %d to translate "
1340 "DramAddr 0x%lx to SysAddr 0x%lx\n", pvt->node_id,
1341 (unsigned long) dram_addr, (unsigned long) sys_addr);
1345 /* input_addr is an InputAddr associated with the node given by mci.
1346 * Translate input_addr to a SysAddr and return the result.
1348 static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci,
1351 return dram_addr_to_sys_addr(
1352 mci, input_addr_to_dram_addr(mci, input_addr));
1355 /* Find the minimum and maximum InputAddr values that map to the given csrow.
1356 * Pass back these values in *input_addr_min and *input_addr_max.
1358 static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
1359 u64 *input_addr_min, u64 *input_addr_max)
1364 pvt = mci->pvt_info;
1365 BUG_ON((csrow < 0) || (csrow >= K8_NR_CSROWS));
1366 base = base_from_dcsb(pvt, csrow);
1367 mask = mask_from_dcsm(pvt, csrow);
1368 *input_addr_min = base & ~mask;
1370 /* To find the max InputAddr for the csrow, start with the base
1371 * address and set all bits that are "don't care" bits in the test at
1372 * the start of section 3.5.4 (p. 84). The "don't care" bits are all
1373 * set bits in the mask and all bits in the gaps between bit ranges
1374 * [35-25] and [19-13]. The value 0x1f01fff represents bits [24-20]
1375 * and [12-0], which are all bits in the above-mentioned gaps.
1377 *input_addr_max = base | mask | pvt->dcs_mask_notused;
1380 /* Extract error address from MCA NB Address Low (section 3.6.4.5) and
1381 * MCA NB Address High (section 3.6.4.6) register values and return the
1384 static inline u64 error_address_from_k8_error_info(
1385 struct k8_error_info *info)
1387 return (((u64) (info->error_info.nbeah & 0xff)) << 32) +
1388 (info->error_info.nbeal & ~0x03);
1391 static inline void error_address_to_page_and_offset(u64 error_address,
1392 u32 *page, u32 *offset)
1394 *page = (u32) (error_address >> PAGE_SHIFT);
1395 *offset = ((u32) error_address) & ~PAGE_MASK;
1398 /* Return 1 if registers contain valid error information. Else return 0. */
1399 static inline int k8_error_info_valid(struct k8_error_info_regs *regs)
1401 return ((regs->nbsh & K8_NBSH_VALID_BIT) != 0);
1404 /* return 0 if regs contains valid error info; else return 1 */
1405 static int k8_get_error_info_regs(struct mem_ctl_info *mci,
1406 struct k8_error_info_regs *regs)
1410 pvt = mci->pvt_info;
1411 pci_read_config_dword(pvt->misc_ctl, K8_NBSH, ®s->nbsh);
1413 if (!k8_error_info_valid(regs))
1416 pci_read_config_dword(pvt->misc_ctl, K8_NBSL, ®s->nbsl);
1417 pci_read_config_dword(pvt->misc_ctl, K8_NBEAH, ®s->nbeah);
1418 pci_read_config_dword(pvt->misc_ctl, K8_NBEAL, ®s->nbeal);
1422 static void k8_get_error_info(struct mem_ctl_info *mci,
1423 struct k8_error_info *info)
1426 struct k8_error_info_regs regs;
1428 pvt = mci->pvt_info;
1429 info->race_condition_detected = 0;
1431 if (k8_get_error_info_regs(mci, &info->error_info))
1435 * Here's the problem with the K8's EDAC reporting:
1436 * There are four registers which report pieces of error
1437 * information. These four registers are shared between
1438 * CEs and UEs. Furthermore, contrary to what is stated in
1439 * the OBKG, the overflow bit is never used! Every error
1440 * always updates the reporting registers.
1442 * Can you see the race condition? All four error reporting
1443 * registers must be read before a new error updates them!
1444 * There is no way to read all four registers atomically. The
1445 * best than can be done is to detect that a race has occured
1446 * and then report the error without any kind of precision.
1448 * What is still positive is that errors are
1449 * still reported and thus problems can still be detected -
1450 * just not localized because the syndrome and address are
1451 * spread out across registers.
1453 * Grrrrr!!!!! Here's hoping that AMD fixes this in some
1454 * future K8 rev. UEs and CEs should have separate
1455 * register sets with proper overflow bits that are used!
1456 * At very least the problem can be fixed by honoring the
1457 * ErrValid bit in nbsh and not updating registers - just
1458 * set the overflow bit - unless the current error is CE
1459 * and the new error is UE which would be the only situation
1460 * for overwriting the current values.
1463 regs = info->error_info;
1465 /* Use info from the second read - most current */
1466 if (unlikely(k8_get_error_info_regs(mci, &info->error_info)))
1469 /* clear the error */
1470 pci_write_bits32(pvt->misc_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT);
1472 pci_read_config_dword(pvt->misc_ctl, K8_NBCFG, &pvt->nbcfg);
1473 info->race_condition_detected =
1474 ((regs.nbsh != info->error_info.nbsh) ||
1475 (regs.nbsl != info->error_info.nbsl) ||
1476 (regs.nbeah != info->error_info.nbeah) ||
1477 (regs.nbeal != info->error_info.nbeal));
1480 static inline void decode_gart_tlb_error(struct mem_ctl_info *mci,
1481 struct k8_error_info *info)
1484 u32 ec_tt; /* error code transaction type (2b) */
1485 u32 ec_ll; /* error code cache level (2b) */
1487 err_code = info->error_info.nbsl & 0xffffUL;
1488 ec_tt = (err_code >> 2) & 0x03UL;
1489 ec_ll = (err_code >> 0) & 0x03UL;
1490 k8_mc_printk(mci, KERN_ERR,
1491 "GART TLB errorr: transaction type(%s), "
1492 "cache level(%s)\n", tt_msgs[ec_tt], ll_msgs[ec_ll]);
1495 static inline void decode_cache_error(struct mem_ctl_info *mci,
1496 struct k8_error_info *info)
1499 u32 ec_rrrr; /* error code memory transaction (4b) */
1500 u32 ec_tt; /* error code transaction type (2b) */
1501 u32 ec_ll; /* error code cache level (2b) */
1503 err_code = info->error_info.nbsl & 0xffffUL;
1504 ec_rrrr = (err_code >> 4) & 0x0fUL;
1505 ec_tt = (err_code >> 2) & 0x03UL;
1506 ec_ll = (err_code >> 0) & 0x03UL;
1507 k8_mc_printk(mci, KERN_ERR,
1508 "cache heirarchy error: memory transaction type(%s), "
1509 "transaction type(%s), cache level(%s)\n",
1510 memtt_msgs[ec_rrrr], tt_msgs[ec_tt], ll_msgs[ec_ll]);
1513 /* sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
1514 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
1515 * of a node that detected an ECC memory error. mci represents the node that
1516 * the error address maps to (possibly different from the node that detected
1517 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
1520 static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
1524 csrow = input_addr_to_csrow(mci,
1525 sys_addr_to_input_addr(mci, sys_addr));
1528 k8_mc_printk(mci, KERN_ERR,
1529 "Failed to translate InputAddr to csrow for "
1530 "address 0x%lx\n", (unsigned long) sys_addr);
1535 static void k8_handle_ce(struct mem_ctl_info *mci, struct k8_error_info *info)
1542 struct mem_ctl_info *log_mci, *src_mci;
1545 pvt = mci->pvt_info;
1547 if ((info->error_info.nbsh & BIT(26)) == 0)
1548 goto no_info; /* error address not valid */
1550 error_address = error_address_from_k8_error_info(info);
1551 syndrome = ((info->error_info.nbsh >> 15) & 0xff);
1553 if (pvt->nbcfg & BIT(K8_NBCFG_CHIPKILL)) {
1554 /* chipkill ecc mode */
1555 syndrome += (info->error_info.nbsl >> 16) & 0xff00;
1556 channel = chan_from_chipkill_syndrome(syndrome);
1559 /* If the syndrome couldn't be found then the race
1560 * condition for error reporting registers likely
1561 * occurred. There's alot more in doubt than just the
1562 * channel. Might as well just log the error without
1565 k8_mc_printk(mci, KERN_WARNING,
1566 "unknown syndrome 0x%x - possible error "
1567 "reporting race\n", syndrome);
1571 /* non-chipkill ecc mode
1573 * The k8 documentation is unclear about how to determine the
1574 * channel number when using non-chipkill memory. This method
1575 * was obtained from email communication with someone at AMD.
1577 channel = ((error_address & BIT(3)) != 0);
1579 /* Find out which node the error address belongs to. This may be
1580 * different from the node that detected the error.
1582 if ((src_mci = find_mc_by_sys_addr(mci, error_address)) == NULL) {
1583 k8_mc_printk(mci, KERN_ERR,
1584 "failed to map error address 0x%lx to a node\n",
1585 (unsigned long) error_address);
1591 if ((csrow = sys_addr_to_csrow(log_mci, error_address)) < 0)
1594 error_address_to_page_and_offset(error_address, &page, &offset);
1595 edac_mc_handle_ce(log_mci, page, offset, syndrome, csrow, channel,
1600 edac_mc_handle_ce_no_info(log_mci,EDAC_MOD_STR);
1603 static void k8_handle_ue(struct mem_ctl_info *mci, struct k8_error_info *info)
1608 struct mem_ctl_info *log_mci, *src_mci;
1612 if ((info->error_info.nbsh & BIT(26)) == 0)
1613 goto no_info; /* error address not valid */
1615 error_address = error_address_from_k8_error_info(info);
1617 /* Find out which node the error address belongs to. This may be
1618 * different from the node that detected the error.
1620 if ((src_mci = find_mc_by_sys_addr(mci, error_address)) == NULL) {
1621 k8_mc_printk(mci, KERN_ERR,
1622 "failed to map error address 0x%lx to a node\n",
1623 (unsigned long) error_address);
1629 if ((csrow = sys_addr_to_csrow(log_mci, error_address)) < 0)
1632 error_address_to_page_and_offset(error_address, &page, &offset);
1633 edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR);
1637 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
1640 static void decode_bus_error(struct mem_ctl_info *mci,
1641 struct k8_error_info *info)
1643 u32 err_code, ext_ec;
1644 u32 ec_pp; /* error code participating processor (2p) */
1645 u32 ec_to; /* error code timed out (1b) */
1646 u32 ec_rrrr; /* error code memory transaction (4b) */
1647 u32 ec_ii; /* error code memory or I/O (2b) */
1648 u32 ec_ll; /* error code cache level (2b) */
1650 debugf0("MC%d: %s()\n", mci->mc_idx, __func__);
1651 err_code = info->error_info.nbsl & 0xffffUL;
1652 ec_pp = (err_code >> 9) & 0x03UL;
1653 ec_to = (err_code >> 8) & 0x01UL;
1654 ec_rrrr = (err_code >> 4) & 0x0fUL;
1655 ec_ii = (err_code >> 2) & 0x03UL;
1656 ec_ll = (err_code >> 0) & 0x03UL;
1657 ext_ec = (info->error_info.nbsl >> 16) & 0xfUL;
1659 /* FIXME - these should report through EDAC channels */
1660 k8_mc_printk(mci, KERN_ERR, "general bus error: participating "
1661 "processor(%s), time-out(%s) memory transaction "
1662 "type(%s), mem or i/o(%s), cache level(%s)\n",
1663 pp_msgs[ec_pp], to_msgs[ec_to], memtt_msgs[ec_rrrr],
1664 ii_msgs[ec_ii], ll_msgs[ec_ll]);
1667 return; /* We aren't the node involved */
1669 /* FIXME - other errors should have other error handling mechanisms */
1670 if (ext_ec && (ext_ec != 0x8)) {
1671 k8_mc_printk(mci, KERN_ERR,
1672 "no special error handling for this error\n");
1676 if (info->error_info.nbsh & BIT(14))
1677 k8_handle_ce(mci, info);
1678 else if (info->error_info.nbsh & BIT(13))
1679 k8_handle_ue(mci, info);
1681 /* If main error is CE then overflow must be CE. If main error is UE
1682 * then overflow is unknown. We'll call the overflow a CE - if
1683 * panic_on_ue is set then we're already panic'ed and won't arrive
1684 * here. If panic_on_ue is not set then apparently someone doesn't
1685 * think that UE's are catastrophic.
1687 if (info->error_info.nbsh & BIT(30))
1688 edac_mc_handle_ce_no_info(mci,
1689 EDAC_MOD_STR " Error Overflow set");
1692 /* return 1 if error found or 0 if error not found */
1693 static int k8_process_error_info(struct mem_ctl_info *mci,
1694 struct k8_error_info *info, int handle_errors)
1697 struct k8_error_info_regs *regs;
1698 u32 err_code, ext_ec;
1701 pvt = mci->pvt_info;
1703 /* check for an error */
1704 if (!k8_error_info_valid(&info->error_info))
1710 if (info->race_condition_detected)
1711 k8_mc_printk(mci, KERN_WARNING, "race condition detected!\n");
1714 regs = &info->error_info;
1715 err_code = info->error_info.nbsl & 0xffffUL;
1716 ext_ec = (info->error_info.nbsl >> 16) & 0x0fUL;
1717 debugf1("NorthBridge ERROR: mci(0x%p) node(%d) ErrAddr(0x%.8x-%.8x) "
1718 "nbsh(0x%.8x) nbsl(0x%.8x)\n", mci, pvt->node_id, regs->nbeah,
1719 regs->nbeal, regs->nbsh, regs->nbsl);
1721 if ((err_code & 0xfff0UL) == 0x0010UL) {
1722 debugf1("GART TLB error\n");
1724 decode_gart_tlb_error(mci, info);
1725 } else if ((err_code & 0xff00UL) == 0x0100UL) {
1726 debugf1("Cache error\n");
1727 decode_cache_error(mci, info);
1728 } else if ((err_code & 0xf800UL) == 0x0800UL) {
1729 debugf1("Bus error\n");
1730 decode_bus_error(mci, info);
1732 /* shouldn't reach here! */
1733 k8_mc_printk(mci, KERN_WARNING,
1734 "%s(): unknown MCE error 0x%x\n", __func__,
1737 k8_mc_printk(mci, KERN_ERR, "extended error code: %s\n",
1740 if (((ext_ec >= 1 && ext_ec <= 4) || (ext_ec == 6)) &&
1741 ((info->error_info.nbsh >> 4) & 0x07UL))
1742 k8_mc_printk(mci, KERN_ERR,
1743 "Error on hypertransport link: %s\n",
1744 htlink_msgs[(info->error_info.nbsh >> 4) & 0x07UL]);
1746 /* GART errors are benign as per AMD, do not panic on them */
1747 if (!gart_tlb_error && (regs->nbsh & BIT(29))) {
1748 k8_mc_printk(mci, KERN_CRIT, "uncorrected error\n");
1749 edac_mc_handle_ue_no_info(mci, "UE bit is set\n");
1752 if (regs->nbsh & BIT(25))
1753 panic("MC%d: processor context corrupt", mci->mc_idx);
1758 static void k8_check(struct mem_ctl_info *mci)
1760 struct k8_error_info info;
1762 debugf3("%s()\n", __func__);
1763 k8_get_error_info(mci, &info);
1764 k8_process_error_info(mci, &info, 1);
1767 static int k8_get_devs(struct mem_ctl_info *mci, int dev_idx)
1769 const struct k8_dev_info *k8_dev = &k8_devs[dev_idx];
1771 struct pci_dev *pdev;
1773 pdev = to_pci_dev(mci->dev);
1774 pvt = mci->pvt_info;
1776 /* The address mapping device provides a table that indicates which
1777 * physical address ranges are owned by which node. Each node's
1778 * memory controller has memory controller addresses that begin at
1781 pvt->addr_map = pci_get_related_function(PCI_VENDOR_ID_AMD,
1782 k8_dev->addr_map, pdev);
1784 if (pvt->addr_map == NULL) {
1785 k8_printk(KERN_ERR, "error address map device not found: "
1786 "vendor %x device 0x%x (broken BIOS?)\n",
1787 PCI_VENDOR_ID_AMD, k8_dev->addr_map);
1791 debugf1("Addr Map device PCI Bus ID:\t%s\n",
1792 pci_name(pvt->addr_map));
1794 pvt->misc_ctl = pci_get_related_function(PCI_VENDOR_ID_AMD,
1795 k8_dev->misc_ctl, pdev);
1797 if (pvt->misc_ctl == NULL) {
1798 pci_dev_put(pvt->addr_map);
1799 pvt->addr_map = NULL;
1800 k8_printk(KERN_ERR, "error miscellaneous device not found: "
1801 "vendor %x device 0x%x (broken BIOS?)\n",
1802 PCI_VENDOR_ID_AMD, k8_dev->misc_ctl);
1806 debugf1("Misc device PCI Bus ID:\t\t%s\n",
1807 pci_name(pvt->misc_ctl));
1812 static void k8_get_mc_regs(struct mem_ctl_info *mci)
1815 struct pci_dev *pdev;
1818 pdev = to_pci_dev(mci->dev);
1819 pvt = mci->pvt_info;
1820 debugf1("%s(MC node-id=%d): (ExtModel=%d) %s\n",
1821 __func__, pvt->node_id, pvt->ext_model,
1822 (pvt->ext_model >= OPTERON_CPU_REV_F) ?
1823 "Rev F or later" : "Rev E or earlier");
1825 for (i = 0; i < MAX_K8_NODES; i++) {
1826 pci_read_config_dword(pvt->addr_map, K8_DBR + (i * 8),
1828 pci_read_config_dword(pvt->addr_map, K8_DLR + (i * 8),
1830 debugf1(" dbr[%d]: 0x%x\n", i, pvt->dbr[i]);
1831 debugf1(" dlr[%d]: 0x%x\n", i, pvt->dlr[i]);
1834 /* Setup the DCSB and DCSM arrays from hardware */
1835 setup_dcsb_dcsm(pvt,pdev);
1837 pci_read_config_dword(pvt->addr_map, K8_DHAR, &pvt->dhar);
1838 pci_read_config_dword(pdev, K8_DBAM, &pvt->dbam);
1839 pci_read_config_dword(pvt->misc_ctl, K8_NBCAP, &pvt->nbcap);
1840 debugf1(" dhar: 0x%x\n", pvt->dhar);
1841 debugf1(" dbam: 0x%x\n", pvt->dbam);
1842 debugf1(" dcl: 0x%x\n", pvt->dcl);
1843 debugf1(" nbcap: %u\n", pvt->nbcap);
1846 /* Return 1 if dual channel mode is active. Else return 0. */
1847 static inline int dual_channel_active(u32 dcl, int mc_device_index)
1850 int ext_model = node_rev(mc_device_index);
1852 if (ext_model >= OPTERON_CPU_REV_F) {
1853 /* Rev F (NPT) and later */
1854 flag = (dcl >> 11) & 0x1;
1856 /* Rev E and earlier */
1857 flag = (dcl >> 16) & 0x1;
1863 static u32 csrow_nr_pages(int csrow_nr, struct k8_pvt *pvt)
1865 u32 shift, nr_pages;
1866 int ext_model = pvt->ext_model;
1868 /* The math on this doesn't look right on the surface because x/2*4
1869 * can be simplified to x*2 but this expression makes use of the fact
1870 * that it is integral math where 1/2=0
1872 shift = (pvt->dbam >> ((csrow_nr / 2) * 4)) & 0xF; /*PG88 */
1873 debugf0(" %s(csrow=%d) DBAM index= %d\n", __func__, csrow_nr,
1875 /* First step is to calc the number of bits to shift a value of 1
1876 * left to indicate show many pages. Start with the DBAM value
1877 * as the starting bits, then proceed to adjust those shift
1878 * bits, based on CPU REV and the table. See BKDG on the DBAM
1881 if (ext_model >= OPTERON_CPU_REV_F) {
1882 /* 27 shift, is 128Mib minimum DIMM size in REV F and later
1883 * upto 8 Gb, in a step function progression
1885 static u32 rev_f_shift[] = { 27, 28, 29, 29, 29, 30, 30, 31,
1886 31, 32, 32, 33, 0, 0, 0, 0 };
1887 nr_pages = 1 << (rev_f_shift[shift] - PAGE_SHIFT);
1889 /* REV E and less section This line is tricky.
1890 * It collapses the table used by revision D and later to one
1891 * that matches revision CG and earlier
1893 shift -= (ext_model >= OPTERON_CPU_REV_D)?
1896 (shift > 2 ? 1 : 0))): 0;
1897 /* 25 shift, is 32MiB minimum DIMM size in REV E and prior */
1898 nr_pages = 1 << (shift + 25 - PAGE_SHIFT);
1901 /* If dual channel then double thememory size of single channel */
1902 nr_pages <<= dual_channel_active(pvt->dcl, pvt->node_id);
1904 debugf0(" nr_pages= %u dual channel_active = %d\n",
1905 nr_pages, dual_channel_active(pvt->dcl, pvt->node_id));
1911 * determine_parity_enabled()
1913 * NOTE: CPU Revision Dependent code
1915 * determine if Parity is Enabled
1917 static int determine_parity_enabled(struct k8_pvt *pvt)
1921 if (pvt->ext_model >= OPTERON_CPU_REV_F) {
1922 if (pvt->dcl & BIT(8))
1930 * determine_memory_type()
1932 * NOTE: CPU Revision Dependent code
1934 * determine the memory type in operation on this controller
1936 static enum mem_type determine_memory_type(struct k8_pvt *pvt)
1940 if (pvt->ext_model >= OPTERON_CPU_REV_F) {
1941 /* Rev F and later */
1942 type = ((pvt->dcl >> 16) & 0x1) ? MEM_DDR2 : MEM_RDDR2;
1944 /* Rev E and earlier */
1945 type = ((pvt->dcl >> 18) & 0x1) ? MEM_DDR : MEM_RDDR;
1948 debugf1(" Memory type is: %s\n",
1949 (type == MEM_DDR2) ? "MEM_DDR2" :
1950 (type == MEM_RDDR2) ? "MEM_RDDR2" :
1951 (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR");
1957 * determine_dram_type()
1959 * NOTE: CPU Revision Dependent code
1961 * determine the DRAM type in operation
1962 * There are K8_NR_CSROWS (8) and 2 CSROWS per DIMM, therefore
1963 * there are 4 Logical DIMMs possible, thus 4 bits in the
1964 * configuration register indicating whether there are
1965 * X4 or X8 devices, one per logical DIMM
1967 static enum dev_type determine_dram_type(struct k8_pvt *pvt, int row)
1972 /* the starting bit depends on Revision value */
1973 bit = (pvt->ext_model >= OPTERON_CPU_REV_F) ? 12 : 20;
1974 type = ((pvt->dcl >> (bit + (row / 2))) & 0x01) ? DEV_X4 : DEV_X8;
1976 debugf1(" DRAM type is: %s\n", (type == DEV_X4) ? "DEV-x4" : "DEV-x8");
1982 * determine_edac_cap()
1984 * NOTE: CPU Revision Dependent code
1986 * determine if the DIMMs have ECC enabled
1987 * ECC is enabled ONLY if all the DIMMs are ECC capable
1989 static enum edac_type determine_edac_cap(struct k8_pvt *pvt)
1992 enum dev_type edac_cap = EDAC_NONE;
1994 bit = (pvt->ext_model >= OPTERON_CPU_REV_F) ? 19 : 17;
1995 if ((pvt->dcl >> bit) & 0x1) {
1996 debugf1(" edac_type is: EDAC_FLAG_SECDED\n");
1997 edac_cap = EDAC_FLAG_SECDED;
2003 static int k8_init_csrows(struct mem_ctl_info *mci)
2005 struct csrow_info *csrow;
2008 u64 input_addr_min, input_addr_max, sys_addr;
2010 pvt = mci->pvt_info;
2011 pci_read_config_dword(pvt->misc_ctl, K8_NBCFG, &pvt->nbcfg);
2014 for (i = 0; i < K8_NR_CSROWS; i++) {
2015 csrow = &mci->csrows[i];
2017 if ((pvt->dcsb[i] & K8_DCSB_CS_ENABLE) == 0) {
2018 debugf1("csrow %d empty for node %d\n", i,
2020 continue; /* empty */
2023 debugf1("revision for this node (%d) is %d\n",
2024 pvt->node_id, node_rev(pvt->node_id));
2026 csrow->nr_pages = csrow_nr_pages(i, pvt);
2027 find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
2028 sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
2029 csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
2030 sys_addr = input_addr_to_sys_addr(mci, input_addr_max);
2031 csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT);
2032 csrow->page_mask = ~mask_from_dcsm(pvt, i);
2033 csrow->grain = 8; /* 8 bytes of resolution */
2034 csrow->mtype = determine_memory_type(pvt);
2035 csrow->dtype = determine_dram_type(pvt, i);
2036 debugf1("for node %d csrow %d:\n nr_pages: %u "
2037 "input_addr_min: 0x%lx input_addr_max: 0x%lx "
2038 "sys_addr: 0x%lx first_page: 0x%lx last_page: 0x%lx "
2039 "page_mask: 0x%lx\n", pvt->node_id, i,
2040 (unsigned) csrow->nr_pages,
2041 (unsigned long) input_addr_min,
2042 (unsigned long) input_addr_max,
2043 (unsigned long) sys_addr,
2044 csrow->first_page, csrow->last_page,
2047 if (pvt->nbcfg & BIT(K8_NBCFG_ECC_ENABLE))
2048 csrow->edac_mode = (pvt->nbcfg & BIT(K8_NBCFG_CHIPKILL)) ?
2049 EDAC_S4ECD4ED : EDAC_SECDED;
2051 csrow->edac_mode = EDAC_NONE;
2057 static void k8_enable_error_reporting(struct mem_ctl_info *mci)
2060 u32 mc4ctl_l=0, mc4ctl_h=0, mcgctl_l=0, mcgctl_h=0;
2062 pvt = mci->pvt_info;
2063 pci_write_bits32(pvt->misc_ctl, K8_NBCTL, 0x3UL, 0x3UL);
2064 do_rdmsr(pvt->node_id, K8_MSR_MC4CTL, &mc4ctl_l, &mc4ctl_h);
2065 mc4ctl_l |= BIT(0) | BIT(1);
2066 do_wrmsr(pvt->node_id, K8_MSR_MC4CTL, mc4ctl_l, mc4ctl_h);
2067 do_rdmsr(pvt->node_id, K8_MSR_MC4CTL, &mc4ctl_l, &mc4ctl_h);
2068 do_rdmsr(pvt->node_id, K8_MSR_MCGCTL, &mcgctl_l, &mcgctl_h);
2070 do_wrmsr(pvt->node_id, K8_MSR_MCGCTL, mcgctl_l, mcgctl_h);
2071 do_rdmsr(pvt->node_id, K8_MSR_MCGCTL, &mcgctl_l, &mcgctl_h);
2074 static int k8_probe1(struct pci_dev *pdev, int dev_idx)
2076 struct mem_ctl_info *mci;
2078 u32 dcl, dual_channel;
2081 debugf0("%s()\n", __func__);
2082 build_node_revision_table();
2083 debugf1("pdev bus %u devfn %u\n", pdev->bus->number, pdev->devfn);
2084 pci_read_config_dword(pdev, K8_DCL, &dcl);
2085 dual_channel = dual_channel_active(dcl,
2086 MCI_TO_NODE_ID(pdev));
2087 debugf1("dual_channel is %u (dcl is 0x%x)\n", dual_channel, dcl);
2089 mci = edac_mc_alloc(sizeof(*pvt), K8_NR_CSROWS, dual_channel + 1);
2093 debugf0("%s(): mci = %p\n", __func__, mci);
2094 pvt = mci->pvt_info;
2096 mci->dev = &pdev->dev;
2097 pvt->node_id = MCI_TO_NODE_ID(pdev);
2098 pvt->ext_model = node_rev(pvt->node_id);
2100 if (k8_get_devs(mci, dev_idx))
2103 k8_get_mc_regs(mci);
2104 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
2105 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2106 debugf1("Initializing mci->edac_cap to EDAC_FLAG_NONE\n");
2107 mci->edac_cap = EDAC_FLAG_NONE;
2109 if (pvt->nbcap & BIT(K8_NBCAP_SECDED))
2110 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
2112 if (pvt->nbcap & BIT(K8_NBCAP_CHIPKILL))
2113 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
2115 mci->edac_cap = determine_edac_cap(pvt);
2116 if (mci->edac_cap & EDAC_FLAG_SECDED) {
2117 debugf1("setting EDAC_FLAG_SECDED in mci->edac_cap\n");
2118 mci->edac_cap |= EDAC_FLAG_SECDED;
2122 debugf1("setting EDAC_FLAG_S4ECD4ED in "
2124 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
2129 parity_enable = determine_parity_enabled(pvt);
2130 debugf1(" Parity is %s\n", parity_enable ? "Enabled" : "Disabled");
2132 mci->mod_name = EDAC_MOD_STR;
2133 mci->mod_ver = EDAC_K8_VERSION;
2134 mci->ctl_name = k8_devs[dev_idx].ctl_name;
2135 mci->edac_check = k8_check;
2136 mci->ctl_page_to_phys = NULL;
2138 if (k8_init_csrows(mci)) {
2139 debugf1("Setting mci->edac_cap to EDAC_FLAG_NONE "
2140 "because k8_init_csrows() returned nonzero "
2142 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
2144 k8_enable_error_reporting(mci);
2146 if (edac_mc_add_mc(mci, pvt->node_id)) {
2147 debugf1("%s(): failed edac_mc_add_mc()\n", __func__);
2148 /* FIXME: perhaps some code should go here that disables error
2149 * reporting if we just enabled it
2154 debugf1("%s(): success\n", __func__);
2158 pci_dev_put(pvt->addr_map);
2159 pci_dev_put(pvt->misc_ctl);
2166 /* returns count (>= 0), or negative on error */
2167 static int __devinit k8_init_one(struct pci_dev *pdev,
2168 const struct pci_device_id *ent)
2170 debugf0("%s()\n", __func__);
2172 /* wake up and enable device */
2173 return pci_enable_device(pdev) ?
2174 -EIO : k8_probe1(pdev, ent->driver_data);
2177 static void __devexit k8_remove_one(struct pci_dev *pdev)
2179 struct mem_ctl_info *mci;
2182 debugf0("%s()\n", __func__);
2184 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
2187 pvt = mci->pvt_info;
2188 pci_dev_put(pvt->addr_map);
2189 pci_dev_put(pvt->misc_ctl);
2193 static const struct pci_device_id k8_pci_tbl[] __devinitdata = {
2194 {PCI_VEND_DEV(AMD, OPT_2_MEMCTL), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2196 {0,} /* 0 terminated list. */
2199 MODULE_DEVICE_TABLE(pci, k8_pci_tbl);
2201 static struct pci_driver k8_driver = {
2202 .name = EDAC_MOD_STR,
2203 .probe = k8_init_one,
2204 .remove = __devexit_p(k8_remove_one),
2205 .id_table = k8_pci_tbl,
2208 int __init k8_init(void)
2210 return pci_module_init(&k8_driver);
2213 static void __exit k8_exit(void)
2215 pci_unregister_driver(&k8_driver);
2218 module_init(k8_init);
2219 module_exit(k8_exit);
2221 MODULE_LICENSE("GPL");
2222 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh, Doug Thompson, Dave Peterson");
2223 MODULE_DESCRIPTION("MC support for AMD K8 memory controllers - " EDAC_K8_VERSION );