vserver 1.9.3
[linux-2.6.git] / drivers / i2c / algos / i2c-algo-ite.c
1 /*
2    -------------------------------------------------------------------------
3    i2c-algo-ite.c i2c driver algorithms for ITE adapters            
4    
5    Hai-Pao Fan, MontaVista Software, Inc.
6    hpfan@mvista.com or source@mvista.com
7
8    Copyright 2000 MontaVista Software Inc.
9
10    ---------------------------------------------------------------------------
11    This file was highly leveraged from i2c-algo-pcf.c, which was created
12    by Simon G. Vogl and Hans Berglund:
13
14
15      Copyright (C) 1995-1997 Simon G. Vogl
16                    1998-2000 Hans Berglund
17
18     This program is free software; you can redistribute it and/or modify
19     it under the terms of the GNU General Public License as published by
20     the Free Software Foundation; either version 2 of the License, or
21     (at your option) any later version.
22
23     This program is distributed in the hope that it will be useful,
24     but WITHOUT ANY WARRANTY; without even the implied warranty of
25     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26     GNU General Public License for more details.
27
28     You should have received a copy of the GNU General Public License
29     along with this program; if not, write to the Free Software
30     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
31 /* ------------------------------------------------------------------------- */
32
33 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and 
34    Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
35    <mbailey@littlefeet-inc.com> */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <asm/uaccess.h>
43 #include <linux/ioport.h>
44 #include <linux/errno.h>
45 #include <linux/sched.h>
46
47 #include <linux/i2c.h>
48 #include <linux/i2c-algo-ite.h>
49 #include "i2c-algo-ite.h"
50
51 #define PM_DSR          IT8172_PCI_IO_BASE + IT_PM_DSR
52 #define PM_IBSR         IT8172_PCI_IO_BASE + IT_PM_DSR + 0x04 
53 #define GPIO_CCR        IT8172_PCI_IO_BASE + IT_GPCCR
54
55 #define DEB2(x) if (i2c_debug>=2) x
56 #define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
57 #define DEF_TIMEOUT 16
58
59
60 /* module parameters:
61  */
62 static int i2c_debug;
63 static int iic_test;    /* see if the line-setting functions work       */
64
65 /* --- setting states on the bus with the right timing: --------------- */
66
67 #define get_clock(adap) adap->getclock(adap->data)
68 #define iic_outw(adap, reg, val) adap->setiic(adap->data, reg, val)
69 #define iic_inw(adap, reg) adap->getiic(adap->data, reg)
70
71
72 /* --- other auxiliary functions -------------------------------------- */
73
74 static void iic_start(struct i2c_algo_iic_data *adap)
75 {
76         iic_outw(adap,ITE_I2CHCR,ITE_CMD);
77 }
78
79 static void iic_stop(struct i2c_algo_iic_data *adap)
80 {
81         iic_outw(adap,ITE_I2CHCR,0);
82         iic_outw(adap,ITE_I2CHSR,ITE_I2CHSR_TDI);
83 }
84
85 static void iic_reset(struct i2c_algo_iic_data *adap)
86 {
87         iic_outw(adap, PM_IBSR, iic_inw(adap, PM_IBSR) | 0x80);
88 }
89
90
91 static int wait_for_bb(struct i2c_algo_iic_data *adap)
92 {
93         int timeout = DEF_TIMEOUT;
94         short status;
95
96         status = iic_inw(adap, ITE_I2CHSR);
97 #ifndef STUB_I2C
98         while (timeout-- && (status & ITE_I2CHSR_HB)) {
99                 udelay(1000); /* How much is this? */
100                 status = iic_inw(adap, ITE_I2CHSR);
101         }
102 #endif
103         if (timeout<=0) {
104                 printk(KERN_ERR "Timeout, host is busy\n");
105                 iic_reset(adap);
106         }
107         return(timeout<=0);
108 }
109
110 /*
111  * Puts this process to sleep for a period equal to timeout 
112  */
113 static inline void iic_sleep(unsigned long timeout)
114 {
115         schedule_timeout( timeout * HZ);
116 }
117
118 /* After we issue a transaction on the IIC bus, this function
119  * is called.  It puts this process to sleep until we get an interrupt from
120  * from the controller telling us that the transaction we requested in complete.
121  */
122 static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) {
123
124         int timeout = DEF_TIMEOUT;
125         
126         timeout = wait_for_bb(adap);
127         if (timeout) {
128                 DEB2(printk("Timeout waiting for host not busy\n");)
129                 return -EIO;
130         }                           
131         timeout = DEF_TIMEOUT;
132
133         *status = iic_inw(adap, ITE_I2CHSR);
134 #ifndef STUB_I2C
135         while (timeout-- && !(*status & ITE_I2CHSR_TDI)) {
136            adap->waitforpin();
137            *status = iic_inw(adap, ITE_I2CHSR);
138         }
139 #endif
140         if (timeout <= 0)
141                 return(-1);
142         else
143                 return(0);
144 }
145
146 static int wait_for_fe(struct i2c_algo_iic_data *adap, short *status)
147 {
148         int timeout = DEF_TIMEOUT;
149
150         *status = iic_inw(adap, ITE_I2CFSR);
151 #ifndef STUB_I2C 
152         while (timeout-- && (*status & ITE_I2CFSR_FE)) {
153                 udelay(1000);
154                 iic_inw(adap, ITE_I2CFSR);
155         }
156 #endif
157         if (timeout <= 0) 
158                 return(-1);
159         else
160                 return(0);
161 }
162
163 static int iic_init (struct i2c_algo_iic_data *adap)
164 {
165         short i;
166
167         /* Clear bit 7 to set I2C to normal operation mode */
168         i=iic_inw(adap, PM_DSR)& 0xff7f;
169         iic_outw(adap, PM_DSR, i);
170
171         /* set IT_GPCCR port C bit 2&3 as function 2 */
172         i = iic_inw(adap, GPIO_CCR) & 0xfc0f;
173         iic_outw(adap,GPIO_CCR,i);
174
175         /* Clear slave address/sub-address */
176         iic_outw(adap,ITE_I2CSAR, 0);
177         iic_outw(adap,ITE_I2CSSAR, 0);
178
179         /* Set clock counter register */
180         iic_outw(adap,ITE_I2CCKCNT, get_clock(adap));
181
182         /* Set START/reSTART/STOP time registers */
183         iic_outw(adap,ITE_I2CSHDR, 0x0a);
184         iic_outw(adap,ITE_I2CRSUR, 0x0a);
185         iic_outw(adap,ITE_I2CPSUR, 0x0a);
186
187         /* Enable interrupts on completing the current transaction */
188         iic_outw(adap,ITE_I2CHCR, ITE_I2CHCR_IE | ITE_I2CHCR_HCE);
189
190         /* Clear transfer count */
191         iic_outw(adap,ITE_I2CFBCR, 0x0);
192
193         DEB2(printk("iic_init: Initialized IIC on ITE 0x%x\n",
194                 iic_inw(adap, ITE_I2CHSR)));
195         return 0;
196 }
197
198
199 /*
200  * Sanity check for the adapter hardware - check the reaction of
201  * the bus lines only if it seems to be idle.
202  */
203 static int test_bus(struct i2c_algo_iic_data *adap, char *name) {
204 #if 0
205         int scl,sda;
206         sda=getsda(adap);
207         if (adap->getscl==NULL) {
208                 printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n");
209                 return 0;               
210         }
211         scl=getscl(adap);
212         printk("test_bus: Adapter: %s scl: %d  sda: %d -- testing...\n",
213         name,getscl(adap),getsda(adap));
214         if (!scl || !sda ) {
215                 printk("test_bus: %s seems to be busy.\n",adap->name);
216                 goto bailout;
217         }
218         sdalo(adap);
219         printk("test_bus:1 scl: %d  sda: %d \n",getscl(adap),
220                getsda(adap));
221         if ( 0 != getsda(adap) ) {
222                 printk("test_bus: %s SDA stuck high!\n",name);
223                 sdahi(adap);
224                 goto bailout;
225         }
226         if ( 0 == getscl(adap) ) {
227                 printk("test_bus: %s SCL unexpected low while pulling SDA low!\n",
228                         name);
229                 goto bailout;
230         }               
231         sdahi(adap);
232         printk("test_bus:2 scl: %d  sda: %d \n",getscl(adap),
233                getsda(adap));
234         if ( 0 == getsda(adap) ) {
235                 printk("test_bus: %s SDA stuck low!\n",name);
236                 sdahi(adap);
237                 goto bailout;
238         }
239         if ( 0 == getscl(adap) ) {
240                 printk("test_bus: %s SCL unexpected low while SDA high!\n",
241                        adap->name);
242         goto bailout;
243         }
244         scllo(adap);
245         printk("test_bus:3 scl: %d  sda: %d \n",getscl(adap),
246                getsda(adap));
247         if ( 0 != getscl(adap) ) {
248
249                 sclhi(adap);
250                 goto bailout;
251         }
252         if ( 0 == getsda(adap) ) {
253                 printk("test_bus: %s SDA unexpected low while pulling SCL low!\n",
254                         name);
255                 goto bailout;
256         }
257         sclhi(adap);
258         printk("test_bus:4 scl: %d  sda: %d \n",getscl(adap),
259                getsda(adap));
260         if ( 0 == getscl(adap) ) {
261                 printk("test_bus: %s SCL stuck low!\n",name);
262                 sclhi(adap);
263                 goto bailout;
264         }
265         if ( 0 == getsda(adap) ) {
266                 printk("test_bus: %s SDA unexpected low while SCL high!\n",
267                         name);
268                 goto bailout;
269         }
270         printk("test_bus: %s passed test.\n",name);
271         return 0;
272 bailout:
273         sdahi(adap);
274         sclhi(adap);
275         return -ENODEV;
276 #endif
277         return (0);
278 }
279
280 /* ----- Utility functions
281  */
282
283
284 /* Verify the device we want to talk to on the IIC bus really exists. */
285 static inline int try_address(struct i2c_algo_iic_data *adap,
286                        unsigned int addr, int retries)
287 {
288         int i, ret = -1;
289         short status;
290
291         for (i=0;i<retries;i++) {
292                 iic_outw(adap, ITE_I2CSAR, addr);
293                 iic_start(adap);
294                 if (wait_for_pin(adap, &status) == 0) {
295                         if ((status & ITE_I2CHSR_DNE) == 0) { 
296                                 iic_stop(adap);
297                                 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
298                                 ret=1;
299                                 break;  /* success! */
300                         }
301                 }
302                 iic_stop(adap);
303                 udelay(adap->udelay);
304         }
305         DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i,
306                            addr));
307         return ret;
308 }
309
310
311 static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf,
312                          int count)
313 {
314         struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
315         int wrcount=0, timeout;
316         short status;
317         int loops, remainder, i, j;
318         union {
319                 char byte[2];
320                 unsigned short word;
321         } tmp;
322    
323         iic_outw(adap, ITE_I2CSSAR, (unsigned short)buf[wrcount++]);
324         count--;
325         if (count == 0)
326                 return -EIO;
327
328         loops =  count / 32;            /* 32-byte FIFO */
329         remainder = count % 32;
330
331         if(loops) {
332                 for(i=0; i<loops; i++) {
333
334                         iic_outw(adap, ITE_I2CFBCR, 32);
335                         for(j=0; j<32/2; j++) {
336                                 tmp.byte[1] = buf[wrcount++];
337                                 tmp.byte[0] = buf[wrcount++];
338                                 iic_outw(adap, ITE_I2CFDR, tmp.word); 
339                         }
340
341                         /* status FIFO overrun */
342                         iic_inw(adap, ITE_I2CFSR);
343                         iic_inw(adap, ITE_I2CFBCR);
344
345                         iic_outw(adap, ITE_I2CHCR, ITE_WRITE);  /* Issue WRITE command */
346
347                         /* Wait for transmission to complete */
348                         timeout = wait_for_pin(adap, &status);
349                         if(timeout) {
350                                 iic_stop(adap);
351                                 printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
352                                 return -EREMOTEIO; /* got a better one ?? */
353         }
354                         if (status & ITE_I2CHSR_DB) {
355                                 iic_stop(adap);
356                                 printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
357                                 return -EREMOTEIO; /* got a better one ?? */
358                         }
359                 }
360         }
361         if(remainder) {
362                 iic_outw(adap, ITE_I2CFBCR, remainder);
363                 for(i=0; i<remainder/2; i++) {
364                         tmp.byte[1] = buf[wrcount++];
365                         tmp.byte[0] = buf[wrcount++];
366                         iic_outw(adap, ITE_I2CFDR, tmp.word);
367                 }
368
369                 /* status FIFO overrun */
370                 iic_inw(adap, ITE_I2CFSR);
371                 iic_inw(adap, ITE_I2CFBCR);
372
373                 iic_outw(adap, ITE_I2CHCR, ITE_WRITE);  /* Issue WRITE command */
374
375                 timeout = wait_for_pin(adap, &status);
376                 if(timeout) {
377                         iic_stop(adap);
378                         printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
379                         return -EREMOTEIO; /* got a better one ?? */
380                 }
381 #ifndef STUB_I2C
382                 if (status & ITE_I2CHSR_DB) { 
383                         iic_stop(adap);
384                         printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
385                         return -EREMOTEIO; /* got a better one ?? */
386                 }
387 #endif
388         }
389         iic_stop(adap);
390         return wrcount;
391 }
392
393
394 static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count,
395         int sread)
396 {
397         int rdcount=0, i, timeout;
398         short status;
399         struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
400         int loops, remainder, j;
401         union {
402                 char byte[2];
403                 unsigned short word;
404         } tmp;
405                 
406         loops = count / 32;                             /* 32-byte FIFO */
407         remainder = count % 32;
408
409         if(loops) {
410                 for(i=0; i<loops; i++) {
411                         iic_outw(adap, ITE_I2CFBCR, 32);
412                         if (sread)
413                                 iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
414                         else
415                                 iic_outw(adap, ITE_I2CHCR, ITE_READ);           /* Issue READ command */
416
417                         timeout = wait_for_pin(adap, &status);
418                         if(timeout) {
419                                 iic_stop(adap);
420                                 printk("iic_readbytes:  %s read timeout.\n", i2c_adap->name);
421                                 return (-1);
422                         }
423 #ifndef STUB_I2C
424                         if (status & ITE_I2CHSR_DB) {
425                                 iic_stop(adap);
426                                 printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
427                                 return (-1);
428                         }
429 #endif
430
431                         timeout = wait_for_fe(adap, &status);
432                         if(timeout) {
433                                 iic_stop(adap);
434                                 printk("iic_readbytes:  %s FIFO is empty\n", i2c_adap->name);
435                                 return (-1); 
436                         }
437
438                         for(j=0; j<32/2; j++) {
439                                 tmp.word = iic_inw(adap, ITE_I2CFDR);
440                                 buf[rdcount++] = tmp.byte[1];
441                                 buf[rdcount++] = tmp.byte[0];
442                         }
443
444                         /* status FIFO underrun */
445                         iic_inw(adap, ITE_I2CFSR);
446
447                 }
448         }
449
450
451         if(remainder) {
452                 remainder=(remainder+1)/2 * 2;
453                 iic_outw(adap, ITE_I2CFBCR, remainder);
454                 if (sread)
455                         iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
456                 else
457                 iic_outw(adap, ITE_I2CHCR, ITE_READ);           /* Issue READ command */
458
459                 timeout = wait_for_pin(adap, &status);
460                 if(timeout) {
461                         iic_stop(adap);
462                         printk("iic_readbytes:  %s read timeout.\n", i2c_adap->name);
463                         return (-1);
464                 }
465 #ifndef STUB_I2C
466                 if (status & ITE_I2CHSR_DB) {
467                         iic_stop(adap);
468                         printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
469                         return (-1);
470                 }
471 #endif
472                 timeout = wait_for_fe(adap, &status);
473                 if(timeout) {
474                         iic_stop(adap);
475                         printk("iic_readbytes:  %s FIFO is empty\n", i2c_adap->name);
476                         return (-1);
477                 }         
478
479                 for(i=0; i<(remainder+1)/2; i++) {
480                         tmp.word = iic_inw(adap, ITE_I2CFDR);
481                         buf[rdcount++] = tmp.byte[1];
482                         buf[rdcount++] = tmp.byte[0];
483                 }
484
485                 /* status FIFO underrun */
486                 iic_inw(adap, ITE_I2CFSR);
487
488         }
489
490         iic_stop(adap);
491         return rdcount;
492 }
493
494
495 /* This function implements combined transactions.  Combined
496  * transactions consist of combinations of reading and writing blocks of data.
497  * Each transfer (i.e. a read or a write) is separated by a repeated start
498  * condition.
499  */
500 #if 0
501 static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 
502 {
503    int i;
504    struct i2c_msg *pmsg;
505    int ret;
506
507    DEB2(printk("Beginning combined transaction\n"));
508
509    for(i=0; i<(num-1); i++) {
510       pmsg = &msgs[i];
511       if(pmsg->flags & I2C_M_RD) {
512          DEB2(printk("  This one is a read\n"));
513          ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
514       }
515       else if(!(pmsg->flags & I2C_M_RD)) {
516          DEB2(printk("This one is a write\n"));
517          ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
518       }
519    }
520    /* Last read or write segment needs to be terminated with a stop */
521    pmsg = &msgs[i];
522
523    if(pmsg->flags & I2C_M_RD) {
524       DEB2(printk("Doing the last read\n"));
525       ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
526    }
527    else if(!(pmsg->flags & I2C_M_RD)) {
528       DEB2(printk("Doing the last write\n"));
529       ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
530    }
531
532    return ret;
533 }
534 #endif
535
536
537 /* Whenever we initiate a transaction, the first byte clocked
538  * onto the bus after the start condition is the address (7 bit) of the
539  * device we want to talk to.  This function manipulates the address specified
540  * so that it makes sense to the hardware when written to the IIC peripheral.
541  *
542  * Note: 10 bit addresses are not supported in this driver, although they are
543  * supported by the hardware.  This functionality needs to be implemented.
544  */
545 static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
546                                 struct i2c_msg *msg, int retries) 
547 {
548         unsigned short flags = msg->flags;
549         unsigned int addr;
550         int ret;
551
552 /* Ten bit addresses not supported right now */
553         if ( (flags & I2C_M_TEN)  ) { 
554 #if 0
555                 addr = 0xf0 | (( msg->addr >> 7) & 0x03);
556                 DEB2(printk("addr0: %d\n",addr));
557                 ret = try_address(adap, addr, retries);
558                 if (ret!=1) {
559                         printk("iic_doAddress: died at extended address code.\n");
560                         return -EREMOTEIO;
561                 }
562                 iic_outw(adap,msg->addr & 0x7f);
563                 if (ret != 1) {
564                         printk("iic_doAddress: died at 2nd address code.\n");
565                         return -EREMOTEIO;
566                 }
567                 if ( flags & I2C_M_RD ) {
568                         i2c_repstart(adap);
569                         addr |= 0x01;
570                         ret = try_address(adap, addr, retries);
571                         if (ret!=1) {
572                                 printk("iic_doAddress: died at extended address code.\n");
573                                 return -EREMOTEIO;
574                         }
575                 }
576 #endif
577         } else {
578
579                 addr = ( msg->addr << 1 );
580
581 #if 0
582                 if (flags & I2C_M_RD )
583                         addr |= 1;
584                 if (flags & I2C_M_REV_DIR_ADDR )
585                         addr ^= 1;
586 #endif
587
588                 if (iic_inw(adap, ITE_I2CSAR) != addr) {
589                         iic_outw(adap, ITE_I2CSAR, addr);
590                         ret = try_address(adap, addr, retries);
591                         if (ret!=1) {
592                                 printk("iic_doAddress: died at address code.\n");
593                                 return -EREMOTEIO;
594                         }
595                 }
596
597   }
598
599         return 0;
600 }
601
602
603 /* Description: Prepares the controller for a transaction (clearing status
604  * registers, data buffers, etc), and then calls either iic_readbytes or
605  * iic_sendbytes to do the actual transaction.
606  *
607  * still to be done: Before we issue a transaction, we should
608  * verify that the bus is not busy or in some unknown state.
609  */
610 static int iic_xfer(struct i2c_adapter *i2c_adap,
611                     struct i2c_msg msgs[], 
612                     int num)
613 {
614         struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
615         struct i2c_msg *pmsg;
616         int i = 0;
617         int ret, timeout;
618     
619         pmsg = &msgs[i];
620
621         if(!pmsg->len) {
622                 DEB2(printk("iic_xfer: read/write length is 0\n");)
623                 return -EIO;
624         }
625         if(!(pmsg->flags & I2C_M_RD) && (!(pmsg->len)%2) ) {
626                 DEB2(printk("iic_xfer: write buffer length is not odd\n");)
627                 return -EIO; 
628         }
629
630         /* Wait for any pending transfers to complete */
631         timeout = wait_for_bb(adap);
632         if (timeout) {
633                 DEB2(printk("iic_xfer: Timeout waiting for host not busy\n");)
634                 return -EIO;
635         }
636
637         /* Flush FIFO */
638         iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
639
640         /* Load address */
641         ret = iic_doAddress(adap, pmsg, i2c_adap->retries);
642         if (ret)
643                 return -EIO;
644
645 #if 0
646         /* Combined transaction (read and write) */
647         if(num > 1) {
648            DEB2(printk("iic_xfer: Call combined transaction\n"));
649            ret = iic_combined_transaction(i2c_adap, msgs, num);
650   }
651 #endif
652
653         DEB3(printk("iic_xfer: Msg %d, addr=0x%x, flags=0x%x, len=%d\n",
654                 i, msgs[i].addr, msgs[i].flags, msgs[i].len);)
655
656         if(pmsg->flags & I2C_M_RD)              /* Read */
657                 ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, 0);
658         else {                                                                                                  /* Write */ 
659                 udelay(1000);
660                 ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len);
661         }
662
663         if (ret != pmsg->len)
664                 DEB3(printk("iic_xfer: error or fail on read/write %d bytes.\n",ret)); 
665         else
666                 DEB3(printk("iic_xfer: read/write %d bytes.\n",ret));
667
668         return ret;
669 }
670
671
672 /* Implements device specific ioctls.  Higher level ioctls can
673  * be found in i2c-core.c and are typical of any i2c controller (specifying
674  * slave address, timeouts, etc).  These ioctls take advantage of any hardware
675  * features built into the controller for which this algorithm-adapter set
676  * was written.  These ioctls allow you to take control of the data and clock
677  * lines and set the either high or low,
678  * similar to a GPIO pin.
679  */
680 static int algo_control(struct i2c_adapter *adapter, 
681         unsigned int cmd, unsigned long arg)
682 {
683
684   struct i2c_algo_iic_data *adap = adapter->algo_data;
685   struct i2c_iic_msg s_msg;
686   char *buf;
687         int ret;
688
689   if (cmd == I2C_SREAD) {
690                 if(copy_from_user(&s_msg, (struct i2c_iic_msg *)arg, 
691                                 sizeof(struct i2c_iic_msg))) 
692                         return -EFAULT;
693                 buf = kmalloc(s_msg.len, GFP_KERNEL);
694                 if (buf== NULL)
695                         return -ENOMEM;
696
697                 /* Flush FIFO */
698                 iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
699
700                 /* Load address */
701                 iic_outw(adap, ITE_I2CSAR,s_msg.addr<<1);
702                 iic_outw(adap, ITE_I2CSSAR,s_msg.waddr & 0xff);
703
704                 ret = iic_readbytes(adapter, buf, s_msg.len, 1);
705                 if (ret>=0) {
706                         if(copy_to_user( s_msg.buf, buf, s_msg.len) ) 
707                                 ret = -EFAULT;
708                 }
709                 kfree(buf);
710         }
711         return 0;
712 }
713
714
715 static u32 iic_func(struct i2c_adapter *adap)
716 {
717         return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 
718                I2C_FUNC_PROTOCOL_MANGLING; 
719 }
720
721 /* -----exported algorithm data: -------------------------------------  */
722
723 static struct i2c_algorithm iic_algo = {
724         "ITE IIC algorithm",
725         I2C_ALGO_IIC,
726         iic_xfer,               /* master_xfer  */
727         NULL,                           /* smbus_xfer   */
728         NULL,                           /* slave_xmit           */
729         NULL,                           /* slave_recv           */
730         algo_control,                   /* ioctl                */
731         iic_func,                       /* functionality        */
732 };
733
734
735 /* 
736  * registering functions to load algorithms at runtime 
737  */
738 int i2c_iic_add_bus(struct i2c_adapter *adap)
739 {
740         struct i2c_algo_iic_data *iic_adap = adap->algo_data;
741
742         if (iic_test) {
743                 int ret = test_bus(iic_adap, adap->name);
744                 if (ret<0)
745                         return -ENODEV;
746         }
747
748         DEB2(printk("i2c-algo-ite: hw routines for %s registered.\n",
749                     adap->name));
750
751         /* register new adapter to i2c module... */
752
753         adap->id |= iic_algo.id;
754         adap->algo = &iic_algo;
755
756         adap->timeout = 100;    /* default values, should       */
757         adap->retries = 3;              /* be replaced by defines       */
758         adap->flags = 0;
759
760         i2c_add_adapter(adap);
761         iic_init(iic_adap);
762
763         return 0;
764 }
765
766
767 int i2c_iic_del_bus(struct i2c_adapter *adap)
768 {
769         int res;
770         if ((res = i2c_del_adapter(adap)) < 0)
771                 return res;
772         DEB2(printk("i2c-algo-ite: adapter unregistered: %s\n",adap->name));
773
774         return 0;
775 }
776
777
778 int __init i2c_algo_iic_init (void)
779 {
780         printk(KERN_INFO "ITE iic (i2c) algorithm module\n");
781         return 0;
782 }
783
784
785 void i2c_algo_iic_exit(void)
786 {
787         return;
788 }
789
790
791 EXPORT_SYMBOL(i2c_iic_add_bus);
792 EXPORT_SYMBOL(i2c_iic_del_bus);
793
794 /* The MODULE_* macros resolve to nothing if MODULES is not defined
795  * when this file is compiled.
796  */
797 MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
798 MODULE_DESCRIPTION("ITE iic algorithm");
799 MODULE_LICENSE("GPL");
800
801 module_param(iic_test, bool, 0);
802 module_param(i2c_debug, int, S_IRUGO | S_IWUSR);
803
804 MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available");
805 MODULE_PARM_DESC(i2c_debug,
806         "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
807
808
809 /* This function resolves to init_module (the function invoked when a module
810  * is loaded via insmod) when this file is compiled with MODULES defined.
811  * Otherwise (i.e. if you want this driver statically linked to the kernel),
812  * a pointer to this function is stored in a table and called
813  * during the initialization of the kernel (in do_basic_setup in /init/main.c) 
814  *
815  * All this functionality is complements of the macros defined in linux/init.h
816  */
817 module_init(i2c_algo_iic_init);
818
819
820 /* If MODULES is defined when this file is compiled, then this function will
821  * resolved to cleanup_module.
822  */
823 module_exit(i2c_algo_iic_exit);