drivers/i2c/busses/i2c-i801.c

   1 /*
   2     i801.c - Part of lm_sensors, Linux kernel modules for hardware
   3               monitoring
   4     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   5     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   6     <mdsxyz123@yahoo.com>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23 /*
  24     SUPPORTED DEVICES   PCI ID
  25     82801AA             2413
  26     82801AB             2423
  27     82801BA             2443
  28     82801CA/CAM         2483
  29     82801DB             24C3   (HW PEC supported, 32 byte buffer not supported)
  30     82801EB             24D3   (HW PEC supported, 32 byte buffer not supported)
  31
  32     This driver supports several versions of Intel's I/O Controller Hubs (ICH).
  33     For SMBus support, they are similar to the PIIX4 and are part
  34     of Intel's '810' and other chipsets.
  35     See the doc/busses/i2c-i801 file for details.
  36     I2C Block Read and Process Call are not supported.
  37 */
  38
  39 /* Note: we assume there can only be one I801, with one SMBus interface */
  40
  41 #include <linux/config.h>
  42 #include <linux/module.h>
  43 #include <linux/pci.h>
  44 #include <linux/kernel.h>
  45 #include <linux/stddef.h>
  46 #include <linux/sched.h>
  47 #include <linux/ioport.h>
  48 #include <linux/init.h>
  49 #include <linux/i2c.h>
  50 #include <asm/io.h>
  51
  52 #ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
  53 #define HAVE_PEC
  54 #endif
  55
  56 /* I801 SMBus address offsets */
  57 #define SMBHSTSTS       (0 + i801_smba)
  58 #define SMBHSTCNT       (2 + i801_smba)
  59 #define SMBHSTCMD       (3 + i801_smba)
  60 #define SMBHSTADD       (4 + i801_smba)
  61 #define SMBHSTDAT0      (5 + i801_smba)
  62 #define SMBHSTDAT1      (6 + i801_smba)
  63 #define SMBBLKDAT       (7 + i801_smba)
  64 #define SMBPEC          (8 + i801_smba) /* ICH4 only */
  65 #define SMBAUXSTS       (12 + i801_smba)        /* ICH4 only */
  66 #define SMBAUXCTL       (13 + i801_smba)        /* ICH4 only */
  67
  68 /* PCI Address Constants */
  69 #define SMBBA           0x020
  70 #define SMBHSTCFG       0x040
  71 #define SMBREV          0x008
  72
  73 /* Host configuration bits for SMBHSTCFG */
  74 #define SMBHSTCFG_HST_EN        1
  75 #define SMBHSTCFG_SMB_SMI_EN    2
  76 #define SMBHSTCFG_I2C_EN        4
  77
  78 /* Other settings */
  79 #define MAX_TIMEOUT             100
  80 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
  81
  82 /* I801 command constants */
  83 #define I801_QUICK              0x00
  84 #define I801_BYTE               0x04
  85 #define I801_BYTE_DATA          0x08
  86 #define I801_WORD_DATA          0x0C
  87 #define I801_PROC_CALL          0x10    /* later chips only, unimplemented */
  88 #define I801_BLOCK_DATA         0x14
  89 #define I801_I2C_BLOCK_DATA     0x18    /* unimplemented */
  90 #define I801_BLOCK_LAST         0x34
  91 #define I801_I2C_BLOCK_LAST     0x38    /* unimplemented */
  92 #define I801_START              0x40
  93 #define I801_PEC_EN             0x80    /* ICH4 only */
  94
  95 /* insmod parameters */
  96
  97 /* If force_addr is set to anything different from 0, we forcibly enable
  98    the I801 at the given address. VERY DANGEROUS! */
  99 static int force_addr = 0;
 100 MODULE_PARM(force_addr, "i");
 101 MODULE_PARM_DESC(force_addr,
 102                  "Forcibly enable the I801 at the given address. "
 103                  "EXTREMELY DANGEROUS!");
 104
 105 static int i801_transaction(void);
 106 static int i801_block_transaction(union i2c_smbus_data *data,
 107                                   char read_write, int command);
 108
 109 static unsigned short i801_smba;
 110 static struct pci_dev *I801_dev;
 111 static int isich4;
 112
 113 static int i801_setup(struct pci_dev *dev)
 114 {
 115         int error_return = 0;
 116         unsigned char temp;
 117
 118         /* Note: we keep on searching until we have found 'function 3' */
 119         if(PCI_FUNC(dev->devfn) != 3)
 120                 return -ENODEV;
 121
 122         I801_dev = dev;
 123         if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
 124             (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3))
 125                 isich4 = 1;
 126         else
 127                 isich4 = 0;
 128
 129         /* Determine the address of the SMBus areas */
 130         if (force_addr) {
 131                 i801_smba = force_addr & 0xfff0;
 132         } else {
 133                 pci_read_config_word(I801_dev, SMBBA, &i801_smba);
 134                 i801_smba &= 0xfff0;
 135                 if(i801_smba == 0) {
 136                         dev_err(&dev->dev, "SMB base address uninitialized"
 137                                 "- upgrade BIOS or use force_addr=0xaddr\n");
 138                         return -ENODEV;
 139                 }
 140         }
 141
 142         if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
 143                 dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
 144                         i801_smba);
 145                 error_return = -EBUSY;
 146                 goto END;
 147         }
 148
 149         pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
 150         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 151         pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
 152
 153         /* If force_addr is set, we program the new address here. Just to make
 154            sure, we disable the device first. */
 155         if (force_addr) {
 156                 pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
 157                 pci_write_config_word(I801_dev, SMBBA, i801_smba);
 158                 pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 0x01);
 159                 dev_warn(&dev->dev, "WARNING: I801 SMBus interface set to "
 160                         "new address %04x!\n", i801_smba);
 161         } else if ((temp & 1) == 0) {
 162                 pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 1);
 163                 dev_warn(&dev->dev, "enabling SMBus device\n");
 164         }
 165
 166         if (temp & 0x02)
 167                 dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
 168         else
 169                 dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
 170
 171         pci_read_config_byte(I801_dev, SMBREV, &temp);
 172         dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
 173         dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
 174
 175 END:
 176         return error_return;
 177 }
 178
 179 static int i801_transaction(void)
 180 {
 181         int temp;
 182         int result = 0;
 183         int timeout = 0;
 184
 185         dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
 186                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 187                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 188                 inb_p(SMBHSTDAT1));
 189
 190         /* Make sure the SMBus host is ready to start transmitting */
 191         /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
 192         if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 193                 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting... \n",
 194                         temp);
 195                 outb_p(temp, SMBHSTSTS);
 196                 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 197                         dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
 198                         return -1;
 199                 } else {
 200                         dev_dbg(&I801_dev->dev, "Successfull!\n");
 201                 }
 202         }
 203
 204         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 205
 206         /* We will always wait for a fraction of a second! */
 207         do {
 208                 i2c_delay(1);
 209                 temp = inb_p(SMBHSTSTS);
 210         } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
 211
 212         /* If the SMBus is still busy, we give up */
 213         if (timeout >= MAX_TIMEOUT) {
 214                 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
 215                 result = -1;
 216         }
 217
 218         if (temp & 0x10) {
 219                 result = -1;
 220                 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
 221         }
 222
 223         if (temp & 0x08) {
 224                 result = -1;
 225                 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
 226                         "until next hard reset. (sorry!)\n");
 227                 /* Clock stops and slave is stuck in mid-transmission */
 228         }
 229
 230         if (temp & 0x04) {
 231                 result = -1;
 232                 dev_dbg(&I801_dev->dev, "Error: no response!\n");
 233         }
 234
 235         if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
 236                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 237
 238         if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 239                 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction"
 240                         "(%02x)\n", temp);
 241         }
 242         dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 243                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 244                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 245                 inb_p(SMBHSTDAT1));
 246         return result;
 247 }
 248
 249 /* All-inclusive block transaction function */
 250 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
 251                                   int command)
 252 {
 253         int i, len;
 254         int smbcmd;
 255         int temp;
 256         int result = 0;
 257         int timeout;
 258         unsigned char hostc, errmask;
 259
 260         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 261                 if (read_write == I2C_SMBUS_WRITE) {
 262                         /* set I2C_EN bit in configuration register */
 263                         pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
 264                         pci_write_config_byte(I801_dev, SMBHSTCFG,
 265                                               hostc | SMBHSTCFG_I2C_EN);
 266                 } else {
 267                         dev_err(&I801_dev->dev,
 268                                 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
 269                         return -1;
 270                 }
 271         }
 272
 273         if (read_write == I2C_SMBUS_WRITE) {
 274                 len = data->block[0];
 275                 if (len < 1)
 276                         len = 1;
 277                 if (len > 32)
 278                         len = 32;
 279                 outb_p(len, SMBHSTDAT0);
 280                 outb_p(data->block[1], SMBBLKDAT);
 281         } else {
 282                 len = 32;       /* max for reads */
 283         }
 284
 285         if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 286                 /* set 32 byte buffer */
 287         }
 288
 289         for (i = 1; i <= len; i++) {
 290                 if (i == len && read_write == I2C_SMBUS_READ)
 291                         smbcmd = I801_BLOCK_LAST;
 292                 else
 293                         smbcmd = I801_BLOCK_DATA;
 294                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
 295
 296                 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
 297                         "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
 298                         inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
 299                         inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
 300
 301                 /* Make sure the SMBus host is ready to start transmitting */
 302                 temp = inb_p(SMBHSTSTS);
 303                 if (i == 1) {
 304                         /* Erronenous conditions before transaction:
 305                          * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
 306                         errmask=0x9f;
 307                 } else {
 308                         /* Erronenous conditions during transaction:
 309                          * Failed, Bus_Err, Dev_Err, Intr */
 310                         errmask=0x1e;
 311                 }
 312                 if (temp & errmask) {
 313                         dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
 314                                 "Resetting... \n", temp);
 315                         outb_p(temp, SMBHSTSTS);
 316                         if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
 317                                 dev_err(&I801_dev->dev,
 318                                         "Reset failed! (%02x)\n", temp);
 319                                 result = -1;
 320                                 goto END;
 321                         }
 322                         if (i != 1) {
 323                                 /* if die in middle of block transaction, fail */
 324                                 result = -1;
 325                                 goto END;
 326                         }
 327                 }
 328
 329                 if (i == 1)
 330                         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 331
 332                 /* We will always wait for a fraction of a second! */
 333                 timeout = 0;
 334                 do {
 335                         temp = inb_p(SMBHSTSTS);
 336                         i2c_delay(1);
 337                 }
 338                     while ((!(temp & 0x80))
 339                            && (timeout++ < MAX_TIMEOUT));
 340
 341                 /* If the SMBus is still busy, we give up */
 342                 if (timeout >= MAX_TIMEOUT) {
 343                         result = -1;
 344                         dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
 345                 }
 346
 347                 if (temp & 0x10) {
 348                         result = -1;
 349                         dev_dbg(&I801_dev->dev,
 350                                 "Error: Failed bus transaction\n");
 351                 } else if (temp & 0x08) {
 352                         result = -1;
 353                         dev_err(&I801_dev->dev, "Bus collision!\n");
 354                 } else if (temp & 0x04) {
 355                         result = -1;
 356                         dev_dbg(&I801_dev->dev, "Error: no response!\n");
 357                 }
 358
 359                 if (i == 1 && read_write == I2C_SMBUS_READ) {
 360                         len = inb_p(SMBHSTDAT0);
 361                         if (len < 1)
 362                                 len = 1;
 363                         if (len > 32)
 364                                 len = 32;
 365                         data->block[0] = len;
 366                 }
 367
 368                 /* Retrieve/store value in SMBBLKDAT */
 369                 if (read_write == I2C_SMBUS_READ)
 370                         data->block[i] = inb_p(SMBBLKDAT);
 371                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 372                         outb_p(data->block[i+1], SMBBLKDAT);
 373                 if ((temp & 0x9e) != 0x00)
 374                         outb_p(temp, SMBHSTSTS);  /* signals SMBBLKDAT ready */
 375
 376                 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
 377                         dev_dbg(&I801_dev->dev,
 378                                 "Bad status (%02x) at end of transaction\n",
 379                                 temp);
 380                 }
 381                 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
 382                         "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
 383                         inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
 384                         inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
 385
 386                 if (result < 0)
 387                         goto END;
 388         }
 389
 390 #ifdef HAVE_PEC
 391         if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
 392                 /* wait for INTR bit as advised by Intel */
 393                 timeout = 0;
 394                 do {
 395                         temp = inb_p(SMBHSTSTS);
 396                         i2c_delay(1);
 397                 } while ((!(temp & 0x02))
 398                            && (timeout++ < MAX_TIMEOUT));
 399
 400                 if (timeout >= MAX_TIMEOUT) {
 401                         dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
 402                 }
 403                 outb_p(temp, SMBHSTSTS);
 404         }
 405 #endif
 406         result = 0;
 407 END:
 408         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 409                 /* restore saved configuration register value */
 410                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
 411         }
 412         return result;
 413 }
 414
 415 /* Return -1 on error. */
 416 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
 417                        unsigned short flags, char read_write, u8 command,
 418                        int size, union i2c_smbus_data * data)
 419 {
 420         int hwpec = 0;
 421         int block = 0;
 422         int ret, xact = 0;
 423
 424 #ifdef HAVE_PEC
 425         if(isich4)
 426                 hwpec = (flags & I2C_CLIENT_PEC) != 0;
 427 #endif
 428
 429         switch (size) {
 430         case I2C_SMBUS_QUICK:
 431                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 432                        SMBHSTADD);
 433                 xact = I801_QUICK;
 434                 break;
 435         case I2C_SMBUS_BYTE:
 436                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 437                        SMBHSTADD);
 438                 if (read_write == I2C_SMBUS_WRITE)
 439                         outb_p(command, SMBHSTCMD);
 440                 xact = I801_BYTE;
 441                 break;
 442         case I2C_SMBUS_BYTE_DATA:
 443                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 444                        SMBHSTADD);
 445                 outb_p(command, SMBHSTCMD);
 446                 if (read_write == I2C_SMBUS_WRITE)
 447                         outb_p(data->byte, SMBHSTDAT0);
 448                 xact = I801_BYTE_DATA;
 449                 break;
 450         case I2C_SMBUS_WORD_DATA:
 451                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 452                        SMBHSTADD);
 453                 outb_p(command, SMBHSTCMD);
 454                 if (read_write == I2C_SMBUS_WRITE) {
 455                         outb_p(data->word & 0xff, SMBHSTDAT0);
 456                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 457                 }
 458                 xact = I801_WORD_DATA;
 459                 break;
 460         case I2C_SMBUS_BLOCK_DATA:
 461         case I2C_SMBUS_I2C_BLOCK_DATA:
 462 #ifdef HAVE_PEC
 463         case I2C_SMBUS_BLOCK_DATA_PEC:
 464                 if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
 465                         size = I2C_SMBUS_BLOCK_DATA_PEC;
 466 #endif
 467                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 468                        SMBHSTADD);
 469                 outb_p(command, SMBHSTCMD);
 470                 block = 1;
 471                 break;
 472         case I2C_SMBUS_PROC_CALL:
 473         default:
 474                 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
 475                 return -1;
 476         }
 477
 478 #ifdef HAVE_PEC
 479         if(isich4 && hwpec) {
 480                 if(size != I2C_SMBUS_QUICK &&
 481                    size != I2C_SMBUS_I2C_BLOCK_DATA)
 482                         outb_p(1, SMBAUXCTL);   /* enable HW PEC */
 483         }
 484 #endif
 485         if(block)
 486                 ret = i801_block_transaction(data, read_write, size);
 487         else {
 488                 outb_p(xact | ENABLE_INT9, SMBHSTCNT);
 489                 ret = i801_transaction();
 490         }
 491
 492 #ifdef HAVE_PEC
 493         if(isich4 && hwpec) {
 494                 if(size != I2C_SMBUS_QUICK &&
 495                    size != I2C_SMBUS_I2C_BLOCK_DATA)
 496                         outb_p(0, SMBAUXCTL);
 497         }
 498 #endif
 499
 500         if(block)
 501                 return ret;
 502         if(ret)
 503                 return -1;
 504         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 505                 return 0;
 506
 507         switch (xact & 0x7f) {
 508         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 509         case I801_BYTE_DATA:
 510                 data->byte = inb_p(SMBHSTDAT0);
 511                 break;
 512         case I801_WORD_DATA:
 513                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 514                 break;
 515         }
 516         return 0;
 517 }
 518
 519
 520 static u32 i801_func(struct i2c_adapter *adapter)
 521 {
 522         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 523             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 524             I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
 525 #ifdef HAVE_PEC
 526              | (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC |
 527                          I2C_FUNC_SMBUS_HWPEC_CALC
 528                        : 0)
 529 #endif
 530             ;
 531 }
 532
 533 static struct i2c_algorithm smbus_algorithm = {
 534         .name           = "Non-I2C SMBus adapter",
 535         .id             = I2C_ALGO_SMBUS,
 536         .smbus_xfer     = i801_access,
 537         .functionality  = i801_func,
 538 };
 539
 540 static struct i2c_adapter i801_adapter = {
 541         .owner          = THIS_MODULE,
 542         .class          = I2C_ADAP_CLASS_SMBUS,
 543         .algo           = &smbus_algorithm,
 544         .name           = "unset",
 545 };
 546
 547 static struct pci_device_id i801_ids[] = {
 548         {
 549                 .vendor =       PCI_VENDOR_ID_INTEL,
 550                 .device =       PCI_DEVICE_ID_INTEL_82801AA_3,
 551                 .subvendor =    PCI_ANY_ID,
 552                 .subdevice =    PCI_ANY_ID,
 553         },
 554         {
 555                 .vendor =       PCI_VENDOR_ID_INTEL,
 556                 .device =       PCI_DEVICE_ID_INTEL_82801AB_3,
 557                 .subvendor =    PCI_ANY_ID,
 558                 .subdevice =    PCI_ANY_ID,
 559         },
 560         {
 561                 .vendor =       PCI_VENDOR_ID_INTEL,
 562                 .device =       PCI_DEVICE_ID_INTEL_82801BA_2,
 563                 .subvendor =    PCI_ANY_ID,
 564                 .subdevice =    PCI_ANY_ID,
 565         },
 566         {
 567                 .vendor =       PCI_VENDOR_ID_INTEL,
 568                 .device =       PCI_DEVICE_ID_INTEL_82801CA_3,
 569                 .subvendor =    PCI_ANY_ID,
 570                 .subdevice =    PCI_ANY_ID,
 571         },
 572         {
 573                 .vendor =       PCI_VENDOR_ID_INTEL,
 574                 .device =       PCI_DEVICE_ID_INTEL_82801DB_3,
 575                 .subvendor =    PCI_ANY_ID,
 576                 .subdevice =    PCI_ANY_ID,
 577         },
 578         {
 579                 .vendor =   PCI_VENDOR_ID_INTEL,
 580                 .device =   PCI_DEVICE_ID_INTEL_82801EB_3,
 581                 .subvendor =    PCI_ANY_ID,
 582                 .subdevice =    PCI_ANY_ID,
 583         },
 584         { 0, }
 585 };
 586
 587 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 588 {
 589
 590         if (i801_setup(dev)) {
 591                 dev_warn(&dev->dev,
 592                         "I801 not detected, module not inserted.\n");
 593                 return -ENODEV;
 594         }
 595
 596         /* set up the driverfs linkage to our parent device */
 597         i801_adapter.dev.parent = &dev->dev;
 598
 599         snprintf(i801_adapter.name, I2C_NAME_SIZE,
 600                 "SMBus I801 adapter at %04x", i801_smba);
 601         return i2c_add_adapter(&i801_adapter);
 602 }
 603
 604 static void __devexit i801_remove(struct pci_dev *dev)
 605 {
 606         i2c_del_adapter(&i801_adapter);
 607         release_region(i801_smba, (isich4 ? 16 : 8));
 608 }
 609
 610 static struct pci_driver i801_driver = {
 611         .name           = "i801 smbus",
 612         .id_table       = i801_ids,
 613         .probe          = i801_probe,
 614         .remove         = __devexit_p(i801_remove),
 615 };
 616
 617 static int __init i2c_i801_init(void)
 618 {
 619         return pci_module_init(&i801_driver);
 620 }
 621
 622 static void __exit i2c_i801_exit(void)
 623 {
 624         pci_unregister_driver(&i801_driver);
 625 }
 626
 627 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
 628                 "Philip Edelbrock <phil@netroedge.com>, "
 629                 "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
 630 MODULE_DESCRIPTION("I801 SMBus driver");
 631 MODULE_LICENSE("GPL");
 632
 633 module_init(i2c_i801_init);
 634 module_exit(i2c_i801_exit);