drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/string.h>
  11 #include <linux/module.h>
  12 #include <linux/ioport.h>
  13 #include <linux/slab.h>
  14 #include <linux/blkdev.h>
  15 #include <linux/errno.h>
  16 #include <linux/hdreg.h>
  17 #include <linux/ide.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/device.h>
  20 #include <linux/init.h>
  21 #include <linux/scatterlist.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25 #include <asm/io.h>
  26
  27 #define ICS_IDENT_OFFSET                0x2280
  28
  29 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  30 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  31 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  32 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  33 #define ICS_ARCIN_V5_IDESTEPPING        6
  34
  35 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  36 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  37 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  38 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  39 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  40 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  41 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  42 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  43 #define ICS_ARCIN_V6_IDESTEPPING        6
  44
  45 struct cardinfo {
  46         unsigned int dataoffset;
  47         unsigned int ctrloffset;
  48         unsigned int stepping;
  49 };
  50
  51 static struct cardinfo icside_cardinfo_v5 = {
  52         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  53         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  54         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  55 };
  56
  57 static struct cardinfo icside_cardinfo_v6_1 = {
  58         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  59         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  60         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  61 };
  62
  63 static struct cardinfo icside_cardinfo_v6_2 = {
  64         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  65         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  66         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  67 };
  68
  69 struct icside_state {
  70         unsigned int channel;
  71         unsigned int enabled;
  72         void __iomem *irq_port;
  73         void __iomem *ioc_base;
  74         unsigned int type;
  75         /* parent device... until the IDE core gets one of its own */
  76         struct device *dev;
  77         ide_hwif_t *hwif[2];
  78 };
  79
  80 #define ICS_TYPE_A3IN   0
  81 #define ICS_TYPE_A3USER 1
  82 #define ICS_TYPE_V6     3
  83 #define ICS_TYPE_V5     15
  84 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  85
  86 /* ---------------- Version 5 PCB Support Functions --------------------- */
  87 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  88  * Purpose  : enable interrupts from card
  89  */
  90 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  91 {
  92         struct icside_state *state = ec->irq_data;
  93
  94         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  95 }
  96
  97 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  98  * Purpose  : disable interrupts from card
  99  */
 100 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 101 {
 102         struct icside_state *state = ec->irq_data;
 103
 104         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 105 }
 106
 107 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 108         .irqenable      = icside_irqenable_arcin_v5,
 109         .irqdisable     = icside_irqdisable_arcin_v5,
 110 };
 111
 112
 113 /* ---------------- Version 6 PCB Support Functions --------------------- */
 114 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 115  * Purpose  : enable interrupts from card
 116  */
 117 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 118 {
 119         struct icside_state *state = ec->irq_data;
 120         void __iomem *base = state->irq_port;
 121
 122         state->enabled = 1;
 123
 124         switch (state->channel) {
 125         case 0:
 126                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 127                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 128                 break;
 129         case 1:
 130                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 131                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 132                 break;
 133         }
 134 }
 135
 136 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 137  * Purpose  : disable interrupts from card
 138  */
 139 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 140 {
 141         struct icside_state *state = ec->irq_data;
 142
 143         state->enabled = 0;
 144
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 146         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 147 }
 148
 149 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 150  * Purpose  : detect an active interrupt from card
 151  */
 152 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 153 {
 154         struct icside_state *state = ec->irq_data;
 155
 156         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 157                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 158 }
 159
 160 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 161         .irqenable      = icside_irqenable_arcin_v6,
 162         .irqdisable     = icside_irqdisable_arcin_v6,
 163         .irqpending     = icside_irqpending_arcin_v6,
 164 };
 165
 166 /*
 167  * Handle routing of interrupts.  This is called before
 168  * we write the command to the drive.
 169  */
 170 static void icside_maskproc(ide_drive_t *drive, int mask)
 171 {
 172         ide_hwif_t *hwif = HWIF(drive);
 173         struct icside_state *state = hwif->hwif_data;
 174         unsigned long flags;
 175
 176         local_irq_save(flags);
 177
 178         state->channel = hwif->channel;
 179
 180         if (state->enabled && !mask) {
 181                 switch (hwif->channel) {
 182                 case 0:
 183                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 184                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 185                         break;
 186                 case 1:
 187                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 188                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 189                         break;
 190                 }
 191         } else {
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 193                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 194         }
 195
 196         local_irq_restore(flags);
 197 }
 198
 199 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 200
 201 #ifndef CONFIG_IDEDMA_ICS_AUTO
 202 #warning CONFIG_IDEDMA_ICS_AUTO=n support is obsolete, and will be removed soon.
 203 #endif
 204
 205 /*
 206  * SG-DMA support.
 207  *
 208  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 209  * There is only one DMA controller per card, which means that only
 210  * one drive can be accessed at one time.  NOTE! We do not enforce that
 211  * here, but we rely on the main IDE driver spotting that both
 212  * interfaces use the same IRQ, which should guarantee this.
 213  */
 214
 215 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 216 {
 217         ide_hwif_t *hwif = drive->hwif;
 218         struct icside_state *state = hwif->hwif_data;
 219         struct scatterlist *sg = hwif->sg_table;
 220
 221         ide_map_sg(drive, rq);
 222
 223         if (rq_data_dir(rq) == READ)
 224                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 225         else
 226                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 227
 228         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 229                                     hwif->sg_dma_direction);
 230 }
 231
 232 /*
 233  * Configure the IOMD to give the appropriate timings for the transfer
 234  * mode being requested.  We take the advice of the ATA standards, and
 235  * calculate the cycle time based on the transfer mode, and the EIDE
 236  * MW DMA specs that the drive provides in the IDENTIFY command.
 237  *
 238  * We have the following IOMD DMA modes to choose from:
 239  *
 240  *      Type    Active          Recovery        Cycle
 241  *      A       250 (250)       312 (550)       562 (800)
 242  *      B       187             250             437
 243  *      C       125 (125)       125 (375)       250 (500)
 244  *      D       62              125             187
 245  *
 246  * (figures in brackets are actual measured timings)
 247  *
 248  * However, we also need to take care of the read/write active and
 249  * recovery timings:
 250  *
 251  *                      Read    Write
 252  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 253  *      MW0     215     50      215     480     A
 254  *      MW1     80      50      50      150     C
 255  *      MW2     70      25      25      120     C
 256  */
 257 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
 258 {
 259         int on = 0, cycle_time = 0, use_dma_info = 0;
 260
 261         /*
 262          * Limit the transfer speed to MW_DMA_2.
 263          */
 264         if (xfer_mode > XFER_MW_DMA_2)
 265                 xfer_mode = XFER_MW_DMA_2;
 266
 267         switch (xfer_mode) {
 268         case XFER_MW_DMA_2:
 269                 cycle_time = 250;
 270                 use_dma_info = 1;
 271                 break;
 272
 273         case XFER_MW_DMA_1:
 274                 cycle_time = 250;
 275                 use_dma_info = 1;
 276                 break;
 277
 278         case XFER_MW_DMA_0:
 279                 cycle_time = 480;
 280                 break;
 281
 282         case XFER_SW_DMA_2:
 283         case XFER_SW_DMA_1:
 284         case XFER_SW_DMA_0:
 285                 cycle_time = 480;
 286                 break;
 287         }
 288
 289         /*
 290          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 291          * take care to note the values in the ID...
 292          */
 293         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 294                 cycle_time = drive->id->eide_dma_time;
 295
 296         drive->drive_data = cycle_time;
 297
 298         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 299                 on = 1;
 300         else
 301                 drive->drive_data = 480;
 302
 303         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 304                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 305
 306         drive->current_speed = xfer_mode;
 307
 308         return on;
 309 }
 310
 311 static int icside_dma_host_off(ide_drive_t *drive)
 312 {
 313         return 0;
 314 }
 315
 316 static int icside_dma_off_quietly(ide_drive_t *drive)
 317 {
 318         drive->using_dma = 0;
 319         return icside_dma_host_off(drive);
 320 }
 321
 322 static int icside_dma_host_on(ide_drive_t *drive)
 323 {
 324         return 0;
 325 }
 326
 327 static int icside_dma_on(ide_drive_t *drive)
 328 {
 329         drive->using_dma = 1;
 330         return icside_dma_host_on(drive);
 331 }
 332
 333 static int icside_dma_check(ide_drive_t *drive)
 334 {
 335         struct hd_driveid *id = drive->id;
 336         ide_hwif_t *hwif = HWIF(drive);
 337         int xfer_mode = XFER_PIO_2;
 338         int on;
 339
 340         if (!(id->capability & 1) || !hwif->autodma)
 341                 goto out;
 342
 343         /*
 344          * Consult the list of known "bad" drives
 345          */
 346         if (__ide_dma_bad_drive(drive))
 347                 goto out;
 348
 349         /*
 350          * Enable DMA on any drive that has multiword DMA
 351          */
 352         if (id->field_valid & 2) {
 353                 xfer_mode = ide_dma_speed(drive, 0);
 354                 goto out;
 355         }
 356
 357         /*
 358          * Consult the list of known "good" drives
 359          */
 360         if (__ide_dma_good_drive(drive)) {
 361                 if (id->eide_dma_time > 150)
 362                         goto out;
 363                 xfer_mode = XFER_MW_DMA_1;
 364         }
 365
 366 out:
 367         on = icside_set_speed(drive, xfer_mode);
 368
 369         if (on)
 370                 return icside_dma_on(drive);
 371         else
 372                 return icside_dma_off_quietly(drive);
 373 }
 374
 375 static int icside_dma_end(ide_drive_t *drive)
 376 {
 377         ide_hwif_t *hwif = HWIF(drive);
 378         struct icside_state *state = hwif->hwif_data;
 379
 380         drive->waiting_for_dma = 0;
 381
 382         disable_dma(hwif->hw.dma);
 383
 384         /* Teardown mappings after DMA has completed. */
 385         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 386                      hwif->sg_dma_direction);
 387
 388         return get_dma_residue(hwif->hw.dma) != 0;
 389 }
 390
 391 static void icside_dma_start(ide_drive_t *drive)
 392 {
 393         ide_hwif_t *hwif = HWIF(drive);
 394
 395         /* We can not enable DMA on both channels simultaneously. */
 396         BUG_ON(dma_channel_active(hwif->hw.dma));
 397         enable_dma(hwif->hw.dma);
 398 }
 399
 400 /*
 401  * dma_intr() is the handler for disk read/write DMA interrupts
 402  */
 403 static ide_startstop_t icside_dmaintr(ide_drive_t *drive)
 404 {
 405         unsigned int stat;
 406         int dma_stat;
 407
 408         dma_stat = icside_dma_end(drive);
 409         stat = HWIF(drive)->INB(IDE_STATUS_REG);
 410         if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | DRQ_STAT)) {
 411                 if (!dma_stat) {
 412                         struct request *rq = HWGROUP(drive)->rq;
 413                         int i;
 414
 415                         for (i = rq->nr_sectors; i > 0; ) {
 416                                 i -= rq->current_nr_sectors;
 417                                 DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
 418                         }
 419
 420                         return ide_stopped;
 421                 }
 422                 printk(KERN_ERR "%s: bad DMA status (dma_stat=%x)\n",
 423                        drive->name, dma_stat);
 424         }
 425
 426         return DRIVER(drive)->error(drive, __FUNCTION__, stat);
 427 }
 428
 429 static int icside_dma_setup(ide_drive_t *drive)
 430 {
 431         ide_hwif_t *hwif = HWIF(drive);
 432         struct request *rq = hwif->hwgroup->rq;
 433         unsigned int dma_mode;
 434
 435         if (rq_data_dir(rq))
 436                 dma_mode = DMA_MODE_WRITE;
 437         else
 438                 dma_mode = DMA_MODE_READ;
 439
 440         /*
 441          * We can not enable DMA on both channels.
 442          */
 443         BUG_ON(dma_channel_active(hwif->hw.dma));
 444
 445         icside_build_sglist(drive, rq);
 446
 447         /*
 448          * Ensure that we have the right interrupt routed.
 449          */
 450         icside_maskproc(drive, 0);
 451
 452         /*
 453          * Route the DMA signals to the correct interface.
 454          */
 455         writeb(hwif->select_data, hwif->config_data);
 456
 457         /*
 458          * Select the correct timing for this drive.
 459          */
 460         set_dma_speed(hwif->hw.dma, drive->drive_data);
 461
 462         /*
 463          * Tell the DMA engine about the SG table and
 464          * data direction.
 465          */
 466         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 467         set_dma_mode(hwif->hw.dma, dma_mode);
 468
 469         drive->waiting_for_dma = 1;
 470
 471         return 0;
 472 }
 473
 474 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 475 {
 476         /* issue cmd to drive */
 477         ide_execute_command(drive, cmd, icside_dmaintr, 2*WAIT_CMD, NULL);
 478 }
 479
 480 static int icside_dma_test_irq(ide_drive_t *drive)
 481 {
 482         ide_hwif_t *hwif = HWIF(drive);
 483         struct icside_state *state = hwif->hwif_data;
 484
 485         return readb(state->irq_port +
 486                      (hwif->channel ?
 487                         ICS_ARCIN_V6_INTRSTAT_2 :
 488                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 489 }
 490
 491 static int icside_dma_timeout(ide_drive_t *drive)
 492 {
 493         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 494
 495         if (icside_dma_test_irq(drive))
 496                 return 0;
 497
 498         ide_dump_status(drive, "DMA timeout",
 499                 HWIF(drive)->INB(IDE_STATUS_REG));
 500
 501         return icside_dma_end(drive);
 502 }
 503
 504 static int icside_dma_lostirq(ide_drive_t *drive)
 505 {
 506         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 507         return 1;
 508 }
 509
 510 static void icside_dma_init(ide_hwif_t *hwif)
 511 {
 512         int autodma = 0;
 513
 514 #ifdef CONFIG_IDEDMA_ICS_AUTO
 515         autodma = 1;
 516 #endif
 517
 518         printk("    %s: SG-DMA", hwif->name);
 519
 520         hwif->atapi_dma         = 1;
 521         hwif->mwdma_mask        = 7; /* MW0..2 */
 522         hwif->swdma_mask        = 7; /* SW0..2 */
 523
 524         hwif->dmatable_cpu      = NULL;
 525         hwif->dmatable_dma      = 0;
 526         hwif->speedproc         = icside_set_speed;
 527         hwif->autodma           = autodma;
 528
 529         hwif->ide_dma_check     = icside_dma_check;
 530         hwif->ide_dma_host_off  = icside_dma_host_off;
 531         hwif->ide_dma_off_quietly = icside_dma_off_quietly;
 532         hwif->ide_dma_host_on   = icside_dma_host_on;
 533         hwif->ide_dma_on        = icside_dma_on;
 534         hwif->ide_dma_setup     = icside_dma_setup;
 535         hwif->ide_dma_exec_cmd  = icside_dma_exec_cmd;
 536         hwif->ide_dma_start     = icside_dma_start;
 537         hwif->ide_dma_end       = icside_dma_end;
 538         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 539         hwif->ide_dma_timeout   = icside_dma_timeout;
 540         hwif->ide_dma_lostirq   = icside_dma_lostirq;
 541
 542         hwif->drives[0].autodma = hwif->autodma;
 543         hwif->drives[1].autodma = hwif->autodma;
 544
 545         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 546 }
 547 #else
 548 #define icside_dma_init(hwif)   (0)
 549 #endif
 550
 551 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 552 {
 553         ide_hwif_t *hwif;
 554         int index;
 555
 556         for (index = 0; index < MAX_HWIFS; ++index) {
 557                 hwif = &ide_hwifs[index];
 558                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 559                         goto found;
 560         }
 561
 562         for (index = 0; index < MAX_HWIFS; ++index) {
 563                 hwif = &ide_hwifs[index];
 564                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 565                         goto found;
 566         }
 567
 568         hwif = NULL;
 569 found:
 570         return hwif;
 571 }
 572
 573 static ide_hwif_t *
 574 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 575 {
 576         unsigned long port = (unsigned long)base + info->dataoffset;
 577         ide_hwif_t *hwif;
 578
 579         hwif = icside_find_hwif(port);
 580         if (hwif) {
 581                 int i;
 582
 583                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 584
 585                 /*
 586                  * Ensure we're using MMIO
 587                  */
 588                 default_hwif_mmiops(hwif);
 589                 hwif->mmio = 2;
 590
 591                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 592                         hwif->hw.io_ports[i] = port;
 593                         hwif->io_ports[i] = port;
 594                         port += 1 << info->stepping;
 595                 }
 596                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 597                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 598                 hwif->hw.irq  = ec->irq;
 599                 hwif->irq     = ec->irq;
 600                 hwif->noprobe = 0;
 601                 hwif->chipset = ide_acorn;
 602                 hwif->gendev.parent = &ec->dev;
 603         }
 604
 605         return hwif;
 606 }
 607
 608 static int __init
 609 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 610 {
 611         ide_hwif_t *hwif;
 612         void __iomem *base;
 613
 614         base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
 615                        ecard_resource_len(ec, ECARD_RES_MEMC));
 616         if (!base)
 617                 return -ENOMEM;
 618
 619         state->irq_port = base;
 620
 621         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 622         ec->irqmask  = 1;
 623         ec->irq_data = state;
 624         ec->ops      = &icside_ops_arcin_v5;
 625
 626         /*
 627          * Be on the safe side - disable interrupts
 628          */
 629         icside_irqdisable_arcin_v5(ec, 0);
 630
 631         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 632         if (!hwif) {
 633                 iounmap(base);
 634                 return -ENODEV;
 635         }
 636
 637         state->hwif[0] = hwif;
 638
 639         probe_hwif_init(hwif);
 640         create_proc_ide_interfaces();
 641
 642         return 0;
 643 }
 644
 645 static int __init
 646 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 647 {
 648         ide_hwif_t *hwif, *mate;
 649         void __iomem *ioc_base, *easi_base;
 650         unsigned int sel = 0;
 651         int ret;
 652
 653         ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
 654                            ecard_resource_len(ec, ECARD_RES_IOCFAST));
 655         if (!ioc_base) {
 656                 ret = -ENOMEM;
 657                 goto out;
 658         }
 659
 660         easi_base = ioc_base;
 661
 662         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 663                 easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI),
 664                                     ecard_resource_len(ec, ECARD_RES_EASI));
 665                 if (!easi_base) {
 666                         ret = -ENOMEM;
 667                         goto unmap_slot;
 668                 }
 669
 670                 /*
 671                  * Enable access to the EASI region.
 672                  */
 673                 sel = 1 << 5;
 674         }
 675
 676         writeb(sel, ioc_base);
 677
 678         ec->irq_data      = state;
 679         ec->ops           = &icside_ops_arcin_v6;
 680
 681         state->irq_port   = easi_base;
 682         state->ioc_base   = ioc_base;
 683
 684         /*
 685          * Be on the safe side - disable interrupts
 686          */
 687         icside_irqdisable_arcin_v6(ec, 0);
 688
 689         /*
 690          * Find and register the interfaces.
 691          */
 692         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 693         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 694
 695         if (!hwif || !mate) {
 696                 ret = -ENODEV;
 697                 goto unmap_port;
 698         }
 699
 700         state->hwif[0]    = hwif;
 701         state->hwif[1]    = mate;
 702
 703         hwif->maskproc    = icside_maskproc;
 704         hwif->channel     = 0;
 705         hwif->hwif_data   = state;
 706         hwif->mate        = mate;
 707         hwif->serialized  = 1;
 708         hwif->config_data = (unsigned long)ioc_base;
 709         hwif->select_data = sel;
 710         hwif->hw.dma      = ec->dma;
 711
 712         mate->maskproc    = icside_maskproc;
 713         mate->channel     = 1;
 714         mate->hwif_data   = state;
 715         mate->mate        = hwif;
 716         mate->serialized  = 1;
 717         mate->config_data = (unsigned long)ioc_base;
 718         mate->select_data = sel | 1;
 719         mate->hw.dma      = ec->dma;
 720
 721         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 722                 icside_dma_init(hwif);
 723                 icside_dma_init(mate);
 724         }
 725
 726         probe_hwif_init(hwif);
 727         probe_hwif_init(mate);
 728         create_proc_ide_interfaces();
 729
 730         return 0;
 731
 732  unmap_port:
 733         if (easi_base != ioc_base)
 734                 iounmap(easi_base);
 735  unmap_slot:
 736         iounmap(ioc_base);
 737  out:
 738         return ret;
 739 }
 740
 741 static int __devinit
 742 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 743 {
 744         struct icside_state *state;
 745         void *idmem;
 746         int ret;
 747
 748         ret = ecard_request_resources(ec);
 749         if (ret)
 750                 goto out;
 751
 752         state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
 753         if (!state) {
 754                 ret = -ENOMEM;
 755                 goto release;
 756         }
 757
 758         memset(state, 0, sizeof(state));
 759         state->type     = ICS_TYPE_NOTYPE;
 760         state->dev      = &ec->dev;
 761
 762         idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
 763                         ecard_resource_len(ec, ECARD_RES_IOCFAST));
 764         if (idmem) {
 765                 unsigned int type;
 766
 767                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 768                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 769                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 770                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 771                 iounmap(idmem);
 772
 773                 state->type = type;
 774         }
 775
 776         switch (state->type) {
 777         case ICS_TYPE_A3IN:
 778                 dev_warn(&ec->dev, "A3IN unsupported\n");
 779                 ret = -ENODEV;
 780                 break;
 781
 782         case ICS_TYPE_A3USER:
 783                 dev_warn(&ec->dev, "A3USER unsupported\n");
 784                 ret = -ENODEV;
 785                 break;
 786
 787         case ICS_TYPE_V5:
 788                 ret = icside_register_v5(state, ec);
 789                 break;
 790
 791         case ICS_TYPE_V6:
 792                 ret = icside_register_v6(state, ec);
 793                 break;
 794
 795         default:
 796                 dev_warn(&ec->dev, "unknown interface type\n");
 797                 ret = -ENODEV;
 798                 break;
 799         }
 800
 801         if (ret == 0) {
 802                 ecard_set_drvdata(ec, state);
 803                 goto out;
 804         }
 805
 806         kfree(state);
 807  release:
 808         ecard_release_resources(ec);
 809  out:
 810         return ret;
 811 }
 812
 813 static void __devexit icside_remove(struct expansion_card *ec)
 814 {
 815         struct icside_state *state = ecard_get_drvdata(ec);
 816
 817         switch (state->type) {
 818         case ICS_TYPE_V5:
 819                 /* FIXME: tell IDE to stop using the interface */
 820
 821                 /* Disable interrupts */
 822                 icside_irqdisable_arcin_v5(ec, 0);
 823                 break;
 824
 825         case ICS_TYPE_V6:
 826                 /* FIXME: tell IDE to stop using the interface */
 827                 if (ec->dma != NO_DMA)
 828                         free_dma(ec->dma);
 829
 830                 /* Disable interrupts */
 831                 icside_irqdisable_arcin_v6(ec, 0);
 832
 833                 /* Reset the ROM pointer/EASI selection */
 834                 writeb(0, state->ioc_base);
 835                 break;
 836         }
 837
 838         ecard_set_drvdata(ec, NULL);
 839         ec->ops = NULL;
 840         ec->irq_data = NULL;
 841
 842         if (state->ioc_base)
 843                 iounmap(state->ioc_base);
 844         if (state->ioc_base != state->irq_port)
 845                 iounmap(state->irq_port);
 846
 847         kfree(state);
 848         ecard_release_resources(ec);
 849 }
 850
 851 static void icside_shutdown(struct expansion_card *ec)
 852 {
 853         struct icside_state *state = ecard_get_drvdata(ec);
 854         unsigned long flags;
 855
 856         /*
 857          * Disable interrupts from this card.  We need to do
 858          * this before disabling EASI since we may be accessing
 859          * this register via that region.
 860          */
 861         local_irq_save(flags);
 862         ec->ops->irqdisable(ec, 0);
 863         local_irq_restore(flags);
 864
 865         /*
 866          * Reset the ROM pointer so that we can read the ROM
 867          * after a soft reboot.  This also disables access to
 868          * the IDE taskfile via the EASI region.
 869          */
 870         if (state->ioc_base)
 871                 writeb(0, state->ioc_base);
 872 }
 873
 874 static const struct ecard_id icside_ids[] = {
 875         { MANU_ICS,  PROD_ICS_IDE  },
 876         { MANU_ICS2, PROD_ICS2_IDE },
 877         { 0xffff, 0xffff }
 878 };
 879
 880 static struct ecard_driver icside_driver = {
 881         .probe          = icside_probe,
 882         .remove         = __devexit_p(icside_remove),
 883         .shutdown       = icside_shutdown,
 884         .id_table       = icside_ids,
 885         .drv = {
 886                 .name   = "icside",
 887         },
 888 };
 889
 890 static int __init icside_init(void)
 891 {
 892         return ecard_register_driver(&icside_driver);
 893 }
 894
 895 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 896 MODULE_LICENSE("GPL");
 897 MODULE_DESCRIPTION("ICS IDE driver");
 898
 899 module_init(icside_init);