drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2003 Russell King.
   5  */
   6
   7 #include <linux/config.h>
   8 #include <linux/string.h>
   9 #include <linux/module.h>
  10 #include <linux/ioport.h>
  11 #include <linux/slab.h>
  12 #include <linux/blkdev.h>
  13 #include <linux/errno.h>
  14 #include <linux/hdreg.h>
  15 #include <linux/ide.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/device.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/dma.h>
  21 #include <asm/ecard.h>
  22 #include <asm/io.h>
  23
  24 #define ICS_IDENT_OFFSET                0x2280
  25
  26 #define ICS_ARCIN_V5_INTRSTAT           0x000
  27 #define ICS_ARCIN_V5_INTROFFSET         0x001
  28 #define ICS_ARCIN_V5_IDEOFFSET          0xa00
  29 #define ICS_ARCIN_V5_IDEALTOFFSET       0xae0
  30 #define ICS_ARCIN_V5_IDESTEPPING        4
  31
  32 #define ICS_ARCIN_V6_IDEOFFSET_1        0x800
  33 #define ICS_ARCIN_V6_INTROFFSET_1       0x880
  34 #define ICS_ARCIN_V6_INTRSTAT_1         0x8a4
  35 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x8e0
  36 #define ICS_ARCIN_V6_IDEOFFSET_2        0xc00
  37 #define ICS_ARCIN_V6_INTROFFSET_2       0xc80
  38 #define ICS_ARCIN_V6_INTRSTAT_2         0xca4
  39 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0xce0
  40 #define ICS_ARCIN_V6_IDESTEPPING        4
  41
  42 struct cardinfo {
  43         unsigned int dataoffset;
  44         unsigned int ctrloffset;
  45         unsigned int stepping;
  46 };
  47
  48 static struct cardinfo icside_cardinfo_v5 = {
  49         ICS_ARCIN_V5_IDEOFFSET,
  50         ICS_ARCIN_V5_IDEALTOFFSET,
  51         ICS_ARCIN_V5_IDESTEPPING
  52 };
  53
  54 static struct cardinfo icside_cardinfo_v6_1 = {
  55         ICS_ARCIN_V6_IDEOFFSET_1,
  56         ICS_ARCIN_V6_IDEALTOFFSET_1,
  57         ICS_ARCIN_V6_IDESTEPPING
  58 };
  59
  60 static struct cardinfo icside_cardinfo_v6_2 = {
  61         ICS_ARCIN_V6_IDEOFFSET_2,
  62         ICS_ARCIN_V6_IDEALTOFFSET_2,
  63         ICS_ARCIN_V6_IDESTEPPING
  64 };
  65
  66 struct icside_state {
  67         unsigned int channel;
  68         unsigned int enabled;
  69         unsigned long irq_port;
  70         unsigned long slot_port;
  71         unsigned int type;
  72         /* parent device... until the IDE core gets one of its own */
  73         struct device *dev;
  74         ide_hwif_t *hwif[2];
  75 };
  76
  77 #define ICS_TYPE_A3IN   0
  78 #define ICS_TYPE_A3USER 1
  79 #define ICS_TYPE_V6     3
  80 #define ICS_TYPE_V5     15
  81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  82
  83 /* ---------------- Version 5 PCB Support Functions --------------------- */
  84 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  85  * Purpose  : enable interrupts from card
  86  */
  87 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  88 {
  89         struct icside_state *state = ec->irq_data;
  90         unsigned int base = state->irq_port;
  91
  92         outb(0, base + ICS_ARCIN_V5_INTROFFSET);
  93 }
  94
  95 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  96  * Purpose  : disable interrupts from card
  97  */
  98 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  99 {
 100         struct icside_state *state = ec->irq_data;
 101         unsigned int base = state->irq_port;
 102
 103         inb(base + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         unsigned int base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 outb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 inb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 outb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 inb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208 #define NR_ENTRIES 256
 209 #define TABLE_SIZE (NR_ENTRIES * 8)
 210
 211 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 212 {
 213         ide_hwif_t *hwif = drive->hwif;
 214         struct icside_state *state = hwif->hwif_data;
 215         struct scatterlist *sg = hwif->sg_table;
 216         int nents;
 217
 218         BUG_ON(hwif->sg_dma_active);
 219
 220         if (rq->flags & REQ_DRIVE_TASKFILE) {
 221                 ide_task_t *args = rq->special;
 222
 223                 if (args->command_type == IDE_DRIVE_TASK_RAW_WRITE)
 224                         hwif->sg_dma_direction = DMA_TO_DEVICE;
 225                 else
 226                         hwif->sg_dma_direction = DMA_FROM_DEVICE;
 227
 228                 memset(sg, 0, sizeof(*sg));
 229                 sg->page   = virt_to_page(rq->buffer);
 230                 sg->offset = offset_in_page(rq->buffer);
 231                 sg->length = rq->nr_sectors * SECTOR_SIZE;
 232                 nents = 1;
 233         } else {
 234                 nents = blk_rq_map_sg(drive->queue, rq, sg);
 235
 236                 if (rq_data_dir(rq) == READ)
 237                         hwif->sg_dma_direction = DMA_FROM_DEVICE;
 238                 else
 239                         hwif->sg_dma_direction = DMA_TO_DEVICE;
 240         }
 241
 242         nents = dma_map_sg(state->dev, sg, nents, hwif->sg_dma_direction);
 243
 244         hwif->sg_nents = nents;
 245 }
 246
 247
 248 /*
 249  * Configure the IOMD to give the appropriate timings for the transfer
 250  * mode being requested.  We take the advice of the ATA standards, and
 251  * calculate the cycle time based on the transfer mode, and the EIDE
 252  * MW DMA specs that the drive provides in the IDENTIFY command.
 253  *
 254  * We have the following IOMD DMA modes to choose from:
 255  *
 256  *      Type    Active          Recovery        Cycle
 257  *      A       250 (250)       312 (550)       562 (800)
 258  *      B       187             250             437
 259  *      C       125 (125)       125 (375)       250 (500)
 260  *      D       62              125             187
 261  *
 262  * (figures in brackets are actual measured timings)
 263  *
 264  * However, we also need to take care of the read/write active and
 265  * recovery timings:
 266  *
 267  *                      Read    Write
 268  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 269  *      MW0     215     50      215     480     A
 270  *      MW1     80      50      50      150     C
 271  *      MW2     70      25      25      120     C
 272  */
 273 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
 274 {
 275         int on = 0, cycle_time = 0, use_dma_info = 0;
 276
 277         /*
 278          * Limit the transfer speed to MW_DMA_2.
 279          */
 280         if (xfer_mode > XFER_MW_DMA_2)
 281                 xfer_mode = XFER_MW_DMA_2;
 282
 283         switch (xfer_mode) {
 284         case XFER_MW_DMA_2:
 285                 cycle_time = 250;
 286                 use_dma_info = 1;
 287                 break;
 288
 289         case XFER_MW_DMA_1:
 290                 cycle_time = 250;
 291                 use_dma_info = 1;
 292                 break;
 293
 294         case XFER_MW_DMA_0:
 295                 cycle_time = 480;
 296                 break;
 297
 298         case XFER_SW_DMA_2:
 299         case XFER_SW_DMA_1:
 300         case XFER_SW_DMA_0:
 301                 cycle_time = 480;
 302                 break;
 303         }
 304
 305         /*
 306          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 307          * take care to note the values in the ID...
 308          */
 309         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 310                 cycle_time = drive->id->eide_dma_time;
 311
 312         drive->drive_data = cycle_time;
 313
 314         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 315                 on = 1;
 316         else
 317                 drive->drive_data = 480;
 318
 319         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 320                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 321
 322         drive->current_speed = xfer_mode;
 323
 324         return on;
 325 }
 326
 327 static int icside_dma_host_off(ide_drive_t *drive)
 328 {
 329         return 0;
 330 }
 331
 332 static int icside_dma_off_quietly(ide_drive_t *drive)
 333 {
 334         drive->using_dma = 0;
 335         return icside_dma_host_off(drive);
 336 }
 337
 338 static int icside_dma_host_on(ide_drive_t *drive)
 339 {
 340         return 0;
 341 }
 342
 343 static int icside_dma_on(ide_drive_t *drive)
 344 {
 345         drive->using_dma = 1;
 346         return icside_dma_host_on(drive);
 347 }
 348
 349 static int icside_dma_check(ide_drive_t *drive)
 350 {
 351         struct hd_driveid *id = drive->id;
 352         ide_hwif_t *hwif = HWIF(drive);
 353         int xfer_mode = XFER_PIO_2;
 354         int on;
 355
 356         if (!(id->capability & 1) || !hwif->autodma)
 357                 goto out;
 358
 359         /*
 360          * Consult the list of known "bad" drives
 361          */
 362         if (__ide_dma_bad_drive(drive))
 363                 goto out;
 364
 365         /*
 366          * Enable DMA on any drive that has multiword DMA
 367          */
 368         if (id->field_valid & 2) {
 369                 xfer_mode = ide_dma_speed(drive, 0);
 370                 goto out;
 371         }
 372
 373         /*
 374          * Consult the list of known "good" drives
 375          */
 376         if (__ide_dma_good_drive(drive)) {
 377                 if (id->eide_dma_time > 150)
 378                         goto out;
 379                 xfer_mode = XFER_MW_DMA_1;
 380         }
 381
 382 out:
 383         on = icside_set_speed(drive, xfer_mode);
 384
 385         if (on)
 386                 return icside_dma_on(drive);
 387         else
 388                 return icside_dma_off_quietly(drive);
 389 }
 390
 391 static int icside_dma_end(ide_drive_t *drive)
 392 {
 393         ide_hwif_t *hwif = HWIF(drive);
 394         struct icside_state *state = hwif->hwif_data;
 395
 396         drive->waiting_for_dma = 0;
 397
 398         disable_dma(hwif->hw.dma);
 399
 400         /* Teardown mappings after DMA has completed. */
 401         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 402                      hwif->sg_dma_direction);
 403
 404         hwif->sg_dma_active = 0;
 405
 406         return get_dma_residue(hwif->hw.dma) != 0;
 407 }
 408
 409 static int icside_dma_begin(ide_drive_t *drive)
 410 {
 411         ide_hwif_t *hwif = HWIF(drive);
 412
 413         /* We can not enable DMA on both channels simultaneously. */
 414         BUG_ON(dma_channel_active(hwif->hw.dma));
 415         enable_dma(hwif->hw.dma);
 416         return 0;
 417 }
 418
 419 /*
 420  * dma_intr() is the handler for disk read/write DMA interrupts
 421  */
 422 static ide_startstop_t icside_dmaintr(ide_drive_t *drive)
 423 {
 424         unsigned int stat;
 425         int dma_stat;
 426
 427         dma_stat = icside_dma_end(drive);
 428         stat = HWIF(drive)->INB(IDE_STATUS_REG);
 429         if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | DRQ_STAT)) {
 430                 if (!dma_stat) {
 431                         struct request *rq = HWGROUP(drive)->rq;
 432                         int i;
 433
 434                         for (i = rq->nr_sectors; i > 0; ) {
 435                                 i -= rq->current_nr_sectors;
 436                                 DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
 437                         }
 438
 439                         return ide_stopped;
 440                 }
 441                 printk(KERN_ERR "%s: bad DMA status (dma_stat=%x)\n",
 442                        drive->name, dma_stat);
 443         }
 444
 445         return DRIVER(drive)->error(drive, __FUNCTION__, stat);
 446 }
 447
 448 static int
 449 icside_dma_common(ide_drive_t *drive, struct request *rq,
 450                   unsigned int dma_mode)
 451 {
 452         ide_hwif_t *hwif = HWIF(drive);
 453
 454         /*
 455          * We can not enable DMA on both channels.
 456          */
 457         BUG_ON(hwif->sg_dma_active);
 458         BUG_ON(dma_channel_active(hwif->hw.dma));
 459
 460         icside_build_sglist(drive, rq);
 461
 462         /*
 463          * Ensure that we have the right interrupt routed.
 464          */
 465         icside_maskproc(drive, 0);
 466
 467         /*
 468          * Route the DMA signals to the correct interface.
 469          */
 470         outb(hwif->select_data, hwif->config_data);
 471
 472         /*
 473          * Select the correct timing for this drive.
 474          */
 475         set_dma_speed(hwif->hw.dma, drive->drive_data);
 476
 477         /*
 478          * Tell the DMA engine about the SG table and
 479          * data direction.
 480          */
 481         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 482         set_dma_mode(hwif->hw.dma, dma_mode);
 483
 484         drive->waiting_for_dma = 1;
 485
 486         return 0;
 487 }
 488
 489 static int icside_dma_read(ide_drive_t *drive)
 490 {
 491         struct request *rq = HWGROUP(drive)->rq;
 492         task_ioreg_t cmd;
 493
 494         if (icside_dma_common(drive, rq, DMA_MODE_READ))
 495                 return 1;
 496
 497         if (drive->media != ide_disk)
 498                 return 0;
 499
 500         BUG_ON(HWGROUP(drive)->handler != NULL);
 501
 502         /*
 503          * FIX ME to use only ACB ide_task_t args Struct
 504          */
 505 #if 0
 506         {
 507                 ide_task_t *args = rq->special;
 508                 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
 509         }
 510 #else
 511         if (rq->flags & REQ_DRIVE_TASKFILE) {
 512                 ide_task_t *args = rq->special;
 513                 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
 514         } else if (drive->addressing == 1) {
 515                 cmd = WIN_READDMA_EXT;
 516         } else {
 517                 cmd = WIN_READDMA;
 518         }
 519 #endif
 520         /* issue cmd to drive */
 521         ide_execute_command(drive, cmd, icside_dmaintr, 2*WAIT_CMD, NULL);
 522
 523         return icside_dma_begin(drive);
 524 }
 525
 526 static int icside_dma_write(ide_drive_t *drive)
 527 {
 528         struct request *rq = HWGROUP(drive)->rq;
 529         task_ioreg_t cmd;
 530
 531         if (icside_dma_common(drive, rq, DMA_MODE_WRITE))
 532                 return 1;
 533
 534         if (drive->media != ide_disk)
 535                 return 0;
 536
 537         BUG_ON(HWGROUP(drive)->handler != NULL);
 538
 539         /*
 540          * FIX ME to use only ACB ide_task_t args Struct
 541          */
 542 #if 0
 543         {
 544                 ide_task_t *args = rq->special;
 545                 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
 546         }
 547 #else
 548         if (rq->flags & REQ_DRIVE_TASKFILE) {
 549                 ide_task_t *args = rq->special;
 550                 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
 551         } else if (drive->addressing == 1) {
 552                 cmd = WIN_WRITEDMA_EXT;
 553         } else {
 554                 cmd = WIN_WRITEDMA;
 555         }
 556 #endif
 557
 558         /* issue cmd to drive */
 559         ide_execute_command(drive, cmd, icside_dmaintr, 2*WAIT_CMD, NULL);
 560
 561         return icside_dma_begin(drive);
 562 }
 563
 564 static int icside_dma_test_irq(ide_drive_t *drive)
 565 {
 566         ide_hwif_t *hwif = HWIF(drive);
 567         struct icside_state *state = hwif->hwif_data;
 568
 569         return inb(state->irq_port +
 570                    (hwif->channel ?
 571                         ICS_ARCIN_V6_INTRSTAT_2 :
 572                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 573 }
 574
 575 static int icside_dma_verbose(ide_drive_t *drive)
 576 {
 577         printk(", %s (peak %dMB/s)",
 578                 ide_xfer_verbose(drive->current_speed),
 579                 2000 / drive->drive_data);
 580         return 1;
 581 }
 582
 583 static int icside_dma_timeout(ide_drive_t *drive)
 584 {
 585         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 586
 587         if (icside_dma_test_irq(drive))
 588                 return 0;
 589
 590         ide_dump_status(drive, "DMA timeout",
 591                 HWIF(drive)->INB(IDE_STATUS_REG));
 592
 593         return icside_dma_end(drive);
 594 }
 595
 596 static int icside_dma_lostirq(ide_drive_t *drive)
 597 {
 598         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 599         return 1;
 600 }
 601
 602 static int icside_dma_init(ide_hwif_t *hwif)
 603 {
 604         int autodma = 0;
 605
 606 #ifdef CONFIG_IDEDMA_ICS_AUTO
 607         autodma = 1;
 608 #endif
 609
 610         printk("    %s: SG-DMA", hwif->name);
 611
 612         hwif->sg_table = kmalloc(sizeof(struct scatterlist) * NR_ENTRIES,
 613                                  GFP_KERNEL);
 614         if (!hwif->sg_table)
 615                 goto failed;
 616
 617         hwif->atapi_dma         = 1;
 618         hwif->mwdma_mask        = 7; /* MW0..2 */
 619         hwif->swdma_mask        = 7; /* SW0..2 */
 620
 621         hwif->dmatable_cpu      = NULL;
 622         hwif->dmatable_dma      = 0;
 623         hwif->speedproc         = icside_set_speed;
 624         hwif->autodma           = autodma;
 625
 626         hwif->ide_dma_check     = icside_dma_check;
 627         hwif->ide_dma_host_off  = icside_dma_host_off;
 628         hwif->ide_dma_off_quietly = icside_dma_off_quietly;
 629         hwif->ide_dma_host_on   = icside_dma_host_on;
 630         hwif->ide_dma_on        = icside_dma_on;
 631         hwif->ide_dma_read      = icside_dma_read;
 632         hwif->ide_dma_write     = icside_dma_write;
 633         hwif->ide_dma_begin     = icside_dma_begin;
 634         hwif->ide_dma_end       = icside_dma_end;
 635         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 636         hwif->ide_dma_verbose   = icside_dma_verbose;
 637         hwif->ide_dma_timeout   = icside_dma_timeout;
 638         hwif->ide_dma_lostirq   = icside_dma_lostirq;
 639
 640         hwif->drives[0].autodma = hwif->autodma;
 641         hwif->drives[1].autodma = hwif->autodma;
 642
 643         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 644
 645         return 1;
 646
 647 failed:
 648         printk(" disabled, unable to allocate DMA table\n");
 649         return 0;
 650 }
 651
 652 static void icside_dma_exit(ide_hwif_t *hwif)
 653 {
 654         if (hwif->sg_table) {
 655                 kfree(hwif->sg_table);
 656                 hwif->sg_table = NULL;
 657         }
 658 }
 659 #else
 660 #define icside_dma_init(hwif)   (0)
 661 #define icside_dma_exit(hwif)   do { } while (0)
 662 #endif
 663
 664 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 665 {
 666         ide_hwif_t *hwif;
 667         int index;
 668
 669         for (index = 0; index < MAX_HWIFS; ++index) {
 670                 hwif = &ide_hwifs[index];
 671                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 672                         goto found;
 673         }
 674
 675         for (index = 0; index < MAX_HWIFS; ++index) {
 676                 hwif = &ide_hwifs[index];
 677                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 678                         goto found;
 679         }
 680
 681         hwif = NULL;
 682 found:
 683         return hwif;
 684 }
 685
 686 static ide_hwif_t *
 687 icside_setup(unsigned long base, struct cardinfo *info, struct expansion_card *ec)
 688 {
 689         unsigned long port = base + info->dataoffset;
 690         ide_hwif_t *hwif;
 691
 692         hwif = icside_find_hwif(base);
 693         if (hwif) {
 694                 int i;
 695
 696                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 697
 698                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 699                         hwif->hw.io_ports[i] = port;
 700                         hwif->io_ports[i] = port;
 701                         port += 1 << info->stepping;
 702                 }
 703                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
 704                 hwif->io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
 705                 hwif->hw.irq  = ec->irq;
 706                 hwif->irq     = ec->irq;
 707                 hwif->noprobe = 0;
 708                 hwif->chipset = ide_acorn;
 709                 hwif->gendev.parent = &ec->dev;
 710         }
 711
 712         return hwif;
 713 }
 714
 715 static int __init
 716 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 717 {
 718         unsigned long slot_port;
 719         ide_hwif_t *hwif;
 720
 721         slot_port = ecard_address(ec, ECARD_MEMC, 0);
 722
 723         state->irq_port = slot_port;
 724
 725         ec->irqaddr  = (unsigned char *)ioaddr(slot_port + ICS_ARCIN_V5_INTRSTAT);
 726         ec->irqmask  = 1;
 727         ec->irq_data = state;
 728         ec->ops      = &icside_ops_arcin_v5;
 729
 730         /*
 731          * Be on the safe side - disable interrupts
 732          */
 733         inb(slot_port + ICS_ARCIN_V5_INTROFFSET);
 734
 735         hwif = icside_setup(slot_port, &icside_cardinfo_v5, ec);
 736
 737         state->hwif[0] = hwif;
 738
 739         return hwif ? 0 : -ENODEV;
 740 }
 741
 742 static int __init
 743 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 744 {
 745         unsigned long slot_port, port;
 746         ide_hwif_t *hwif, *mate;
 747         unsigned int sel = 0;
 748
 749         slot_port = ecard_address(ec, ECARD_IOC, ECARD_FAST);
 750         port      = ecard_address(ec, ECARD_EASI, ECARD_FAST);
 751
 752         if (port == 0)
 753                 port = slot_port;
 754         else
 755                 sel = 1 << 5;
 756
 757         outb(sel, slot_port);
 758
 759         /*
 760          * Be on the safe side - disable interrupts
 761          */
 762         inb(port + ICS_ARCIN_V6_INTROFFSET_1);
 763         inb(port + ICS_ARCIN_V6_INTROFFSET_2);
 764
 765         /*
 766          * Find and register the interfaces.
 767          */
 768         hwif = icside_setup(port, &icside_cardinfo_v6_1, ec);
 769         mate = icside_setup(port, &icside_cardinfo_v6_2, ec);
 770
 771         if (!hwif || !mate)
 772                 return -ENODEV;
 773
 774         state->irq_port   = port;
 775         state->slot_port  = slot_port;
 776         state->hwif[0]    = hwif;
 777         state->hwif[1]    = mate;
 778
 779         ec->irq_data      = state;
 780         ec->ops           = &icside_ops_arcin_v6;
 781
 782         hwif->maskproc    = icside_maskproc;
 783         hwif->channel     = 0;
 784         hwif->hwif_data   = state;
 785         hwif->mate        = mate;
 786         hwif->serialized  = 1;
 787         hwif->config_data = slot_port;
 788         hwif->select_data = sel;
 789         hwif->hw.dma      = ec->dma;
 790
 791         mate->maskproc    = icside_maskproc;
 792         mate->channel     = 1;
 793         mate->hwif_data   = state;
 794         mate->mate        = hwif;
 795         mate->serialized  = 1;
 796         mate->config_data = slot_port;
 797         mate->select_data = sel | 1;
 798         mate->hw.dma      = ec->dma;
 799
 800         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 801                 icside_dma_init(hwif);
 802                 icside_dma_init(mate);
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int __devinit
 809 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 810 {
 811         struct icside_state *state;
 812         void *idmem;
 813         int ret;
 814
 815         state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
 816         if (!state) {
 817                 ret = -ENOMEM;
 818                 goto out;
 819         }
 820
 821         memset(state, 0, sizeof(state));
 822         state->type     = ICS_TYPE_NOTYPE;
 823         state->dev      = &ec->dev;
 824
 825         idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
 826                         ecard_resource_len(ec, ECARD_RES_IOCFAST));
 827         if (idmem) {
 828                 unsigned int type;
 829
 830                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 831                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 832                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 833                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 834                 iounmap(idmem);
 835
 836                 state->type = type;
 837         }
 838
 839         switch (state->type) {
 840         case ICS_TYPE_A3IN:
 841                 printk(KERN_WARNING "icside: A3IN unsupported\n");
 842                 ret = -ENODEV;
 843                 break;
 844
 845         case ICS_TYPE_A3USER:
 846                 printk(KERN_WARNING "icside: A3USER unsupported\n");
 847                 ret = -ENODEV;
 848                 break;
 849
 850         case ICS_TYPE_V5:
 851                 ret = icside_register_v5(state, ec);
 852                 break;
 853
 854         case ICS_TYPE_V6:
 855                 ret = icside_register_v6(state, ec);
 856                 break;
 857
 858         default:
 859                 printk(KERN_WARNING "icside: unknown interface type\n");
 860                 ret = -ENODEV;
 861                 break;
 862         }
 863
 864         if (ret == 0)
 865                 ecard_set_drvdata(ec, state);
 866         else
 867                 kfree(state);
 868  out:
 869         return ret;
 870 }
 871
 872 static void __devexit icside_remove(struct expansion_card *ec)
 873 {
 874         struct icside_state *state = ecard_get_drvdata(ec);
 875
 876         switch (state->type) {
 877         case ICS_TYPE_V5:
 878                 /* FIXME: tell IDE to stop using the interface */
 879
 880                 /* Disable interrupts */
 881                 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
 882                 break;
 883
 884         case ICS_TYPE_V6:
 885                 /* FIXME: tell IDE to stop using the interface */
 886                 icside_dma_exit(state->hwif[1]);
 887                 icside_dma_exit(state->hwif[0]);
 888
 889                 if (ec->dma != NO_DMA)
 890                         free_dma(ec->dma);
 891
 892                 /* Disable interrupts */
 893                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 894                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 895
 896                 /* Reset the ROM pointer/EASI selection */
 897                 outb(0, state->slot_port);
 898                 break;
 899         }
 900
 901         ecard_set_drvdata(ec, NULL);
 902         ec->ops = NULL;
 903         ec->irq_data = NULL;
 904
 905         kfree(state);
 906 }
 907
 908 static void icside_shutdown(struct expansion_card *ec)
 909 {
 910         struct icside_state *state = ecard_get_drvdata(ec);
 911
 912         switch (state->type) {
 913         case ICS_TYPE_V5:
 914                 /* Disable interrupts */
 915                 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
 916                 break;
 917
 918         case ICS_TYPE_V6:
 919                 /* Disable interrupts */
 920                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 921                 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 922
 923                 /* Reset the ROM pointer/EASI selection */
 924                 outb(0, state->slot_port);
 925                 break;
 926         }
 927 }
 928
 929 static const struct ecard_id icside_ids[] = {
 930         { MANU_ICS,  PROD_ICS_IDE  },
 931         { MANU_ICS2, PROD_ICS2_IDE },
 932         { 0xffff, 0xffff }
 933 };
 934
 935 static struct ecard_driver icside_driver = {
 936         .probe          = icside_probe,
 937         .remove         = __devexit_p(icside_remove),
 938         .shutdown       = icside_shutdown,
 939         .id_table       = icside_ids,
 940         .drv = {
 941                 .name   = "icside",
 942         },
 943 };
 944
 945 static int __init icside_init(void)
 946 {
 947         return ecard_register_driver(&icside_driver);
 948 }
 949
 950 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 951 MODULE_LICENSE("GPL");
 952 MODULE_DESCRIPTION("ICS IDE driver");
 953
 954 module_init(icside_init);