drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.11    March 27, 2002
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  *
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 #include "aec62xx.h"
  20
  21 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
  22 #include <linux/stat.h>
  23 #include <linux/proc_fs.h>
  24
  25 static u8 aec62xx_proc = 0;
  26
  27 #define AEC_MAX_DEVS            5
  28
  29 static struct pci_dev *aec_devs[AEC_MAX_DEVS];
  30 static int n_aec_devs;
  31
  32 #undef DEBUG_AEC_REGS
  33
  34 static int aec62xx_get_info (char *buffer, char **addr, off_t offset, int count)
  35 {
  36         char *p = buffer;
  37         char *chipset_nums[] = {"error", "error", "error", "error",
  38                                 "error", "error", "850UF",   "860",
  39                                  "860R",   "865",  "865R", "error"  };
  40         int len;
  41         int i;
  42
  43         for (i = 0; i < n_aec_devs; i++) {
  44                 struct pci_dev *dev     = aec_devs[i];
  45                 unsigned long iobase = pci_resource_start(dev, 4);
  46                 u8 c0 = 0, c1 = 0, art  = 0;
  47 #ifdef DEBUG_AEC_REGS
  48                 u8 uart                 = 0;
  49 #endif /* DEBUG_AEC_REGS */
  50
  51                 c0 = inb(iobase + 0x02);
  52                 c1 = inb(iobase + 0x0a);
  53
  54                 p += sprintf(p, "\nController: %d\n", i);
  55                 p += sprintf(p, "Chipset: AEC%s\n", chipset_nums[dev->device]);
  56
  57                 p += sprintf(p, "--------------- Primary Channel "
  58                                 "---------------- Secondary Channel "
  59                                 "-------------\n");
  60                 (void) pci_read_config_byte(dev, 0x4a, &art);
  61                 p += sprintf(p, "                %sabled ",
  62                         (art&0x02)?" en":"dis");
  63                 p += sprintf(p, "                        %sabled\n",
  64                         (art&0x04)?" en":"dis");
  65                 p += sprintf(p, "--------------- drive0 --------- drive1 "
  66                                 "-------- drive0 ---------- drive1 ------\n");
  67                 p += sprintf(p, "DMA enabled:    %s              %s ",
  68                         (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ");
  69                 p += sprintf(p, "            %s               %s\n",
  70                         (c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
  71
  72                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
  73                         (void) pci_read_config_byte(dev, 0x54, &art);
  74                         p += sprintf(p, "DMA Mode:       %s(%s)",
  75                                 (c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
  76                                 (art&0x02)?"2":(art&0x01)?"1":"0");
  77                         p += sprintf(p, "          %s(%s)",
  78                                 (c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
  79                                 (art&0x08)?"2":(art&0x04)?"1":"0");
  80                         p += sprintf(p, "         %s(%s)",
  81                                 (c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
  82                                 (art&0x20)?"2":(art&0x10)?"1":"0");
  83                         p += sprintf(p, "           %s(%s)\n",
  84                                 (c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
  85                                 (art&0x80)?"2":(art&0x40)?"1":"0");
  86 #ifdef DEBUG_AEC_REGS
  87                         (void) pci_read_config_byte(dev, 0x40, &art);
  88                         p += sprintf(p, "Active:         0x%02x", art);
  89                         (void) pci_read_config_byte(dev, 0x42, &art);
  90                         p += sprintf(p, "             0x%02x", art);
  91                         (void) pci_read_config_byte(dev, 0x44, &art);
  92                         p += sprintf(p, "            0x%02x", art);
  93                         (void) pci_read_config_byte(dev, 0x46, &art);
  94                         p += sprintf(p, "              0x%02x\n", art);
  95                         (void) pci_read_config_byte(dev, 0x41, &art);
  96                         p += sprintf(p, "Recovery:       0x%02x", art);
  97                         (void) pci_read_config_byte(dev, 0x43, &art);
  98                         p += sprintf(p, "             0x%02x", art);
  99                         (void) pci_read_config_byte(dev, 0x45, &art);
 100                         p += sprintf(p, "            0x%02x", art);
 101                         (void) pci_read_config_byte(dev, 0x47, &art);
 102                         p += sprintf(p, "              0x%02x\n", art);
 103 #endif /* DEBUG_AEC_REGS */
 104                 } else {
 105                         /*
 106                          * case PCI_DEVICE_ID_ARTOP_ATP860:
 107                          * case PCI_DEVICE_ID_ARTOP_ATP860R:
 108                          * case PCI_DEVICE_ID_ARTOP_ATP865:
 109                          * case PCI_DEVICE_ID_ARTOP_ATP865R:
 110                          */
 111                         (void) pci_read_config_byte(dev, 0x44, &art);
 112                         p += sprintf(p, "DMA Mode:       %s(%s)",
 113                                 (c0&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
 114                                 ((art&0x07)==0x07)?"6":
 115                                 ((art&0x06)==0x06)?"5":
 116                                 ((art&0x05)==0x05)?"4":
 117                                 ((art&0x04)==0x04)?"3":
 118                                 ((art&0x03)==0x03)?"2":
 119                                 ((art&0x02)==0x02)?"1":
 120                                 ((art&0x01)==0x01)?"0":"?");
 121                         p += sprintf(p, "          %s(%s)",
 122                                 (c0&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
 123                                 ((art&0x70)==0x70)?"6":
 124                                 ((art&0x60)==0x60)?"5":
 125                                 ((art&0x50)==0x50)?"4":
 126                                 ((art&0x40)==0x40)?"3":
 127                                 ((art&0x30)==0x30)?"2":
 128                                 ((art&0x20)==0x20)?"1":
 129                                 ((art&0x10)==0x10)?"0":"?");
 130                         (void) pci_read_config_byte(dev, 0x45, &art);
 131                         p += sprintf(p, "         %s(%s)",
 132                                 (c1&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
 133                                 ((art&0x07)==0x07)?"6":
 134                                 ((art&0x06)==0x06)?"5":
 135                                 ((art&0x05)==0x05)?"4":
 136                                 ((art&0x04)==0x04)?"3":
 137                                 ((art&0x03)==0x03)?"2":
 138                                 ((art&0x02)==0x02)?"1":
 139                                 ((art&0x01)==0x01)?"0":"?");
 140                         p += sprintf(p, "           %s(%s)\n",
 141                                 (c1&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
 142                                 ((art&0x70)==0x70)?"6":
 143                                 ((art&0x60)==0x60)?"5":
 144                                 ((art&0x50)==0x50)?"4":
 145                                 ((art&0x40)==0x40)?"3":
 146                                 ((art&0x30)==0x30)?"2":
 147                                 ((art&0x20)==0x20)?"1":
 148                                 ((art&0x10)==0x10)?"0":"?");
 149 #ifdef DEBUG_AEC_REGS
 150                         (void) pci_read_config_byte(dev, 0x40, &art);
 151                         p += sprintf(p, "Active:         0x%02x", HIGH_4(art));
 152                         (void) pci_read_config_byte(dev, 0x41, &art);
 153                         p += sprintf(p, "             0x%02x", HIGH_4(art));
 154                         (void) pci_read_config_byte(dev, 0x42, &art);
 155                         p += sprintf(p, "            0x%02x", HIGH_4(art));
 156                         (void) pci_read_config_byte(dev, 0x43, &art);
 157                         p += sprintf(p, "              0x%02x\n", HIGH_4(art));
 158                         (void) pci_read_config_byte(dev, 0x40, &art);
 159                         p += sprintf(p, "Recovery:       0x%02x", LOW_4(art));
 160                         (void) pci_read_config_byte(dev, 0x41, &art);
 161                         p += sprintf(p, "             0x%02x", LOW_4(art));
 162                         (void) pci_read_config_byte(dev, 0x42, &art);
 163                         p += sprintf(p, "            0x%02x", LOW_4(art));
 164                         (void) pci_read_config_byte(dev, 0x43, &art);
 165                         p += sprintf(p, "              0x%02x\n", LOW_4(art));
 166                         (void) pci_read_config_byte(dev, 0x49, &uart);
 167                         p += sprintf(p, "reg49h = 0x%02x ", uart);
 168                         (void) pci_read_config_byte(dev, 0x4a, &uart);
 169                         p += sprintf(p, "reg4ah = 0x%02x\n", uart);
 170 #endif /* DEBUG_AEC_REGS */
 171                 }
 172         }
 173         /* p - buffer must be less than 4k! */
 174         len = (p - buffer) - offset;
 175         *addr = buffer + offset;
 176
 177         return len > count ? count : len;
 178 }
 179 #endif  /* defined(DISPLAY_AEC62xx_TIMINGS) && defined(CONFIG_PROC_FS) */
 180
 181 /*
 182  * TO DO: active tuning and correction of cards without a bios.
 183  */
 184 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 185 {
 186         for ( ; chipset_table->xfer_speed ; chipset_table++)
 187                 if (chipset_table->xfer_speed == speed) {
 188                         return chipset_table->chipset_settings;
 189                 }
 190         return chipset_table->chipset_settings;
 191 }
 192
 193 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 194 {
 195         for ( ; chipset_table->xfer_speed ; chipset_table++)
 196                 if (chipset_table->xfer_speed == speed) {
 197                         return chipset_table->ultra_settings;
 198                 }
 199         return chipset_table->ultra_settings;
 200 }
 201
 202 static u8 aec62xx_ratemask (ide_drive_t *drive)
 203 {
 204         ide_hwif_t *hwif        = HWIF(drive);
 205         u8 mode;
 206
 207         switch(hwif->pci_dev->device) {
 208                 case PCI_DEVICE_ID_ARTOP_ATP865:
 209                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 210 #if 0
 211                         mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
 212 #else
 213                         mode = (hwif->INB(((hwif->channel) ?
 214                                         hwif->mate->dma_status :
 215                                         hwif->dma_status)) & 0x10) ? 4 : 3;
 216 #endif
 217                         break;
 218                 case PCI_DEVICE_ID_ARTOP_ATP860:
 219                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 220                         mode = 2;
 221                         break;
 222                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 223                 default:
 224                         return 1;
 225         }
 226
 227         if (!eighty_ninty_three(drive))
 228                 mode = min(mode, (u8)1);
 229         return mode;
 230 }
 231
 232 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 233 {
 234         ide_hwif_t *hwif        = HWIF(drive);
 235         struct pci_dev *dev     = hwif->pci_dev;
 236         u16 d_conf              = 0;
 237         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 238         u8 ultra = 0, ultra_conf = 0;
 239         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
 240         unsigned long flags;
 241
 242         local_irq_save(flags);
 243         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 244         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 245         SPLIT_BYTE(tmp0,tmp1,tmp2);
 246         MAKE_WORD(d_conf,tmp1,tmp2);
 247         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 248
 249         tmp1 = 0x00;
 250         tmp2 = 0x00;
 251         pci_read_config_byte(dev, 0x54, &ultra);
 252         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 253         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 254         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 255         pci_write_config_byte(dev, 0x54, tmp2);
 256         local_irq_restore(flags);
 257         return(ide_config_drive_speed(drive, speed));
 258 }
 259
 260 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 261 {
 262         ide_hwif_t *hwif        = HWIF(drive);
 263         struct pci_dev *dev     = hwif->pci_dev;
 264         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 265         u8 unit         = (drive->select.b.unit & 0x01);
 266         u8 tmp1 = 0, tmp2 = 0;
 267         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 268         unsigned long flags;
 269
 270         local_irq_save(flags);
 271         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 272         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 273         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 274
 275         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 276         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 277         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 278         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 279         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 280         local_irq_restore(flags);
 281         return(ide_config_drive_speed(drive, speed));
 282 }
 283
 284 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
 285 {
 286         switch (HWIF(drive)->pci_dev->device) {
 287                 case PCI_DEVICE_ID_ARTOP_ATP865:
 288                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 289                 case PCI_DEVICE_ID_ARTOP_ATP860:
 290                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 291                         return ((int) aec6260_tune_chipset(drive, speed));
 292                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 293                         return ((int) aec6210_tune_chipset(drive, speed));
 294                 default:
 295                         return -1;
 296         }
 297 }
 298
 299 static int config_chipset_for_dma (ide_drive_t *drive)
 300 {
 301         u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
 302
 303         if (!(speed))
 304                 return 0;
 305
 306         (void) aec62xx_tune_chipset(drive, speed);
 307         return ide_dma_enable(drive);
 308 }
 309
 310 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
 311 {
 312         u8 speed = 0;
 313         u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 314
 315         switch(pio) {
 316                 case 5:         speed = new_pio; break;
 317                 case 4:         speed = XFER_PIO_4; break;
 318                 case 3:         speed = XFER_PIO_3; break;
 319                 case 2:         speed = XFER_PIO_2; break;
 320                 case 1:         speed = XFER_PIO_1; break;
 321                 default:        speed = XFER_PIO_0; break;
 322         }
 323         (void) aec62xx_tune_chipset(drive, speed);
 324 }
 325
 326 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
 327 {
 328         ide_hwif_t *hwif        = HWIF(drive);
 329         struct hd_driveid *id   = drive->id;
 330
 331         if ((id->capability & 1) && drive->autodma) {
 332                 /* Consult the list of known "bad" drives */
 333                 if (__ide_dma_bad_drive(drive))
 334                         goto fast_ata_pio;
 335                 if (id->field_valid & 4) {
 336                         if (id->dma_ultra & hwif->ultra_mask) {
 337                                 /* Force if Capable UltraDMA */
 338                                 int dma = config_chipset_for_dma(drive);
 339                                 if ((id->field_valid & 2) && !dma)
 340                                         goto try_dma_modes;
 341                         }
 342                 } else if (id->field_valid & 2) {
 343 try_dma_modes:
 344                         if ((id->dma_mword & hwif->mwdma_mask) ||
 345                             (id->dma_1word & hwif->swdma_mask)) {
 346                                 /* Force if Capable regular DMA modes */
 347                                 if (!config_chipset_for_dma(drive))
 348                                         goto no_dma_set;
 349                         }
 350                 } else if (__ide_dma_good_drive(drive) &&
 351                            (id->eide_dma_time < 150)) {
 352                         /* Consult the list of known "good" drives */
 353                         if (!config_chipset_for_dma(drive))
 354                                 goto no_dma_set;
 355                 } else {
 356                         goto fast_ata_pio;
 357                 }
 358                 return hwif->ide_dma_on(drive);
 359         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 360 fast_ata_pio:
 361 no_dma_set:
 362                 aec62xx_tune_drive(drive, 5);
 363                 return hwif->ide_dma_off_quietly(drive);
 364         }
 365         /* IORDY not supported */
 366         return 0;
 367 }
 368
 369 static int aec62xx_irq_timeout (ide_drive_t *drive)
 370 {
 371         ide_hwif_t *hwif        = HWIF(drive);
 372         struct pci_dev *dev     = hwif->pci_dev;
 373
 374         switch(dev->device) {
 375                 case PCI_DEVICE_ID_ARTOP_ATP860:
 376                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 377                 case PCI_DEVICE_ID_ARTOP_ATP865:
 378                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 379                         printk(" AEC62XX time out ");
 380 #if 0
 381                         {
 382                                 int i = 0;
 383                                 u8 reg49h = 0;
 384                                 pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, &reg49h);
 385                                 for (i=0;i<256;i++)
 386                                         pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
 387                                 pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
 388                         }
 389                         return 0;
 390 #endif
 391                 default:
 392                         break;
 393         }
 394 #if 0
 395         {
 396                 ide_hwif_t *hwif        = HWIF(drive);
 397                 struct pci_dev *dev     = hwif->pci_dev;
 398                 u8 tmp1 = 0, tmp2 = 0, mode6 = 0;
 399
 400                 pci_read_config_byte(dev, 0x44, &tmp1);
 401                 pci_read_config_byte(dev, 0x45, &tmp2);
 402                 printk(" AEC6280 r44=%x r45=%x ",tmp1,tmp2);
 403                 mode6 = HWIF(drive)->INB(((hwif->channel) ?
 404                                            hwif->mate->dma_status :
 405                                            hwif->dma_status));
 406                 printk(" AEC6280 133=%x ", (mode6 & 0x10));
 407         }
 408 #endif
 409         return 0;
 410 }
 411
 412 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 413 {
 414         int bus_speed = system_bus_clock();
 415
 416         if (dev->resource[PCI_ROM_RESOURCE].start) {
 417                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 418                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
 419         }
 420
 421 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
 422         aec_devs[n_aec_devs++] = dev;
 423
 424         if (!aec62xx_proc) {
 425                 aec62xx_proc = 1;
 426                 ide_pci_create_host_proc("aec62xx", aec62xx_get_info);
 427         }
 428 #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */
 429
 430         if (bus_speed <= 33)
 431                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 432         else
 433                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 434
 435         return dev->irq;
 436 }
 437
 438 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
 439 {
 440         hwif->autodma = 0;
 441         hwif->tuneproc = &aec62xx_tune_drive;
 442         hwif->speedproc = &aec62xx_tune_chipset;
 443
 444         if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 445                 hwif->serialized = hwif->channel;
 446                 hwif->no_dsc = 1;
 447         }
 448
 449         if (hwif->mate)
 450                 hwif->mate->serialized = hwif->serialized;
 451
 452         if (!hwif->dma_base) {
 453                 hwif->drives[0].autotune = 1;
 454                 hwif->drives[1].autotune = 1;
 455                 return;
 456         }
 457
 458         hwif->ultra_mask = 0x7f;
 459         hwif->mwdma_mask = 0x07;
 460         hwif->swdma_mask = 0x07;
 461
 462         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
 463         hwif->ide_dma_lostirq   = &aec62xx_irq_timeout;
 464         hwif->ide_dma_timeout   = &aec62xx_irq_timeout;
 465         if (!noautodma)
 466                 hwif->autodma = 1;
 467         hwif->drives[0].autodma = hwif->autodma;
 468         hwif->drives[1].autodma = hwif->autodma;
 469 }
 470
 471 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
 472 {
 473         struct pci_dev *dev     = hwif->pci_dev;
 474
 475         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 476                 u8 reg54h = 0;
 477                 unsigned long flags;
 478
 479                 spin_lock_irqsave(&ide_lock, flags);
 480                 pci_read_config_byte(dev, 0x54, &reg54h);
 481                 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
 482                 spin_unlock_irqrestore(&ide_lock, flags);
 483         } else {
 484                 u8 ata66        = 0;
 485                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 486                 if (!(hwif->udma_four))
 487                         hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
 488         }
 489
 490         ide_setup_dma(hwif, dmabase, 8);
 491 }
 492
 493 static void __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
 494 {
 495         ide_setup_pci_device(dev, d);
 496 }
 497
 498 static void __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
 499 {
 500         unsigned long bar4reg = pci_resource_start(dev, 4);
 501
 502         if (inb(bar4reg+2) & 0x10) {
 503                 strcpy(d->name, "AEC6880");
 504                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 505                         strcpy(d->name, "AEC6880R");
 506         } else {
 507                 strcpy(d->name, "AEC6280");
 508                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 509                         strcpy(d->name, "AEC6280R");
 510         }
 511
 512         ide_setup_pci_device(dev, d);
 513 }
 514
 515 /**
 516  *      aec62xx_init_one        -       called when a AEC is found
 517  *      @dev: the aec62xx device
 518  *      @id: the matching pci id
 519  *
 520  *      Called when the PCI registration layer (or the IDE initialization)
 521  *      finds a device matching our IDE device tables.
 522  */
 523
 524 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 525 {
 526         ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
 527
 528         d->init_setup(dev, d);
 529         return 0;
 530 }
 531
 532 static struct pci_device_id aec62xx_pci_tbl[] = {
 533         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 534         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
 535         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
 536         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
 537         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
 538         { 0, },
 539 };
 540 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 541
 542 static struct pci_driver driver = {
 543         .name           = "AEC62xx IDE",
 544         .id_table       = aec62xx_pci_tbl,
 545         .probe          = aec62xx_init_one,
 546 };
 547
 548 static int aec62xx_ide_init(void)
 549 {
 550         return ide_pci_register_driver(&driver);
 551 }
 552
 553 module_init(aec62xx_ide_init);
 554
 555 MODULE_AUTHOR("Andre Hedrick");
 556 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 557 MODULE_LICENSE("GPL");