drivers/ide/pci/aec62xx.h

   1 #ifndef AEC62XX_H
   2 #define AEC62XX_H
   3
   4 #include <linux/config.h>
   5 #include <linux/pci.h>
   6 #include <linux/ide.h>
   7
   8 #define DISPLAY_AEC62XX_TIMINGS
   9
  10 struct chipset_bus_clock_list_entry {
  11         byte            xfer_speed;
  12         byte            chipset_settings;
  13         byte            ultra_settings;
  14 };
  15
  16 struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  17         {       XFER_UDMA_6,    0x31,   0x07    },
  18         {       XFER_UDMA_5,    0x31,   0x06    },
  19         {       XFER_UDMA_4,    0x31,   0x05    },
  20         {       XFER_UDMA_3,    0x31,   0x04    },
  21         {       XFER_UDMA_2,    0x31,   0x03    },
  22         {       XFER_UDMA_1,    0x31,   0x02    },
  23         {       XFER_UDMA_0,    0x31,   0x01    },
  24
  25         {       XFER_MW_DMA_2,  0x31,   0x00    },
  26         {       XFER_MW_DMA_1,  0x31,   0x00    },
  27         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  28         {       XFER_PIO_4,     0x31,   0x00    },
  29         {       XFER_PIO_3,     0x33,   0x00    },
  30         {       XFER_PIO_2,     0x08,   0x00    },
  31         {       XFER_PIO_1,     0x0a,   0x00    },
  32         {       XFER_PIO_0,     0x00,   0x00    },
  33         {       0,              0x00,   0x00    }
  34 };
  35
  36 struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  37         {       XFER_UDMA_6,    0x41,   0x06    },
  38         {       XFER_UDMA_5,    0x41,   0x05    },
  39         {       XFER_UDMA_4,    0x41,   0x04    },
  40         {       XFER_UDMA_3,    0x41,   0x03    },
  41         {       XFER_UDMA_2,    0x41,   0x02    },
  42         {       XFER_UDMA_1,    0x41,   0x01    },
  43         {       XFER_UDMA_0,    0x41,   0x01    },
  44
  45         {       XFER_MW_DMA_2,  0x41,   0x00    },
  46         {       XFER_MW_DMA_1,  0x42,   0x00    },
  47         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  48         {       XFER_PIO_4,     0x41,   0x00    },
  49         {       XFER_PIO_3,     0x43,   0x00    },
  50         {       XFER_PIO_2,     0x78,   0x00    },
  51         {       XFER_PIO_1,     0x7a,   0x00    },
  52         {       XFER_PIO_0,     0x70,   0x00    },
  53         {       0,              0x00,   0x00    }
  54 };
  55
  56
  57 #ifndef HIGH_4
  58 #define HIGH_4(H)               ((H)=(H>>4))
  59 #endif
  60 #ifndef LOW_4
  61 #define LOW_4(L)                ((L)=(L-((L>>4)<<4)))
  62 #endif
  63 #ifndef SPLIT_BYTE
  64 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
  65 #endif
  66 #ifndef MAKE_WORD
  67 #define MAKE_WORD(W,HB,LB)      ((W)=((HB<<8)+LB))
  68 #endif
  69
  70 #define BUSCLOCK(D)     \
  71         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  72
  73 static void init_setup_aec6x80(struct pci_dev *, ide_pci_device_t *);
  74 static void init_setup_aec62xx(struct pci_dev *, ide_pci_device_t *);
  75 static unsigned int init_chipset_aec62xx(struct pci_dev *, const char *);
  76 static void init_hwif_aec62xx(ide_hwif_t *);
  77 static void init_dma_aec62xx(ide_hwif_t *, unsigned long);
  78
  79 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
  80         {       /* 0 */
  81                 .name           = "AEC6210",
  82                 .init_setup     = init_setup_aec62xx,
  83                 .init_chipset   = init_chipset_aec62xx,
  84                 .init_hwif      = init_hwif_aec62xx,
  85                 .init_dma       = init_dma_aec62xx,
  86                 .channels       = 2,
  87                 .autodma        = AUTODMA,
  88                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
  89                 .bootable       = OFF_BOARD,
  90         },{     /* 1 */
  91                 .name           = "AEC6260",
  92                 .init_setup     = init_setup_aec62xx,
  93                 .init_chipset   = init_chipset_aec62xx,
  94                 .init_hwif      = init_hwif_aec62xx,
  95                 .init_dma       = init_dma_aec62xx,
  96                 .channels       = 2,
  97                 .autodma        = NOAUTODMA,
  98                 .bootable       = OFF_BOARD,
  99         },{     /* 2 */
 100                 .name           = "AEC6260R",
 101                 .init_setup     = init_setup_aec62xx,
 102                 .init_chipset   = init_chipset_aec62xx,
 103                 .init_hwif      = init_hwif_aec62xx,
 104                 .init_dma       = init_dma_aec62xx,
 105                 .channels       = 2,
 106                 .autodma        = AUTODMA,
 107                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 108                 .bootable       = NEVER_BOARD,
 109         },{     /* 3 */
 110                 .name           = "AEC6X80",
 111                 .init_setup     = init_setup_aec6x80,
 112                 .init_chipset   = init_chipset_aec62xx,
 113                 .init_hwif      = init_hwif_aec62xx,
 114                 .init_dma       = init_dma_aec62xx,
 115                 .channels       = 2,
 116                 .autodma        = AUTODMA,
 117                 .bootable       = OFF_BOARD,
 118         },{     /* 4 */
 119                 .name           = "AEC6X80R",
 120                 .init_setup     = init_setup_aec6x80,
 121                 .init_chipset   = init_chipset_aec62xx,
 122                 .init_hwif      = init_hwif_aec62xx,
 123                 .init_dma       = init_dma_aec62xx,
 124                 .channels       = 2,
 125                 .autodma        = AUTODMA,
 126                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 127                 .bootable       = OFF_BOARD,
 128         }
 129 };
 130
 131 #endif /* AEC62XX_H */