2 * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
4 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
5 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
7 * CYPRESS CY82C693 chipset IDE controller
9 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
10 * Writing the driver was quite simple, since most of the job is
11 * done by the generic pci-ide support.
12 * The hard part was finding the CY82C693's datasheet on Cypress's
13 * web page :-(. But Altavista solved this problem :-).
17 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
18 * a large and fast disk - the results look great, so I'd say the
19 * driver is working fine :-)
20 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
21 * - this is my first linux driver, so there's probably a lot of room
22 * for optimizations and bug fixing, so feel free to do it.
23 * - use idebus=xx parameter to set PCI bus speed - needed to calc
24 * timings for PIO modes (default will be 40)
25 * - if using PIO mode it's a good idea to set the PIO mode and
26 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
27 * - I had some problems with my IBM DHEA with PIO modes < 2
28 * (lost interrupts) ?????
29 * - first tests with DMA look okay, they seem to work, but there is a
30 * problem with sound - the BusMaster IDE TimeOut should fixed this
33 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
34 * ASK@1999-01-23: v0.33 made a few minor code clean ups
35 * removed DMA clock speed setting by default
37 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
38 * added support to set DMA Controller Clock Speed
39 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
41 * ASK@1998-10-29: v0.3 added support to set DMA modes
42 * ASK@1998-10-28: v0.2 added support to set PIO modes
43 * ASK@1998-10-27: v0.1 first version - chipset detection
47 #include <linux/config.h>
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/delay.h>
52 #include <linux/ide.h>
53 #include <linux/init.h>
60 * calc clocks using bus_speed
61 * returns (rounded up) time in bus clocks for time in ns
63 static int calc_clk (int time, int bus_speed)
67 clocks = (time*bus_speed+999)/1000 -1;
79 * compute the values for the clock registers for PIO
80 * mode and pci_clk [MHz] speed
82 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
83 * for mode 3 and 4 drives 8 and 16-bit timings are the same
86 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
89 int bus_speed = system_bus_clock(); /* get speed of PCI bus */
91 /* we don't check against CY82C693's min and max speed,
92 * so you can play with the idebus=xx parameter
95 if (pio > CY82C693_MAX_PIO)
96 pio = CY82C693_MAX_PIO;
98 /* let's calc the address setup time clocks */
99 p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
101 /* let's calc the active and recovery time clocks */
102 clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
104 /* calc recovery timing */
105 clk2 = ide_pio_timings[pio].cycle_time -
106 ide_pio_timings[pio].active_time -
107 ide_pio_timings[pio].setup_time;
109 clk2 = calc_clk(clk2, bus_speed);
111 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
113 /* note: we use the same values for 16bit IOR and IOW
114 * those are all the same, since I don't have other
115 * timings than those from ide-lib.c
118 p_pclk->time_16r = (u8)clk1;
119 p_pclk->time_16w = (u8)clk1;
121 /* what are good values for 8bit ?? */
122 p_pclk->time_8 = (u8)clk1;
126 * set DMA mode a specific channel for CY82C693
129 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
131 u8 index = 0, data = 0;
133 if (mode>2) /* make sure we set a valid mode */
136 if (mode > drive->id->tDMA) /* to be absolutly sure we have a valid mode */
137 mode = drive->id->tDMA;
139 index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
141 #if CY82C693_DEBUG_LOGS
142 /* for debug let's show the previous values */
144 HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
145 data = HWIF(drive)->INB(CY82_DATA_PORT);
147 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
148 drive->name, HWIF(drive)->channel, drive->select.b.unit,
149 (data&0x3), ((data>>2)&1));
150 #endif /* CY82C693_DEBUG_LOGS */
152 data = (u8)mode|(u8)(single<<2);
154 HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
155 HWIF(drive)->OUTB(data, CY82_DATA_PORT);
157 #if CY82C693_DEBUG_INFO
158 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
159 drive->name, HWIF(drive)->channel, drive->select.b.unit,
161 #endif /* CY82C693_DEBUG_INFO */
164 * note: below we set the value for Bus Master IDE TimeOut Register
165 * I'm not absolutly sure what this does, but it solved my problem
166 * with IDE DMA and sound, so I now can play sound and work with
167 * my IDE driver at the same time :-)
169 * If you know the correct (best) value for this register please
173 data = BUSMASTER_TIMEOUT;
174 HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
175 HWIF(drive)->OUTB(data, CY82_DATA_PORT);
177 #if CY82C693_DEBUG_INFO
178 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
180 #endif /* CY82C693_DEBUG_INFO */
184 * used to set DMA mode for CY82C693 (single and multi modes)
186 int cy82c693_ide_dma_on (ide_drive_t *drive)
188 struct hd_driveid *id = drive->id;
190 #if CY82C693_DEBUG_INFO
191 printk (KERN_INFO "dma_on: %s\n", drive->name);
192 #endif /* CY82C693_DEBUG_INFO */
195 /* Enable DMA on any drive that has DMA
196 * (multi or single) enabled
198 if (id->field_valid & 2) { /* regular DMA */
201 mmode = id->dma_mword & (id->dma_mword >> 8);
202 smode = id->dma_1word & (id->dma_1word >> 8);
206 cy82c693_dma_enable(drive, (mmode >> 1), 0);
207 } else if (smode != 0) {
209 cy82c693_dma_enable(drive, (smode >> 1), 1);
213 return __ide_dma_on(drive);
217 * tune ide drive - set PIO mode
219 static void cy82c693_tune_drive (ide_drive_t *drive, u8 pio)
221 ide_hwif_t *hwif = HWIF(drive);
222 struct pci_dev *dev = hwif->pci_dev;
224 unsigned int addrCtrl;
226 /* select primary or secondary channel */
227 if (hwif->index > 0) { /* drive is on the secondary channel */
228 dev = pci_find_slot(dev->bus->number, dev->devfn+1);
230 printk(KERN_ERR "%s: tune_drive: "
231 "Cannot find secondary interface!\n",
237 #if CY82C693_DEBUG_LOGS
238 /* for debug let's show the register values */
240 if (drive->select.b.unit == 0) {
242 * get master drive registers
243 * address setup control register
246 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
249 /* now let's get the remaining registers */
250 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
251 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
252 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
255 * set slave drive registers
256 * address setup control register
259 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
264 /* now let's get the remaining registers */
265 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
266 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
267 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
270 printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
271 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
272 drive->name, hwif->channel, drive->select.b.unit,
273 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
274 #endif /* CY82C693_DEBUG_LOGS */
276 /* first let's calc the pio modes */
277 pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
279 #if CY82C693_DEBUG_INFO
280 printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
281 #endif /* CY82C693_DEBUG_INFO */
283 /* let's calc the values for this PIO mode */
284 compute_clocks(pio, &pclk);
286 /* now let's write the clocks registers */
287 if (drive->select.b.unit == 0) {
290 * address setup control register
293 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
296 addrCtrl |= (unsigned int)pclk.address_time;
297 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
299 /* now let's set the remaining registers */
300 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
301 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
302 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
308 * address setup control register
311 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
314 addrCtrl |= ((unsigned int)pclk.address_time<<4);
315 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
317 /* now let's set the remaining registers */
318 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
319 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
320 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
326 #if CY82C693_DEBUG_INFO
327 printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
328 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
329 drive->name, hwif->channel, drive->select.b.unit,
330 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
331 #endif /* CY82C693_DEBUG_INFO */
335 * this function is called during init and is used to setup the cy82c693 chip
337 static unsigned int __init init_chipset_cy82c693(struct pci_dev *dev, const char *name)
339 if (PCI_FUNC(dev->devfn) != 1)
342 #ifdef CY82C693_SETDMA_CLOCK
344 #endif /* CY82C693_SETDMA_CLOCK */
346 /* write info about this verion of the driver */
347 printk(KERN_INFO CY82_VERSION "\n");
349 #ifdef CY82C693_SETDMA_CLOCK
350 /* okay let's set the DMA clock speed */
352 outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
353 data = inb(CY82_DATA_PORT);
355 #if CY82C693_DEBUG_INFO
356 printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
358 #endif /* CY82C693_DEBUG_INFO */
361 * for some reason sometimes the DMA controller
362 * speed is set to ATCLK/2 ???? - we fix this here
364 * note: i don't know what causes this strange behaviour,
365 * but even changing the dma speed doesn't solve it :-(
366 * the ide performance is still only half the normal speed
368 * if anybody knows what goes wrong with my machine, please
374 outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
375 outb(data, CY82_DATA_PORT);
377 #if CY82C693_DEBUG_INFO
378 printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
380 #endif /* CY82C693_DEBUG_INFO */
382 #endif /* CY82C693_SETDMA_CLOCK */
387 * the init function - called for each ide channel once
389 static void __init init_hwif_cy82c693(ide_hwif_t *hwif)
393 hwif->chipset = ide_cy82c693;
394 hwif->tuneproc = &cy82c693_tune_drive;
396 if (!hwif->dma_base) {
397 hwif->drives[0].autotune = 1;
398 hwif->drives[1].autotune = 1;
403 hwif->mwdma_mask = 0x04;
404 hwif->swdma_mask = 0x04;
406 hwif->ide_dma_on = &cy82c693_ide_dma_on;
409 hwif->drives[0].autodma = hwif->autodma;
410 hwif->drives[1].autodma = hwif->autodma;
413 static __initdata ide_hwif_t *primary;
415 void __init init_iops_cy82c693(ide_hwif_t *hwif)
417 if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
420 hwif->mate = primary;
425 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
427 ide_pci_device_t *d = &cy82c693_chipsets[id->driver_data];
428 struct pci_dev *dev2;
430 /* CY82C693 is more than only a IDE controller.
431 Function 1 is primary IDE channel, function 2 - secondary. */
432 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
433 PCI_FUNC(dev->devfn) == 1) {
434 dev2 = pci_find_slot(dev->bus->number, dev->devfn + 1);
435 ide_setup_pci_devices(dev, dev2, d);
440 static struct pci_device_id cy82c693_pci_tbl[] = {
441 { PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
444 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
446 static struct pci_driver driver = {
447 .name = "Cypress_IDE",
448 .id_table = cy82c693_pci_tbl,
449 .probe = cy82c693_init_one,
452 static int cy82c693_ide_init(void)
454 return ide_pci_register_driver(&driver);
457 module_init(cy82c693_ide_init);
459 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
460 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
461 MODULE_LICENSE("GPL");