drivers/ide/pci/hpt34x.c

   1 /*
   2  * linux/drivers/ide/pci/hpt34x.c               Version 0.40    Sept 10, 2002
   3  *
   4  * Copyright (C) 1998-2000      Andre Hedrick <andre@linux-ide.org>
   5  * May be copied or modified under the terms of the GNU General Public License
   6  *
   7  *
   8  * 00:12.0 Unknown mass storage controller:
   9  * Triones Technologies, Inc.
  10  * Unknown device 0003 (rev 01)
  11  *
  12  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
  13  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
  14  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
  15  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
  16  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
  17  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
  18  *
  19  * ide-pci.c reference
  20  *
  21  * Since there are two cards that report almost identically,
  22  * the only discernable difference is the values reported in pcicmd.
  23  * Booting-BIOS card or HPT363 :: pcicmd == 0x07
  24  * Non-bootable card or HPT343 :: pcicmd == 0x05
  25  */
  26
  27 #include <linux/config.h>
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/kernel.h>
  31 #include <linux/delay.h>
  32 #include <linux/timer.h>
  33 #include <linux/mm.h>
  34 #include <linux/ioport.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/hdreg.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/pci.h>
  39 #include <linux/init.h>
  40 #include <linux/ide.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44
  45 #include "hpt34x.h"
  46
  47 static u8 hpt34x_ratemask (ide_drive_t *drive)
  48 {
  49         return 1;
  50 }
  51
  52 static void hpt34x_clear_chipset (ide_drive_t *drive)
  53 {
  54         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  55         u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
  56
  57         pci_read_config_dword(dev, 0x44, &reg1);
  58         pci_read_config_dword(dev, 0x48, &reg2);
  59         tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
  60         tmp2 = (reg2 & ~(0x11 << drive->dn));
  61         pci_write_config_dword(dev, 0x44, tmp1);
  62         pci_write_config_dword(dev, 0x48, tmp2);
  63 }
  64
  65 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
  66 {
  67         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  68         u8 speed        = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
  69         u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
  70         u8                      hi_speed, lo_speed;
  71
  72         SPLIT_BYTE(speed, hi_speed, lo_speed);
  73
  74         if (hi_speed & 7) {
  75                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
  76         } else {
  77                 lo_speed <<= 5;
  78                 lo_speed >>= 5;
  79         }
  80
  81         pci_read_config_dword(dev, 0x44, &reg1);
  82         pci_read_config_dword(dev, 0x48, &reg2);
  83         tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
  84         tmp2 = ((hi_speed << drive->dn) | reg2);
  85         pci_write_config_dword(dev, 0x44, tmp1);
  86         pci_write_config_dword(dev, 0x48, tmp2);
  87
  88 #if HPT343_DEBUG_DRIVE_INFO
  89         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
  90                 " (0x%02x 0x%02x)\n",
  91                 drive->name, ide_xfer_verbose(speed),
  92                 drive->dn, reg1, tmp1, reg2, tmp2,
  93                 hi_speed, lo_speed);
  94 #endif /* HPT343_DEBUG_DRIVE_INFO */
  95
  96         return(ide_config_drive_speed(drive, speed));
  97 }
  98
  99 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
 100 {
 101         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
 102         hpt34x_clear_chipset(drive);
 103         (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
 104 }
 105
 106 /*
 107  * This allows the configuration of ide_pci chipset registers
 108  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 109  * after the drive is reported by the OS.  Initially for designed for
 110  * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
 111  */
 112
 113 static int config_chipset_for_dma (ide_drive_t *drive)
 114 {
 115         u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
 116
 117         if (!(speed))
 118                 return 0;
 119
 120         hpt34x_clear_chipset(drive);
 121         (void) hpt34x_tune_chipset(drive, speed);
 122         return ide_dma_enable(drive);
 123 }
 124
 125 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
 126 {
 127         ide_hwif_t *hwif        = HWIF(drive);
 128         struct hd_driveid *id   = drive->id;
 129
 130         drive->init_speed = 0;
 131
 132         if (id && (id->capability & 1) && drive->autodma) {
 133                 /* Consult the list of known "bad" drives */
 134                 if (__ide_dma_bad_drive(drive))
 135                         goto fast_ata_pio;
 136                 if (id->field_valid & 4) {
 137                         if (id->dma_ultra & hwif->ultra_mask) {
 138                                 /* Force if Capable UltraDMA */
 139                                 int dma = config_chipset_for_dma(drive);
 140                                 if ((id->field_valid & 2) && dma)
 141                                         goto try_dma_modes;
 142                         }
 143                 } else if (id->field_valid & 2) {
 144 try_dma_modes:
 145                         if ((id->dma_mword & hwif->mwdma_mask) ||
 146                             (id->dma_1word & hwif->swdma_mask)) {
 147                                 /* Force if Capable regular DMA modes */
 148                                 if (!config_chipset_for_dma(drive))
 149                                         goto no_dma_set;
 150                         }
 151                 } else if (__ide_dma_good_drive(drive) &&
 152                            (id->eide_dma_time < 150)) {
 153                         /* Consult the list of known "good" drives */
 154                         if (!config_chipset_for_dma(drive))
 155                                 goto no_dma_set;
 156                 } else {
 157                         goto fast_ata_pio;
 158                 }
 159 #ifndef CONFIG_HPT34X_AUTODMA
 160                 return hwif->ide_dma_off_quietly(drive);
 161 #else
 162                 return hwif->ide_dma_on(drive);
 163 #endif
 164         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 165 fast_ata_pio:
 166 no_dma_set:
 167                 hpt34x_tune_drive(drive, 255);
 168                 return hwif->ide_dma_off_quietly(drive);
 169         }
 170         /* IORDY not supported */
 171         return 0;
 172 }
 173
 174 /*
 175  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
 176  */
 177 #define HPT34X_PCI_INIT_REG             0x80
 178
 179 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
 180 {
 181         int i = 0;
 182         unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
 183         unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
 184         unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
 185         u16 cmd;
 186         unsigned long flags;
 187
 188         local_irq_save(flags);
 189
 190         pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
 191         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 192
 193         if (cmd & PCI_COMMAND_MEMORY) {
 194                 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
 195                         pci_write_config_byte(dev, PCI_ROM_ADDRESS,
 196                                 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 197                         printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
 198                                 dev->resource[PCI_ROM_RESOURCE].start);
 199                 }
 200                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
 201         } else {
 202                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 203         }
 204
 205         /*
 206          * Since 20-23 can be assigned and are R/W, we correct them.
 207          */
 208         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
 209         for(i=0; i<4; i++) {
 210                 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
 211                 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
 212                 dev->resource[i].flags = IORESOURCE_IO;
 213                 pci_write_config_dword(dev,
 214                                 (PCI_BASE_ADDRESS_0 + (i * 4)),
 215                                 dev->resource[i].start);
 216         }
 217         pci_write_config_word(dev, PCI_COMMAND, cmd);
 218
 219         local_irq_restore(flags);
 220
 221         return dev->irq;
 222 }
 223
 224 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
 225 {
 226         u16 pcicmd = 0;
 227
 228         hwif->autodma = 0;
 229
 230         hwif->tuneproc = &hpt34x_tune_drive;
 231         hwif->speedproc = &hpt34x_tune_chipset;
 232         hwif->no_dsc = 1;
 233         hwif->drives[0].autotune = 1;
 234         hwif->drives[1].autotune = 1;
 235
 236         pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
 237
 238         if (!hwif->dma_base)
 239                 return;
 240
 241         hwif->ultra_mask = 0x07;
 242         hwif->mwdma_mask = 0x07;
 243         hwif->swdma_mask = 0x07;
 244
 245         hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
 246         if (!noautodma)
 247                 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
 248         hwif->drives[0].autodma = hwif->autodma;
 249         hwif->drives[1].autodma = hwif->autodma;
 250 }
 251
 252 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 253 {
 254         ide_pci_device_t *d = &hpt34x_chipsets[id->driver_data];
 255         static char *chipset_names[] = {"HPT343", "HPT345"};
 256         u16 pcicmd = 0;
 257
 258         pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
 259
 260         d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
 261         d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
 262
 263         ide_setup_pci_device(dev, d);
 264         return 0;
 265 }
 266
 267 static struct pci_device_id hpt34x_pci_tbl[] = {
 268         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 269         { 0, },
 270 };
 271 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
 272
 273 static struct pci_driver driver = {
 274         .name           = "HPT34x_IDE",
 275         .id_table       = hpt34x_pci_tbl,
 276         .probe          = hpt34x_init_one,
 277 };
 278
 279 static int hpt34x_ide_init(void)
 280 {
 281         return ide_pci_register_driver(&driver);
 282 }
 283
 284 module_init(hpt34x_ide_init);
 285
 286 MODULE_AUTHOR("Andre Hedrick");
 287 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
 288 MODULE_LICENSE("GPL");