drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  *
   8  * Thanks to HighPoint Technologies for their assistance, and hardware.
   9  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  10  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  11  * development and support.
  12  *
  13  *
  14  * Highpoint have their own driver (source except for the raid part)
  15  * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz
  16  * This may be useful to anyone wanting to work on the mainstream hpt IDE.
  17  *
  18  * Note that final HPT370 support was done by force extraction of GPL.
  19  *
  20  * - add function for getting/setting power status of drive
  21  * - the HPT370's state machine can get confused. reset it before each dma
  22  *   xfer to prevent that from happening.
  23  * - reset state engine whenever we get an error.
  24  * - check for busmaster state at end of dma.
  25  * - use new highpoint timings.
  26  * - detect bus speed using highpoint register.
  27  * - use pll if we don't have a clock table. added a 66MHz table that's
  28  *   just 2x the 33MHz table.
  29  * - removed turnaround. NOTE: we never want to switch between pll and
  30  *   pci clocks as the chip can glitch in those cases. the highpoint
  31  *   approved workaround slows everything down too much to be useful. in
  32  *   addition, we would have to serialize access to each chip.
  33  *      Adrian Sun <a.sun@sun.com>
  34  *
  35  * add drive timings for 66MHz PCI bus,
  36  * fix ATA Cable signal detection, fix incorrect /proc info
  37  * add /proc display for per-drive PIO/DMA/UDMA mode and
  38  * per-channel ATA-33/66 Cable detect.
  39  *      Duncan Laurie <void@sun.com>
  40  *
  41  * fixup /proc output for multiple controllers
  42  *      Tim Hockin <thockin@sun.com>
  43  *
  44  * On hpt366:
  45  * Reset the hpt366 on error, reset on dma
  46  * Fix disabling Fast Interrupt hpt366.
  47  *      Mike Waychison <crlf@sun.com>
  48  *
  49  * Added support for 372N clocking and clock switching. The 372N needs
  50  * different clocks on read/write. This requires overloading rw_disk and
  51  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  52  * keeping me sane.
  53  *              Alan Cox <alan@redhat.com>
  54  *
  55  */
  56
  57
  58 #include <linux/config.h>
  59 #include <linux/types.h>
  60 #include <linux/module.h>
  61 #include <linux/kernel.h>
  62 #include <linux/delay.h>
  63 #include <linux/timer.h>
  64 #include <linux/mm.h>
  65 #include <linux/ioport.h>
  66 #include <linux/blkdev.h>
  67 #include <linux/hdreg.h>
  68
  69 #include <linux/interrupt.h>
  70 #include <linux/pci.h>
  71 #include <linux/init.h>
  72 #include <linux/ide.h>
  73
  74 #include <asm/uaccess.h>
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77
  78 #include "hpt366.h"
  79
  80 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  81 #include <linux/stat.h>
  82 #include <linux/proc_fs.h>
  83 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
  84
  85 static unsigned int hpt_revision(struct pci_dev *dev);
  86 static unsigned int hpt_minimum_revision(struct pci_dev *dev, int revision);
  87
  88 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  89
  90 static u8 hpt366_proc = 0;
  91 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
  92 static int n_hpt_devs;
  93
  94 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
  95 {
  96         char *p = buffer;
  97         char *chipset_nums[] = {"366", "366",  "368",
  98                                 "370", "370A", "372",
  99                                 "302", "371",  "374" };
 100         int i, len;
 101
 102         p += sprintf(p, "\n                             "
 103                 "HighPoint HPT366/368/370/372/374\n");
 104         for (i = 0; i < n_hpt_devs; i++) {
 105                 struct pci_dev *dev = hpt_devs[i];
 106                 unsigned long iobase = dev->resource[4].start;
 107                 u32 class_rev = hpt_revision(dev);
 108                 u8 c0, c1;
 109
 110                 p += sprintf(p, "\nController: %d\n", i);
 111                 if(class_rev < 9)
 112                         p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]);
 113                 else
 114                         p += sprintf(p, "Chipset: HPT revision %d\n", class_rev);
 115                 p += sprintf(p, "--------------- Primary Channel "
 116                                 "--------------- Secondary Channel "
 117                                 "--------------\n");
 118
 119                 /* get the bus master status registers */
 120                 c0 = inb(iobase + 0x2);
 121                 c1 = inb(iobase + 0xa);
 122                 p += sprintf(p, "Enabled:        %s"
 123                                 "                             %s\n",
 124                         (c0 & 0x80) ? "no" : "yes",
 125                         (c1 & 0x80) ? "no" : "yes");
 126 #if 0
 127                 if (hpt_minimum_revision(dev, 3)) {
 128                         u8 cbl;
 129                         cbl = inb(iobase + 0x7b);
 130                         outb(cbl | 1, iobase + 0x7b);
 131                         outb(cbl & ~1, iobase + 0x7b);
 132                         cbl = inb(iobase + 0x7a);
 133                         p += sprintf(p, "Cable:          ATA-%d"
 134                                         "                          ATA-%d\n",
 135                                 (cbl & 0x02) ? 33 : 66,
 136                                 (cbl & 0x01) ? 33 : 66);
 137                         p += sprintf(p, "\n");
 138                 }
 139 #endif
 140                 p += sprintf(p, "--------------- drive0 --------- drive1 "
 141                                 "------- drive0 ---------- drive1 -------\n");
 142                 p += sprintf(p, "DMA capable:    %s              %s"
 143                                 "            %s               %s\n",
 144                         (c0 & 0x20) ? "yes" : "no ",
 145                         (c0 & 0x40) ? "yes" : "no ",
 146                         (c1 & 0x20) ? "yes" : "no ",
 147                         (c1 & 0x40) ? "yes" : "no ");
 148
 149                 {
 150                         u8 c2, c3;
 151                         /* older revs don't have these registers mapped
 152                          * into io space */
 153                         pci_read_config_byte(dev, 0x43, &c0);
 154                         pci_read_config_byte(dev, 0x47, &c1);
 155                         pci_read_config_byte(dev, 0x4b, &c2);
 156                         pci_read_config_byte(dev, 0x4f, &c3);
 157
 158                         p += sprintf(p, "Mode:           %s             %s"
 159                                         "           %s              %s\n",
 160                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
 161                                         (c0 & 0x80) ? "PIO " : "off ",
 162                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
 163                                         (c1 & 0x80) ? "PIO " : "off ",
 164                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
 165                                         (c2 & 0x80) ? "PIO " : "off ",
 166                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
 167                                         (c3 & 0x80) ? "PIO " : "off ");
 168                 }
 169         }
 170         p += sprintf(p, "\n");
 171
 172         /* p - buffer must be less than 4k! */
 173         len = (p - buffer) - offset;
 174         *addr = buffer + offset;
 175
 176         return len > count ? count : len;
 177 }
 178 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
 179
 180 /*
 181  *      This wants fixing so that we do everything not by classrev
 182  *      (which breaks on the newest chips) but by creating an
 183  *      enumeration of chip variants and using that
 184  */
 185
 186 static u32 hpt_revision (struct pci_dev *dev)
 187 {
 188         u32 class_rev;
 189         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 190         class_rev &= 0xff;
 191
 192         switch(dev->device) {
 193                 /* Remap new 372N onto 372 */
 194                 case PCI_DEVICE_ID_TTI_HPT372N:
 195                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 196                 case PCI_DEVICE_ID_TTI_HPT374:
 197                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 198                 case PCI_DEVICE_ID_TTI_HPT371:
 199                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 200                 case PCI_DEVICE_ID_TTI_HPT302:
 201                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 202                 case PCI_DEVICE_ID_TTI_HPT372:
 203                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 204                 default:
 205                         break;
 206         }
 207         return class_rev;
 208 }
 209
 210 static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
 211 {
 212         unsigned int class_rev = hpt_revision(dev);
 213         revision--;
 214         return ((int) (class_rev > revision) ? 1 : 0);
 215 }
 216
 217 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 218
 219 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 220 {
 221         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 222         u8 mode                 = 0;
 223
 224         if (hpt_minimum_revision(dev, 8)) {             /* HPT374 */
 225                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 226         } else if (hpt_minimum_revision(dev, 7)) {      /* HPT371 */
 227                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 228         } else if (hpt_minimum_revision(dev, 6)) {      /* HPT302 */
 229                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 230         } else if (hpt_minimum_revision(dev, 5)) {      /* HPT372 */
 231                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 232         } else if (hpt_minimum_revision(dev, 4)) {      /* HPT370A */
 233                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 234         } else if (hpt_minimum_revision(dev, 3)) {      /* HPT370 */
 235                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 236                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 237         } else {                                /* HPT366 and HPT368 */
 238                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 239         }
 240         if (!eighty_ninty_three(drive) && (mode))
 241                 mode = min(mode, (u8)1);
 242         return mode;
 243 }
 244
 245 /*
 246  *      Note for the future; the SATA hpt37x we must set
 247  *      either PIO or UDMA modes 0,4,5
 248  */
 249
 250 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 251 {
 252         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 253         u8 mode                 = hpt3xx_ratemask(drive);
 254
 255         if (drive->media != ide_disk)
 256                 return min(speed, (u8)XFER_PIO_4);
 257
 258         switch(mode) {
 259                 case 0x04:
 260                         speed = min(speed, (u8)XFER_UDMA_6);
 261                         break;
 262                 case 0x03:
 263                         speed = min(speed, (u8)XFER_UDMA_5);
 264                         if (hpt_minimum_revision(dev, 5))
 265                                 break;
 266                         if (check_in_drive_lists(drive, bad_ata100_5))
 267                                 speed = min(speed, (u8)XFER_UDMA_4);
 268                         break;
 269                 case 0x02:
 270                         speed = min(speed, (u8)XFER_UDMA_4);
 271         /*
 272          * CHECK ME, Does this need to be set to 5 ??
 273          */
 274                         if (hpt_minimum_revision(dev, 3))
 275                                 break;
 276                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 277                             (!(HPT366_ALLOW_ATA66_4)))
 278                                 speed = min(speed, (u8)XFER_UDMA_3);
 279                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 280                             (!(HPT366_ALLOW_ATA66_3)))
 281                                 speed = min(speed, (u8)XFER_UDMA_2);
 282                         break;
 283                 case 0x01:
 284                         speed = min(speed, (u8)XFER_UDMA_2);
 285         /*
 286          * CHECK ME, Does this need to be set to 5 ??
 287          */
 288                         if (hpt_minimum_revision(dev, 3))
 289                                 break;
 290                         if (check_in_drive_lists(drive, bad_ata33))
 291                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 292                         break;
 293                 case 0x00:
 294                 default:
 295                         speed = min(speed, (u8)XFER_MW_DMA_2);
 296                         break;
 297         }
 298         return speed;
 299 }
 300
 301 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 302 {
 303         struct hd_driveid *id = drive->id;
 304
 305         if (quirk_drives == list) {
 306                 while (*list)
 307                         if (strstr(id->model, *list++))
 308                                 return 1;
 309         } else {
 310                 while (*list)
 311                         if (!strcmp(*list++,id->model))
 312                                 return 1;
 313         }
 314         return 0;
 315 }
 316
 317 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 318 {
 319         for ( ; chipset_table->xfer_speed ; chipset_table++)
 320                 if (chipset_table->xfer_speed == speed)
 321                         return chipset_table->chipset_settings;
 322         return chipset_table->chipset_settings;
 323 }
 324
 325 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 326 {
 327         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 328         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 329 //      u8 speed                = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 330         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 331         u8 regfast              = (HWIF(drive)->channel) ? 0x55 : 0x51;
 332         u8 drive_fast           = 0;
 333         u32 reg1 = 0, reg2      = 0;
 334
 335         /*
 336          * Disable the "fast interrupt" prediction.
 337          */
 338         pci_read_config_byte(dev, regfast, &drive_fast);
 339 #if 0
 340         if (drive_fast & 0x02)
 341                 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
 342 #else
 343         if (drive_fast & 0x80)
 344                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 345 #endif
 346
 347         reg2 = pci_bus_clock_list(speed,
 348                 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
 349         /*
 350          * Disable on-chip PIO FIFO/buffer
 351          *  (to avoid problems handling I/O errors later)
 352          */
 353         pci_read_config_dword(dev, regtime, &reg1);
 354         if (speed >= XFER_MW_DMA_0) {
 355                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 356         } else {
 357                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 358         }
 359         reg2 &= ~0x80000000;
 360
 361         pci_write_config_dword(dev, regtime, reg2);
 362
 363         return ide_config_drive_speed(drive, speed);
 364 }
 365
 366 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 367 {
 368         struct pci_dev *dev = HWIF(drive)->pci_dev;
 369         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 370 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 371         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 372         u8 drive_pci    = 0x40 + (drive->dn * 4);
 373         u8 new_fast     = 0, drive_fast = 0;
 374         u32 list_conf   = 0, drive_conf = 0;
 375         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 376
 377         /*
 378          * Disable the "fast interrupt" prediction.
 379          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 380          */
 381         pci_read_config_byte(dev, regfast, &drive_fast);
 382         new_fast = drive_fast;
 383         if (new_fast & 0x02)
 384                 new_fast &= ~0x02;
 385
 386 #ifdef HPT_DELAY_INTERRUPT
 387         if (new_fast & 0x01)
 388                 new_fast &= ~0x01;
 389 #else
 390         if ((new_fast & 0x01) == 0)
 391                 new_fast |= 0x01;
 392 #endif
 393         if (new_fast != drive_fast)
 394                 pci_write_config_byte(dev, regfast, new_fast);
 395
 396         list_conf = pci_bus_clock_list(speed,
 397                                        (struct chipset_bus_clock_list_entry *)
 398                                        pci_get_drvdata(dev));
 399
 400         pci_read_config_dword(dev, drive_pci, &drive_conf);
 401         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 402
 403         if (speed < XFER_MW_DMA_0) {
 404                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 405         }
 406
 407         pci_write_config_dword(dev, drive_pci, list_conf);
 408
 409         return ide_config_drive_speed(drive, speed);
 410 }
 411
 412 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 413 {
 414         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 415         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 416 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 417         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 418         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 419         u32 list_conf   = 0, drive_conf = 0;
 420         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 421
 422         /*
 423          * Disable the "fast interrupt" prediction.
 424          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 425          */
 426         pci_read_config_byte(dev, regfast, &drive_fast);
 427         drive_fast &= ~0x07;
 428         pci_write_config_byte(dev, regfast, drive_fast);
 429
 430         list_conf = pci_bus_clock_list(speed,
 431                         (struct chipset_bus_clock_list_entry *)
 432                                         pci_get_drvdata(dev));
 433         pci_read_config_dword(dev, drive_pci, &drive_conf);
 434         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 435         if (speed < XFER_MW_DMA_0)
 436                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 437         pci_write_config_dword(dev, drive_pci, list_conf);
 438
 439         return ide_config_drive_speed(drive, speed);
 440 }
 441
 442 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 443 {
 444         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 445
 446         if (hpt_minimum_revision(dev, 8))
 447                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 448 #if 0
 449         else if (hpt_minimum_revision(dev, 7))
 450                 hpt371_tune_chipset(drive, speed);
 451         else if (hpt_minimum_revision(dev, 6))
 452                 hpt302_tune_chipset(drive, speed);
 453 #endif
 454         else if (hpt_minimum_revision(dev, 5))
 455                 return hpt372_tune_chipset(drive, speed);
 456         else if (hpt_minimum_revision(dev, 3))
 457                 return hpt370_tune_chipset(drive, speed);
 458         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 459                 return hpt36x_tune_chipset(drive, speed);
 460 }
 461
 462 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 463 {
 464         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 465         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 466 }
 467
 468 /*
 469  * This allows the configuration of ide_pci chipset registers
 470  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 471  * after the drive is reported by the OS.  Initially for designed for
 472  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 473  *
 474  * check_in_drive_lists(drive, bad_ata66_4)
 475  * check_in_drive_lists(drive, bad_ata66_3)
 476  * check_in_drive_lists(drive, bad_ata33)
 477  *
 478  */
 479 static int config_chipset_for_dma (ide_drive_t *drive)
 480 {
 481         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 482
 483         if (!speed)
 484                 return 0;
 485
 486         /* If we don't have any timings we can't do a lot */
 487         if (pci_get_drvdata(HWIF(drive)->pci_dev) == NULL)
 488                 return 0;
 489
 490         (void) hpt3xx_tune_chipset(drive, speed);
 491         return ide_dma_enable(drive);
 492 }
 493
 494 static int hpt3xx_quirkproc (ide_drive_t *drive)
 495 {
 496         return ((int) check_in_drive_lists(drive, quirk_drives));
 497 }
 498
 499 static void hpt3xx_intrproc (ide_drive_t *drive)
 500 {
 501         ide_hwif_t *hwif = HWIF(drive);
 502
 503         if (drive->quirk_list)
 504                 return;
 505         /* drives in the quirk_list may not like intr setups/cleanups */
 506         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 507 }
 508
 509 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 510 {
 511         struct pci_dev *dev = HWIF(drive)->pci_dev;
 512
 513         if (drive->quirk_list) {
 514                 if (hpt_minimum_revision(dev,3)) {
 515                         u8 reg5a = 0;
 516                         pci_read_config_byte(dev, 0x5a, &reg5a);
 517                         if (((reg5a & 0x10) >> 4) != mask)
 518                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 519                 } else {
 520                         if (mask) {
 521                                 disable_irq(HWIF(drive)->irq);
 522                         } else {
 523                                 enable_irq(HWIF(drive)->irq);
 524                         }
 525                 }
 526         } else {
 527                 if (IDE_CONTROL_REG)
 528                         HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
 529                                                  (drive->ctl & ~2),
 530                                                  IDE_CONTROL_REG);
 531         }
 532 }
 533
 534 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 535 {
 536         ide_hwif_t *hwif        = HWIF(drive);
 537         struct hd_driveid *id   = drive->id;
 538
 539         drive->init_speed = 0;
 540
 541         if (id && (id->capability & 1) && drive->autodma) {
 542                 /* Consult the list of known "bad" drives */
 543                 if (__ide_dma_bad_drive(drive))
 544                         goto fast_ata_pio;
 545                 if (id->field_valid & 4) {
 546                         if (id->dma_ultra & hwif->ultra_mask) {
 547                                 /* Force if Capable UltraDMA */
 548                                 int dma = config_chipset_for_dma(drive);
 549                                 if ((id->field_valid & 2) && !dma)
 550                                         goto try_dma_modes;
 551                         }
 552                 } else if (id->field_valid & 2) {
 553 try_dma_modes:
 554                         if (id->dma_mword & hwif->mwdma_mask) {
 555                                 /* Force if Capable regular DMA modes */
 556                                 if (!config_chipset_for_dma(drive))
 557                                         goto no_dma_set;
 558                         }
 559                 } else if (__ide_dma_good_drive(drive) &&
 560                            (id->eide_dma_time < 150)) {
 561                         /* Consult the list of known "good" drives */
 562                         if (!config_chipset_for_dma(drive))
 563                                 goto no_dma_set;
 564                 } else {
 565                         goto fast_ata_pio;
 566                 }
 567                 return hwif->ide_dma_on(drive);
 568         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 569 fast_ata_pio:
 570 no_dma_set:
 571                 hpt3xx_tune_drive(drive, 5);
 572                 return hwif->ide_dma_off_quietly(drive);
 573         }
 574         /* IORDY not supported */
 575         return 0;
 576 }
 577
 578 /*
 579  * This is specific to the HPT366 UDMA bios chipset
 580  * by HighPoint|Triones Technologies, Inc.
 581  */
 582 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 583 {
 584         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 585         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 586
 587         pci_read_config_byte(dev, 0x50, &reg50h);
 588         pci_read_config_byte(dev, 0x52, &reg52h);
 589         pci_read_config_byte(dev, 0x5a, &reg5ah);
 590         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 591                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 592         if (reg5ah & 0x10)
 593                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 594 #if 0
 595         /* how about we flush and reset, mmmkay? */
 596         pci_write_config_byte(dev, 0x51, 0x1F);
 597         /* fall through to a reset */
 598         case ide_dma_begin:
 599         case ide_dma_end:
 600         /* reset the chips state over and over.. */
 601         pci_write_config_byte(dev, 0x51, 0x13);
 602 #endif
 603         return __ide_dma_lostirq(drive);
 604 }
 605
 606 static void hpt370_clear_engine (ide_drive_t *drive)
 607 {
 608         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 609         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 610         udelay(10);
 611 }
 612
 613 static int hpt370_ide_dma_begin (ide_drive_t *drive)
 614 {
 615 #ifdef HPT_RESET_STATE_ENGINE
 616         hpt370_clear_engine(drive);
 617 #endif
 618         return __ide_dma_begin(drive);
 619 }
 620
 621 static int hpt370_ide_dma_end (ide_drive_t *drive)
 622 {
 623         ide_hwif_t *hwif        = HWIF(drive);
 624         u8 dma_stat             = hwif->INB(hwif->dma_status);
 625
 626         if (dma_stat & 0x01) {
 627                 /* wait a little */
 628                 udelay(20);
 629                 dma_stat = hwif->INB(hwif->dma_status);
 630         }
 631         if ((dma_stat & 0x01) != 0)
 632                 /* fallthrough */
 633                 (void) HWIF(drive)->ide_dma_timeout(drive);
 634
 635         return __ide_dma_end(drive);
 636 }
 637
 638 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 639 {
 640         ide_hwif_t *hwif        = HWIF(drive);
 641         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 642         u8 dma_stat = 0, dma_cmd = 0;
 643
 644         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 645         printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 646         hpt370_clear_engine(drive);
 647         /* get dma command mode */
 648         dma_cmd = hwif->INB(hwif->dma_command);
 649         /* stop dma */
 650         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 651         dma_stat = hwif->INB(hwif->dma_status);
 652         /* clear errors */
 653         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 654 }
 655
 656 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 657 {
 658         hpt370_lostirq_timeout(drive);
 659         hpt370_clear_engine(drive);
 660         return __ide_dma_timeout(drive);
 661 }
 662
 663 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 664 {
 665         hpt370_lostirq_timeout(drive);
 666         hpt370_clear_engine(drive);
 667         return __ide_dma_lostirq(drive);
 668 }
 669
 670 /* returns 1 if DMA IRQ issued, 0 otherwise */
 671 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 672 {
 673         ide_hwif_t *hwif        = HWIF(drive);
 674         u16 bfifo               = 0;
 675         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 676         u8 dma_stat;
 677
 678         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 679         if (bfifo & 0x1FF) {
 680 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 681                 return 0;
 682         }
 683
 684         dma_stat = hwif->INB(hwif->dma_status);
 685         /* return 1 if INTR asserted */
 686         if ((dma_stat & 4) == 4)
 687                 return 1;
 688
 689         if (!drive->waiting_for_dma)
 690                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 691                                 drive->name, __FUNCTION__);
 692         return 0;
 693 }
 694
 695 static int hpt374_ide_dma_end (ide_drive_t *drive)
 696 {
 697         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 698         ide_hwif_t *hwif        = HWIF(drive);
 699         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 700         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 701
 702         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 703         pci_read_config_byte(dev, mscreg, &msc_stat);
 704         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 705                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 706         return __ide_dma_end(drive);
 707 }
 708
 709 /**
 710  *      hpt372n_set_clock       -       perform clock switching dance
 711  *      @drive: Drive to switch
 712  *      @mode: Switching mode (0x21 for write, 0x23 otherwise)
 713  *
 714  *      Switch the DPLL clock on the HPT372N devices. This is a
 715  *      right mess.
 716  */
 717
 718 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
 719 {
 720         ide_hwif_t *hwif        = HWIF(drive);
 721
 722         /* FIXME: should we check for DMA active and BUG() */
 723         /* Tristate the bus */
 724         outb(0x80, hwif->dma_base+0x73);
 725         outb(0x80, hwif->dma_base+0x77);
 726
 727         /* Switch clock and reset channels */
 728         outb(mode, hwif->dma_base+0x7B);
 729         outb(0xC0, hwif->dma_base+0x79);
 730
 731         /* Reset state machines */
 732         outb(0x37, hwif->dma_base+0x70);
 733         outb(0x37, hwif->dma_base+0x74);
 734
 735         /* Complete reset */
 736         outb(0x00, hwif->dma_base+0x79);
 737
 738         /* Reconnect channels to bus */
 739         outb(0x00, hwif->dma_base+0x73);
 740         outb(0x00, hwif->dma_base+0x77);
 741 }
 742
 743 /**
 744  *      hpt372n_rw_disk         -       wrapper for I/O
 745  *      @drive: drive for command
 746  *      @rq: block request structure
 747  *      @block: block number
 748  *
 749  *      This is called when a disk I/O is issued to the 372N instead
 750  *      of the default functionality. We need it because of the clock
 751  *      switching
 752  *
 753  */
 754
 755 static ide_startstop_t hpt372n_rw_disk(ide_drive_t *drive, struct request *rq, sector_t block)
 756 {
 757         int wantclock;
 758
 759         if(rq_data_dir(rq) == READ)
 760                 wantclock = 0x21;
 761         else
 762                 wantclock = 0x23;
 763
 764         if(HWIF(drive)->config_data != wantclock)
 765         {
 766                 hpt372n_set_clock(drive, wantclock);
 767                 HWIF(drive)->config_data = wantclock;
 768         }
 769         return __ide_do_rw_disk(drive, rq, block);
 770 }
 771
 772 /*
 773  * Since SUN Cobalt is attempting to do this operation, I should disclose
 774  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 775  * HOTSWAP ATA Infrastructure.
 776  */
 777
 778 static void hpt3xx_reset (ide_drive_t *drive)
 779 {
 780 #if 0
 781         unsigned long high_16   = pci_resource_start(HWIF(drive)->pci_dev, 4);
 782         u8 reset        = (HWIF(drive)->channel) ? 0x80 : 0x40;
 783         u8 reg59h       = 0;
 784
 785         pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
 786         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
 787         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
 788 #endif
 789 }
 790
 791 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 792 {
 793         ide_hwif_t *hwif        = HWIF(drive);
 794         struct pci_dev *dev     = hwif->pci_dev;
 795         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 796         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 797
 798 //      hwif->bus_state = state;
 799
 800         pci_read_config_byte(dev, 0x59, &reg59h);
 801         pci_read_config_byte(dev, state_reg, &regXXh);
 802
 803         if (state) {
 804                 (void) ide_do_reset(drive);
 805                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 806                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 807         } else {
 808                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 809                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 810                 (void) ide_do_reset(drive);
 811         }
 812         return 0;
 813 }
 814
 815 /*
 816  * set/get power state for a drive.
 817  * turning the power off does the following things:
 818  *   1) soft-reset the drive
 819  *   2) tri-states the ide bus
 820  *
 821  * when we turn things back on, we need to re-initialize things.
 822  */
 823 #define TRISTATE_BIT  0x8000
 824 static int hpt370_busproc(ide_drive_t * drive, int state)
 825 {
 826         ide_hwif_t *hwif        = HWIF(drive);
 827         struct pci_dev *dev     = hwif->pci_dev;
 828         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 829         u16 tri_reg;
 830
 831         hwif->bus_state = state;
 832
 833         if (hwif->channel) {
 834                 /* secondary channel */
 835                 tristate = 0x56;
 836                 resetmask = 0x80;
 837         } else {
 838                 /* primary channel */
 839                 tristate = 0x52;
 840                 resetmask = 0x40;
 841         }
 842
 843         /* grab status */
 844         pci_read_config_word(dev, tristate, &tri_reg);
 845         pci_read_config_byte(dev, 0x59, &bus_reg);
 846
 847         /* set the state. we don't set it if we don't need to do so.
 848          * make sure that the drive knows that it has failed if it's off */
 849         switch (state) {
 850         case BUSSTATE_ON:
 851                 hwif->drives[0].failures = 0;
 852                 hwif->drives[1].failures = 0;
 853                 if ((bus_reg & resetmask) == 0)
 854                         return 0;
 855                 tri_reg &= ~TRISTATE_BIT;
 856                 bus_reg &= ~resetmask;
 857                 break;
 858         case BUSSTATE_OFF:
 859                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 860                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 861                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 862                         return 0;
 863                 tri_reg &= ~TRISTATE_BIT;
 864                 bus_reg |= resetmask;
 865                 break;
 866         case BUSSTATE_TRISTATE:
 867                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 868                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 869                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
 870                         return 0;
 871                 tri_reg |= TRISTATE_BIT;
 872                 bus_reg |= resetmask;
 873                 break;
 874         }
 875         pci_write_config_byte(dev, 0x59, bus_reg);
 876         pci_write_config_word(dev, tristate, tri_reg);
 877
 878         return 0;
 879 }
 880
 881 static int __devinit init_hpt37x(struct pci_dev *dev)
 882 {
 883         int adjust, i;
 884         u16 freq;
 885         u32 pll;
 886         u8 reg5bh;
 887         u8 reg5ah = 0;
 888         unsigned long dmabase = pci_resource_start(dev, 4);
 889         u8 did, rid;
 890         int is_372n = 0;
 891
 892         pci_read_config_byte(dev, 0x5a, &reg5ah);
 893         /* interrupt force enable */
 894         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
 895
 896         if(dmabase)
 897         {
 898                 did = inb(dmabase + 0x22);
 899                 rid = inb(dmabase + 0x28);
 900
 901                 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
 902                         is_372n = 1;
 903         }
 904
 905         /*
 906          * default to pci clock. make sure MA15/16 are set to output
 907          * to prevent drives having problems with 40-pin cables. Needed
 908          * for some drives such as IBM-DTLA which will not enter ready
 909          * state on reset when PDIAG is a input.
 910          *
 911          * ToDo: should we set 0x21 when using PLL mode ?
 912          */
 913         pci_write_config_byte(dev, 0x5b, 0x23);
 914
 915         /*
 916          * set up the PLL. we need to adjust it so that it's stable.
 917          * freq = Tpll * 192 / Tpci
 918          *
 919          * Todo. For non x86 should probably check the dword is
 920          * set to 0xABCDExxx indicating the BIOS saved f_CNT
 921          */
 922         pci_read_config_word(dev, 0x78, &freq);
 923         freq &= 0x1FF;
 924
 925         /*
 926          * The 372N uses different PCI clock information and has
 927          * some other complications
 928          *      On PCI33 timing we must clock switch
 929          *      On PCI66 timing we must NOT use the PCI clock
 930          *
 931          * Currently we always set up the PLL for the 372N
 932          */
 933
 934         pci_set_drvdata(dev, NULL);
 935
 936         if(is_372n)
 937         {
 938                 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
 939                 if(freq < 0x55)
 940                         pll = F_LOW_PCI_33;
 941                 else if(freq < 0x70)
 942                         pll = F_LOW_PCI_40;
 943                 else if(freq < 0x7F)
 944                         pll = F_LOW_PCI_50;
 945                 else
 946                         pll = F_LOW_PCI_66;
 947
 948                 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
 949
 950                 /* We always use the pll not the PCI clock on 372N */
 951         }
 952         else
 953         {
 954                 if(freq < 0x9C)
 955                         pll = F_LOW_PCI_33;
 956                 else if(freq < 0xb0)
 957                         pll = F_LOW_PCI_40;
 958                 else if(freq <0xc8)
 959                         pll = F_LOW_PCI_50;
 960                 else
 961                         pll = F_LOW_PCI_66;
 962
 963                 if (pll == F_LOW_PCI_33) {
 964                         if (hpt_minimum_revision(dev,8))
 965                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
 966                         else if (hpt_minimum_revision(dev,5))
 967                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
 968                         else if (hpt_minimum_revision(dev,4))
 969                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
 970                         else
 971                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
 972                         printk("HPT37X: using 33MHz PCI clock\n");
 973                 } else if (pll == F_LOW_PCI_40) {
 974                         /* Unsupported */
 975                 } else if (pll == F_LOW_PCI_50) {
 976                         if (hpt_minimum_revision(dev,8))
 977                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 978                         else if (hpt_minimum_revision(dev,5))
 979                                 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 980                         else if (hpt_minimum_revision(dev,4))
 981                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 982                         else
 983                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 984                         printk("HPT37X: using 50MHz PCI clock\n");
 985                 } else {
 986                         if (hpt_minimum_revision(dev,8))
 987                         {
 988                                 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
 989                         }
 990                         else if (hpt_minimum_revision(dev,5))
 991                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
 992                         else if (hpt_minimum_revision(dev,4))
 993                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
 994                         else
 995                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
 996                         printk("HPT37X: using 66MHz PCI clock\n");
 997                 }
 998         }
 999
1000         /*
1001          * only try the pll if we don't have a table for the clock
1002          * speed that we're running at. NOTE: the internal PLL will
1003          * result in slow reads when using a 33MHz PCI clock. we also
1004          * don't like to use the PLL because it will cause glitches
1005          * on PRST/SRST when the HPT state engine gets reset.
1006          *
1007          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1008          * 372 device so we can get ATA133 support
1009          */
1010         if (pci_get_drvdata(dev))
1011                 goto init_hpt37X_done;
1012
1013         /*
1014          * adjust PLL based upon PCI clock, enable it, and wait for
1015          * stabilization.
1016          */
1017         adjust = 0;
1018         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1019         while (adjust++ < 6) {
1020                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1021                                        pll | 0x100);
1022
1023                 /* wait for clock stabilization */
1024                 for (i = 0; i < 0x50000; i++) {
1025                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1026                         if (reg5bh & 0x80) {
1027                                 /* spin looking for the clock to destabilize */
1028                                 for (i = 0; i < 0x1000; ++i) {
1029                                         pci_read_config_byte(dev, 0x5b,
1030                                                              &reg5bh);
1031                                         if ((reg5bh & 0x80) == 0)
1032                                                 goto pll_recal;
1033                                 }
1034                                 pci_read_config_dword(dev, 0x5c, &pll);
1035                                 pci_write_config_dword(dev, 0x5c,
1036                                                        pll & ~0x100);
1037                                 pci_write_config_byte(dev, 0x5b, 0x21);
1038                                 if (hpt_minimum_revision(dev,8))
1039                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1040                                 else if (hpt_minimum_revision(dev,5))
1041                                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1042                                 else if (hpt_minimum_revision(dev,4))
1043                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1044                                 else
1045                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1046                                 printk("HPT37X: using 50MHz internal PLL\n");
1047                                 goto init_hpt37X_done;
1048                         }
1049                 }
1050 pll_recal:
1051                 if (adjust & 1)
1052                         pll -= (adjust >> 1);
1053                 else
1054                         pll += (adjust >> 1);
1055         }
1056
1057 init_hpt37X_done:
1058         if (!pci_get_drvdata(dev))
1059                 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n",
1060                         is_372n?"N":"", pll, freq);
1061         /* reset state engine */
1062         pci_write_config_byte(dev, 0x50, 0x37);
1063         pci_write_config_byte(dev, 0x54, 0x37);
1064         udelay(100);
1065         return 0;
1066 }
1067
1068 static int __devinit init_hpt366(struct pci_dev *dev)
1069 {
1070         u32 reg1        = 0;
1071         u8 drive_fast   = 0;
1072
1073         /*
1074          * Disable the "fast interrupt" prediction.
1075          */
1076         pci_read_config_byte(dev, 0x51, &drive_fast);
1077         if (drive_fast & 0x80)
1078                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1079         pci_read_config_dword(dev, 0x40, &reg1);
1080
1081         /* detect bus speed by looking at control reg timing: */
1082         switch((reg1 >> 8) & 7) {
1083                 case 5:
1084                         pci_set_drvdata(dev, (void *) forty_base_hpt366);
1085                         break;
1086                 case 9:
1087                         pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1088                         break;
1089                 case 7:
1090                 default:
1091                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1092                         break;
1093         }
1094
1095         if (!pci_get_drvdata(dev))
1096         {
1097                 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1098                 pci_set_drvdata(dev, NULL);
1099         }
1100         return 0;
1101 }
1102
1103 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1104 {
1105         int ret = 0;
1106         u8 test = 0;
1107
1108         if (dev->resource[PCI_ROM_RESOURCE].start)
1109                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1110                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1111
1112         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1113         if (test != (L1_CACHE_BYTES / 4))
1114                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1115                         (L1_CACHE_BYTES / 4));
1116
1117         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1118         if (test != 0x78)
1119                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1120
1121         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1122         if (test != 0x08)
1123                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1124
1125         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1126         if (test != 0x08)
1127                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1128
1129         if (hpt_minimum_revision(dev, 3)) {
1130                 ret = init_hpt37x(dev);
1131         } else {
1132                 ret =init_hpt366(dev);
1133         }
1134         if (ret)
1135                 return ret;
1136
1137 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
1138         hpt_devs[n_hpt_devs++] = dev;
1139
1140         if (!hpt366_proc) {
1141                 hpt366_proc = 1;
1142                 ide_pci_create_host_proc("hpt366", hpt366_get_info);
1143         }
1144 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
1145
1146         return dev->irq;
1147 }
1148
1149 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1150 {
1151         struct pci_dev *dev             = hwif->pci_dev;
1152         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1153         u8 did, rid;
1154         unsigned long dmabase           = hwif->dma_base;
1155         int is_372n = 0;
1156
1157         if(dmabase)
1158         {
1159                 did = inb(dmabase + 0x22);
1160                 rid = inb(dmabase + 0x28);
1161
1162                 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1163                         is_372n = 1;
1164         }
1165
1166         hwif->tuneproc                  = &hpt3xx_tune_drive;
1167         hwif->speedproc                 = &hpt3xx_tune_chipset;
1168         hwif->quirkproc                 = &hpt3xx_quirkproc;
1169         hwif->intrproc                  = &hpt3xx_intrproc;
1170         hwif->maskproc                  = &hpt3xx_maskproc;
1171
1172         if(is_372n)
1173                 hwif->rw_disk = &hpt372n_rw_disk;
1174
1175         /*
1176          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1177          * address lines to access an external eeprom.  To read valid
1178          * cable detect state the pins must be enabled as inputs.
1179          */
1180         if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1181                 /*
1182                  * HPT374 PCI function 1
1183                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1184                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1185                  */
1186                 u16 mcr3, mcr6;
1187                 pci_read_config_word(dev, 0x52, &mcr3);
1188                 pci_read_config_word(dev, 0x56, &mcr6);
1189                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1190                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1191                 /* now read cable id register */
1192                 pci_read_config_byte(dev, 0x5a, &ata66);
1193                 pci_write_config_word(dev, 0x52, mcr3);
1194                 pci_write_config_word(dev, 0x56, mcr6);
1195         } else if (hpt_minimum_revision(dev, 3)) {
1196                 /*
1197                  * HPT370/372 and 374 pcifn 0
1198                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1199                  */
1200                 u8 scr2;
1201                 pci_read_config_byte(dev, 0x5b, &scr2);
1202                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1203                 /* now read cable id register */
1204                 pci_read_config_byte(dev, 0x5a, &ata66);
1205                 pci_write_config_byte(dev, 0x5b, scr2);
1206         } else {
1207                 pci_read_config_byte(dev, 0x5a, &ata66);
1208         }
1209
1210 #ifdef DEBUG
1211         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1212                 ata66, (ata66 & regmask) ? "33" : "66",
1213                 PCI_FUNC(hwif->pci_dev->devfn));
1214 #endif /* DEBUG */
1215
1216 #ifdef HPT_SERIALIZE_IO
1217         /* serialize access to this device */
1218         if (hwif->mate)
1219                 hwif->serialized = hwif->mate->serialized = 1;
1220 #endif
1221
1222         if (hpt_minimum_revision(dev,3)) {
1223                 u8 reg5ah = 0;
1224                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1225                 /*
1226                  * set up ioctl for power status.
1227                  * note: power affects both
1228                  * drives on each channel
1229                  */
1230                 hwif->resetproc = &hpt3xx_reset;
1231                 hwif->busproc   = &hpt370_busproc;
1232 //              hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1233         } else if (hpt_minimum_revision(dev,2)) {
1234                 hwif->resetproc = &hpt3xx_reset;
1235                 hwif->busproc   = &hpt3xx_tristate;
1236         } else {
1237                 hwif->resetproc = &hpt3xx_reset;
1238                 hwif->busproc   = &hpt3xx_tristate;
1239         }
1240
1241         if (!hwif->dma_base) {
1242                 hwif->drives[0].autotune = 1;
1243                 hwif->drives[1].autotune = 1;
1244                 return;
1245         }
1246
1247         hwif->ultra_mask = 0x7f;
1248         hwif->mwdma_mask = 0x07;
1249
1250         if (!(hwif->udma_four))
1251                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1252         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1253
1254         if (hpt_minimum_revision(dev,8)) {
1255                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1256                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1257         } else if (hpt_minimum_revision(dev,5)) {
1258                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1259                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1260         } else if (hpt_minimum_revision(dev,3)) {
1261                 hwif->ide_dma_begin = &hpt370_ide_dma_begin;
1262                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1263                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1264                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1265         } else if (hpt_minimum_revision(dev,2))
1266                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1267         else
1268                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1269
1270         if (!noautodma)
1271                 hwif->autodma = 1;
1272         hwif->drives[0].autodma = hwif->autodma;
1273         hwif->drives[1].autodma = hwif->autodma;
1274 }
1275
1276 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1277 {
1278         u8 masterdma    = 0, slavedma = 0;
1279         u8 dma_new      = 0, dma_old = 0;
1280         u8 primary      = hwif->channel ? 0x4b : 0x43;
1281         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1282         unsigned long flags;
1283
1284         if (!dmabase)
1285                 return;
1286
1287         if(pci_get_drvdata(hwif->pci_dev) == NULL)
1288         {
1289                 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1290                 return;
1291         }
1292
1293         dma_old = hwif->INB(dmabase+2);
1294
1295         local_irq_save(flags);
1296
1297         dma_new = dma_old;
1298         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1299         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1300
1301         if (masterdma & 0x30)   dma_new |= 0x20;
1302         if (slavedma & 0x30)    dma_new |= 0x40;
1303         if (dma_new != dma_old)
1304                 hwif->OUTB(dma_new, dmabase+2);
1305
1306         local_irq_restore(flags);
1307
1308         ide_setup_dma(hwif, dmabase, 8);
1309 }
1310
1311 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1312 {
1313         struct pci_dev *findev = NULL;
1314
1315         if (PCI_FUNC(dev->devfn) & 1)
1316                 return;
1317
1318         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1319                 if ((findev->vendor == dev->vendor) &&
1320                     (findev->device == dev->device) &&
1321                     ((findev->devfn - dev->devfn) == 1) &&
1322                     (PCI_FUNC(findev->devfn) & 1)) {
1323                         if (findev->irq != dev->irq) {
1324                                 /* FIXME: we need a core pci_set_interrupt() */
1325                                 findev->irq = dev->irq;
1326                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1327                                         "fixed.\n", d->name);
1328                         }
1329                         ide_setup_pci_devices(dev, findev, d);
1330                         return;
1331                 }
1332         }
1333         ide_setup_pci_device(dev, d);
1334 }
1335
1336 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1337 {
1338         ide_setup_pci_device(dev, d);
1339 }
1340
1341 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1342 {
1343         struct pci_dev *findev = NULL;
1344         u8 pin1 = 0, pin2 = 0;
1345         unsigned int class_rev;
1346         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1347                                  "HPT370", "HPT370A", "HPT372",
1348                                  "HPT372N" };
1349
1350         if (PCI_FUNC(dev->devfn) & 1)
1351                 return;
1352
1353         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1354         class_rev &= 0xff;
1355
1356         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1357                 class_rev = 6;
1358
1359         if(class_rev <= 6)
1360                 d->name = chipset_names[class_rev];
1361
1362         switch(class_rev) {
1363                 case 6:
1364                 case 5:
1365                 case 4:
1366                 case 3: ide_setup_pci_device(dev, d);
1367                         return;
1368                 default:        break;
1369         }
1370
1371         d->channels = 1;
1372
1373         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1374         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1375                 if ((findev->vendor == dev->vendor) &&
1376                     (findev->device == dev->device) &&
1377                     ((findev->devfn - dev->devfn) == 1) &&
1378                     (PCI_FUNC(findev->devfn) & 1)) {
1379                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1380                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1381                                 d->bootable = ON_BOARD;
1382                                 printk("%s: onboard version of chipset, "
1383                                         "pin1=%d pin2=%d\n", d->name,
1384                                         pin1, pin2);
1385                         }
1386                         ide_setup_pci_devices(dev, findev, d);
1387                         return;
1388                 }
1389         }
1390         ide_setup_pci_device(dev, d);
1391 }
1392
1393
1394 /**
1395  *      hpt366_init_one -       called when an HPT366 is found
1396  *      @dev: the hpt366 device
1397  *      @id: the matching pci id
1398  *
1399  *      Called when the PCI registration layer (or the IDE initialization)
1400  *      finds a device matching our IDE device tables.
1401  */
1402
1403 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1404 {
1405         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1406
1407         d->init_setup(dev, d);
1408         return 0;
1409 }
1410
1411 static struct pci_device_id hpt366_pci_tbl[] = {
1412         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1413         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1414         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1415         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1416         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1417         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1418         { 0, },
1419 };
1420 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1421
1422 static struct pci_driver driver = {
1423         .name           = "HPT366_IDE",
1424         .id_table       = hpt366_pci_tbl,
1425         .probe          = hpt366_init_one,
1426 };
1427
1428 static int hpt366_ide_init(void)
1429 {
1430         return ide_pci_register_driver(&driver);
1431 }
1432
1433 module_init(hpt366_ide_init);
1434
1435 MODULE_AUTHOR("Andre Hedrick");
1436 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1437 MODULE_LICENSE("GPL");