drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.34    Sept 17, 2002
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  *
   7  * Thanks to HighPoint Technologies for their assistance, and hardware.
   8  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
   9  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  10  * development and support.
  11  *
  12  * Note that final HPT370 support was done by force extraction of GPL.
  13  *
  14  * - add function for getting/setting power status of drive
  15  * - the HPT370's state machine can get confused. reset it before each dma
  16  *   xfer to prevent that from happening.
  17  * - reset state engine whenever we get an error.
  18  * - check for busmaster state at end of dma.
  19  * - use new highpoint timings.
  20  * - detect bus speed using highpoint register.
  21  * - use pll if we don't have a clock table. added a 66MHz table that's
  22  *   just 2x the 33MHz table.
  23  * - removed turnaround. NOTE: we never want to switch between pll and
  24  *   pci clocks as the chip can glitch in those cases. the highpoint
  25  *   approved workaround slows everything down too much to be useful. in
  26  *   addition, we would have to serialize access to each chip.
  27  *      Adrian Sun <a.sun@sun.com>
  28  *
  29  * add drive timings for 66MHz PCI bus,
  30  * fix ATA Cable signal detection, fix incorrect /proc info
  31  * add /proc display for per-drive PIO/DMA/UDMA mode and
  32  * per-channel ATA-33/66 Cable detect.
  33  *      Duncan Laurie <void@sun.com>
  34  *
  35  * fixup /proc output for multiple controllers
  36  *      Tim Hockin <thockin@sun.com>
  37  *
  38  * On hpt366:
  39  * Reset the hpt366 on error, reset on dma
  40  * Fix disabling Fast Interrupt hpt366.
  41  *      Mike Waychison <crlf@sun.com>
  42  */
  43
  44
  45 #include <linux/config.h>
  46 #include <linux/types.h>
  47 #include <linux/module.h>
  48 #include <linux/kernel.h>
  49 #include <linux/delay.h>
  50 #include <linux/timer.h>
  51 #include <linux/mm.h>
  52 #include <linux/ioport.h>
  53 #include <linux/blkdev.h>
  54 #include <linux/hdreg.h>
  55
  56 #include <linux/interrupt.h>
  57 #include <linux/pci.h>
  58 #include <linux/init.h>
  59 #include <linux/ide.h>
  60
  61 #include <asm/uaccess.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64
  65 #include "hpt366.h"
  66
  67 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  68 #include <linux/stat.h>
  69 #include <linux/proc_fs.h>
  70 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
  71
  72 static unsigned int hpt_revision(struct pci_dev *dev);
  73 static unsigned int hpt_minimum_revision(struct pci_dev *dev, int revision);
  74
  75 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  76
  77 static u8 hpt366_proc = 0;
  78 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
  79 static int n_hpt_devs;
  80
  81 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
  82 {
  83         char *p = buffer;
  84         char *chipset_nums[] = {"366", "366",  "368",
  85                                 "370", "370A", "372",
  86                                 "302", "371",  "374" };
  87         int i, len;
  88
  89         p += sprintf(p, "\n                             "
  90                 "HighPoint HPT366/368/370/372/374\n");
  91         for (i = 0; i < n_hpt_devs; i++) {
  92                 struct pci_dev *dev = hpt_devs[i];
  93                 unsigned long iobase = dev->resource[4].start;
  94                 u32 class_rev = hpt_revision(dev);
  95                 u8 c0, c1;
  96
  97                 p += sprintf(p, "\nController: %d\n", i);
  98                 p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]);
  99                 p += sprintf(p, "--------------- Primary Channel "
 100                                 "--------------- Secondary Channel "
 101                                 "--------------\n");
 102
 103                 /* get the bus master status registers */
 104                 c0 = inb(iobase + 0x2);
 105                 c1 = inb(iobase + 0xa);
 106                 p += sprintf(p, "Enabled:        %s"
 107                                 "                             %s\n",
 108                         (c0 & 0x80) ? "no" : "yes",
 109                         (c1 & 0x80) ? "no" : "yes");
 110 #if 0
 111                 if (hpt_minimum_revision(dev, 3)) {
 112                         u8 cbl;
 113                         cbl = inb(iobase + 0x7b);
 114                         outb(cbl | 1, iobase + 0x7b);
 115                         outb(cbl & ~1, iobase + 0x7b);
 116                         cbl = inb(iobase + 0x7a);
 117                         p += sprintf(p, "Cable:          ATA-%d"
 118                                         "                          ATA-%d\n",
 119                                 (cbl & 0x02) ? 33 : 66,
 120                                 (cbl & 0x01) ? 33 : 66);
 121                         p += sprintf(p, "\n");
 122                 }
 123 #endif
 124                 p += sprintf(p, "--------------- drive0 --------- drive1 "
 125                                 "------- drive0 ---------- drive1 -------\n");
 126                 p += sprintf(p, "DMA capable:    %s              %s"
 127                                 "            %s               %s\n",
 128                         (c0 & 0x20) ? "yes" : "no ",
 129                         (c0 & 0x40) ? "yes" : "no ",
 130                         (c1 & 0x20) ? "yes" : "no ",
 131                         (c1 & 0x40) ? "yes" : "no ");
 132
 133                 {
 134                         u8 c2, c3;
 135                         /* older revs don't have these registers mapped
 136                          * into io space */
 137                         pci_read_config_byte(dev, 0x43, &c0);
 138                         pci_read_config_byte(dev, 0x47, &c1);
 139                         pci_read_config_byte(dev, 0x4b, &c2);
 140                         pci_read_config_byte(dev, 0x4f, &c3);
 141
 142                         p += sprintf(p, "Mode:           %s             %s"
 143                                         "           %s              %s\n",
 144                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
 145                                         (c0 & 0x80) ? "PIO " : "off ",
 146                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
 147                                         (c1 & 0x80) ? "PIO " : "off ",
 148                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
 149                                         (c2 & 0x80) ? "PIO " : "off ",
 150                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
 151                                         (c3 & 0x80) ? "PIO " : "off ");
 152                 }
 153         }
 154         p += sprintf(p, "\n");
 155
 156         /* p - buffer must be less than 4k! */
 157         len = (p - buffer) - offset;
 158         *addr = buffer + offset;
 159
 160         return len > count ? count : len;
 161 }
 162 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
 163
 164 static u32 hpt_revision (struct pci_dev *dev)
 165 {
 166         u32 class_rev;
 167         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 168         class_rev &= 0xff;
 169
 170         switch(dev->device) {
 171                 case PCI_DEVICE_ID_TTI_HPT374:
 172                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 173                 case PCI_DEVICE_ID_TTI_HPT371:
 174                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 175                 case PCI_DEVICE_ID_TTI_HPT302:
 176                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 177                 case PCI_DEVICE_ID_TTI_HPT372:
 178                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 179                 default:
 180                         break;
 181         }
 182         return class_rev;
 183 }
 184
 185 static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
 186 {
 187         unsigned int class_rev = hpt_revision(dev);
 188         revision--;
 189         return ((int) (class_rev > revision) ? 1 : 0);
 190 }
 191
 192 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 193
 194 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 195 {
 196         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 197         u8 mode                 = 0;
 198
 199         if (hpt_minimum_revision(dev, 8)) {             /* HPT374 */
 200                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 201         } else if (hpt_minimum_revision(dev, 7)) {      /* HPT371 */
 202                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 203         } else if (hpt_minimum_revision(dev, 6)) {      /* HPT302 */
 204                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 205         } else if (hpt_minimum_revision(dev, 5)) {      /* HPT372 */
 206                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 207         } else if (hpt_minimum_revision(dev, 4)) {      /* HPT370A */
 208                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 209         } else if (hpt_minimum_revision(dev, 3)) {      /* HPT370 */
 210                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 211                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 212         } else {                                /* HPT366 and HPT368 */
 213                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 214         }
 215         if (!eighty_ninty_three(drive) && (mode))
 216                 mode = min(mode, (u8)1);
 217         return mode;
 218 }
 219
 220 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 221 {
 222         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 223         u8 mode                 = hpt3xx_ratemask(drive);
 224
 225         if (drive->media != ide_disk)
 226                 return min(speed, (u8)XFER_PIO_4);
 227
 228         switch(mode) {
 229                 case 0x04:
 230                         speed = min(speed, (u8)XFER_UDMA_6);
 231                         break;
 232                 case 0x03:
 233                         speed = min(speed, (u8)XFER_UDMA_5);
 234                         if (hpt_minimum_revision(dev, 5))
 235                                 break;
 236                         if (check_in_drive_lists(drive, bad_ata100_5))
 237                                 speed = min(speed, (u8)XFER_UDMA_4);
 238                         break;
 239                 case 0x02:
 240                         speed = min(speed, (u8)XFER_UDMA_4);
 241         /*
 242          * CHECK ME, Does this need to be set to 5 ??
 243          */
 244                         if (hpt_minimum_revision(dev, 3))
 245                                 break;
 246                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 247                             (!(HPT366_ALLOW_ATA66_4)))
 248                                 speed = min(speed, (u8)XFER_UDMA_3);
 249                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 250                             (!(HPT366_ALLOW_ATA66_3)))
 251                                 speed = min(speed, (u8)XFER_UDMA_2);
 252                         break;
 253                 case 0x01:
 254                         speed = min(speed, (u8)XFER_UDMA_2);
 255         /*
 256          * CHECK ME, Does this need to be set to 5 ??
 257          */
 258                         if (hpt_minimum_revision(dev, 3))
 259                                 break;
 260                         if (check_in_drive_lists(drive, bad_ata33))
 261                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 262                         break;
 263                 case 0x00:
 264                 default:
 265                         speed = min(speed, (u8)XFER_MW_DMA_2);
 266                         break;
 267         }
 268         return speed;
 269 }
 270
 271 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 272 {
 273         struct hd_driveid *id = drive->id;
 274
 275         if (quirk_drives == list) {
 276                 while (*list)
 277                         if (strstr(id->model, *list++))
 278                                 return 1;
 279         } else {
 280                 while (*list)
 281                         if (!strcmp(*list++,id->model))
 282                                 return 1;
 283         }
 284         return 0;
 285 }
 286
 287 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 288 {
 289         for ( ; chipset_table->xfer_speed ; chipset_table++)
 290                 if (chipset_table->xfer_speed == speed)
 291                         return chipset_table->chipset_settings;
 292         return chipset_table->chipset_settings;
 293 }
 294
 295 static void hpt366_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 296 {
 297         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 298         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 299 //      u8 speed                = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 300         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 301         u8 regfast              = (HWIF(drive)->channel) ? 0x55 : 0x51;
 302         u8 drive_fast           = 0;
 303         u32 reg1 = 0, reg2      = 0;
 304
 305         /*
 306          * Disable the "fast interrupt" prediction.
 307          */
 308         pci_read_config_byte(dev, regfast, &drive_fast);
 309 #if 0
 310         if (drive_fast & 0x02)
 311                 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
 312 #else
 313         if (drive_fast & 0x80)
 314                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 315 #endif
 316
 317         reg2 = pci_bus_clock_list(speed,
 318                 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
 319         /*
 320          * Disable on-chip PIO FIFO/buffer
 321          *  (to avoid problems handling I/O errors later)
 322          */
 323         pci_read_config_dword(dev, regtime, &reg1);
 324         if (speed >= XFER_MW_DMA_0) {
 325                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 326         } else {
 327                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 328         }
 329         reg2 &= ~0x80000000;
 330
 331         pci_write_config_dword(dev, regtime, reg2);
 332 }
 333
 334 static void hpt368_tune_chipset (ide_drive_t *drive, u8 speed)
 335 {
 336         hpt366_tune_chipset(drive, speed);
 337 }
 338
 339 static void hpt370_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 340 {
 341         struct pci_dev *dev = HWIF(drive)->pci_dev;
 342         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 343 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 344         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 345         u8 drive_pci    = 0x40 + (drive->dn * 4);
 346         u8 new_fast     = 0, drive_fast = 0;
 347         u32 list_conf   = 0, drive_conf = 0;
 348         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 349
 350         /*
 351          * Disable the "fast interrupt" prediction.
 352          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 353          */
 354         pci_read_config_byte(dev, regfast, &drive_fast);
 355         new_fast = drive_fast;
 356         if (new_fast & 0x02)
 357                 new_fast &= ~0x02;
 358
 359 #ifdef HPT_DELAY_INTERRUPT
 360         if (new_fast & 0x01)
 361                 new_fast &= ~0x01;
 362 #else
 363         if ((new_fast & 0x01) == 0)
 364                 new_fast |= 0x01;
 365 #endif
 366         if (new_fast != drive_fast)
 367                 pci_write_config_byte(dev, regfast, new_fast);
 368
 369         list_conf = pci_bus_clock_list(speed,
 370                                        (struct chipset_bus_clock_list_entry *)
 371                                        pci_get_drvdata(dev));
 372
 373         pci_read_config_dword(dev, drive_pci, &drive_conf);
 374         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 375
 376         if (speed < XFER_MW_DMA_0) {
 377                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 378         }
 379
 380         pci_write_config_dword(dev, drive_pci, list_conf);
 381 }
 382
 383 static void hpt372_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 384 {
 385         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 386         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 387 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 388         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 389         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 390         u32 list_conf   = 0, drive_conf = 0;
 391         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 392
 393         /*
 394          * Disable the "fast interrupt" prediction.
 395          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 396          */
 397         pci_read_config_byte(dev, regfast, &drive_fast);
 398         drive_fast &= ~0x07;
 399         pci_write_config_byte(dev, regfast, drive_fast);
 400
 401         list_conf = pci_bus_clock_list(speed,
 402                         (struct chipset_bus_clock_list_entry *)
 403                                         pci_get_drvdata(dev));
 404         pci_read_config_dword(dev, drive_pci, &drive_conf);
 405         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 406         if (speed < XFER_MW_DMA_0)
 407                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 408         pci_write_config_dword(dev, drive_pci, list_conf);
 409 }
 410
 411 static void hpt374_tune_chipset (ide_drive_t *drive, u8 speed)
 412 {
 413         hpt372_tune_chipset(drive, speed);
 414 }
 415
 416 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 417 {
 418         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 419
 420         if (hpt_minimum_revision(dev, 8))
 421                 hpt374_tune_chipset(drive, speed);
 422 #if 0
 423         else if (hpt_minimum_revision(dev, 7))
 424                 hpt371_tune_chipset(drive, speed);
 425         else if (hpt_minimum_revision(dev, 6))
 426                 hpt302_tune_chipset(drive, speed);
 427 #endif
 428         else if (hpt_minimum_revision(dev, 5))
 429                 hpt372_tune_chipset(drive, speed);
 430         else if (hpt_minimum_revision(dev, 3))
 431                 hpt370_tune_chipset(drive, speed);
 432         else if (hpt_minimum_revision(dev, 2))
 433                 hpt368_tune_chipset(drive, speed);
 434         else
 435                 hpt366_tune_chipset(drive, speed);
 436
 437         return ((int) ide_config_drive_speed(drive, speed));
 438 }
 439
 440 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 441 {
 442         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 443         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 444 }
 445
 446 /*
 447  * This allows the configuration of ide_pci chipset registers
 448  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 449  * after the drive is reported by the OS.  Initially for designed for
 450  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 451  *
 452  * check_in_drive_lists(drive, bad_ata66_4)
 453  * check_in_drive_lists(drive, bad_ata66_3)
 454  * check_in_drive_lists(drive, bad_ata33)
 455  *
 456  */
 457 static int config_chipset_for_dma (ide_drive_t *drive)
 458 {
 459         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 460
 461         if (!(speed))
 462                 return 0;
 463
 464         (void) hpt3xx_tune_chipset(drive, speed);
 465         return ide_dma_enable(drive);
 466 }
 467
 468 static int hpt3xx_quirkproc (ide_drive_t *drive)
 469 {
 470         return ((int) check_in_drive_lists(drive, quirk_drives));
 471 }
 472
 473 static void hpt3xx_intrproc (ide_drive_t *drive)
 474 {
 475         ide_hwif_t *hwif = HWIF(drive);
 476
 477         if (drive->quirk_list)
 478                 return;
 479         /* drives in the quirk_list may not like intr setups/cleanups */
 480         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 481 }
 482
 483 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 484 {
 485         struct pci_dev *dev = HWIF(drive)->pci_dev;
 486
 487         if (drive->quirk_list) {
 488                 if (hpt_minimum_revision(dev,3)) {
 489                         u8 reg5a = 0;
 490                         pci_read_config_byte(dev, 0x5a, &reg5a);
 491                         if (((reg5a & 0x10) >> 4) != mask)
 492                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 493                 } else {
 494                         if (mask) {
 495                                 disable_irq(HWIF(drive)->irq);
 496                         } else {
 497                                 enable_irq(HWIF(drive)->irq);
 498                         }
 499                 }
 500         } else {
 501                 if (IDE_CONTROL_REG)
 502                         HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
 503                                                  (drive->ctl & ~2),
 504                                                  IDE_CONTROL_REG);
 505         }
 506 }
 507
 508 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 509 {
 510         ide_hwif_t *hwif        = HWIF(drive);
 511         struct hd_driveid *id   = drive->id;
 512
 513         drive->init_speed = 0;
 514
 515         if (id && (id->capability & 1) && drive->autodma) {
 516                 /* Consult the list of known "bad" drives */
 517                 if (__ide_dma_bad_drive(drive))
 518                         goto fast_ata_pio;
 519                 if (id->field_valid & 4) {
 520                         if (id->dma_ultra & hwif->ultra_mask) {
 521                                 /* Force if Capable UltraDMA */
 522                                 int dma = config_chipset_for_dma(drive);
 523                                 if ((id->field_valid & 2) && !dma)
 524                                         goto try_dma_modes;
 525                         }
 526                 } else if (id->field_valid & 2) {
 527 try_dma_modes:
 528                         if (id->dma_mword & hwif->mwdma_mask) {
 529                                 /* Force if Capable regular DMA modes */
 530                                 if (!config_chipset_for_dma(drive))
 531                                         goto no_dma_set;
 532                         }
 533                 } else if (__ide_dma_good_drive(drive) &&
 534                            (id->eide_dma_time < 150)) {
 535                         /* Consult the list of known "good" drives */
 536                         if (!config_chipset_for_dma(drive))
 537                                 goto no_dma_set;
 538                 } else {
 539                         goto fast_ata_pio;
 540                 }
 541                 return hwif->ide_dma_on(drive);
 542         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 543 fast_ata_pio:
 544 no_dma_set:
 545                 hpt3xx_tune_drive(drive, 5);
 546                 return hwif->ide_dma_off_quietly(drive);
 547         }
 548         /* IORDY not supported */
 549         return 0;
 550 }
 551
 552 /*
 553  * This is specific to the HPT366 UDMA bios chipset
 554  * by HighPoint|Triones Technologies, Inc.
 555  */
 556 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 557 {
 558         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 559         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 560
 561         pci_read_config_byte(dev, 0x50, &reg50h);
 562         pci_read_config_byte(dev, 0x52, &reg52h);
 563         pci_read_config_byte(dev, 0x5a, &reg5ah);
 564         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 565                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 566         if (reg5ah & 0x10)
 567                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 568 #if 0
 569         /* how about we flush and reset, mmmkay? */
 570         pci_write_config_byte(dev, 0x51, 0x1F);
 571         /* fall through to a reset */
 572         case ide_dma_begin:
 573         case ide_dma_end:
 574         /* reset the chips state over and over.. */
 575         pci_write_config_byte(dev, 0x51, 0x13);
 576 #endif
 577         return __ide_dma_lostirq(drive);
 578 }
 579
 580 static void hpt370_clear_engine (ide_drive_t *drive)
 581 {
 582         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 583         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 584         udelay(10);
 585 }
 586
 587 static int hpt370_ide_dma_begin (ide_drive_t *drive)
 588 {
 589 #ifdef HPT_RESET_STATE_ENGINE
 590         hpt370_clear_engine(drive);
 591 #endif
 592         return __ide_dma_begin(drive);
 593 }
 594
 595 static int hpt370_ide_dma_end (ide_drive_t *drive)
 596 {
 597         ide_hwif_t *hwif        = HWIF(drive);
 598         u8 dma_stat             = hwif->INB(hwif->dma_status);
 599
 600         if (dma_stat & 0x01) {
 601                 /* wait a little */
 602                 udelay(20);
 603                 dma_stat = hwif->INB(hwif->dma_status);
 604         }
 605         if ((dma_stat & 0x01) != 0)
 606                 /* fallthrough */
 607                 (void) HWIF(drive)->ide_dma_timeout(drive);
 608
 609         return __ide_dma_end(drive);
 610 }
 611
 612 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 613 {
 614         ide_hwif_t *hwif        = HWIF(drive);
 615         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 616         u8 dma_stat = 0, dma_cmd = 0;
 617
 618         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 619         printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 620         hpt370_clear_engine(drive);
 621         /* get dma command mode */
 622         dma_cmd = hwif->INB(hwif->dma_command);
 623         /* stop dma */
 624         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 625         dma_stat = hwif->INB(hwif->dma_status);
 626         /* clear errors */
 627         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 628 }
 629
 630 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 631 {
 632         hpt370_lostirq_timeout(drive);
 633         hpt370_clear_engine(drive);
 634         return __ide_dma_timeout(drive);
 635 }
 636
 637 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 638 {
 639         hpt370_lostirq_timeout(drive);
 640         hpt370_clear_engine(drive);
 641         return __ide_dma_lostirq(drive);
 642 }
 643
 644 /* returns 1 if DMA IRQ issued, 0 otherwise */
 645 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 646 {
 647         ide_hwif_t *hwif        = HWIF(drive);
 648         u16 bfifo               = 0;
 649         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 650         u8 dma_stat;
 651
 652         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 653         if (bfifo & 0x1FF) {
 654 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 655                 return 0;
 656         }
 657
 658         dma_stat = hwif->INB(hwif->dma_status);
 659         /* return 1 if INTR asserted */
 660         if ((dma_stat & 4) == 4)
 661                 return 1;
 662
 663         if (!drive->waiting_for_dma)
 664                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 665                                 drive->name, __FUNCTION__);
 666         return 0;
 667 }
 668
 669 static int hpt374_ide_dma_end (ide_drive_t *drive)
 670 {
 671         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 672         ide_hwif_t *hwif        = HWIF(drive);
 673         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 674         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 675
 676         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 677         pci_read_config_byte(dev, mscreg, &msc_stat);
 678         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 679                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 680         return __ide_dma_end(drive);
 681 }
 682
 683 /*
 684  * Since SUN Cobalt is attempting to do this operation, I should disclose
 685  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 686  * HOTSWAP ATA Infrastructure.
 687  */
 688
 689 static void hpt3xx_reset (ide_drive_t *drive)
 690 {
 691 #if 0
 692         unsigned long high_16   = pci_resource_start(HWIF(drive)->pci_dev, 4);
 693         u8 reset        = (HWIF(drive)->channel) ? 0x80 : 0x40;
 694         u8 reg59h       = 0;
 695
 696         pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
 697         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
 698         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
 699 #endif
 700 }
 701
 702 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 703 {
 704         ide_hwif_t *hwif        = HWIF(drive);
 705         struct pci_dev *dev     = hwif->pci_dev;
 706         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 707         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 708
 709         if (!hwif)
 710                 return -EINVAL;
 711
 712 //      hwif->bus_state = state;
 713
 714         pci_read_config_byte(dev, 0x59, &reg59h);
 715         pci_read_config_byte(dev, state_reg, &regXXh);
 716
 717         if (state) {
 718                 (void) ide_do_reset(drive);
 719                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 720                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 721         } else {
 722                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 723                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 724                 (void) ide_do_reset(drive);
 725         }
 726         return 0;
 727 }
 728
 729 /*
 730  * set/get power state for a drive.
 731  * turning the power off does the following things:
 732  *   1) soft-reset the drive
 733  *   2) tri-states the ide bus
 734  *
 735  * when we turn things back on, we need to re-initialize things.
 736  */
 737 #define TRISTATE_BIT  0x8000
 738 static int hpt370_busproc(ide_drive_t * drive, int state)
 739 {
 740         ide_hwif_t *hwif        = HWIF(drive);
 741         struct pci_dev *dev     = hwif->pci_dev;
 742         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 743         u16 tri_reg;
 744
 745         if (!hwif)
 746                 return -EINVAL;
 747
 748         hwif->bus_state = state;
 749
 750         if (hwif->channel) {
 751                 /* secondary channel */
 752                 tristate = 0x56;
 753                 resetmask = 0x80;
 754         } else {
 755                 /* primary channel */
 756                 tristate = 0x52;
 757                 resetmask = 0x40;
 758         }
 759
 760         /* grab status */
 761         pci_read_config_word(dev, tristate, &tri_reg);
 762         pci_read_config_byte(dev, 0x59, &bus_reg);
 763
 764         /* set the state. we don't set it if we don't need to do so.
 765          * make sure that the drive knows that it has failed if it's off */
 766         switch (state) {
 767         case BUSSTATE_ON:
 768                 hwif->drives[0].failures = 0;
 769                 hwif->drives[1].failures = 0;
 770                 if ((bus_reg & resetmask) == 0)
 771                         return 0;
 772                 tri_reg &= ~TRISTATE_BIT;
 773                 bus_reg &= ~resetmask;
 774                 break;
 775         case BUSSTATE_OFF:
 776                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 777                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 778                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 779                         return 0;
 780                 tri_reg &= ~TRISTATE_BIT;
 781                 bus_reg |= resetmask;
 782                 break;
 783         case BUSSTATE_TRISTATE:
 784                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 785                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 786                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
 787                         return 0;
 788                 tri_reg |= TRISTATE_BIT;
 789                 bus_reg |= resetmask;
 790                 break;
 791         }
 792         pci_write_config_byte(dev, 0x59, bus_reg);
 793         pci_write_config_word(dev, tristate, tri_reg);
 794
 795         return 0;
 796 }
 797
 798 static int __devinit init_hpt37x(struct pci_dev *dev)
 799 {
 800         int adjust, i;
 801         u16 freq;
 802         u32 pll;
 803         u8 reg5bh;
 804
 805 #if 1
 806         u8 reg5ah = 0;
 807         pci_read_config_byte(dev, 0x5a, &reg5ah);
 808         /* interrupt force enable */
 809         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
 810 #endif
 811
 812         /*
 813          * default to pci clock. make sure MA15/16 are set to output
 814          * to prevent drives having problems with 40-pin cables.
 815          */
 816         pci_write_config_byte(dev, 0x5b, 0x23);
 817
 818         /*
 819          * set up the PLL. we need to adjust it so that it's stable.
 820          * freq = Tpll * 192 / Tpci
 821          */
 822         pci_read_config_word(dev, 0x78, &freq);
 823         freq &= 0x1FF;
 824         if (freq < 0xa0) {
 825                 pll = F_LOW_PCI_33;
 826                 if (hpt_minimum_revision(dev,8))
 827                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
 828                 else if (hpt_minimum_revision(dev,5))
 829                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
 830                 else if (hpt_minimum_revision(dev,4))
 831                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
 832                 else
 833                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
 834                 printk("HPT37X: using 33MHz PCI clock\n");
 835         } else if (freq < 0xb0) {
 836                 pll = F_LOW_PCI_40;
 837         } else if (freq < 0xc8) {
 838                 pll = F_LOW_PCI_50;
 839                 if (hpt_minimum_revision(dev,8))
 840                         pci_set_drvdata(dev, NULL);
 841                 else if (hpt_minimum_revision(dev,5))
 842                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 843                 else if (hpt_minimum_revision(dev,4))
 844                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 845                 else
 846                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 847                 printk("HPT37X: using 50MHz PCI clock\n");
 848         } else {
 849                 pll = F_LOW_PCI_66;
 850                 if (hpt_minimum_revision(dev,8))
 851                 {
 852                         printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
 853                         pci_set_drvdata(dev, NULL);
 854                 }
 855                 else if (hpt_minimum_revision(dev,5))
 856                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
 857                 else if (hpt_minimum_revision(dev,4))
 858                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
 859                 else
 860                         pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
 861                 printk("HPT37X: using 66MHz PCI clock\n");
 862         }
 863
 864         /*
 865          * only try the pll if we don't have a table for the clock
 866          * speed that we're running at. NOTE: the internal PLL will
 867          * result in slow reads when using a 33MHz PCI clock. we also
 868          * don't like to use the PLL because it will cause glitches
 869          * on PRST/SRST when the HPT state engine gets reset.
 870          */
 871         if (pci_get_drvdata(dev))
 872                 goto init_hpt37X_done;
 873
 874         /*
 875          * adjust PLL based upon PCI clock, enable it, and wait for
 876          * stabilization.
 877          */
 878         adjust = 0;
 879         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
 880         while (adjust++ < 6) {
 881                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
 882                                        pll | 0x100);
 883
 884                 /* wait for clock stabilization */
 885                 for (i = 0; i < 0x50000; i++) {
 886                         pci_read_config_byte(dev, 0x5b, &reg5bh);
 887                         if (reg5bh & 0x80) {
 888                                 /* spin looking for the clock to destabilize */
 889                                 for (i = 0; i < 0x1000; ++i) {
 890                                         pci_read_config_byte(dev, 0x5b,
 891                                                              &reg5bh);
 892                                         if ((reg5bh & 0x80) == 0)
 893                                                 goto pll_recal;
 894                                 }
 895                                 pci_read_config_dword(dev, 0x5c, &pll);
 896                                 pci_write_config_dword(dev, 0x5c,
 897                                                        pll & ~0x100);
 898                                 pci_write_config_byte(dev, 0x5b, 0x21);
 899                                 if (hpt_minimum_revision(dev,8))
 900                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 901                                 else if (hpt_minimum_revision(dev,5))
 902                                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 903                                 else if (hpt_minimum_revision(dev,4))
 904                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 905                                 else
 906                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 907                                 printk("HPT37X: using 50MHz internal PLL\n");
 908                                 goto init_hpt37X_done;
 909                         }
 910                 }
 911 pll_recal:
 912                 if (adjust & 1)
 913                         pll -= (adjust >> 1);
 914                 else
 915                         pll += (adjust >> 1);
 916         }
 917
 918 init_hpt37X_done:
 919         /* reset state engine */
 920         pci_write_config_byte(dev, 0x50, 0x37);
 921         pci_write_config_byte(dev, 0x54, 0x37);
 922         udelay(100);
 923         return 0;
 924 }
 925
 926 static int __devinit init_hpt366(struct pci_dev *dev)
 927 {
 928         u32 reg1        = 0;
 929         u8 drive_fast   = 0;
 930
 931         /*
 932          * Disable the "fast interrupt" prediction.
 933          */
 934         pci_read_config_byte(dev, 0x51, &drive_fast);
 935         if (drive_fast & 0x80)
 936                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 937         pci_read_config_dword(dev, 0x40, &reg1);
 938
 939         /* detect bus speed by looking at control reg timing: */
 940         switch((reg1 >> 8) & 7) {
 941                 case 5:
 942                         pci_set_drvdata(dev, (void *) forty_base_hpt366);
 943                         break;
 944                 case 9:
 945                         pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
 946                         break;
 947                 case 7:
 948                 default:
 949                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
 950                         break;
 951         }
 952
 953         if (!pci_get_drvdata(dev))
 954         {
 955                 printk(KERN_ERR "hpt366: unknown bus timing.\n");
 956                 pci_set_drvdata(dev, NULL);
 957         }
 958         return 0;
 959 }
 960
 961 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
 962 {
 963         int ret = 0;
 964         u8 test = 0;
 965
 966         if (dev->resource[PCI_ROM_RESOURCE].start)
 967                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
 968                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 969
 970         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
 971         if (test != (L1_CACHE_BYTES / 4))
 972                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
 973                         (L1_CACHE_BYTES / 4));
 974
 975         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
 976         if (test != 0x78)
 977                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 978
 979         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
 980         if (test != 0x08)
 981                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 982
 983         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
 984         if (test != 0x08)
 985                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 986
 987         if (hpt_minimum_revision(dev, 3)) {
 988                 ret = init_hpt37x(dev);
 989         } else {
 990                 ret =init_hpt366(dev);
 991         }
 992         if (ret)
 993                 return ret;
 994
 995 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
 996         hpt_devs[n_hpt_devs++] = dev;
 997
 998         if (!hpt366_proc) {
 999                 hpt366_proc = 1;
1000                 ide_pci_create_host_proc("hpt366", hpt366_get_info);
1001         }
1002 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
1003
1004         return dev->irq;
1005 }
1006
1007 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1008 {
1009         struct pci_dev *dev             = hwif->pci_dev;
1010         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1011
1012         hwif->tuneproc                  = &hpt3xx_tune_drive;
1013         hwif->speedproc                 = &hpt3xx_tune_chipset;
1014         hwif->quirkproc                 = &hpt3xx_quirkproc;
1015         hwif->intrproc                  = &hpt3xx_intrproc;
1016         hwif->maskproc                  = &hpt3xx_maskproc;
1017
1018         /*
1019          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1020          * address lines to access an external eeprom.  To read valid
1021          * cable detect state the pins must be enabled as inputs.
1022          */
1023         if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1024                 /*
1025                  * HPT374 PCI function 1
1026                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1027                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1028                  */
1029                 u16 mcr3, mcr6;
1030                 pci_read_config_word(dev, 0x52, &mcr3);
1031                 pci_read_config_word(dev, 0x56, &mcr6);
1032                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1033                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1034                 /* now read cable id register */
1035                 pci_read_config_byte(dev, 0x5a, &ata66);
1036                 pci_write_config_word(dev, 0x52, mcr3);
1037                 pci_write_config_word(dev, 0x56, mcr6);
1038         } else if (hpt_minimum_revision(dev, 3)) {
1039                 /*
1040                  * HPT370/372 and 374 pcifn 0
1041                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1042                  */
1043                 u8 scr2;
1044                 pci_read_config_byte(dev, 0x5b, &scr2);
1045                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1046                 /* now read cable id register */
1047                 pci_read_config_byte(dev, 0x5a, &ata66);
1048                 pci_write_config_byte(dev, 0x5b, scr2);
1049         } else {
1050                 pci_read_config_byte(dev, 0x5a, &ata66);
1051         }
1052
1053 #ifdef DEBUG
1054         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1055                 ata66, (ata66 & regmask) ? "33" : "66",
1056                 PCI_FUNC(hwif->pci_dev->devfn));
1057 #endif /* DEBUG */
1058
1059 #ifdef HPT_SERIALIZE_IO
1060         /* serialize access to this device */
1061         if (hwif->mate)
1062                 hwif->serialized = hwif->mate->serialized = 1;
1063 #endif
1064
1065         if (hpt_minimum_revision(dev,3)) {
1066                 u8 reg5ah = 0;
1067                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1068                 /*
1069                  * set up ioctl for power status.
1070                  * note: power affects both
1071                  * drives on each channel
1072                  */
1073                 hwif->resetproc = &hpt3xx_reset;
1074                 hwif->busproc   = &hpt370_busproc;
1075 //              hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1076         } else if (hpt_minimum_revision(dev,2)) {
1077                 hwif->resetproc = &hpt3xx_reset;
1078                 hwif->busproc   = &hpt3xx_tristate;
1079         } else {
1080                 hwif->resetproc = &hpt3xx_reset;
1081                 hwif->busproc   = &hpt3xx_tristate;
1082         }
1083
1084         if (!hwif->dma_base) {
1085                 hwif->drives[0].autotune = 1;
1086                 hwif->drives[1].autotune = 1;
1087                 return;
1088         }
1089
1090         hwif->ultra_mask = 0x7f;
1091         hwif->mwdma_mask = 0x07;
1092
1093         if (!(hwif->udma_four))
1094                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1095         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1096
1097         if (hpt_minimum_revision(dev,8)) {
1098                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1099                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1100         } else if (hpt_minimum_revision(dev,5)) {
1101                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1102                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1103         } else if (hpt_minimum_revision(dev,3)) {
1104                 hwif->ide_dma_begin = &hpt370_ide_dma_begin;
1105                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1106                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1107                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1108         } else if (hpt_minimum_revision(dev,2))
1109                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1110         else
1111                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1112
1113         if (!noautodma)
1114                 hwif->autodma = 1;
1115         hwif->drives[0].autodma = hwif->autodma;
1116         hwif->drives[1].autodma = hwif->autodma;
1117 }
1118
1119 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1120 {
1121         u8 masterdma    = 0, slavedma = 0;
1122         u8 dma_new      = 0, dma_old = 0;
1123         u8 primary      = hwif->channel ? 0x4b : 0x43;
1124         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1125         unsigned long flags;
1126
1127         if (!dmabase)
1128                 return;
1129
1130         if(pci_get_drvdata(hwif->pci_dev) == NULL)
1131         {
1132                 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1133                 return;
1134         }
1135
1136         dma_old = hwif->INB(dmabase+2);
1137
1138         local_irq_save(flags);
1139
1140         dma_new = dma_old;
1141         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1142         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1143
1144         if (masterdma & 0x30)   dma_new |= 0x20;
1145         if (slavedma & 0x30)    dma_new |= 0x40;
1146         if (dma_new != dma_old)
1147                 hwif->OUTB(dma_new, dmabase+2);
1148
1149         local_irq_restore(flags);
1150
1151         ide_setup_dma(hwif, dmabase, 8);
1152 }
1153
1154 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1155 {
1156         struct pci_dev *findev = NULL;
1157
1158         if (PCI_FUNC(dev->devfn) & 1)
1159                 return;
1160
1161         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1162                 if ((findev->vendor == dev->vendor) &&
1163                     (findev->device == dev->device) &&
1164                     ((findev->devfn - dev->devfn) == 1) &&
1165                     (PCI_FUNC(findev->devfn) & 1)) {
1166                         if (findev->irq != dev->irq) {
1167                                 /* FIXME: we need a core pci_set_interrupt() */
1168                                 findev->irq = dev->irq;
1169                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1170                                         "fixed.\n", d->name);
1171                         }
1172                         ide_setup_pci_devices(dev, findev, d);
1173                         return;
1174                 }
1175         }
1176         ide_setup_pci_device(dev, d);
1177 }
1178
1179 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1180 {
1181         ide_setup_pci_device(dev, d);
1182 }
1183
1184 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1185 {
1186         struct pci_dev *findev = NULL;
1187         u8 pin1 = 0, pin2 = 0;
1188         unsigned int class_rev;
1189         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1190                                  "HPT370", "HPT370A", "HPT372"};
1191
1192         if (PCI_FUNC(dev->devfn) & 1)
1193                 return;
1194
1195         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1196         class_rev &= 0xff;
1197
1198         strcpy(d->name, chipset_names[class_rev]);
1199
1200         switch(class_rev) {
1201                 case 5:
1202                 case 4:
1203                 case 3: ide_setup_pci_device(dev, d);
1204                         return;
1205                 default:        break;
1206         }
1207
1208         d->channels = 1;
1209
1210         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1211         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1212                 if ((findev->vendor == dev->vendor) &&
1213                     (findev->device == dev->device) &&
1214                     ((findev->devfn - dev->devfn) == 1) &&
1215                     (PCI_FUNC(findev->devfn) & 1)) {
1216                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1217                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1218                                 d->bootable = ON_BOARD;
1219                                 printk("%s: onboard version of chipset, "
1220                                         "pin1=%d pin2=%d\n", d->name,
1221                                         pin1, pin2);
1222                         }
1223                         ide_setup_pci_devices(dev, findev, d);
1224                         return;
1225                 }
1226         }
1227         ide_setup_pci_device(dev, d);
1228 }
1229
1230
1231 /**
1232  *      hpt366_init_one -       called when an HPT366 is found
1233  *      @dev: the hpt366 device
1234  *      @id: the matching pci id
1235  *
1236  *      Called when the PCI registration layer (or the IDE initialization)
1237  *      finds a device matching our IDE device tables.
1238  */
1239
1240 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1241 {
1242         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1243
1244         d->init_setup(dev, d);
1245         return 0;
1246 }
1247
1248 static struct pci_device_id hpt366_pci_tbl[] = {
1249         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1250         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1251         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1252         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1253         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1254         { 0, },
1255 };
1256 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1257
1258 static struct pci_driver driver = {
1259         .name           = "HPT366 IDE",
1260         .id_table       = hpt366_pci_tbl,
1261         .probe          = hpt366_init_one,
1262 };
1263
1264 static int hpt366_ide_init(void)
1265 {
1266         return ide_pci_register_driver(&driver);
1267 }
1268
1269 module_init(hpt366_ide_init);
1270
1271 MODULE_AUTHOR("Andre Hedrick");
1272 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1273 MODULE_LICENSE("GPL");