drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  *
   8  * Thanks to HighPoint Technologies for their assistance, and hardware.
   9  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  10  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  11  * development and support.
  12  *
  13  * Note that final HPT370 support was done by force extraction of GPL.
  14  *
  15  * - add function for getting/setting power status of drive
  16  * - the HPT370's state machine can get confused. reset it before each dma
  17  *   xfer to prevent that from happening.
  18  * - reset state engine whenever we get an error.
  19  * - check for busmaster state at end of dma.
  20  * - use new highpoint timings.
  21  * - detect bus speed using highpoint register.
  22  * - use pll if we don't have a clock table. added a 66MHz table that's
  23  *   just 2x the 33MHz table.
  24  * - removed turnaround. NOTE: we never want to switch between pll and
  25  *   pci clocks as the chip can glitch in those cases. the highpoint
  26  *   approved workaround slows everything down too much to be useful. in
  27  *   addition, we would have to serialize access to each chip.
  28  *      Adrian Sun <a.sun@sun.com>
  29  *
  30  * add drive timings for 66MHz PCI bus,
  31  * fix ATA Cable signal detection, fix incorrect /proc info
  32  * add /proc display for per-drive PIO/DMA/UDMA mode and
  33  * per-channel ATA-33/66 Cable detect.
  34  *      Duncan Laurie <void@sun.com>
  35  *
  36  * fixup /proc output for multiple controllers
  37  *      Tim Hockin <thockin@sun.com>
  38  *
  39  * On hpt366:
  40  * Reset the hpt366 on error, reset on dma
  41  * Fix disabling Fast Interrupt hpt366.
  42  *      Mike Waychison <crlf@sun.com>
  43  *
  44  * Added support for 372N clocking and clock switching. The 372N needs
  45  * different clocks on read/write. This requires overloading rw_disk and
  46  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  47  * keeping me sane.
  48  *              Alan Cox <alan@redhat.com>
  49  *
  50  */
  51
  52
  53 #include <linux/config.h>
  54 #include <linux/types.h>
  55 #include <linux/module.h>
  56 #include <linux/kernel.h>
  57 #include <linux/delay.h>
  58 #include <linux/timer.h>
  59 #include <linux/mm.h>
  60 #include <linux/ioport.h>
  61 #include <linux/blkdev.h>
  62 #include <linux/hdreg.h>
  63
  64 #include <linux/interrupt.h>
  65 #include <linux/pci.h>
  66 #include <linux/init.h>
  67 #include <linux/ide.h>
  68
  69 #include <asm/uaccess.h>
  70 #include <asm/io.h>
  71 #include <asm/irq.h>
  72
  73 #include "hpt366.h"
  74
  75 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  76 #include <linux/stat.h>
  77 #include <linux/proc_fs.h>
  78 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
  79
  80 static unsigned int hpt_revision(struct pci_dev *dev);
  81 static unsigned int hpt_minimum_revision(struct pci_dev *dev, int revision);
  82
  83 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  84
  85 static u8 hpt366_proc = 0;
  86 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
  87 static int n_hpt_devs;
  88
  89 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
  90 {
  91         char *p = buffer;
  92         char *chipset_nums[] = {"366", "366",  "368",
  93                                 "370", "370A", "372",
  94                                 "302", "371",  "374" };
  95         int i, len;
  96
  97         p += sprintf(p, "\n                             "
  98                 "HighPoint HPT366/368/370/372/374\n");
  99         for (i = 0; i < n_hpt_devs; i++) {
 100                 struct pci_dev *dev = hpt_devs[i];
 101                 unsigned long iobase = dev->resource[4].start;
 102                 u32 class_rev = hpt_revision(dev);
 103                 u8 c0, c1;
 104
 105                 p += sprintf(p, "\nController: %d\n", i);
 106                 p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]);
 107                 p += sprintf(p, "--------------- Primary Channel "
 108                                 "--------------- Secondary Channel "
 109                                 "--------------\n");
 110
 111                 /* get the bus master status registers */
 112                 c0 = inb(iobase + 0x2);
 113                 c1 = inb(iobase + 0xa);
 114                 p += sprintf(p, "Enabled:        %s"
 115                                 "                             %s\n",
 116                         (c0 & 0x80) ? "no" : "yes",
 117                         (c1 & 0x80) ? "no" : "yes");
 118 #if 0
 119                 if (hpt_minimum_revision(dev, 3)) {
 120                         u8 cbl;
 121                         cbl = inb(iobase + 0x7b);
 122                         outb(cbl | 1, iobase + 0x7b);
 123                         outb(cbl & ~1, iobase + 0x7b);
 124                         cbl = inb(iobase + 0x7a);
 125                         p += sprintf(p, "Cable:          ATA-%d"
 126                                         "                          ATA-%d\n",
 127                                 (cbl & 0x02) ? 33 : 66,
 128                                 (cbl & 0x01) ? 33 : 66);
 129                         p += sprintf(p, "\n");
 130                 }
 131 #endif
 132                 p += sprintf(p, "--------------- drive0 --------- drive1 "
 133                                 "------- drive0 ---------- drive1 -------\n");
 134                 p += sprintf(p, "DMA capable:    %s              %s"
 135                                 "            %s               %s\n",
 136                         (c0 & 0x20) ? "yes" : "no ",
 137                         (c0 & 0x40) ? "yes" : "no ",
 138                         (c1 & 0x20) ? "yes" : "no ",
 139                         (c1 & 0x40) ? "yes" : "no ");
 140
 141                 {
 142                         u8 c2, c3;
 143                         /* older revs don't have these registers mapped
 144                          * into io space */
 145                         pci_read_config_byte(dev, 0x43, &c0);
 146                         pci_read_config_byte(dev, 0x47, &c1);
 147                         pci_read_config_byte(dev, 0x4b, &c2);
 148                         pci_read_config_byte(dev, 0x4f, &c3);
 149
 150                         p += sprintf(p, "Mode:           %s             %s"
 151                                         "           %s              %s\n",
 152                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
 153                                         (c0 & 0x80) ? "PIO " : "off ",
 154                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
 155                                         (c1 & 0x80) ? "PIO " : "off ",
 156                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
 157                                         (c2 & 0x80) ? "PIO " : "off ",
 158                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
 159                                         (c3 & 0x80) ? "PIO " : "off ");
 160                 }
 161         }
 162         p += sprintf(p, "\n");
 163
 164         /* p - buffer must be less than 4k! */
 165         len = (p - buffer) - offset;
 166         *addr = buffer + offset;
 167
 168         return len > count ? count : len;
 169 }
 170 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
 171
 172 static u32 hpt_revision (struct pci_dev *dev)
 173 {
 174         u32 class_rev;
 175         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 176         class_rev &= 0xff;
 177
 178         switch(dev->device) {
 179                 /* Remap new 372N onto 372 */
 180                 case PCI_DEVICE_ID_TTI_HPT372N:
 181                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 182                 case PCI_DEVICE_ID_TTI_HPT374:
 183                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 184                 case PCI_DEVICE_ID_TTI_HPT371:
 185                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 186                 case PCI_DEVICE_ID_TTI_HPT302:
 187                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 188                 case PCI_DEVICE_ID_TTI_HPT372:
 189                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 190                 default:
 191                         break;
 192         }
 193         return class_rev;
 194 }
 195
 196 static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
 197 {
 198         unsigned int class_rev = hpt_revision(dev);
 199         revision--;
 200         return ((int) (class_rev > revision) ? 1 : 0);
 201 }
 202
 203 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 204
 205 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 206 {
 207         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 208         u8 mode                 = 0;
 209
 210         if (hpt_minimum_revision(dev, 8)) {             /* HPT374 */
 211                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 212         } else if (hpt_minimum_revision(dev, 7)) {      /* HPT371 */
 213                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 214         } else if (hpt_minimum_revision(dev, 6)) {      /* HPT302 */
 215                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 216         } else if (hpt_minimum_revision(dev, 5)) {      /* HPT372 */
 217                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 218         } else if (hpt_minimum_revision(dev, 4)) {      /* HPT370A */
 219                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 220         } else if (hpt_minimum_revision(dev, 3)) {      /* HPT370 */
 221                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 222                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 223         } else {                                /* HPT366 and HPT368 */
 224                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 225         }
 226         if (!eighty_ninty_three(drive) && (mode))
 227                 mode = min(mode, (u8)1);
 228         return mode;
 229 }
 230
 231 /*
 232  *      Note for the future; the SATA hpt37x we must set
 233  *      either PIO or UDMA modes 0,4,5
 234  */
 235
 236 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 237 {
 238         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 239         u8 mode                 = hpt3xx_ratemask(drive);
 240
 241         if (drive->media != ide_disk)
 242                 return min(speed, (u8)XFER_PIO_4);
 243
 244         switch(mode) {
 245                 case 0x04:
 246                         speed = min(speed, (u8)XFER_UDMA_6);
 247                         break;
 248                 case 0x03:
 249                         speed = min(speed, (u8)XFER_UDMA_5);
 250                         if (hpt_minimum_revision(dev, 5))
 251                                 break;
 252                         if (check_in_drive_lists(drive, bad_ata100_5))
 253                                 speed = min(speed, (u8)XFER_UDMA_4);
 254                         break;
 255                 case 0x02:
 256                         speed = min(speed, (u8)XFER_UDMA_4);
 257         /*
 258          * CHECK ME, Does this need to be set to 5 ??
 259          */
 260                         if (hpt_minimum_revision(dev, 3))
 261                                 break;
 262                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 263                             (!(HPT366_ALLOW_ATA66_4)))
 264                                 speed = min(speed, (u8)XFER_UDMA_3);
 265                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 266                             (!(HPT366_ALLOW_ATA66_3)))
 267                                 speed = min(speed, (u8)XFER_UDMA_2);
 268                         break;
 269                 case 0x01:
 270                         speed = min(speed, (u8)XFER_UDMA_2);
 271         /*
 272          * CHECK ME, Does this need to be set to 5 ??
 273          */
 274                         if (hpt_minimum_revision(dev, 3))
 275                                 break;
 276                         if (check_in_drive_lists(drive, bad_ata33))
 277                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 278                         break;
 279                 case 0x00:
 280                 default:
 281                         speed = min(speed, (u8)XFER_MW_DMA_2);
 282                         break;
 283         }
 284         return speed;
 285 }
 286
 287 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 288 {
 289         struct hd_driveid *id = drive->id;
 290
 291         if (quirk_drives == list) {
 292                 while (*list)
 293                         if (strstr(id->model, *list++))
 294                                 return 1;
 295         } else {
 296                 while (*list)
 297                         if (!strcmp(*list++,id->model))
 298                                 return 1;
 299         }
 300         return 0;
 301 }
 302
 303 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 304 {
 305         for ( ; chipset_table->xfer_speed ; chipset_table++)
 306                 if (chipset_table->xfer_speed == speed)
 307                         return chipset_table->chipset_settings;
 308         return chipset_table->chipset_settings;
 309 }
 310
 311 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 312 {
 313         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 314         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 315 //      u8 speed                = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 316         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 317         u8 regfast              = (HWIF(drive)->channel) ? 0x55 : 0x51;
 318         u8 drive_fast           = 0;
 319         u32 reg1 = 0, reg2      = 0;
 320
 321         /*
 322          * Disable the "fast interrupt" prediction.
 323          */
 324         pci_read_config_byte(dev, regfast, &drive_fast);
 325 #if 0
 326         if (drive_fast & 0x02)
 327                 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
 328 #else
 329         if (drive_fast & 0x80)
 330                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 331 #endif
 332
 333         reg2 = pci_bus_clock_list(speed,
 334                 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
 335         /*
 336          * Disable on-chip PIO FIFO/buffer
 337          *  (to avoid problems handling I/O errors later)
 338          */
 339         pci_read_config_dword(dev, regtime, &reg1);
 340         if (speed >= XFER_MW_DMA_0) {
 341                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 342         } else {
 343                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 344         }
 345         reg2 &= ~0x80000000;
 346
 347         pci_write_config_dword(dev, regtime, reg2);
 348
 349         return ide_config_drive_speed(drive, speed);
 350 }
 351
 352 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 353 {
 354         struct pci_dev *dev = HWIF(drive)->pci_dev;
 355         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 356 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 357         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 358         u8 drive_pci    = 0x40 + (drive->dn * 4);
 359         u8 new_fast     = 0, drive_fast = 0;
 360         u32 list_conf   = 0, drive_conf = 0;
 361         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 362
 363         /*
 364          * Disable the "fast interrupt" prediction.
 365          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 366          */
 367         pci_read_config_byte(dev, regfast, &drive_fast);
 368         new_fast = drive_fast;
 369         if (new_fast & 0x02)
 370                 new_fast &= ~0x02;
 371
 372 #ifdef HPT_DELAY_INTERRUPT
 373         if (new_fast & 0x01)
 374                 new_fast &= ~0x01;
 375 #else
 376         if ((new_fast & 0x01) == 0)
 377                 new_fast |= 0x01;
 378 #endif
 379         if (new_fast != drive_fast)
 380                 pci_write_config_byte(dev, regfast, new_fast);
 381
 382         list_conf = pci_bus_clock_list(speed,
 383                                        (struct chipset_bus_clock_list_entry *)
 384                                        pci_get_drvdata(dev));
 385
 386         pci_read_config_dword(dev, drive_pci, &drive_conf);
 387         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 388
 389         if (speed < XFER_MW_DMA_0) {
 390                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 391         }
 392
 393         pci_write_config_dword(dev, drive_pci, list_conf);
 394
 395         return ide_config_drive_speed(drive, speed);
 396 }
 397
 398 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 399 {
 400         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 401         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 402 //      u8 speed        = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
 403         u8 regfast      = (HWIF(drive)->channel) ? 0x55 : 0x51;
 404         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 405         u32 list_conf   = 0, drive_conf = 0;
 406         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 407
 408         /*
 409          * Disable the "fast interrupt" prediction.
 410          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 411          */
 412         pci_read_config_byte(dev, regfast, &drive_fast);
 413         drive_fast &= ~0x07;
 414         pci_write_config_byte(dev, regfast, drive_fast);
 415
 416         list_conf = pci_bus_clock_list(speed,
 417                         (struct chipset_bus_clock_list_entry *)
 418                                         pci_get_drvdata(dev));
 419         pci_read_config_dword(dev, drive_pci, &drive_conf);
 420         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 421         if (speed < XFER_MW_DMA_0)
 422                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 423         pci_write_config_dword(dev, drive_pci, list_conf);
 424
 425         return ide_config_drive_speed(drive, speed);
 426 }
 427
 428 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 429 {
 430         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 431
 432         if (hpt_minimum_revision(dev, 8))
 433                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 434 #if 0
 435         else if (hpt_minimum_revision(dev, 7))
 436                 hpt371_tune_chipset(drive, speed);
 437         else if (hpt_minimum_revision(dev, 6))
 438                 hpt302_tune_chipset(drive, speed);
 439 #endif
 440         else if (hpt_minimum_revision(dev, 5))
 441                 return hpt372_tune_chipset(drive, speed);
 442         else if (hpt_minimum_revision(dev, 3))
 443                 return hpt370_tune_chipset(drive, speed);
 444         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 445                 return hpt36x_tune_chipset(drive, speed);
 446 }
 447
 448 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 449 {
 450         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 451         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 452 }
 453
 454 /*
 455  * This allows the configuration of ide_pci chipset registers
 456  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 457  * after the drive is reported by the OS.  Initially for designed for
 458  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 459  *
 460  * check_in_drive_lists(drive, bad_ata66_4)
 461  * check_in_drive_lists(drive, bad_ata66_3)
 462  * check_in_drive_lists(drive, bad_ata33)
 463  *
 464  */
 465 static int config_chipset_for_dma (ide_drive_t *drive)
 466 {
 467         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 468
 469         if (!(speed))
 470                 return 0;
 471
 472         (void) hpt3xx_tune_chipset(drive, speed);
 473         return ide_dma_enable(drive);
 474 }
 475
 476 static int hpt3xx_quirkproc (ide_drive_t *drive)
 477 {
 478         return ((int) check_in_drive_lists(drive, quirk_drives));
 479 }
 480
 481 static void hpt3xx_intrproc (ide_drive_t *drive)
 482 {
 483         ide_hwif_t *hwif = HWIF(drive);
 484
 485         if (drive->quirk_list)
 486                 return;
 487         /* drives in the quirk_list may not like intr setups/cleanups */
 488         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 489 }
 490
 491 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 492 {
 493         struct pci_dev *dev = HWIF(drive)->pci_dev;
 494
 495         if (drive->quirk_list) {
 496                 if (hpt_minimum_revision(dev,3)) {
 497                         u8 reg5a = 0;
 498                         pci_read_config_byte(dev, 0x5a, &reg5a);
 499                         if (((reg5a & 0x10) >> 4) != mask)
 500                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 501                 } else {
 502                         if (mask) {
 503                                 disable_irq(HWIF(drive)->irq);
 504                         } else {
 505                                 enable_irq(HWIF(drive)->irq);
 506                         }
 507                 }
 508         } else {
 509                 if (IDE_CONTROL_REG)
 510                         HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
 511                                                  (drive->ctl & ~2),
 512                                                  IDE_CONTROL_REG);
 513         }
 514 }
 515
 516 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 517 {
 518         ide_hwif_t *hwif        = HWIF(drive);
 519         struct hd_driveid *id   = drive->id;
 520
 521         drive->init_speed = 0;
 522
 523         if (id && (id->capability & 1) && drive->autodma) {
 524                 /* Consult the list of known "bad" drives */
 525                 if (__ide_dma_bad_drive(drive))
 526                         goto fast_ata_pio;
 527                 if (id->field_valid & 4) {
 528                         if (id->dma_ultra & hwif->ultra_mask) {
 529                                 /* Force if Capable UltraDMA */
 530                                 int dma = config_chipset_for_dma(drive);
 531                                 if ((id->field_valid & 2) && !dma)
 532                                         goto try_dma_modes;
 533                         }
 534                 } else if (id->field_valid & 2) {
 535 try_dma_modes:
 536                         if (id->dma_mword & hwif->mwdma_mask) {
 537                                 /* Force if Capable regular DMA modes */
 538                                 if (!config_chipset_for_dma(drive))
 539                                         goto no_dma_set;
 540                         }
 541                 } else if (__ide_dma_good_drive(drive) &&
 542                            (id->eide_dma_time < 150)) {
 543                         /* Consult the list of known "good" drives */
 544                         if (!config_chipset_for_dma(drive))
 545                                 goto no_dma_set;
 546                 } else {
 547                         goto fast_ata_pio;
 548                 }
 549                 return hwif->ide_dma_on(drive);
 550         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 551 fast_ata_pio:
 552 no_dma_set:
 553                 hpt3xx_tune_drive(drive, 5);
 554                 return hwif->ide_dma_off_quietly(drive);
 555         }
 556         /* IORDY not supported */
 557         return 0;
 558 }
 559
 560 /*
 561  * This is specific to the HPT366 UDMA bios chipset
 562  * by HighPoint|Triones Technologies, Inc.
 563  */
 564 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 565 {
 566         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 567         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 568
 569         pci_read_config_byte(dev, 0x50, &reg50h);
 570         pci_read_config_byte(dev, 0x52, &reg52h);
 571         pci_read_config_byte(dev, 0x5a, &reg5ah);
 572         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 573                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 574         if (reg5ah & 0x10)
 575                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 576 #if 0
 577         /* how about we flush and reset, mmmkay? */
 578         pci_write_config_byte(dev, 0x51, 0x1F);
 579         /* fall through to a reset */
 580         case ide_dma_begin:
 581         case ide_dma_end:
 582         /* reset the chips state over and over.. */
 583         pci_write_config_byte(dev, 0x51, 0x13);
 584 #endif
 585         return __ide_dma_lostirq(drive);
 586 }
 587
 588 static void hpt370_clear_engine (ide_drive_t *drive)
 589 {
 590         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 591         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 592         udelay(10);
 593 }
 594
 595 static int hpt370_ide_dma_begin (ide_drive_t *drive)
 596 {
 597 #ifdef HPT_RESET_STATE_ENGINE
 598         hpt370_clear_engine(drive);
 599 #endif
 600         return __ide_dma_begin(drive);
 601 }
 602
 603 static int hpt370_ide_dma_end (ide_drive_t *drive)
 604 {
 605         ide_hwif_t *hwif        = HWIF(drive);
 606         u8 dma_stat             = hwif->INB(hwif->dma_status);
 607
 608         if (dma_stat & 0x01) {
 609                 /* wait a little */
 610                 udelay(20);
 611                 dma_stat = hwif->INB(hwif->dma_status);
 612         }
 613         if ((dma_stat & 0x01) != 0)
 614                 /* fallthrough */
 615                 (void) HWIF(drive)->ide_dma_timeout(drive);
 616
 617         return __ide_dma_end(drive);
 618 }
 619
 620 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 621 {
 622         ide_hwif_t *hwif        = HWIF(drive);
 623         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 624         u8 dma_stat = 0, dma_cmd = 0;
 625
 626         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 627         printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 628         hpt370_clear_engine(drive);
 629         /* get dma command mode */
 630         dma_cmd = hwif->INB(hwif->dma_command);
 631         /* stop dma */
 632         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 633         dma_stat = hwif->INB(hwif->dma_status);
 634         /* clear errors */
 635         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 636 }
 637
 638 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 639 {
 640         hpt370_lostirq_timeout(drive);
 641         hpt370_clear_engine(drive);
 642         return __ide_dma_timeout(drive);
 643 }
 644
 645 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 646 {
 647         hpt370_lostirq_timeout(drive);
 648         hpt370_clear_engine(drive);
 649         return __ide_dma_lostirq(drive);
 650 }
 651
 652 /* returns 1 if DMA IRQ issued, 0 otherwise */
 653 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 654 {
 655         ide_hwif_t *hwif        = HWIF(drive);
 656         u16 bfifo               = 0;
 657         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 658         u8 dma_stat;
 659
 660         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 661         if (bfifo & 0x1FF) {
 662 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 663                 return 0;
 664         }
 665
 666         dma_stat = hwif->INB(hwif->dma_status);
 667         /* return 1 if INTR asserted */
 668         if ((dma_stat & 4) == 4)
 669                 return 1;
 670
 671         if (!drive->waiting_for_dma)
 672                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 673                                 drive->name, __FUNCTION__);
 674         return 0;
 675 }
 676
 677 static int hpt374_ide_dma_end (ide_drive_t *drive)
 678 {
 679         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 680         ide_hwif_t *hwif        = HWIF(drive);
 681         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 682         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 683
 684         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 685         pci_read_config_byte(dev, mscreg, &msc_stat);
 686         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 687                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 688         return __ide_dma_end(drive);
 689 }
 690
 691 /**
 692  *      hpt372n_set_clock       -       perform clock switching dance
 693  *      @drive: Drive to switch
 694  *      @mode: Switching mode (0x21 for write, 0x23 otherwise)
 695  *
 696  *      Switch the DPLL clock on the HPT372N devices. This is a
 697  *      right mess.
 698  */
 699
 700 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
 701 {
 702         ide_hwif_t *hwif        = HWIF(drive);
 703
 704         /* FIXME: should we check for DMA active and BUG() */
 705         /* Tristate the bus */
 706         outb(0x80, hwif->dma_base+0x73);
 707         outb(0x80, hwif->dma_base+0x77);
 708
 709         /* Switch clock and reset channels */
 710         outb(mode, hwif->dma_base+0x7B);
 711         outb(0xC0, hwif->dma_base+0x79);
 712
 713         /* Reset state machines */
 714         outb(0x37, hwif->dma_base+0x70);
 715         outb(0x37, hwif->dma_base+0x74);
 716
 717         /* Complete reset */
 718         outb(0x00, hwif->dma_base+0x79);
 719
 720         /* Reconnect channels to bus */
 721         outb(0x00, hwif->dma_base+0x73);
 722         outb(0x00, hwif->dma_base+0x77);
 723 }
 724
 725 /**
 726  *      hpt372n_rw_disk         -       wrapper for I/O
 727  *      @drive: drive for command
 728  *      @rq: block request structure
 729  *      @block: block number
 730  *
 731  *      This is called when a disk I/O is issued to the 372N instead
 732  *      of the default functionality. We need it because of the clock
 733  *      switching
 734  *
 735  */
 736
 737 static ide_startstop_t hpt372n_rw_disk(ide_drive_t *drive, struct request *rq, sector_t block)
 738 {
 739         int wantclock;
 740
 741         if(rq_data_dir(rq) == READ)
 742                 wantclock = 0x21;
 743         else
 744                 wantclock = 0x23;
 745
 746         if(HWIF(drive)->config_data != wantclock)
 747         {
 748                 hpt372n_set_clock(drive, wantclock);
 749                 HWIF(drive)->config_data = wantclock;
 750         }
 751         return __ide_do_rw_disk(drive, rq, block);
 752 }
 753
 754 /*
 755  * Since SUN Cobalt is attempting to do this operation, I should disclose
 756  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 757  * HOTSWAP ATA Infrastructure.
 758  */
 759
 760 static void hpt3xx_reset (ide_drive_t *drive)
 761 {
 762 #if 0
 763         unsigned long high_16   = pci_resource_start(HWIF(drive)->pci_dev, 4);
 764         u8 reset        = (HWIF(drive)->channel) ? 0x80 : 0x40;
 765         u8 reg59h       = 0;
 766
 767         pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
 768         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
 769         pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
 770 #endif
 771 }
 772
 773 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 774 {
 775         ide_hwif_t *hwif        = HWIF(drive);
 776         struct pci_dev *dev     = hwif->pci_dev;
 777         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 778         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 779
 780 //      hwif->bus_state = state;
 781
 782         pci_read_config_byte(dev, 0x59, &reg59h);
 783         pci_read_config_byte(dev, state_reg, &regXXh);
 784
 785         if (state) {
 786                 (void) ide_do_reset(drive);
 787                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 788                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 789         } else {
 790                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 791                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 792                 (void) ide_do_reset(drive);
 793         }
 794         return 0;
 795 }
 796
 797 /*
 798  * set/get power state for a drive.
 799  * turning the power off does the following things:
 800  *   1) soft-reset the drive
 801  *   2) tri-states the ide bus
 802  *
 803  * when we turn things back on, we need to re-initialize things.
 804  */
 805 #define TRISTATE_BIT  0x8000
 806 static int hpt370_busproc(ide_drive_t * drive, int state)
 807 {
 808         ide_hwif_t *hwif        = HWIF(drive);
 809         struct pci_dev *dev     = hwif->pci_dev;
 810         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 811         u16 tri_reg;
 812
 813         hwif->bus_state = state;
 814
 815         if (hwif->channel) {
 816                 /* secondary channel */
 817                 tristate = 0x56;
 818                 resetmask = 0x80;
 819         } else {
 820                 /* primary channel */
 821                 tristate = 0x52;
 822                 resetmask = 0x40;
 823         }
 824
 825         /* grab status */
 826         pci_read_config_word(dev, tristate, &tri_reg);
 827         pci_read_config_byte(dev, 0x59, &bus_reg);
 828
 829         /* set the state. we don't set it if we don't need to do so.
 830          * make sure that the drive knows that it has failed if it's off */
 831         switch (state) {
 832         case BUSSTATE_ON:
 833                 hwif->drives[0].failures = 0;
 834                 hwif->drives[1].failures = 0;
 835                 if ((bus_reg & resetmask) == 0)
 836                         return 0;
 837                 tri_reg &= ~TRISTATE_BIT;
 838                 bus_reg &= ~resetmask;
 839                 break;
 840         case BUSSTATE_OFF:
 841                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 842                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 843                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 844                         return 0;
 845                 tri_reg &= ~TRISTATE_BIT;
 846                 bus_reg |= resetmask;
 847                 break;
 848         case BUSSTATE_TRISTATE:
 849                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 850                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 851                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
 852                         return 0;
 853                 tri_reg |= TRISTATE_BIT;
 854                 bus_reg |= resetmask;
 855                 break;
 856         }
 857         pci_write_config_byte(dev, 0x59, bus_reg);
 858         pci_write_config_word(dev, tristate, tri_reg);
 859
 860         return 0;
 861 }
 862
 863 static int __devinit init_hpt37x(struct pci_dev *dev)
 864 {
 865         int adjust, i;
 866         u16 freq;
 867         u32 pll;
 868         u8 reg5bh;
 869         u8 reg5ah = 0;
 870         unsigned long dmabase = pci_resource_start(dev, 4);
 871         u8 did, rid;
 872         int is_372n = 0;
 873
 874         pci_read_config_byte(dev, 0x5a, &reg5ah);
 875         /* interrupt force enable */
 876         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
 877
 878         if(dmabase)
 879         {
 880                 did = inb(dmabase + 0x22);
 881                 rid = inb(dmabase + 0x28);
 882
 883                 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
 884                         is_372n = 1;
 885         }
 886
 887         /*
 888          * default to pci clock. make sure MA15/16 are set to output
 889          * to prevent drives having problems with 40-pin cables.
 890          */
 891         pci_write_config_byte(dev, 0x5b, 0x23);
 892
 893         /*
 894          * set up the PLL. we need to adjust it so that it's stable.
 895          * freq = Tpll * 192 / Tpci
 896          *
 897          * Todo. For non x86 should probably check the dword is
 898          * set to 0xABCDExxx indicating the BIOS saved f_CNT
 899          */
 900         pci_read_config_word(dev, 0x78, &freq);
 901         freq &= 0x1FF;
 902
 903         /*
 904          * The 372N uses different PCI clock information and has
 905          * some other complications
 906          *      On PCI33 timing we must clock switch
 907          *      On PCI66 timing we must NOT use the PCI clock
 908          *
 909          * Currently we always set up the PLL for the 372N
 910          */
 911
 912         pci_set_drvdata(dev, NULL);
 913
 914         if(is_372n)
 915         {
 916                 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
 917                 if(freq < 0x55)
 918                         pll = F_LOW_PCI_33;
 919                 else if(freq < 0x70)
 920                         pll = F_LOW_PCI_40;
 921                 else if(freq < 0x7F)
 922                         pll = F_LOW_PCI_50;
 923                 else
 924                         pll = F_LOW_PCI_66;
 925
 926                 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
 927
 928                 /* We always use the pll not the PCI clock on 372N */
 929         }
 930         else
 931         {
 932                 if(freq < 0x9C)
 933                         pll = F_LOW_PCI_33;
 934                 else if(freq < 0xb0)
 935                         pll = F_LOW_PCI_40;
 936                 else if(freq <0xc8)
 937                         pll = F_LOW_PCI_50;
 938                 else
 939                         pll = F_LOW_PCI_66;
 940
 941                 if (pll == F_LOW_PCI_33) {
 942                         if (hpt_minimum_revision(dev,8))
 943                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
 944                         else if (hpt_minimum_revision(dev,5))
 945                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
 946                         else if (hpt_minimum_revision(dev,4))
 947                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
 948                         else
 949                                 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
 950                         printk("HPT37X: using 33MHz PCI clock\n");
 951                 } else if (pll == F_LOW_PCI_40) {
 952                         /* Unsupported */
 953                 } else if (pll == F_LOW_PCI_50) {
 954                         if (hpt_minimum_revision(dev,8))
 955                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 956                         else if (hpt_minimum_revision(dev,5))
 957                                 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
 958                         else if (hpt_minimum_revision(dev,4))
 959                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 960                         else
 961                                 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
 962                         printk("HPT37X: using 50MHz PCI clock\n");
 963                 } else {
 964                         if (hpt_minimum_revision(dev,8))
 965                         {
 966                                 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
 967                         }
 968                         else if (hpt_minimum_revision(dev,5))
 969                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
 970                         else if (hpt_minimum_revision(dev,4))
 971                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
 972                         else
 973                                 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
 974                         printk("HPT37X: using 66MHz PCI clock\n");
 975                 }
 976         }
 977
 978         /*
 979          * only try the pll if we don't have a table for the clock
 980          * speed that we're running at. NOTE: the internal PLL will
 981          * result in slow reads when using a 33MHz PCI clock. we also
 982          * don't like to use the PLL because it will cause glitches
 983          * on PRST/SRST when the HPT state engine gets reset.
 984          */
 985         if (pci_get_drvdata(dev))
 986                 goto init_hpt37X_done;
 987
 988         /*
 989          * adjust PLL based upon PCI clock, enable it, and wait for
 990          * stabilization.
 991          */
 992         adjust = 0;
 993         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
 994         while (adjust++ < 6) {
 995                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
 996                                        pll | 0x100);
 997
 998                 /* wait for clock stabilization */
 999                 for (i = 0; i < 0x50000; i++) {
1000                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1001                         if (reg5bh & 0x80) {
1002                                 /* spin looking for the clock to destabilize */
1003                                 for (i = 0; i < 0x1000; ++i) {
1004                                         pci_read_config_byte(dev, 0x5b,
1005                                                              &reg5bh);
1006                                         if ((reg5bh & 0x80) == 0)
1007                                                 goto pll_recal;
1008                                 }
1009                                 pci_read_config_dword(dev, 0x5c, &pll);
1010                                 pci_write_config_dword(dev, 0x5c,
1011                                                        pll & ~0x100);
1012                                 pci_write_config_byte(dev, 0x5b, 0x21);
1013                                 if (hpt_minimum_revision(dev,8))
1014                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1015                                 else if (hpt_minimum_revision(dev,5))
1016                                         pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1017                                 else if (hpt_minimum_revision(dev,4))
1018                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1019                                 else
1020                                         pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1021                                 printk("HPT37X: using 50MHz internal PLL\n");
1022                                 goto init_hpt37X_done;
1023                         }
1024                 }
1025 pll_recal:
1026                 if (adjust & 1)
1027                         pll -= (adjust >> 1);
1028                 else
1029                         pll += (adjust >> 1);
1030         }
1031
1032 init_hpt37X_done:
1033         /* reset state engine */
1034         pci_write_config_byte(dev, 0x50, 0x37);
1035         pci_write_config_byte(dev, 0x54, 0x37);
1036         udelay(100);
1037         return 0;
1038 }
1039
1040 static int __devinit init_hpt366(struct pci_dev *dev)
1041 {
1042         u32 reg1        = 0;
1043         u8 drive_fast   = 0;
1044
1045         /*
1046          * Disable the "fast interrupt" prediction.
1047          */
1048         pci_read_config_byte(dev, 0x51, &drive_fast);
1049         if (drive_fast & 0x80)
1050                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1051         pci_read_config_dword(dev, 0x40, &reg1);
1052
1053         /* detect bus speed by looking at control reg timing: */
1054         switch((reg1 >> 8) & 7) {
1055                 case 5:
1056                         pci_set_drvdata(dev, (void *) forty_base_hpt366);
1057                         break;
1058                 case 9:
1059                         pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1060                         break;
1061                 case 7:
1062                 default:
1063                         pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1064                         break;
1065         }
1066
1067         if (!pci_get_drvdata(dev))
1068         {
1069                 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1070                 pci_set_drvdata(dev, NULL);
1071         }
1072         return 0;
1073 }
1074
1075 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1076 {
1077         int ret = 0;
1078         u8 test = 0;
1079
1080         if (dev->resource[PCI_ROM_RESOURCE].start)
1081                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1082                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1083
1084         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1085         if (test != (L1_CACHE_BYTES / 4))
1086                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1087                         (L1_CACHE_BYTES / 4));
1088
1089         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1090         if (test != 0x78)
1091                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1092
1093         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1094         if (test != 0x08)
1095                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1096
1097         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1098         if (test != 0x08)
1099                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1100
1101         if (hpt_minimum_revision(dev, 3)) {
1102                 ret = init_hpt37x(dev);
1103         } else {
1104                 ret =init_hpt366(dev);
1105         }
1106         if (ret)
1107                 return ret;
1108
1109 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
1110         hpt_devs[n_hpt_devs++] = dev;
1111
1112         if (!hpt366_proc) {
1113                 hpt366_proc = 1;
1114                 ide_pci_create_host_proc("hpt366", hpt366_get_info);
1115         }
1116 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
1117
1118         return dev->irq;
1119 }
1120
1121 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1122 {
1123         struct pci_dev *dev             = hwif->pci_dev;
1124         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1125         u8 did, rid;
1126         unsigned long dmabase           = hwif->dma_base;
1127         int is_372n = 0;
1128
1129         if(dmabase)
1130         {
1131                 did = inb(dmabase + 0x22);
1132                 rid = inb(dmabase + 0x28);
1133
1134                 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1135                         is_372n = 1;
1136         }
1137
1138         hwif->tuneproc                  = &hpt3xx_tune_drive;
1139         hwif->speedproc                 = &hpt3xx_tune_chipset;
1140         hwif->quirkproc                 = &hpt3xx_quirkproc;
1141         hwif->intrproc                  = &hpt3xx_intrproc;
1142         hwif->maskproc                  = &hpt3xx_maskproc;
1143
1144         if(is_372n)
1145                 hwif->rw_disk = &hpt372n_rw_disk;
1146
1147         /*
1148          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1149          * address lines to access an external eeprom.  To read valid
1150          * cable detect state the pins must be enabled as inputs.
1151          */
1152         if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1153                 /*
1154                  * HPT374 PCI function 1
1155                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1156                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1157                  */
1158                 u16 mcr3, mcr6;
1159                 pci_read_config_word(dev, 0x52, &mcr3);
1160                 pci_read_config_word(dev, 0x56, &mcr6);
1161                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1162                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1163                 /* now read cable id register */
1164                 pci_read_config_byte(dev, 0x5a, &ata66);
1165                 pci_write_config_word(dev, 0x52, mcr3);
1166                 pci_write_config_word(dev, 0x56, mcr6);
1167         } else if (hpt_minimum_revision(dev, 3)) {
1168                 /*
1169                  * HPT370/372 and 374 pcifn 0
1170                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1171                  */
1172                 u8 scr2;
1173                 pci_read_config_byte(dev, 0x5b, &scr2);
1174                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1175                 /* now read cable id register */
1176                 pci_read_config_byte(dev, 0x5a, &ata66);
1177                 pci_write_config_byte(dev, 0x5b, scr2);
1178         } else {
1179                 pci_read_config_byte(dev, 0x5a, &ata66);
1180         }
1181
1182 #ifdef DEBUG
1183         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1184                 ata66, (ata66 & regmask) ? "33" : "66",
1185                 PCI_FUNC(hwif->pci_dev->devfn));
1186 #endif /* DEBUG */
1187
1188 #ifdef HPT_SERIALIZE_IO
1189         /* serialize access to this device */
1190         if (hwif->mate)
1191                 hwif->serialized = hwif->mate->serialized = 1;
1192 #endif
1193
1194         if (hpt_minimum_revision(dev,3)) {
1195                 u8 reg5ah = 0;
1196                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1197                 /*
1198                  * set up ioctl for power status.
1199                  * note: power affects both
1200                  * drives on each channel
1201                  */
1202                 hwif->resetproc = &hpt3xx_reset;
1203                 hwif->busproc   = &hpt370_busproc;
1204 //              hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1205         } else if (hpt_minimum_revision(dev,2)) {
1206                 hwif->resetproc = &hpt3xx_reset;
1207                 hwif->busproc   = &hpt3xx_tristate;
1208         } else {
1209                 hwif->resetproc = &hpt3xx_reset;
1210                 hwif->busproc   = &hpt3xx_tristate;
1211         }
1212
1213         if (!hwif->dma_base) {
1214                 hwif->drives[0].autotune = 1;
1215                 hwif->drives[1].autotune = 1;
1216                 return;
1217         }
1218
1219         hwif->ultra_mask = 0x7f;
1220         hwif->mwdma_mask = 0x07;
1221
1222         if (!(hwif->udma_four))
1223                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1224         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1225
1226         if (hpt_minimum_revision(dev,8)) {
1227                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1228                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1229         } else if (hpt_minimum_revision(dev,5)) {
1230                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1231                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1232         } else if (hpt_minimum_revision(dev,3)) {
1233                 hwif->ide_dma_begin = &hpt370_ide_dma_begin;
1234                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1235                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1236                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1237         } else if (hpt_minimum_revision(dev,2))
1238                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1239         else
1240                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1241
1242         if (!noautodma)
1243                 hwif->autodma = 1;
1244         hwif->drives[0].autodma = hwif->autodma;
1245         hwif->drives[1].autodma = hwif->autodma;
1246 }
1247
1248 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1249 {
1250         u8 masterdma    = 0, slavedma = 0;
1251         u8 dma_new      = 0, dma_old = 0;
1252         u8 primary      = hwif->channel ? 0x4b : 0x43;
1253         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1254         unsigned long flags;
1255
1256         if (!dmabase)
1257                 return;
1258
1259         if(pci_get_drvdata(hwif->pci_dev) == NULL)
1260         {
1261                 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1262                 return;
1263         }
1264
1265         dma_old = hwif->INB(dmabase+2);
1266
1267         local_irq_save(flags);
1268
1269         dma_new = dma_old;
1270         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1271         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1272
1273         if (masterdma & 0x30)   dma_new |= 0x20;
1274         if (slavedma & 0x30)    dma_new |= 0x40;
1275         if (dma_new != dma_old)
1276                 hwif->OUTB(dma_new, dmabase+2);
1277
1278         local_irq_restore(flags);
1279
1280         ide_setup_dma(hwif, dmabase, 8);
1281 }
1282
1283 static void __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1284 {
1285         struct pci_dev *findev = NULL;
1286
1287         if (PCI_FUNC(dev->devfn) & 1)
1288                 return;
1289
1290         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1291                 if ((findev->vendor == dev->vendor) &&
1292                     (findev->device == dev->device) &&
1293                     ((findev->devfn - dev->devfn) == 1) &&
1294                     (PCI_FUNC(findev->devfn) & 1)) {
1295                         if (findev->irq != dev->irq) {
1296                                 /* FIXME: we need a core pci_set_interrupt() */
1297                                 findev->irq = dev->irq;
1298                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1299                                         "fixed.\n", d->name);
1300                         }
1301                         ide_setup_pci_devices(dev, findev, d);
1302                         return;
1303                 }
1304         }
1305         ide_setup_pci_device(dev, d);
1306 }
1307
1308 static void __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1309 {
1310         ide_setup_pci_device(dev, d);
1311 }
1312
1313 static void __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1314 {
1315         struct pci_dev *findev = NULL;
1316         u8 pin1 = 0, pin2 = 0;
1317         unsigned int class_rev;
1318         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1319                                  "HPT370", "HPT370A", "HPT372",
1320                                  "HPT372N" };
1321
1322         if (PCI_FUNC(dev->devfn) & 1)
1323                 return;
1324
1325         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1326         class_rev &= 0xff;
1327
1328         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1329                 class_rev = 6;
1330
1331         if(class_rev <= 6)
1332                 d->name = chipset_names[class_rev];
1333
1334         switch(class_rev) {
1335                 case 6:
1336                 case 5:
1337                 case 4:
1338                 case 3: ide_setup_pci_device(dev, d);
1339                         return;
1340                 default:        break;
1341         }
1342
1343         d->channels = 1;
1344
1345         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1346         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1347                 if ((findev->vendor == dev->vendor) &&
1348                     (findev->device == dev->device) &&
1349                     ((findev->devfn - dev->devfn) == 1) &&
1350                     (PCI_FUNC(findev->devfn) & 1)) {
1351                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1352                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1353                                 d->bootable = ON_BOARD;
1354                                 printk("%s: onboard version of chipset, "
1355                                         "pin1=%d pin2=%d\n", d->name,
1356                                         pin1, pin2);
1357                         }
1358                         ide_setup_pci_devices(dev, findev, d);
1359                         return;
1360                 }
1361         }
1362         ide_setup_pci_device(dev, d);
1363 }
1364
1365
1366 /**
1367  *      hpt366_init_one -       called when an HPT366 is found
1368  *      @dev: the hpt366 device
1369  *      @id: the matching pci id
1370  *
1371  *      Called when the PCI registration layer (or the IDE initialization)
1372  *      finds a device matching our IDE device tables.
1373  */
1374
1375 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1376 {
1377         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1378
1379         d->init_setup(dev, d);
1380         return 0;
1381 }
1382
1383 static struct pci_device_id hpt366_pci_tbl[] = {
1384         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1385         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1386         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1387         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1388         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1389         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1390         { 0, },
1391 };
1392 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1393
1394 static struct pci_driver driver = {
1395         .name           = "HPT366_IDE",
1396         .id_table       = hpt366_pci_tbl,
1397         .probe          = hpt366_init_one,
1398 };
1399
1400 static int hpt366_ide_init(void)
1401 {
1402         return ide_pci_register_driver(&driver);
1403 }
1404
1405 module_init(hpt366_ide_init);
1406
1407 MODULE_AUTHOR("Andre Hedrick");
1408 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1409 MODULE_LICENSE("GPL");