drivers/ide/pci/hpt366.h

   1 #ifndef HPT366_H
   2 #define HPT366_H
   3
   4 #include <linux/config.h>
   5 #include <linux/pci.h>
   6 #include <linux/ide.h>
   7
   8 /* various tuning parameters */
   9 #define HPT_RESET_STATE_ENGINE
  10 #undef HPT_DELAY_INTERRUPT
  11 #undef HPT_SERIALIZE_IO
  12
  13 static const char *quirk_drives[] = {
  14         "QUANTUM FIREBALLlct08 08",
  15         "QUANTUM FIREBALLP KA6.4",
  16         "QUANTUM FIREBALLP LM20.4",
  17         "QUANTUM FIREBALLP LM20.5",
  18         NULL
  19 };
  20
  21 static const char *bad_ata100_5[] = {
  22         "IBM-DTLA-307075",
  23         "IBM-DTLA-307060",
  24         "IBM-DTLA-307045",
  25         "IBM-DTLA-307030",
  26         "IBM-DTLA-307020",
  27         "IBM-DTLA-307015",
  28         "IBM-DTLA-305040",
  29         "IBM-DTLA-305030",
  30         "IBM-DTLA-305020",
  31         "IC35L010AVER07-0",
  32         "IC35L020AVER07-0",
  33         "IC35L030AVER07-0",
  34         "IC35L040AVER07-0",
  35         "IC35L060AVER07-0",
  36         "WDC AC310200R",
  37         NULL
  38 };
  39
  40 static const char *bad_ata66_4[] = {
  41         "IBM-DTLA-307075",
  42         "IBM-DTLA-307060",
  43         "IBM-DTLA-307045",
  44         "IBM-DTLA-307030",
  45         "IBM-DTLA-307020",
  46         "IBM-DTLA-307015",
  47         "IBM-DTLA-305040",
  48         "IBM-DTLA-305030",
  49         "IBM-DTLA-305020",
  50         "IC35L010AVER07-0",
  51         "IC35L020AVER07-0",
  52         "IC35L030AVER07-0",
  53         "IC35L040AVER07-0",
  54         "IC35L060AVER07-0",
  55         "WDC AC310200R",
  56         NULL
  57 };
  58
  59 static const char *bad_ata66_3[] = {
  60         "WDC AC310200R",
  61         NULL
  62 };
  63
  64 static const char *bad_ata33[] = {
  65         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
  66         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  67         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  68         "Maxtor 90510D4",
  69         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  70         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  71         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  72         NULL
  73 };
  74
  75 struct chipset_bus_clock_list_entry {
  76         byte            xfer_speed;
  77         unsigned int    chipset_settings;
  78 };
  79
  80 /* key for bus clock timings
  81  * bit
  82  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  83  *        DMA. cycles = value + 1
  84  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  85  *        DMA. cycles = value + 1
  86  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  87  *        register access.
  88  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  89  *        register access.
  90  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  91  *        during task file register access.
  92  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  93  *        xfer.
  94  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  95  *        register access.
  96  * 28     UDMA enable
  97  * 29     DMA enable
  98  * 30     PIO_MST enable. if set, the chip is in bus master mode during
  99  *        PIO.
 100  * 31     FIFO enable.
 101  */
 102 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
 103         {       XFER_UDMA_4,    0x900fd943      },
 104         {       XFER_UDMA_3,    0x900ad943      },
 105         {       XFER_UDMA_2,    0x900bd943      },
 106         {       XFER_UDMA_1,    0x9008d943      },
 107         {       XFER_UDMA_0,    0x9008d943      },
 108
 109         {       XFER_MW_DMA_2,  0xa008d943      },
 110         {       XFER_MW_DMA_1,  0xa010d955      },
 111         {       XFER_MW_DMA_0,  0xa010d9fc      },
 112
 113         {       XFER_PIO_4,     0xc008d963      },
 114         {       XFER_PIO_3,     0xc010d974      },
 115         {       XFER_PIO_2,     0xc010d997      },
 116         {       XFER_PIO_1,     0xc010d9c7      },
 117         {       XFER_PIO_0,     0xc018d9d9      },
 118         {       0,              0x0120d9d9      }
 119 };
 120
 121 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
 122         {       XFER_UDMA_4,    0x90c9a731      },
 123         {       XFER_UDMA_3,    0x90cfa731      },
 124         {       XFER_UDMA_2,    0x90caa731      },
 125         {       XFER_UDMA_1,    0x90cba731      },
 126         {       XFER_UDMA_0,    0x90c8a731      },
 127
 128         {       XFER_MW_DMA_2,  0xa0c8a731      },
 129         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
 130         {       XFER_MW_DMA_0,  0xa0c8a797      },
 131
 132         {       XFER_PIO_4,     0xc0c8a731      },
 133         {       XFER_PIO_3,     0xc0c8a742      },
 134         {       XFER_PIO_2,     0xc0d0a753      },
 135         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
 136         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
 137         {       0,              0x0120a7a7      }
 138 };
 139
 140 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
 141
 142         {       XFER_UDMA_4,    0x90c98521      },
 143         {       XFER_UDMA_3,    0x90cf8521      },
 144         {       XFER_UDMA_2,    0x90cf8521      },
 145         {       XFER_UDMA_1,    0x90cb8521      },
 146         {       XFER_UDMA_0,    0x90cb8521      },
 147
 148         {       XFER_MW_DMA_2,  0xa0ca8521      },
 149         {       XFER_MW_DMA_1,  0xa0ca8532      },
 150         {       XFER_MW_DMA_0,  0xa0ca8575      },
 151
 152         {       XFER_PIO_4,     0xc0ca8521      },
 153         {       XFER_PIO_3,     0xc0ca8532      },
 154         {       XFER_PIO_2,     0xc0ca8542      },
 155         {       XFER_PIO_1,     0xc0d08572      },
 156         {       XFER_PIO_0,     0xc0d08585      },
 157         {       0,              0x01208585      }
 158 };
 159
 160 /* from highpoint documentation. these are old values */
 161 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
 162 /*      {       XFER_UDMA_5,    0x1A85F442,     0x16454e31      }, */
 163         {       XFER_UDMA_5,    0x16454e31      },
 164         {       XFER_UDMA_4,    0x16454e31      },
 165         {       XFER_UDMA_3,    0x166d4e31      },
 166         {       XFER_UDMA_2,    0x16494e31      },
 167         {       XFER_UDMA_1,    0x164d4e31      },
 168         {       XFER_UDMA_0,    0x16514e31      },
 169
 170         {       XFER_MW_DMA_2,  0x26514e21      },
 171         {       XFER_MW_DMA_1,  0x26514e33      },
 172         {       XFER_MW_DMA_0,  0x26514e97      },
 173
 174         {       XFER_PIO_4,     0x06514e21      },
 175         {       XFER_PIO_3,     0x06514e22      },
 176         {       XFER_PIO_2,     0x06514e33      },
 177         {       XFER_PIO_1,     0x06914e43      },
 178         {       XFER_PIO_0,     0x06914e57      },
 179         {       0,              0x06514e57      }
 180 };
 181
 182 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
 183         {       XFER_UDMA_5,    0x14846231      },
 184         {       XFER_UDMA_4,    0x14886231      },
 185         {       XFER_UDMA_3,    0x148c6231      },
 186         {       XFER_UDMA_2,    0x148c6231      },
 187         {       XFER_UDMA_1,    0x14906231      },
 188         {       XFER_UDMA_0,    0x14986231      },
 189
 190         {       XFER_MW_DMA_2,  0x26514e21      },
 191         {       XFER_MW_DMA_1,  0x26514e33      },
 192         {       XFER_MW_DMA_0,  0x26514e97      },
 193
 194         {       XFER_PIO_4,     0x06514e21      },
 195         {       XFER_PIO_3,     0x06514e22      },
 196         {       XFER_PIO_2,     0x06514e33      },
 197         {       XFER_PIO_1,     0x06914e43      },
 198         {       XFER_PIO_0,     0x06914e57      },
 199         {       0,              0x06514e57      }
 200 };
 201
 202 /* these are the current (4 sep 2001) timings from highpoint */
 203 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
 204         {       XFER_UDMA_5,    0x12446231      },
 205         {       XFER_UDMA_4,    0x12446231      },
 206         {       XFER_UDMA_3,    0x126c6231      },
 207         {       XFER_UDMA_2,    0x12486231      },
 208         {       XFER_UDMA_1,    0x124c6233      },
 209         {       XFER_UDMA_0,    0x12506297      },
 210
 211         {       XFER_MW_DMA_2,  0x22406c31      },
 212         {       XFER_MW_DMA_1,  0x22406c33      },
 213         {       XFER_MW_DMA_0,  0x22406c97      },
 214
 215         {       XFER_PIO_4,     0x06414e31      },
 216         {       XFER_PIO_3,     0x06414e42      },
 217         {       XFER_PIO_2,     0x06414e53      },
 218         {       XFER_PIO_1,     0x06814e93      },
 219         {       XFER_PIO_0,     0x06814ea7      },
 220         {       0,              0x06814ea7      }
 221 };
 222
 223 /* 2x 33MHz timings */
 224 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
 225         {       XFER_UDMA_5,    0x1488e673       },
 226         {       XFER_UDMA_4,    0x1488e673       },
 227         {       XFER_UDMA_3,    0x1498e673       },
 228         {       XFER_UDMA_2,    0x1490e673       },
 229         {       XFER_UDMA_1,    0x1498e677       },
 230         {       XFER_UDMA_0,    0x14a0e73f       },
 231
 232         {       XFER_MW_DMA_2,  0x2480fa73       },
 233         {       XFER_MW_DMA_1,  0x2480fa77       },
 234         {       XFER_MW_DMA_0,  0x2480fb3f       },
 235
 236         {       XFER_PIO_4,     0x0c82be73       },
 237         {       XFER_PIO_3,     0x0c82be95       },
 238         {       XFER_PIO_2,     0x0c82beb7       },
 239         {       XFER_PIO_1,     0x0d02bf37       },
 240         {       XFER_PIO_0,     0x0d02bf5f       },
 241         {       0,              0x0d02bf5f       }
 242 };
 243
 244 static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
 245         {       XFER_UDMA_5,    0x12848242      },
 246         {       XFER_UDMA_4,    0x12ac8242      },
 247         {       XFER_UDMA_3,    0x128c8242      },
 248         {       XFER_UDMA_2,    0x120c8242      },
 249         {       XFER_UDMA_1,    0x12148254      },
 250         {       XFER_UDMA_0,    0x121882ea      },
 251
 252         {       XFER_MW_DMA_2,  0x22808242      },
 253         {       XFER_MW_DMA_1,  0x22808254      },
 254         {       XFER_MW_DMA_0,  0x228082ea      },
 255
 256         {       XFER_PIO_4,     0x0a81f442      },
 257         {       XFER_PIO_3,     0x0a81f443      },
 258         {       XFER_PIO_2,     0x0a81f454      },
 259         {       XFER_PIO_1,     0x0ac1f465      },
 260         {       XFER_PIO_0,     0x0ac1f48a      },
 261         {       0,              0x0ac1f48a      }
 262 };
 263
 264 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
 265         {       XFER_UDMA_6,    0x1c81dc62      },
 266         {       XFER_UDMA_5,    0x1c6ddc62      },
 267         {       XFER_UDMA_4,    0x1c8ddc62      },
 268         {       XFER_UDMA_3,    0x1c8edc62      },      /* checkme */
 269         {       XFER_UDMA_2,    0x1c91dc62      },
 270         {       XFER_UDMA_1,    0x1c9adc62      },      /* checkme */
 271         {       XFER_UDMA_0,    0x1c82dc62      },      /* checkme */
 272
 273         {       XFER_MW_DMA_2,  0x2c829262      },
 274         {       XFER_MW_DMA_1,  0x2c829266      },      /* checkme */
 275         {       XFER_MW_DMA_0,  0x2c82922e      },      /* checkme */
 276
 277         {       XFER_PIO_4,     0x0c829c62      },
 278         {       XFER_PIO_3,     0x0c829c84      },
 279         {       XFER_PIO_2,     0x0c829ca6      },
 280         {       XFER_PIO_1,     0x0d029d26      },
 281         {       XFER_PIO_0,     0x0d029d5e      },
 282         {       0,              0x0d029d5e      }
 283 };
 284
 285 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
 286         {       XFER_UDMA_5,    0x12848242      },
 287         {       XFER_UDMA_4,    0x12ac8242      },
 288         {       XFER_UDMA_3,    0x128c8242      },
 289         {       XFER_UDMA_2,    0x120c8242      },
 290         {       XFER_UDMA_1,    0x12148254      },
 291         {       XFER_UDMA_0,    0x121882ea      },
 292
 293         {       XFER_MW_DMA_2,  0x22808242      },
 294         {       XFER_MW_DMA_1,  0x22808254      },
 295         {       XFER_MW_DMA_0,  0x228082ea      },
 296
 297         {       XFER_PIO_4,     0x0a81f442      },
 298         {       XFER_PIO_3,     0x0a81f443      },
 299         {       XFER_PIO_2,     0x0a81f454      },
 300         {       XFER_PIO_1,     0x0ac1f465      },
 301         {       XFER_PIO_0,     0x0ac1f48a      },
 302         {       0,              0x0a81f443      }
 303 };
 304
 305 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
 306         {       XFER_UDMA_6,    0x1c869c62      },
 307         {       XFER_UDMA_5,    0x1cae9c62      },
 308         {       XFER_UDMA_4,    0x1c8a9c62      },
 309         {       XFER_UDMA_3,    0x1c8e9c62      },
 310         {       XFER_UDMA_2,    0x1c929c62      },
 311         {       XFER_UDMA_1,    0x1c9a9c62      },
 312         {       XFER_UDMA_0,    0x1c829c62      },
 313
 314         {       XFER_MW_DMA_2,  0x2c829c62      },
 315         {       XFER_MW_DMA_1,  0x2c829c66      },
 316         {       XFER_MW_DMA_0,  0x2c829d2e      },
 317
 318         {       XFER_PIO_4,     0x0c829c62      },
 319         {       XFER_PIO_3,     0x0c829c84      },
 320         {       XFER_PIO_2,     0x0c829ca6      },
 321         {       XFER_PIO_1,     0x0d029d26      },
 322         {       XFER_PIO_0,     0x0d029d5e      },
 323         {       0,              0x0d029d26      }
 324 };
 325
 326 static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
 327         {       XFER_UDMA_6,    0x12808242      },
 328         {       XFER_UDMA_5,    0x12848242      },
 329         {       XFER_UDMA_4,    0x12ac8242      },
 330         {       XFER_UDMA_3,    0x128c8242      },
 331         {       XFER_UDMA_2,    0x120c8242      },
 332         {       XFER_UDMA_1,    0x12148254      },
 333         {       XFER_UDMA_0,    0x121882ea      },
 334
 335         {       XFER_MW_DMA_2,  0x22808242      },
 336         {       XFER_MW_DMA_1,  0x22808254      },
 337         {       XFER_MW_DMA_0,  0x228082ea      },
 338
 339         {       XFER_PIO_4,     0x0a81f442      },
 340         {       XFER_PIO_3,     0x0a81f443      },
 341         {       XFER_PIO_2,     0x0a81f454      },
 342         {       XFER_PIO_1,     0x0ac1f465      },
 343         {       XFER_PIO_0,     0x0ac1f48a      },
 344         {       0,              0x06814e93      }
 345 };
 346
 347 #if 0
 348 static struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
 349         {       XFER_UDMA_6,    },
 350         {       XFER_UDMA_5,    },
 351         {       XFER_UDMA_4,    },
 352         {       XFER_UDMA_3,    },
 353         {       XFER_UDMA_2,    },
 354         {       XFER_UDMA_1,    },
 355         {       XFER_UDMA_0,    },
 356         {       XFER_MW_DMA_2,  },
 357         {       XFER_MW_DMA_1,  },
 358         {       XFER_MW_DMA_0,  },
 359         {       XFER_PIO_4,     },
 360         {       XFER_PIO_3,     },
 361         {       XFER_PIO_2,     },
 362         {       XFER_PIO_1,     },
 363         {       XFER_PIO_0,     },
 364         {       0,      }
 365 };
 366 #endif
 367 #if 0
 368 static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
 369         {       XFER_UDMA_6,    0x12406231      },      /* checkme */
 370         {       XFER_UDMA_5,    0x12446231      },
 371                                 0x14846231
 372         {       XFER_UDMA_4,            0x16814ea7      },
 373                                 0x14886231
 374         {       XFER_UDMA_3,            0x16814ea7      },
 375                                 0x148c6231
 376         {       XFER_UDMA_2,            0x16814ea7      },
 377                                 0x148c6231
 378         {       XFER_UDMA_1,            0x16814ea7      },
 379                                 0x14906231
 380         {       XFER_UDMA_0,            0x16814ea7      },
 381                                 0x14986231
 382         {       XFER_MW_DMA_2,          0x16814ea7      },
 383                                 0x26514e21
 384         {       XFER_MW_DMA_1,          0x16814ea7      },
 385                                 0x26514e97
 386         {       XFER_MW_DMA_0,          0x16814ea7      },
 387                                 0x26514e97
 388         {       XFER_PIO_4,             0x06814ea7      },
 389                                 0x06514e21
 390         {       XFER_PIO_3,             0x06814ea7      },
 391                                 0x06514e22
 392         {       XFER_PIO_2,             0x06814ea7      },
 393                                 0x06514e33
 394         {       XFER_PIO_1,             0x06814ea7      },
 395                                 0x06914e43
 396         {       XFER_PIO_0,             0x06814ea7      },
 397                                 0x06914e57
 398         {       0,              0x06814ea7      }
 399 };
 400 #endif
 401
 402 #define HPT366_DEBUG_DRIVE_INFO         0
 403 #define HPT374_ALLOW_ATA133_6           0
 404 #define HPT371_ALLOW_ATA133_6           0
 405 #define HPT302_ALLOW_ATA133_6           0
 406 #define HPT372_ALLOW_ATA133_6           1
 407 #define HPT370_ALLOW_ATA100_5           1
 408 #define HPT366_ALLOW_ATA66_4            1
 409 #define HPT366_ALLOW_ATA66_3            1
 410 #define HPT366_MAX_DEVS                 8
 411
 412 #define F_LOW_PCI_33      0x23
 413 #define F_LOW_PCI_40      0x29
 414 #define F_LOW_PCI_50      0x2d
 415 #define F_LOW_PCI_66      0x42
 416
 417 static void init_setup_hpt366(struct pci_dev *, ide_pci_device_t *);
 418 static void init_setup_hpt37x(struct pci_dev *, ide_pci_device_t *);
 419 static void init_setup_hpt374(struct pci_dev *, ide_pci_device_t *);
 420 static unsigned int init_chipset_hpt366(struct pci_dev *, const char *);
 421 static void init_hwif_hpt366(ide_hwif_t *);
 422 static void init_iops_hpt366(ide_hwif_t *);
 423 static void init_dma_hpt366(ide_hwif_t *, unsigned long);
 424
 425 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
 426         {       /* 0 */
 427                 .name           = "HPT366",
 428                 .init_setup     = init_setup_hpt366,
 429                 .init_chipset   = init_chipset_hpt366,
 430                 .init_iops      = init_iops_hpt366,
 431                 .init_hwif      = init_hwif_hpt366,
 432                 .init_dma       = init_dma_hpt366,
 433                 .channels       = 2,
 434                 .autodma        = AUTODMA,
 435                 .bootable       = OFF_BOARD,
 436                 .extra          = 240
 437         },{     /* 1 */
 438                 .name           = "HPT372A",
 439                 .init_setup     = init_setup_hpt37x,
 440                 .init_chipset   = init_chipset_hpt366,
 441                 .init_iops      = init_iops_hpt366,
 442                 .init_hwif      = init_hwif_hpt366,
 443                 .init_dma       = init_dma_hpt366,
 444                 .channels       = 2,
 445                 .autodma        = AUTODMA,
 446                 .bootable       = OFF_BOARD,
 447         },{     /* 2 */
 448                 .name           = "HPT302",
 449                 .init_setup     = init_setup_hpt37x,
 450                 .init_chipset   = init_chipset_hpt366,
 451                 .init_iops      = init_iops_hpt366,
 452                 .init_hwif      = init_hwif_hpt366,
 453                 .init_dma       = init_dma_hpt366,
 454                 .channels       = 2,
 455                 .autodma        = AUTODMA,
 456                 .bootable       = OFF_BOARD,
 457         },{     /* 3 */
 458                 .name           = "HPT371",
 459                 .init_setup     = init_setup_hpt37x,
 460                 .init_chipset   = init_chipset_hpt366,
 461                 .init_iops      = init_iops_hpt366,
 462                 .init_hwif      = init_hwif_hpt366,
 463                 .init_dma       = init_dma_hpt366,
 464                 .channels       = 2,
 465                 .autodma        = AUTODMA,
 466                 .bootable       = OFF_BOARD,
 467         },{     /* 4 */
 468                 .name           = "HPT374",
 469                 .init_setup     = init_setup_hpt374,
 470                 .init_chipset   = init_chipset_hpt366,
 471                 .init_iops      = init_iops_hpt366,
 472                 .init_hwif      = init_hwif_hpt366,
 473                 .init_dma       = init_dma_hpt366,
 474                 .channels       = 2,    /* 4 */
 475                 .autodma        = AUTODMA,
 476                 .bootable       = OFF_BOARD,
 477         },{     /* 5 */
 478                 .name           = "HPT372N",
 479                 .init_setup     = init_setup_hpt37x,
 480                 .init_chipset   = init_chipset_hpt366,
 481                 .init_iops      = init_iops_hpt366,
 482                 .init_hwif      = init_hwif_hpt366,
 483                 .init_dma       = init_dma_hpt366,
 484                 .channels       = 2,    /* 4 */
 485                 .autodma        = AUTODMA,
 486                 .bootable       = OFF_BOARD,
 487         }
 488 };
 489
 490 #endif /* HPT366_H */