drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #include "pdc202xx_old.h"
  50
  51 #define PDC202_DEBUG_CABLE      0
  52
  53 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
  54 #include <linux/stat.h>
  55 #include <linux/proc_fs.h>
  56
  57 static u8 pdc202xx_proc = 0;
  58 #define PDC202_MAX_DEVS         5
  59 static struct pci_dev *pdc202_devs[PDC202_MAX_DEVS];
  60 static int n_pdc202_devs;
  61
  62 static char * pdc202xx_info (char *buf, struct pci_dev *dev)
  63 {
  64         char *p = buf;
  65
  66         unsigned long bibma  = pci_resource_start(dev, 4);
  67         u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
  68         u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
  69         u8 hi = 0, lo = 0;
  70
  71         /*
  72          * at that point bibma+0x2 et bibma+0xa are byte registers
  73          * to investigate:
  74          */
  75         u8 c0   = inb_p((u16)bibma + 0x02);
  76         u8 c1   = inb_p((u16)bibma + 0x0a);
  77
  78         u8 sc11 = inb_p((u16)bibma + 0x11);
  79         u8 sc1a = inb_p((u16)bibma + 0x1a);
  80         u8 sc1b = inb_p((u16)bibma + 0x1b);
  81         u8 sc1c = inb_p((u16)bibma + 0x1c);
  82         u8 sc1d = inb_p((u16)bibma + 0x1d);
  83         u8 sc1e = inb_p((u16)bibma + 0x1e);
  84         u8 sc1f = inb_p((u16)bibma + 0x1f);
  85
  86         pci_read_config_word(dev, 0x50, &reg50h);
  87         pci_read_config_dword(dev, 0x60, &reg60h);
  88         pci_read_config_dword(dev, 0x64, &reg64h);
  89         pci_read_config_dword(dev, 0x68, &reg68h);
  90         pci_read_config_dword(dev, 0x6c, &reg6ch);
  91
  92         p += sprintf(p, "\n                                ");
  93         switch(dev->device) {
  94                 case PCI_DEVICE_ID_PROMISE_20267:
  95                         p += sprintf(p, "Ultra100"); break;
  96                 case PCI_DEVICE_ID_PROMISE_20265:
  97                         p += sprintf(p, "Ultra100 on M/B"); break;
  98                 case PCI_DEVICE_ID_PROMISE_20263:
  99                         p += sprintf(p, "FastTrak 66"); break;
 100                 case PCI_DEVICE_ID_PROMISE_20262:
 101                         p += sprintf(p, "Ultra66"); break;
 102                 case PCI_DEVICE_ID_PROMISE_20246:
 103                         p += sprintf(p, "Ultra33");
 104                         reg50h |= 0x0c00;
 105                         break;
 106                 default:
 107                         p += sprintf(p, "Ultra Series"); break;
 108         }
 109         p += sprintf(p, " Chipset.\n");
 110
 111         p += sprintf(p, "------------------------------- General Status "
 112                         "---------------------------------\n");
 113         p += sprintf(p, "Burst Mode                           : %sabled\n",
 114                 (sc1f & 0x01) ? "en" : "dis");
 115         p += sprintf(p, "Host Mode                            : %s\n",
 116                 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
 117         p += sprintf(p, "Bus Clocking                         : %s\n",
 118                 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
 119                 ((sc1f & 0x80) == 0x80) ? "66 External" :
 120                 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
 121         p += sprintf(p, "IO pad select                        : %s mA\n",
 122                 ((sc1c & 0x03) == 0x03) ? "10" :
 123                 ((sc1c & 0x02) == 0x02) ? "8" :
 124                 ((sc1c & 0x01) == 0x01) ? "6" :
 125                 ((sc1c & 0x00) == 0x00) ? "4" : "??");
 126         SPLIT_BYTE(sc1e, hi, lo);
 127         p += sprintf(p, "Status Polling Period                : %d\n", hi);
 128         p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
 129         p += sprintf(p, "--------------- Primary Channel "
 130                         "---------------- Secondary Channel "
 131                         "-------------\n");
 132         p += sprintf(p, "                %s                         %s\n",
 133                 (c0&0x80)?"disabled":"enabled ",
 134                 (c1&0x80)?"disabled":"enabled ");
 135         p += sprintf(p, "66 Clocking     %s                         %s\n",
 136                 (sc11&0x02)?"enabled ":"disabled",
 137                 (sc11&0x08)?"enabled ":"disabled");
 138         p += sprintf(p, "           Mode %s                      Mode %s\n",
 139                 (sc1a & 0x01) ? "MASTER" : "PCI   ",
 140                 (sc1b & 0x01) ? "MASTER" : "PCI   ");
 141         p += sprintf(p, "                %s                     %s\n",
 142                 (sc1d & 0x08) ? "Error       " :
 143                 ((sc1d & 0x05) == 0x05) ? "Not My INTR " :
 144                 (sc1d & 0x04) ? "Interrupting" :
 145                 (sc1d & 0x02) ? "FIFO Full   " :
 146                 (sc1d & 0x01) ? "FIFO Empty  " : "????????????",
 147                 (sc1d & 0x80) ? "Error       " :
 148                 ((sc1d & 0x50) == 0x50) ? "Not My INTR " :
 149                 (sc1d & 0x40) ? "Interrupting" :
 150                 (sc1d & 0x20) ? "FIFO Full   " :
 151                 (sc1d & 0x10) ? "FIFO Empty  " : "????????????");
 152         p += sprintf(p, "--------------- drive0 --------- drive1 "
 153                         "-------- drive0 ---------- drive1 ------\n");
 154         p += sprintf(p, "DMA enabled:    %s              %s "
 155                         "            %s               %s\n",
 156                 (c0&0x20)?"yes":"no ", (c0&0x40)?"yes":"no ",
 157                 (c1&0x20)?"yes":"no ", (c1&0x40)?"yes":"no ");
 158         p += sprintf(p, "DMA Mode:       %s           %s "
 159                         "         %s            %s\n",
 160                 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
 161                 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
 162                 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
 163                 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
 164         p += sprintf(p, "PIO Mode:       %s            %s "
 165                         "          %s            %s\n",
 166                 pdc202xx_pio_verbose(reg60h),
 167                 pdc202xx_pio_verbose(reg64h),
 168                 pdc202xx_pio_verbose(reg68h),
 169                 pdc202xx_pio_verbose(reg6ch));
 170 #if 0
 171         p += sprintf(p, "--------------- Can ATAPI DMA ---------------\n");
 172 #endif
 173         return (char *)p;
 174 }
 175
 176 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
 177 {
 178         char *p = buffer;
 179         int i, len;
 180
 181         for (i = 0; i < n_pdc202_devs; i++) {
 182                 struct pci_dev *dev     = pdc202_devs[i];
 183                 p = pdc202xx_info(buffer, dev);
 184         }
 185         /* p - buffer must be less than 4k! */
 186         len = (p - buffer) - offset;
 187         *addr = buffer + offset;
 188
 189         return len > count ? count : len;
 190 }
 191 #endif  /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
 192
 193
 194 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 195 {
 196         u8 mode;
 197
 198         switch(HWIF(drive)->pci_dev->device) {
 199                 case PCI_DEVICE_ID_PROMISE_20267:
 200                 case PCI_DEVICE_ID_PROMISE_20265:
 201                         mode = 3;
 202                         break;
 203                 case PCI_DEVICE_ID_PROMISE_20263:
 204                 case PCI_DEVICE_ID_PROMISE_20262:
 205                         mode = 2;
 206                         break;
 207                 case PCI_DEVICE_ID_PROMISE_20246:
 208                         return 1;
 209                 default:
 210                         return 0;
 211         }
 212         if (!eighty_ninty_three(drive))
 213                 mode = min(mode, (u8)1);
 214         return mode;
 215 }
 216
 217 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 218 {
 219         struct hd_driveid *id = drive->id;
 220
 221         if (pdc_quirk_drives == list) {
 222                 while (*list) {
 223                         if (strstr(id->model, *list++)) {
 224                                 return 2;
 225                         }
 226                 }
 227         } else {
 228                 while (*list) {
 229                         if (!strcmp(*list++,id->model)) {
 230                                 return 1;
 231                         }
 232                 }
 233         }
 234         return 0;
 235 }
 236
 237 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 238 {
 239         ide_hwif_t *hwif        = HWIF(drive);
 240         struct pci_dev *dev     = hwif->pci_dev;
 241         u8 drive_pci            = 0x60 + (drive->dn << 2);
 242         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 243
 244         u32                     drive_conf;
 245         u8                      AP, BP, CP, DP;
 246         u8                      TA = 0, TB = 0, TC = 0;
 247
 248         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 249                 return -1;
 250
 251         pci_read_config_dword(dev, drive_pci, &drive_conf);
 252         pci_read_config_byte(dev, (drive_pci), &AP);
 253         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 254         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 255         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 256
 257         if (speed < XFER_SW_DMA_0) {
 258                 if ((AP & 0x0F) || (BP & 0x07)) {
 259                         /* clear PIO modes of lower 8421 bits of A Register */
 260                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 261                         pci_read_config_byte(dev, (drive_pci), &AP);
 262
 263                         /* clear PIO modes of lower 421 bits of B Register */
 264                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 265                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 266
 267                         pci_read_config_byte(dev, (drive_pci), &AP);
 268                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 269                 }
 270         } else {
 271                 if ((BP & 0xF0) && (CP & 0x0F)) {
 272                         /* clear DMA modes of upper 842 bits of B Register */
 273                         /* clear PIO forced mode upper 1 bit of B Register */
 274                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 275                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 276
 277                         /* clear DMA modes of lower 8421 bits of C Register */
 278                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 279                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 280                 }
 281         }
 282
 283         pci_read_config_byte(dev, (drive_pci), &AP);
 284         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 285         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 286
 287         switch(speed) {
 288                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 289                 case XFER_UDMA_5:
 290                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 291                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 292                 case XFER_UDMA_3:
 293                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 294                 case XFER_UDMA_0:
 295                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 296                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 297                 case XFER_MW_DMA_0:
 298                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 299                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 300                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 301                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 302                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 303                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 304                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 305                 case XFER_PIO_0:
 306                 default:                TA = 0x09; TB = 0x13; break;
 307         }
 308
 309         if (speed < XFER_SW_DMA_0) {
 310                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 311                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 312         } else {
 313                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 314                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 315         }
 316
 317 #if PDC202XX_DECODE_REGISTER_INFO
 318         pci_read_config_byte(dev, (drive_pci), &AP);
 319         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 320         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 321         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 322
 323         decode_registers(REG_A, AP);
 324         decode_registers(REG_B, BP);
 325         decode_registers(REG_C, CP);
 326         decode_registers(REG_D, DP);
 327 #endif /* PDC202XX_DECODE_REGISTER_INFO */
 328 #if PDC202XX_DEBUG_DRIVE_INFO
 329         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 330                 drive->name, ide_xfer_verbose(speed),
 331                 drive->dn, drive_conf);
 332                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 333         printk("0x%08x\n", drive_conf);
 334 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 335
 336         return (ide_config_drive_speed(drive, speed));
 337 }
 338
 339
 340 /*   0    1    2    3    4    5    6   7   8
 341  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 342  *           180, 150, 120,  90,  60
 343  * DMA_Speed
 344  * 180, 120,  90,  90,  90,  60,  30
 345  *  11,   5,   4,   3,   2,   1,   0
 346  */
 347 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 348 {
 349         u8 speed = 0;
 350
 351         if (pio == 5) pio = 4;
 352         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 353
 354         pdc202xx_tune_chipset(drive, speed);
 355 }
 356
 357 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 358 {
 359         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 360         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 361         return ((u8)(CIS & mask));
 362 }
 363
 364 /*
 365  * Set the control register to use the 66MHz system
 366  * clock for UDMA 3/4/5 mode operation when necessary.
 367  *
 368  * It may also be possible to leave the 66MHz clock on
 369  * and readjust the timing parameters.
 370  */
 371 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 372 {
 373         unsigned long clock_reg = hwif->dma_master + 0x11;
 374         u8 clock = hwif->INB(clock_reg);
 375
 376         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 377 }
 378
 379 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 380 {
 381         unsigned long clock_reg = hwif->dma_master + 0x11;
 382         u8 clock = hwif->INB(clock_reg);
 383
 384         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 385 }
 386
 387 static int config_chipset_for_dma (ide_drive_t *drive)
 388 {
 389         struct hd_driveid *id   = drive->id;
 390         ide_hwif_t *hwif        = HWIF(drive);
 391         struct pci_dev *dev     = hwif->pci_dev;
 392         u32 drive_conf          = 0;
 393         u8 drive_pci            = 0x60 + (drive->dn << 2);
 394         u8 test1 = 0, test2 = 0, speed = -1;
 395         u8 AP = 0, cable = 0;
 396
 397         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 398                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 399
 400         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 401                 cable = pdc202xx_old_cable_detect(hwif);
 402         else
 403                 ultra_66 = 0;
 404
 405         if (ultra_66 && cable) {
 406                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 407                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 408         }
 409
 410         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 411                 pdc_old_disable_66MHz_clock(drive->hwif);
 412
 413         drive_pci = 0x60 + (drive->dn << 2);
 414         pci_read_config_dword(dev, drive_pci, &drive_conf);
 415         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 416                 goto chipset_is_set;
 417
 418         pci_read_config_byte(dev, drive_pci, &test1);
 419         if (!(test1 & SYNC_ERRDY_EN)) {
 420                 if (drive->select.b.unit & 0x01) {
 421                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 422                         if ((test2 & SYNC_ERRDY_EN) &&
 423                             !(test1 & SYNC_ERRDY_EN)) {
 424                                 pci_write_config_byte(dev, drive_pci,
 425                                         test1|SYNC_ERRDY_EN);
 426                         }
 427                 } else {
 428                         pci_write_config_byte(dev, drive_pci,
 429                                 test1|SYNC_ERRDY_EN);
 430                 }
 431         }
 432
 433 chipset_is_set:
 434
 435         if (drive->media == ide_disk) {
 436                 pci_read_config_byte(dev, (drive_pci), &AP);
 437                 if (id->capability & 4) /* IORDY_EN */
 438                         pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 439                 pci_read_config_byte(dev, (drive_pci), &AP);
 440                 if (drive->media == ide_disk)   /* PREFETCH_EN */
 441                         pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 442         }
 443
 444         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 445
 446         if (!(speed)) {
 447                 /* restore original pci-config space */
 448                 pci_write_config_dword(dev, drive_pci, drive_conf);
 449                 hwif->tuneproc(drive, 5);
 450                 return 0;
 451         }
 452
 453         (void) hwif->speedproc(drive, speed);
 454         return ide_dma_enable(drive);
 455 }
 456
 457 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 458 {
 459         ide_hwif_t *hwif        = HWIF(drive);
 460         struct hd_driveid *id   = drive->id;
 461
 462         drive->init_speed = 0;
 463
 464         if (id && (id->capability & 1) && drive->autodma) {
 465                 /* Consult the list of known "bad" drives */
 466                 if (__ide_dma_bad_drive(drive))
 467                         goto fast_ata_pio;
 468                 if (id->field_valid & 4) {
 469                         if (id->dma_ultra & hwif->ultra_mask) {
 470                                 /* Force if Capable UltraDMA */
 471                                 int dma = config_chipset_for_dma(drive);
 472                                 if ((id->field_valid & 2) && !dma)
 473                                         goto try_dma_modes;
 474                         }
 475                 } else if (id->field_valid & 2) {
 476 try_dma_modes:
 477                         if ((id->dma_mword & hwif->mwdma_mask) ||
 478                             (id->dma_1word & hwif->swdma_mask)) {
 479                                 /* Force if Capable regular DMA modes */
 480                                 if (!config_chipset_for_dma(drive))
 481                                         goto no_dma_set;
 482                         }
 483                 } else if (__ide_dma_good_drive(drive) &&
 484                             (id->eide_dma_time < 150)) {
 485                                 goto no_dma_set;
 486                         /* Consult the list of known "good" drives */
 487                         if (!config_chipset_for_dma(drive))
 488                                 goto no_dma_set;
 489                 } else {
 490                         goto fast_ata_pio;
 491                 }
 492                 return hwif->ide_dma_on(drive);
 493         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 494 fast_ata_pio:
 495 no_dma_set:
 496                 hwif->tuneproc(drive, 5);
 497                 return hwif->ide_dma_off_quietly(drive);
 498         }
 499         /* IORDY not supported */
 500         return 0;
 501 }
 502
 503 static int pdc202xx_quirkproc (ide_drive_t *drive)
 504 {
 505         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 506 }
 507
 508 static int pdc202xx_old_ide_dma_begin(ide_drive_t *drive)
 509 {
 510         if (drive->current_speed > XFER_UDMA_2)
 511                 pdc_old_enable_66MHz_clock(drive->hwif);
 512         if (drive->addressing == 1) {
 513                 struct request *rq      = HWGROUP(drive)->rq;
 514                 ide_hwif_t *hwif        = HWIF(drive);
 515 //              struct pci_dev *dev     = hwif->pci_dev;
 516 //              unsgned long high_16    = pci_resource_start(dev, 4);
 517                 unsigned long high_16   = hwif->dma_master;
 518                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 519                 u32 word_count  = 0;
 520                 u8 clock = hwif->INB(high_16 + 0x11);
 521
 522                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 523                 word_count = (rq->nr_sectors << 8);
 524                 word_count = (rq_data_dir(rq) == READ) ?
 525                                         word_count | 0x05000000 :
 526                                         word_count | 0x06000000;
 527                 hwif->OUTL(word_count, atapi_reg);
 528         }
 529         return __ide_dma_begin(drive);
 530 }
 531
 532 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 533 {
 534         if (drive->addressing == 1) {
 535                 ide_hwif_t *hwif        = HWIF(drive);
 536 //              unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 537                 unsigned long high_16   = hwif->dma_master;
 538                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 539                 u8 clock                = 0;
 540
 541                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 542                 clock = hwif->INB(high_16 + 0x11);
 543                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 544         }
 545         if (drive->current_speed > XFER_UDMA_2)
 546                 pdc_old_disable_66MHz_clock(drive->hwif);
 547         return __ide_dma_end(drive);
 548 }
 549
 550 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 551 {
 552         ide_hwif_t *hwif        = HWIF(drive);
 553 //      struct pci_dev *dev     = hwif->pci_dev;
 554 //      unsigned long high_16   = pci_resource_start(dev, 4);
 555         unsigned long high_16   = hwif->dma_master;
 556         u8 dma_stat             = hwif->INB(hwif->dma_status);
 557         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 558
 559         if (hwif->channel) {
 560                 if ((sc1d & 0x50) == 0x50)
 561                         goto somebody_else;
 562                 else if ((sc1d & 0x40) == 0x40)
 563                         return (dma_stat & 4) == 4;
 564         } else {
 565                 if ((sc1d & 0x05) == 0x05)
 566                         goto somebody_else;
 567                 else if ((sc1d & 0x04) == 0x04)
 568                         return (dma_stat & 4) == 4;
 569         }
 570 somebody_else:
 571         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 572 }
 573
 574 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 575 {
 576         if (HWIF(drive)->resetproc != NULL)
 577                 HWIF(drive)->resetproc(drive);
 578         return __ide_dma_lostirq(drive);
 579 }
 580
 581 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 582 {
 583         if (HWIF(drive)->resetproc != NULL)
 584                 HWIF(drive)->resetproc(drive);
 585         return __ide_dma_timeout(drive);
 586 }
 587
 588 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 589 {
 590 #ifdef CONFIG_BLK_DEV_IDEDMA
 591 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 592         unsigned long high_16   = hwif->dma_master;
 593 #else /* !CONFIG_BLK_DEV_IDEDMA */
 594         unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 595 #endif /* CONFIG_BLK_DEV_IDEDMA */
 596         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 597
 598         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 599         mdelay(100);
 600         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 601         mdelay(2000);   /* 2 seconds ?! */
 602
 603         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 604                 hwif->channel ? "Secondary" : "Primary");
 605 }
 606
 607 void pdc202xx_reset (ide_drive_t *drive)
 608 {
 609         ide_hwif_t *hwif        = HWIF(drive);
 610         ide_hwif_t *mate        = hwif->mate;
 611
 612         pdc202xx_reset_host(hwif);
 613         pdc202xx_reset_host(mate);
 614 #if 0
 615         /*
 616          * FIXME: Have to kick all the drives again :-/
 617          * What a pain in the ACE!
 618          */
 619         if (hwif->present) {
 620                 u16 hunit = 0;
 621                 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
 622                         ide_drive_t *hdrive = &hwif->drives[hunit];
 623                         if (hdrive->present) {
 624                                 if (hwif->ide_dma_check)
 625                                         hwif->ide_dma_check(hdrive);
 626                                 else
 627                                         hwif->tuneproc(hdrive, 5);
 628                         }
 629                 }
 630         }
 631         if (mate->present) {
 632                 u16 munit = 0;
 633                 for (munit = 0; munit < MAX_DRIVES; ++munit) {
 634                         ide_drive_t *mdrive = &mate->drives[munit];
 635                         if (mdrive->present) {
 636                                 if (mate->ide_dma_check)
 637                                         mate->ide_dma_check(mdrive);
 638                                 else
 639                                         mate->tuneproc(mdrive, 5);
 640                         }
 641                 }
 642         }
 643 #else
 644         hwif->tuneproc(drive, 5);
 645 #endif
 646 }
 647
 648 /*
 649  * Since SUN Cobalt is attempting to do this operation, I should disclose
 650  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 651  * HOTSWAP ATA Infrastructure.
 652  */
 653 static int pdc202xx_tristate (ide_drive_t * drive, int state)
 654 {
 655         ide_hwif_t *hwif        = HWIF(drive);
 656 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 657         unsigned long high_16   = hwif->dma_master;
 658         u8 sc1f                 = hwif->INB(high_16|0x001f);
 659
 660         if (!hwif)
 661                 return -EINVAL;
 662
 663 //      hwif->bus_state = state;
 664
 665         if (state) {
 666                 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
 667         } else {
 668                 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
 669         }
 670         return 0;
 671 }
 672
 673 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
 674 {
 675         if (dev->resource[PCI_ROM_RESOURCE].start) {
 676                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 677                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 678                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
 679                         name, dev->resource[PCI_ROM_RESOURCE].start);
 680         }
 681
 682 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
 683         pdc202_devs[n_pdc202_devs++] = dev;
 684
 685         if (!pdc202xx_proc) {
 686                 pdc202xx_proc = 1;
 687                 ide_pci_create_host_proc("pdc202xx", pdc202xx_get_info);
 688         }
 689 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
 690
 691         /*
 692          * software reset -  this is required because the bios
 693          * will set UDMA timing on if the hdd supports it. The
 694          * user may want to turn udma off. A bug in the pdc20262
 695          * is that it cannot handle a downgrade in timing from
 696          * UDMA to DMA. Disk accesses after issuing a set
 697          * feature command will result in errors. A software
 698          * reset leaves the timing registers intact,
 699          * but resets the drives.
 700          */
 701 #if 0
 702         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 703             (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
 704             (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
 705             (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
 706                 unsigned long high_16   = pci_resource_start(dev, 4);
 707                 byte udma_speed_flag    = inb(high_16 + 0x001f);
 708                 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
 709                 mdelay(100);
 710                 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
 711                 mdelay(2000);   /* 2 seconds ?! */
 712         }
 713
 714 #endif
 715         return dev->irq;
 716 }
 717
 718 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 719 {
 720         hwif->autodma = 0;
 721         hwif->tuneproc  = &config_chipset_for_pio;
 722         hwif->quirkproc = &pdc202xx_quirkproc;
 723
 724         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 725                 hwif->busproc   = &pdc202xx_tristate;
 726                 hwif->resetproc = &pdc202xx_reset;
 727         }
 728
 729         hwif->speedproc = &pdc202xx_tune_chipset;
 730
 731         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 732
 733         hwif->ultra_mask = 0x3f;
 734         hwif->mwdma_mask = 0x07;
 735         hwif->swdma_mask = 0x07;
 736
 737         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 738         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 739         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 740
 741         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 742                 if (!(hwif->udma_four))
 743                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 744                 hwif->ide_dma_begin = &pdc202xx_old_ide_dma_begin;
 745                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 746         }
 747         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 748
 749         if (!noautodma)
 750                 hwif->autodma = 1;
 751         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 752 #if PDC202_DEBUG_CABLE
 753         printk(KERN_DEBUG "%s: %s-pin cable\n",
 754                 hwif->name, hwif->udma_four ? "80" : "40");
 755 #endif /* PDC202_DEBUG_CABLE */
 756 }
 757
 758 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 759 {
 760         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 761
 762         if (hwif->channel) {
 763                 ide_setup_dma(hwif, dmabase, 8);
 764                 return;
 765         }
 766
 767         udma_speed_flag = hwif->INB((dmabase|0x1f));
 768         primary_mode    = hwif->INB((dmabase|0x1a));
 769         secondary_mode  = hwif->INB((dmabase|0x1b));
 770         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 771                 "Primary %s Mode " \
 772                 "Secondary %s Mode.\n", hwif->cds->name,
 773                 (udma_speed_flag & 1) ? "EN" : "DIS",
 774                 (primary_mode & 1) ? "MASTER" : "PCI",
 775                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 776
 777 #ifdef CONFIG_PDC202XX_BURST
 778         if (!(udma_speed_flag & 1)) {
 779                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 780                         hwif->cds->name, udma_speed_flag,
 781                         (udma_speed_flag|1));
 782                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 783                 printk("%sACTIVE\n",
 784                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 785         }
 786 #endif /* CONFIG_PDC202XX_BURST */
 787 #ifdef CONFIG_PDC202XX_MASTER
 788         if (!(primary_mode & 1)) {
 789                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 790                         "0x%02x -> 0x%02x ", hwif->cds->name,
 791                         primary_mode, (primary_mode|1));
 792                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 793                 printk("%s\n",
 794                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 795         }
 796
 797         if (!(secondary_mode & 1)) {
 798                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 799                         "0x%02x -> 0x%02x ", hwif->cds->name,
 800                         secondary_mode, (secondary_mode|1));
 801                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 802                 printk("%s\n",
 803                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 804         }
 805 #endif /* CONFIG_PDC202XX_MASTER */
 806
 807         ide_setup_dma(hwif, dmabase, 8);
 808 }
 809
 810 static void __devinit init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d)
 811 {
 812         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 813                 u8 irq = 0, irq2 = 0;
 814                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 815                 /* 0xbc */
 816                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 817                 if (irq != irq2) {
 818                         pci_write_config_byte(dev,
 819                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 820                         printk(KERN_INFO "%s: pci-config space interrupt "
 821                                 "mirror fixed.\n", d->name);
 822                 }
 823         }
 824
 825 #if 0
 826         if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
 827         if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
 828              (tmp & e->mask) != e->val))
 829
 830         if (d->enablebits[0].reg != d->enablebits[1].reg) {
 831                 d->enablebits[0].reg    = d->enablebits[1].reg;
 832                 d->enablebits[0].mask   = d->enablebits[1].mask;
 833                 d->enablebits[0].val    = d->enablebits[1].val;
 834         }
 835 #endif
 836
 837         ide_setup_pci_device(dev, d);
 838 }
 839
 840 static void __devinit init_setup_pdc20265(struct pci_dev *dev, ide_pci_device_t *d)
 841 {
 842         if ((dev->bus->self) &&
 843             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 844             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 845              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 846                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 847                         "attached to I2O RAID controller.\n");
 848                 return;
 849         }
 850
 851 #if 0
 852         {
 853                 u8 pri = 0, sec = 0;
 854
 855         if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
 856              (tmp & e->mask) != e->val))
 857
 858         if (d->enablebits[0].reg != d->enablebits[1].reg) {
 859                 d->enablebits[0].reg    = d->enablebits[1].reg;
 860                 d->enablebits[0].mask   = d->enablebits[1].mask;
 861                 d->enablebits[0].val    = d->enablebits[1].val;
 862         }
 863         }
 864 #endif
 865
 866         ide_setup_pci_device(dev, d);
 867 }
 868
 869 static void __devinit init_setup_pdc202xx(struct pci_dev *dev, ide_pci_device_t *d)
 870 {
 871         ide_setup_pci_device(dev, d);
 872 }
 873
 874 /**
 875  *      pdc202xx_init_one       -       called when a PDC202xx is found
 876  *      @dev: the pdc202xx device
 877  *      @id: the matching pci id
 878  *
 879  *      Called when the PCI registration layer (or the IDE initialization)
 880  *      finds a device matching our IDE device tables.
 881  */
 882
 883 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 884 {
 885         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 886
 887         d->init_setup(dev, d);
 888         return 0;
 889 }
 890
 891 static struct pci_device_id pdc202xx_pci_tbl[] = {
 892         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 893         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 894         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 895         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 896         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 897         { 0, },
 898 };
 899 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 900
 901 static struct pci_driver driver = {
 902         .name           = "Promise Old IDE",
 903         .id_table       = pdc202xx_pci_tbl,
 904         .probe          = pdc202xx_init_one,
 905 };
 906
 907 static int pdc202xx_ide_init(void)
 908 {
 909         return ide_pci_register_driver(&driver);
 910 }
 911
 912 module_init(pdc202xx_ide_init);
 913
 914 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 915 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 916 MODULE_LICENSE("GPL");